9240LPRPQK

9240LP 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC REFCOM Vref SENSE NC AVSS AVDD NC NC OTC BIT 1 BIT 2 LPTSTATUS LPTBIT 9240 14 Bit A/D LPTAVDD CURRENT SENSE LPTDVDD LPTDRVDD LPTVINA LPTVINB LPTVREF LPTVREF CROW BAR 9240LP VINB VREF VINB VREF Control Signals NC BIAS CAPB CAPT NC CML LPTref VinA VinB LPTDVDD LPTAVDD BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9 BIT 10 BIT 11 BIT 12 BIT 13 DVDD DRVDD VINA DVDD DRVDD VINA Data Outputs AVDD AVDD Memory DVSS AVSS DVDD AVDD NC DRVDD CLK LPTSTATUS LPTBIT NC BIT 14 9240LP BLOCK DIAGRAM DESCRIPTION: Maxwell Technologies’ 9240LP is a 14-bit, analog-to-digital converter that operates at a 10 MSPS rate. Manufactured with a high speed CMOS process, this ADC contains an on-chip, high performance, low noise, sample-and-hold amplifier and programmable voltage reference. The 9240LP offers single supply operation and dissipates only 295 mW with a 5 volt supply. This device provides no missing codes and excellent temperature drift performance over the full operating temperature range. FEATURES: • • • • • • • • • • • • • • RAD-PAK® radiation-hardened against natural space radiation Low power dissipation: 295 mW Single 5 V supply Integral nonlinearity error: 2.5 LSB Differential nonlinearity error: 0.6 LSB Input referred noise: 0.36 LSB Complete: On-chip sample-and-hold amplifier and voltage reference Signal-to-noise and distortion ration: 77.5 dB Spurious-free dynamic range: 90 dB Out-of-range indicator Straight binary output data Total dose hardened to 100 Krads (Si), dependent on orbit and mission duration Single Event Latchup (SEL) protected The 9240LP utilizes Maxwell’s LPT™ Latchup Protection Circuit.Maxwell Technologies' patented RAD-PAK® packaging technology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding while providing the required radiation shielding for a lifetime in orbit or space mission. In a GEO orbit, RAD-PAK® provides protection to 100 krad (Si) radiation dose tolerance. This product is available with screening up to Maxwell Technologies self-defined Class K. 01.10.05 REV 6 All data sheets are subject to change without notice 1 (858) 503-3300- Fax: (858) 503-3301- www.maxwell.com ©2005 Maxwell Technologies All rights reserved. 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC 9240LP TABLE 1. 9240LP PIN DESCRIPTION PIN NUMBER 1 2, 29 3 4, 28 5 6 7 8 9 NAME DVSS AVSS DVDD AVDD NC DRVDD CLK LPTSTATUS LPTBIT DESCRIPTION Digital Ground Analog Ground 5V Digital Supply 5V Analog Supply No Connect Digital Output Driver Supply Clock Input Pin A 0 to 5V square-wave is output during the decision time and protect time. Normally low. The LPT circuit will crowbar the power supplies to the 9240 for as long as a logic high is applied. Used to verify operation of the LPT. Normally a logical low or ground is applied to this input. No Connect Least Significant Data Bit (LSB) Data Output Bits Most Significant Data Bits (MSB) Out of Range No Connect Reference Select Reference I/O Reference Common No Connect Power/Speed Programming Noise Reduction Pin Noise Reduction Pin Common-Mod Level (Midsupply) Protected Reference I/O Analog Input Pin (+) Analog Input Pin (-) Protected 5V Digital Supply Protected 5V Analog Supply Memory 10 11 12-23 24 25 26, 27, 30 31 32 33 34, 38 35 36 37 39 40 41 42 43 44 NC BIT 14 BIT 13-BIT 2 BIT 1 OTR NC SENSE VREF REFCOM NC BIAS 1 CAPB CAPT CML LPTVREF VINA VINB LPTDVDD LPTAVDD 1. See Speed/Power programmability section. 01.10.05 REV 6 All data sheets are subject to change without notice 2 ©2005 Maxwell Technologies All rights reserved. 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC 9240LP TABLE 2. 9240LP ABSOLUTE MAXIMUM RATINGS 1 PARAMETER AVDD DVDD AVSS AVDD DRVDD DRVSS REFCOM CLK Digital Outputs VINA, VINB VREF SENSE CAPB, CAPT BIAS Junction Temperature Operating Temperature Package Weight Thermal Resistance Storage Temperature Lead Temperature (10 sec) TJC TSTG TL TJ TA SYMBOL WITH RESPECT TO AVSS DVSS DVSS DVDD DRVSS AVSS AVSS AVSS DRVSS AVSS AVSS AVSS AVSS AVSS MIN -0.3 -0.3 -0.3 -6.5 -0.3 -0.3 -0.3 +0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 --55 ---65 -10.5 9.6 TYP MAX 6.5 6.5 0.3 6.5 6.5 0.3 0.3 AVDD -0.5 DRVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + -.3 150 125 --150 300 UNIT V V V V V V V V V V V Memory V V V °C °C Grams ° C/W °C °C 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. 01.10.05 REV 6 All data sheets are subject to change without notice 3 ©2005 Maxwell Technologies All rights reserved. 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC 9240LP TABLE 3. 9240LP DC SPECIFICATIONS (AVDD = 5V, DVDD = 5V, DRVDD = 5V, RBIAS = 2KΩ, VREF = 2.5V, VINA=VINB = ±2.5V DIFFERENTIAL INPUT CENTERED ON VREF(1.25V TO 3.75V ABSOLUTE) TA = -55 TO +125°C, UNLESS OTHERWISE SPECIFIED) PARAMETER RESOLUTION MAX CONVERSION RATE MAX REFERRED NOISE1 VREF= 1 V VREF = 2.5V ACCURACY2 Integral Nonlinearity (INL) Differential Nonlinearity (DNL) INL3 DNL3 No Missing Codes Zero Error (@ 25 °C) Gain Error (@ 25 °C)1,4 Gain Error (@ 25 °C)5 TEMPERATURE DRIFT Zero Error Gain Error4 Gain Error5 POWER SUPPLY REJECTION ANALOG INPUT1 Input Span (with VREF = 1.0 V) (with VREF = 2.5 V) Input (VINA OR VINB) Range Input Capacitance INTERNAL VOLTAGE REFERENCE1 Output Voltage (1V mode) Output Voltage Tolerance (1 V Mode) Output Voltage (2.5 V Mode) Output Voltage Tolerance (2.5 V Mode) Load Regulation VREF Load Regulation LPTVREF6,7 REFERENCE INPUT RESISTANCE 1, 2, 3 1, 2, 3 1, 2, 3 SUBGROUPS 1 9, 10, 11 MIN 14 10 ---3 -1 ---------1, 2, 3 -2 -0 --------TYP1 --0.9 0.36 ±2.5 ±0.6 ±2.5 ±0.7 ----3.0 20.0 5.0 ----16 1 -2.5 -10 -5 MAX ----3 1.0 -14 0.3 1.5 0.75 ---0.1 -5 AVDD -.25 --±14 -±35 -10.0 -UNIT Bits min MHz min LSB rms 1 1 1 1, 2, 3 LSB LSB LSB LSB Bits Guaranteed % FSR % FSR % FSR ppm/°C ppm/°C ppm/°C % FSR V p-p V p-p V pF V mV V mV mV mV kΩ Memory 1, 2, 3 01.10.05 REV 6 All data sheets are subject to change without notice 4 ©2005 Maxwell Technologies All rights reserved. 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC (AVDD = 5V, DVDD = 5V, DRVDD = 5V, RBIAS = 2KΩ, VREF = 2.5V, VINA=VINB = ±2.5V DIFFERENTIAL INPUT CENTERED ON VREF(1.25V TO 3.75V ABSOLUTE) TA = -55 TO +125°C, UNLESS OTHERWISE SPECIFIED) PARAMETER LPT ASIC RDS ON - VREF - AVDD - DVDD - VIN A - VIN B LATCHUP PROTECTION - Decision Time - Protect Time - AVDD Trip Current - AVDD Trip Current Tolerance - DVDD Trip Current - DVDD Trip Current Tolerance POWER SUPPLIES Supply Voltages - AVDD - DVDD - DRVDD Supply Current - IAVDD - IDVDD SUBGROUPS 1, 2, 3 MIN TYP1 MAX 9240LP TABLE 3. 9240LP DC SPECIFICATIONS UNIT 8 8 105 105 10 70 75 ±15 28 ±5 15 Ω Ω Ω Ω µs µs mA mA mA Memory ---1, 2, 3 1, 2, 3 --- 5 5 5 43 3 5 5 5 55 16 V (±5% AVDD Operating) V (±5% DVDD Operating) V (±5% DRVDD Operating) mA mA POWER CONSUMPTION8 1. Guaranteed by design 2. Tested using external VREF with servo control 3. VREF = 1V 4. Including internal reference 5. Excluding internal reference 6. Load regulkation with 1 mA load current 7. LPTVREF should not be capacitively loaded above 0.1uF 8. Calculated from IDD 295 355 mW 01.10.05 REV 6 All data sheets are subject to change without notice 5 ©2005 Maxwell Technologies All rights reserved. 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC 9240LP TABLE 4. 9240LP AC SPECIFICATIONS (AVDD = 5V, DVDD = 5V, DRVDD = 5V, fSAMPLE = 10MSPS, BIAS = 2KΩ, VREF = 2.5V, VINA = -0.5dBFS, AC COUPLED/DIFFERENTIAL INPUT, TA = -55 TO +125°C, UNLESS OTHERWISE SPECIFIED) PARAMETER SIGNAL-TO-NOISE AND DISTORTION RATIO (S/N+D) fINPUT = 500 kHz fINPUT = 1.0 MHz fINPUT = 5.0 MHz EFFECTIVE NUMBER OF BITS (ENOB)2 fINPUT = 500 kHz fINPUT = 1.0 MHz fINPUT = 5.0 MHz SIGNAL-TO-NOISE RATION (SNR) fINPUT = 500 kHz fINPUT = 1.0 MHz fINPUT = 5.0 MHz TOTAL HARMONIC DISTORTION (THD) fINPUT = 500 kHz fINPUT = 1.0 MHz fINPUT = 5.0 MHz SPURIOUS FREE DYNAMIC RANGE fINPUT = 500 kHz fINPUT = 1.0 MHz fINPUT = 5.0 MHz DYNAMIC PERFORMANCE1 Full Power Bandwidth Small Signal Bandwidth Aperture Delay Aperture Jitter Acquisition to Full-Scale Step (0.0025%) Overvoltage Recovery Time 1. Guaranteed by design 2. ENOB calculated from SNR 4, 5, 6 ---------90.0 90.0 80.0 70 70 1 4 45 167 ---------dB dB dB MHz MHz ns ps rms ns ns 4, 5, 6 74.5 -----77 77 77 -76.0 -83.0 -75.0 ------dB dB dB SUBGROUPS MIN ---12 --TYP1 76.0 76.0 75.5 -12.3 11.9 MAX ------UNIT dB dB dB Bits Bits Bits Memory dB dB dB TABLE 5. 9240LP DIGITAL SPECIFICATIONS (AVDD = 5V, DVDD = 5V, TA = -55 TO +125°C, UNLESS OTHERWISE SPECIFIED) PARAMETER CLOCK INPUT1 High Level Input Voltage2 Low Level Input Voltage High Level Input Current (VIN = DVDD) Low Level Input Current (VIN = 0V) Input Capacitance SUBGROUPS 1, 2, 3 VIH VIL IIH IIL CIN 3.5 -----1.0 ±10 ±10 -V V µA µA pF SYMBOL MIN TYP MAX UNIT 5 01.10.05 REV 6 All data sheets are subject to change without notice 6 ©2005 Maxwell Technologies All rights reserved. 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC TABLE 5. 9240LP DIGITAL SPECIFICATIONS (AVDD = 5V, DVDD = 5V, TA = -55 TO +125°C, UNLESS OTHERWISE SPECIFIED) PARAMETER SUBGROUPS SYMBOL MIN TYP 9240LP MAX UNIT 1, 2, 3 LOGIC OUTPUTS (with DRVDD = 5V) V min VOH 4.5 High Level Output Voltage (IOH = 50 µ A) V min 2.4 High Level Output Voltage (IOH = 0.5 mA) VOH V max 0.4 Low Level Output Voltage (IOL = 1.6 mA) VOL V max 0.1 Low Level Output Voltage (IOL = 50 µ A) VOL pF typ -Output Capacitance COUT 5 1. Due to the voltage drop across the LPT circuiry the CLOCK signal must be no greater than AVDD - 0.5V 2. Guaranteed by design TABLE 6. 9240LP SWITCHING CHARACTERISTICS1 (TA = -55 TO +125°C WITH AVDD = 5V, DVDD = 5V, DRVDD = 5V, RBIAS = 2 KW, CL = 20 PF) PARAMETER Clock Period CLOCK Pulse width High CLOCK Pulse width Low Output Delay Pipeline Delay (Latency) 1. Guaranteed by design SYMBOL tC tCH tCL tOD MIN 100 45 45 8 -TYP ---13 -MAX ---19 --3 UNITS ns ns ns ns Clock Cycles Memory 01.10.05 REV 6 All data sheets are subject to change without notice 7 ©2005 Maxwell Technologies All rights reserved. 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC 9240LP RECOMMENDED EXTERNAL REFERENCE CLK 2K VINA VINB LPTREF 0.1UF 10K 5V REF 10UF 0.1UF 0.1UF LPTAVD SENSE MODE SELECT 14 BIT OUTPUT CAPA CAPT VREF MDAC1 MDAC2 MDAC 3 AVDD DVDD DRVDD BIAS CML A/D 4 A/D A/D 4 4 DIGITAL CORRECTION LOGIC 14 OUTPUT DRIVERS A/D 4 OTR REFCOM AVSS DVSS DRVSS Memory TYPICAL DIFFERENTIAL CHARACTERIZATION CURVES/PLOTS (AVDD = 5V, DVDD = 5V, DRVDD = 5V, fSAMPLE = 10 MSPS, RBIAS = 2 KW, TA = 25 ° C, DIFFERENTIAL INPUT) FIGURE 1. TIMING DIAGRAM 01.10.05 REV 6 All data sheets are subject to change without notice 8 ©2005 Maxwell Technologies All rights reserved. 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC 9240LP FIGURE 2. SINAD VS. INPUT FREQUENCY (INPUT SPACE = 2V, VCM = 2.5V) FIGURE 3. THD VS. INPUT FREQUENCY (INPUT SPAN = 5V, VCM = 2.5V) Memory 01.10.05 REV 6 All data sheets are subject to change without notice 9 ©2005 Maxwell Technologies All rights reserved. 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC 9240LP FIGURE 4. TYPICAL FFT, fIN = 1.0 MHZ (INPUT SPACE = 5V, VCM = 2.5V) FIGURE 5. SINAD VS. INPUT FREQUENCY (INPUT SPAN = 2V, VCM = 2.5V) Memory FIGURE 6. THD VS. INPUT FREQUENCY (INPUT SPAN = 2V, VCM = 2.5V) 01.10.05 REV 6 All data sheets are subject to change without notice 10 ©2005 Maxwell Technologies All rights reserved. 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC 9240LP FIGURE 7. TYPICAL FFT, fIN = 5.0 MHZ (INPUT SPAN = 2 V, VCM = 2.5 V) FIGURE 8. THD VS. SAMPLE RATE (fIN = 5.0 MHZ, AIN = -0.5 DBFS, VCM = 2.5 V) Memory FIGURE 9. SINGLE TONE SFDR (fIN = 5.0 MHZ, VCM = 2.5 V) 01.10.05 REV 6 All data sheets are subject to change without notice 11 ©2005 Maxwell Technologies All rights reserved. 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC 9240LP FIGURE 10. DUAL TONE SFDR (F1 = 0.95 MHZ, F2 = 1.04 MHZ, VCM = 2.5 V) FIGURE 11. TYPICAL INL (INPUT SPAN = 5 V) Memory FIGURE 12. TYPICAL DNL (INPUT SPAN = 5 V) 01.10.05 REV 6 All data sheets are subject to change without notice 12 ©2005 Maxwell Technologies All rights reserved. 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC FIGURE 13. “GROUNDED-INPUT” HISTOGRAM (INPUT SPAN = 5 V) 9240LP FIGURE 14. SINAD VS. INPUT FREQUENCY (INPUT SPAN = 2 V, VCM = 2.5V) Memory 01.10.05 REV 6 All data sheets are subject to change without notice 13 ©2005 Maxwell Technologies All rights reserved. 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC 9240LP FIGURE 15. THD VS. INPUT FREQUENCY (INPUT SPAN = 5 V, VCM = 2.5 V) FIGURE 16. CMR VS. INPUT FREQUENCY (INPUT SPAN = 2 V, VCM = 2.5 V) Memory 01.10.05 REV 6 All data sheets are subject to change without notice 14 ©2005 Maxwell Technologies All rights reserved. 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC 9240LP FIGURE 17. SINAD VS. INPUT FREQUENCY (INPUT SPAN = 5 V, VCM = 2.5 V) FIGURE 18. THD VS. INPUT FREQUENCY (INPUT SPAN = 5 V, VCM = 2.5 V) Memory 01.10.05 REV 6 All data sheets are subject to change without notice 15 ©2005 Maxwell Technologies All rights reserved. 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC FIGURE 19. TYPICAL VOLTAGE REFERENCE ERROR VS. TEMPERATURE 9240LP Memory 44 PIN RAD-PAK® QUAD FLAT PACKAGE SYMBOL MIN A b c D 0.185 0.015 0.008 0.643 01.10.05 REV 6 DIMENSION NOM 0.205 0.017 0.010 0.650 MAX 0.225 0.019 0.012 0.657 All data sheets are subject to change without notice 16 ©2005 Maxwell Technologies All rights reserved. 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC 44 PIN RAD-PAK® QUAD FLAT PACKAGE SYMBOL MIN D1 e S1 L Q N 0.005 0.260 0.020 DIMENSION NOM 0.500 BSC 0.050 BSC 0.067 0.270 0.025 44 9240LP MAX -0.280 0.030 Note: All dimensions in inches Important Notice: These data sheets are created using the chip manufacturers published specifications. Maxwell Technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. The specifications presented within these data sheets represent the latest and most accurate information available to date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no responsibility for the use of this information. Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems without express written approval from Maxwell Technologies. Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Technologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts. Memory 01.10.05 REV 6 All data sheets are subject to change without notice 17 ©2005 Maxwell Technologies All rights reserved. 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC Product Ordering Options Model Number 9240LP RP Q X Feature 9240LP Option Details Screening Flow MCM1 K= Maxwell Self-Defined Class K H= Maxwell Self-Defined Class H I = Industrial (testing @ -55°C, +25°C, +125°C) E = Engineering (testing @ +25°C) Memory Package Q = Quad Flat Pack Radiation Feature RP = RAD-PAK® package Base Product Nomenclature 14-Bit, 10MSPS A/D Converter with LPT ASIC 1) Products manufactured and screened to Maxwell Technologies self-defined Calss H and Class K flows. 01.10.05 REV 6 All data sheets are subject to change without notice 18 ©2005 Maxwell Technologies All rights reserved.