23C8000-12

MX23C8000 8M-BIT [1M x 8] CMOS MASK ROM FEATURES • • • • • • 1M x 8 organization Single +5V power supply Fast access time : 100/120/150/200ns Totally static operation Completely TTL compatible Operating current : 25mA • Standby current : 15uA • Package - 32 pin plastic DIP - 32 pin plastic SOP - 32 pin plastic PLCC - 32 pin plastic TSOP GENERAL DESCRIPTION The MX23C8000 is a 5V only, 8M-bit, Read Only Memory. It is organized as 1M words by 8 bits, operates from a single +5V supply, has a static standby mode, and has an access time of 100/120/150/200ns. It is designed to be compatible with all microprocessors and similar applications in which high performance, large bit storage and simple interfacing are important design considerations. MX23C8000 offers automatic power-down, with powerdown controlled by the chip enable (CE) input. When CE goes high, the device automatically powers down and remains in a low-power standby modes as long as CE remains high. PIN CONFIGURATION 32 PDIP A19 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A18 A17 A14 A13 A8 A9 A11 OE A10 CE Q7 Q6 Q5 Q4 Q3 32 SOP A19 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 VSS 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 10 19 18 17 VCC A18 A17 A14 A13 A8 A9 A11 OE A10 CE Q7 Q6 Q5 Q4 Q3 32 PLCC VCC A12 A15 A16 A19 A18 A17 MX23C8000 32 TSOP A11 A9 A8 A13 A14 A17 A18 VCC A19 A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE Q7 Q6 Q5 Q4 Q3 VSS Q2 Q1 Q0 A0 A1 A2 A3 A7 A6 A5 A4 A3 A2 A1 A0 DQ 5 4 1 32 30 29 A14 A13 A8 A9 9 MX23C8000 25 A11 OE A10 CE MX23C8000 13 14 Q1 Q2 VSS 17 Q3 Q4 Q5 21 20 Q6 Q7 P/N:PM0137 MX23C8000 REV. 4.3, JUL. 03, 2003 1 MX23C8000 PIN DESCRIPTION Symbol A0~A19 Q0~Q7 CE OE VCC VSS Pin Function Address Inputs Data Outputs Chip Enable Input Output Enable Input Power Supply Pin (+5V) Ground Pin BLOCK DIAGRAM CE OE CONTROL LOGIC OUTPUT BUFFERS Q0~Q7 . . . . . . . . VCC VSS Y-DECODER . . . . . . . . Y-SELECT A0~A19 ADDRESS INPUTS 8M BIT ROM ARRAY X-DECODER ABSOLUTE MAXIMUM RATINGS RATING Ambient Operating Temperature Storage Temperature Applied Input Voltage Applied Output Voltage VCC to Ground Potential Power Dissipation VALUE 0° C to 70° C -65° C to 125° C -0.5V to VCC+0.5 -0.5V to VCC+0.5 -0.5V to 7.0V 1.0W Note: minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may undershoot VSS to 2.0V for periods of up to 20ns. Maximum DC voltage on input or I/O pins is VCC+0.5V. During voltage transitions, input may overshoot VCC to VCC+2.0V for periods of up to 20ns. P/N:PM0137 REV. 4.3, JUL. 03, 2003 2 MX23C8000 DC CHARACTERISTICS (Ta = 0° C ~ 70° C, VCC = 5.0V ± 10%) Item Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Power-Down Supply Current Standby Supply Current Operating Supply Current Symbol VOH VOL VIH VIL ILI ILO ICC3 ICC2 ICC1 MIN. 2.4V 2.2V -0.3V MAX. 0.4V VCC+0.3V 0.8V 10uA 10uA 15uA 1.0mA 25mA Conditions IOH = -1.0mA IOL = 2.1mA VIN=0 to 5.5V VOUT=0 to 5.5V CE>VCC-0.2V CE=VIH Note 1 CAPACITANCE (Ta = 25° C, f=1.0MHz (Note 2)) Item Input Capacitance Output Capacitance Symbol CIN COUT MIN. MAX. 10 10 UNIT pF pF Conditions VIN=0V VOUT=0V AC CHARACTERISTICS (Ta = -10° C ~ 70° C, VCC = 5.0V ± 10%) 23C8000-10 PARAMETER Cycle Time Address Access Time Output Hold Time After Address Change Chip Enable Access Time Access Time Output Low Z Delay Output High Z Delay tLZ tHZ 0ns 20ns 0ns 20ns 0ns 20ns 0ns 20ns Note 3 Note 4 tCE 100ns 50ns 120ns 50ns 150ns 50ns 200ns 50ns Output Enable/Chip Select tOE SYMBOL MIN. tCYC tAA tOH 0ns MAX. 100ns 23C8000-12 MIN. MAX. 120ns 120ns 0ns 23C8000-15 MIN. 150ns 0ns MAX. 150ns 23C8000-20 MIN. 200ns 0ns MAX. CONDITIONS 200ns - 100ns - Note: 1. Measured with device selected at f=5MHz and output unloaded. 2. This parameter is periodically sampled and is not 100% teseted. 3. Output low-impedance delay (tLA) is measured from CE going low. 4. Output high-impedance delay (tHZ) is measured from CE going high. P/N:PM0137 REV. 4.3, JUL. 03, 2003 3 MX23C8000 AC Test Conditions Input Pulse Levels Input Rise and Fall Times Input Timing Level Output Timing Level Output Load 0.4V~2.4V 10ns 1.5V 0.8V and 2.0V See Figure IOH (load)=-1mA DOUT IOL (load)=2.1mA C