27C024-70

MX27C1100/27C1024 1M-BIT [128K x 8/64K x 16] CMOS EPROM FEATURES • 64K x 16 organization(MX27C1024, JEDEC pin out) • 128K x 8 or 64K x 16 organization(MX27C1100, ROM • • • • pin out compatible) +12.5V programming voltage Fast access time: 55/70/85/100/120/150 ns Totally static operation Completely TTL compatible • Operating current: 40mA • Standby current: 100uA • Package type: - 40 pin plastic DIP - 40 pin plastic SOP - 44 pin PLCC GENERAL DESCRIPTION The MX27C1024 is a 5V only, 1M-bit, One Time Programmable Read Only Memory. It is organized as 64K words by 16 bits per word(MX27C1024), 128K x 8 or 64K x 16(MX27C1100), operates from a single + 5 volt supply, has a static standby mode, and features fast single address location programming. All programming signals are TTL levels, requiring a single pulse. For programming outside from the system, existing EPROM programmers may be used. The MX27C1100/ 1024 supports a intelligent fast programming algorithm which can result in programming time of less than thirty seconds. This EPROM is packaged in industry standard 40 pin dual-in-line packages, 40 lead SOP and 44 lead PLCC packages. PIN CONFIGURATIONS PDIP/SOP(MX27C1100) NC A7 A6 A5 A4 A3 A2 A1 A0 CE GND OE Q0 Q8 Q1 Q9 Q2 Q10 Q3 Q11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 A8 A9 A10 A11 A12 A13 A14 A15 NC BYTE/VPP GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC BLOCK DIAGRAM (MX27C1100) CE OE BYTE/VPP CONTROL LOGIC OUTPUT BUFFERS Q0~Q14 Q15/A-1 A0~A15 ADDRESS INPUTS . . . . . . . . Y-DECODER X-DECODER . . . . . . . . Y-SELECT MX27C1100 1M BIT CELL MAXTRIX VCC GND P/N: PM0156 REV. 4.6, JAN. 14, 2003 1 MX27C1100/27C1024 PIN CONFIGURATIONS PDIP/SOP(MX27C1024) VPP CE Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8 GND Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC PGM NC A15 A14 A13 A12 A11 A10 A9 GND A8 A7 A6 A5 A4 A3 A2 A1 A0 PLCC(MX27C1024) PGM VCC VPP Q13 Q14 Q15 A15 Q12 Q11 Q10 Q9 Q8 GND NC Q7 Q6 Q5 Q4 7 6 1 44 A14 40 39 A13 A12 A11 A10 A9 34 GND NC A8 A7 A6 29 28 A5 NC MX27C1024 12 MX27C1024 17 18 23 Q3 Q2 Q1 Q0 OE NC A0 A1 A2 NC CE A3 BLOCK DIAGRAM (MX27C1024) CE PGM OE CONTROL LOGIC OUTPUT BUFFERS Q0~Q15 A0~A15 ADDRESS INPUTS . . . . . . . . Y-DECODER X-DECODER . . . . . . . . Y-DECODER 1M BIT CELL MAXTRIX VCC GND VPP A4 P/N: PM0156 2 REV. 4.6, JAN. 14, 2003 MX27C1100/27C1024 PIN DESCRIPTION(MX27C1100) SYMBOL A0~A15 Q0~Q14 CE OE BYTE/VPP PIN NAME Address Input Data Input/Output Chip Enable Input Output Enable Input Word/Byte Selection /Program Supply Voltage Q15/A-1 VCC GND Q15(Word mode)/LSB addr. (Byte mode) Power Supply Pin (+5V) Ground Pin PIN DESCRIPTION(MX27C1024) SYMBOL A0~A15 Q0~Q15 CE OE PGM VPP VCC GND PIN NAME Address Input Data Input/Output Chip Enable Input Output Enable Input Program Enable Input Program Supply Voltage Power Supply Pin (+5V) Ground Pin TRUTH TABLE OF BYTE FUNCTION(MX27C1100) BYTE MODE(BYTE = GND) CE H L L OE X H L Q15/A-1 X X A-1 input MODE Non selected Non selected Selected Q0-Q7 High Z High Z DOUT SUPPLY CURRENT Standby(ICC2) Operating(ICC1) Operating(ICC1) WORD MODE(BYTE = VCC) CE H L L NOTE : X = H or L OE X H L Q15/A-1 High Z High Z DOUT MODE Non selected Non selected Selected Q0-Q14 High Z High Z DOUT SUPPLY CURRENT Standby(ICC2) Operating(ICC1) Operating(ICC1) P/N: PM0156 3 REV. 4.6, JAN. 14, 2003 MX27C1100/27C1024 FUNCTIONAL DESCRIPTION THE PROGRAMMING OF THE MX27C1100/1024 When the MX27C1100/1024 is delivered, or it is erased, the chip has all 1M bits in the "ONE" or HIGH state. "ZEROs" are loaded into the MX27C1100/1024 through the procedure of programming. For programming, the data to be programmed is applied with 16 bits in parallel to the data pins. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP. When programming an MXIC EPROM, a 0.1uF capacitor is required across VPP and ground to suppress spurious voltage transients which may damage the device. AUTO IDENTIFY MODE The auto identify mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and device type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25 °C ± 5 °C ambient temperature range that is required when programming the MX27C1100/1024. To activate this mode, the programming equipment must force 12.0 ± 0.5 V on address line A9 of the device. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address lines must be held at VIL during auto identify mode. Byte 0 ( A0 = VIL) represents the manufacturer code, and byte 1 (A0 = VIH), the device identifier code. For the MX27C1100/1024, these two identifier bytes are given in the Mode Select Table. All identifiers for manufacturer and device codes will possess odd parity, with the MSB (Q15) defined as the parity bit. VIL(for MX27C1024), OE at VIL, CE at VIH(for MX27C1100)and VPP at its programming voltage. FAST PROGRAMMING The device is set up in the fast programming mode when the programming voltage VPP = 12.75V is applied, with VCC = 6.25 V and PGM = VIL(or OE = VIH) (Algorithm is shown in Figure 1). The programming is achieved by applying a single TTL low level 100us pulse to the PGM input after addresses and data line are stable. If the data is not verified, an additional pulse is applied for a maximum of 25 pulses. This process is repeated while sequencing through each address of the device. When the programming mode is completed, the data in all address is verified at VCC = VPP = 5V ± 10%. READ MODE The MX27C1100/1024 has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the outputs tOE after the falling edge of OE's, assuming that CE has been LOW and addresses have been stable for at least tACC - t OE. PROGRAM INHIBIT MODE Programming of multiple MX27C1100/1024's in parallel with different data is also easily accomplished by using the Program Inhibit Mode. Except for CE and OE, all like inputs of the parallel MX27C1100/1024 may be common. A TTL low-level program pulse applied to an MX27C1100/1024 CE input with VPP = 12.5 ± 0.5 V will program the MX27C1100/1024. A high-level CE input inhibits the other MX27C1100/1024s from being programmed. WORD-WIDE MODE PROGRAM VERIFY MODE Verification should be performed on the programmed bits to determine that they were correctly programmed. The verification should be performed with OE and CE at With BYTE/VPP at VCC ± 0.2V outputs Q0-7 present data Q0-7 and outputs Q8-15 present data Q8-15, after CE and OE are appropriately enabled. P/N: PM0156 4 REV. 4.6, JAN. 14, 2003 MX27C1100/27C1024 BYTE-WIDE MODE With BYTE/VPP at GND ± 0.2V, outputs Q8-15 are tristated. If Q15/A-1 = VIH, outputs Q0-7 present data bits Q8-15. If Q15/A-1 = VIL, outputs Q0-7 present data bits Q0-7. arrays, a 4.7 uF bulk electrolytic capacitor should be used between VCC and GND for each eight devices. The location of the capacitor should be close to where the power supply is connected to the array. STANDBY MODE The MX27C1100/1024 has a CMOS standby mode which reduces the maximum VCC current to 100 uA. It is placed in CMOS standby when CE is at VCC ± 0.3 V. The MX27C1100/1024 also has a TTL-standby mode which reduces the maximum VCC current to 1.5 mA. It is placed in TTL-standby when CE is at VIH. When in standby mode, the outputs are in a high-impedance state, independent of the OE input. TWO-LINE OUTPUT CONTROL FUNCTION To accommodate multiple memory connections, a twoline control function is provided to allow for: 1. Low memory power dissipation, 2. Assurance that output bus contention will not occur. It is recommended that CE be decoded and used as the primary device-selecting function, while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular memory device. SYSTEM CONSIDERATIONS During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. At a minimum, a 0.1 uF ceramic capacitor (high frequency, low inherent inductance) should be used on each device between Vcc and GND to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on EPROM P/N: PM0156 5 REV. 4.6, JAN. 14, 2003 MX27C1100/27C1024 MODE SELECT TABLE (MX27C1024) PINS MODE Read Output Disable Standby (TTL) Standby (CMOS) Program Program Verify Program Inhibit Manufacturer Code(3) Device Code(3) CE VIL VIL VIH VCC±0.3V VIL VIL VIH VIL VIL OE VIL VIH X X VIH VIL X VIL VIL PGM X X X X VIL VIH X X X A0 X X X X X X X VIL VIH A9 X X X X X X X VH VH VPP VCC VCC VCC VCC VPP VPP VPP VCC VCC OUTPUTS DOUT High Z High Z High Z DIN DOUT High Z 00C2H 0115H NOTES:1. VH = 12.0 V ± 0.5 V 2 . X = Either VIH or VIL 3. A1 - A8 = A10 - A15 = VIL(For auto select) 4. See DC Programming Characteristics for VPP voltage during programming. MODE SELECT TABLE (MX27C1100) BYTE/ MODE Read (Word) Read (Upper Byte) Read (Lower Byte) Output Disable Standby Program Program Verify Program Inhibit Manufacturer Code(3) Device Code(3) CE VIL VIL VIL VIL VIH VIL VIH VIH VIL VIL OE VIL VIL VIL VIH X VIH VIL VIH VIL VIL A9 X X X X X X X X VH VH A0 X X X X X X X X VIL VIH Q15/A-1 Q15 Out VIH VIL High Z High Z Q15 In Q15 Out High Z 0B 0B VPP(5) VCC GND GND X X VPP VPP VPP VCC VCC Q8-14 Q8-14 Out High Z High Z High Z High Z Q8-14 In Q8-14 Out High Z 00H 01H Q0-7 Q0-7 Out Q8-15 Out Q0-7 Out High Z High Z Q0-7 In Q0-7 Out High Z C2H 12H NOTES: 1. VH = 12.0V ± 0.5V 2. X = Either VIH or VIL 3. A1 - A8, A10 - A15 = VIL(For auto select) 4. See DC Programming Characteristics for VPP voltages. 5. BYTE/VPP is intended for operation under DC Voltage conditions only. P/N: PM0156 6 REV. 4.6, JAN. 14, 2003 MX27C1100/27C1024 FIGURE 1. FAST PROGRAMMING FLOW CHART START ADDRESS = FIRST LOCATION VCC = 6.25V VPP = 12.75V X=0 PROGRAM ONE 50us PULSE INTERACTIVE SECTION INCREMENT X YES X = 25? NO FAIL VERIFY WORD ? PASS NO INCREMENT ADDRESS LAST ADDRESS FAIL YES VCC = VPP = 5.25V VERIFY SECTION VERIFY ALL WORDS ? FAIL DEVICE FAILED PASS DEVICE PASSED P/N: PM0156 7 REV. 4.6, JAN. 14, 2003 MX27C1100/27C1024 SWITCHING TEST CIRCUITS DEVICE UNDER TEST 1.8K ohm +5V CL 6.2K ohm DIODES = IN3064 OR EQUIVALENT CL = 100 pF including jig capacitance (30pF for 55/70ns parts) SWITCHING TEST WAVEFORMS 2.0V AC driving levels 2.0V TEST POINTS 0.8V OUTPUT 0.8V INPUT AC TESTING: AC driving levels are 2.4V/0.4V . Input pulse rise and fall times are 10uA 4.2 Add industrial grade 70/85/100/120/150ns 40-TSOP(I) 4.3 Cancel ceramic DIP package type 4.4 Cancel "Ultraviolet Erasable" wording in General Description To modify Package Information 4.5 To modify Package Information 4.6 1. To remove 10 x 14mm 40-TSOP package type. 2. To modify 40-PDIP package information Page Date 10/15/1996 06/14/1997 08/08/1997 11/19/1998 FEB/25/2000 AUG/20/2001 NOV/19/2002 JAN/14/2003 P15 P1,2,4,15,16 P1 P15~18 P15~18 P1,2,14,18 P15 P/N: PM0156 18 REV. 4.6, JAN. 14, 2003 MX27C1100/27C1024 MACRONIX INTERNATIONAL CO., LTD. HEADQUARTERS: TEL:+886-3-578-6688 FAX:+886-3-563-2888 EUROPE OFFICE: TEL:+32-2-456-8020 FAX:+32-2-456-8021 JAPAN OFFICE: TEL:+81-44-246-9100 FAX:+81-44-246-9105 SINGAPORE OFFICE: TEL:+65-348-8385 FAX:+65-348-8096 TAIPEI OFFICE: TEL:+886-2-2509-3300 FAX:+886-2-2509-2200 MACRONIX AMERICA, INC. TEL:+1-408-453-8088 FAX:+1-408-453-8488 CHICAGO OFFICE: TEL:+1-847-963-1900 FAX:+1-847-963-1909 http : //www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.