MX23L3254MC-20G

MX23L3254 32M-BIT Low Voltage, Serial Mask ROM Memory with 50MHz SPI Bus Interface FEATURES • • • • 32Mbit of Mask ROM 2.7 to 3.6V Single Supply Voltage SPI Bus Compatible Serial Interface 50MHz Clock Rate (maximum) DESCRIPTION The MX23L3254 is a 32Mbit (4M x 8) Serial Mask ROM accessed by a high speed SPI-compatible bus. PIN CONFIGURATIONS 16-PIN SOP (300 mil) HOLD# VCC NC NC NC NC S# Q 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 C D NC NC NC NC VSS NC PIN DESCRIPTION SYMBOL C D Q S# HOLD# VCC VSS DESCRIPTION Serial Clock Serial Data Input Serial Data Output Chip Select Hold Supply Voltage Ground Note: 1. NC=No Connection 2. See page 16 (onwards) for package dimensions, and how to identify pin-1. ORDER INFORMATION Part No. MX23L3254MC-20 MX23L3254MC-20G MX23L3254MI-20G Speed 20ns 20ns 20ns Package 16-SOP 16-SOP 16-SOP Remark Pb-free Pb-free (Industrial Grade) Note: * Industrial grade operating temperature: -25 ~ 85 ° C Commercial grade operating temperature: 0 ~ 70 ° C P/N: PM1167 1 REV. 1.2, JUN. 08, 2005 MX23L3254 MEMORY ORGANIZATION The memory is organized as: - 4M bytes (8 bits each) BLOCK DIAGRAM HOLD# Control Logic S# C D Q I/O Shift Register Address Register and Counter 256 Byte Data Buffer Y Decoder Size of the read-only memory area X Decoder P/N: PM1167 2 REV. 1.2, JUN. 08, 2005 MX23L3254 SIGNAL DESCRIPTION Serial Data Output (Q). This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). Serial Data Input (D). This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (C). Serial Clock (C). This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C). Chip Select (S#). When this input signal is High, the device is deselected. Driving Chip Select (S#) Low enables the device, placing it in the active power mode. After Power-up, a falling edge on Chip Select (S#) is required prior to the start of any instruction. Hold (HOLD#). The Hold (HOLD#) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don't Care. To start the Hold condition, the device must be selected, with Chip Select (S#) driven Low. P/N: PM1167 3 REV. 1.2, JUN. 08, 2005 MX23L3254 SPI MODES These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: - CPOL=0, CPHA=0 - CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 2, is the clock polarity when the bus master is in Stand-by mode and not transferring data: - C remains at 0 for (CPOL=0, CPHA=0) - C remains at 1 for (CPOL=1, CPHA=1) Figure 1. Bus Master and Memory Devices on the SPI Bus SDO SPI Interface with (CPOL, CPHA) = (0, 0) or (1, 1) SDI SCK CQD Bus Master (ST6, ST7, ST9, ST10, Others) SPI Memory Device CS3 CS2 CS1 S# HOLD# S# HOLD# S# HOLD# SPI Memory Device SPI Memory Device CQD CQD Note: 1. Hold (HOLD#) signals should be driven, High or Low as appropriate. Figure 2. SPI Modes Supported CPOL CPHA C 0 0 1 1 C D MSB Q MSB P/N: PM1167 4 REV. 1.2, JUN. 08, 2005 MX23L3254 OPERATING FEATURES Active Power, Stand-by Power When Chip Select (S#) is Low, the device is enabled, and in the Active Power mode. When Chip Select (S#) is High, the device is disabled, but could remain in the Active Power mode until all internal cycles have completed. The device then goes in to the Stand-by Power mode. The device consumption drops to ICC1 . The Hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (C) being Low (as shown in Figure 3). The Hold condition ends on the rising edge of the Hold (HOLD#) signal, provided that this coincides with Serial Clock (C) being Low. If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide with Serial Clock (C) being Low, the Hold condition ends after Serial Clock (C) next goes Low. (This is shown in Figure 2). During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don't Care. Normally, the device is kept selected, with Chip Select (S#) driven Low, for the whole duration of the Hold condition. This is to ensure that the state of the internal logic remains unchanged from the moment of entering the Hold condition. If Chip Select (S#) goes High while the device is in the Hold condition, this has the effect of resetting the internal logic of the device. To restart communication with the device, it is necessary to drive Hold (HOLD#) High, and then to drive Chip Select (S#) Low. This prevents the device from going back to the Hold condition. Protection Modes The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the MX23L3254 boasts the following data protection mechanisms: - Power-On Reset and an internal timer (tPUW) can provide protection against inadvertant changes while the power supply is outside the operating specification. Hold Condition The Hold (HOLD#) signal is used to pause any serial communications with the device without resetting the clocking sequence. To enter the Hold condition, the device must be selected, with Chip Select (S#) Low. Figure 3. Hold Condition Activation (for data output only) C HOLD# Q2 Q Q0 Q1 Q2 Q3 Q4 Q5 C HOLD# Q2 Q Q0 Q1 Q2 Q3 Q4 Q5 Q6 P/N: PM1167 5 REV. 1.2, JUN. 08, 2005 MX23L3254 INSTRUCTIONS All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select (S#) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data Input (D), each bit being latched on the rising edges of Serial Clock (C). The instruction set is listed in Table 1. Every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read), the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (S#) can be driven High after any bit of the data-out sequence is being shifted out. Table 1. Instruction Set Instruction READ FAST_READ Description Read Data Bytes Read Data Bytes at Higher Speed One-byte Instruction Code 0000 0011 0000 1011 03h 0Bh Address Bytes 3 3 Dummy Bytes 0 1 Data Bytes 1 to ∞ 1 to ∞ P/N: PM1167 6 REV. 1.2, JUN. 08, 2005 MX23L3254 Figure 4. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence S# 0 C Instruction 24-Bit Address 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 D High Impedance Q 23 22 21 MSB 3 2 1 0 Data Out 1 7 6 5 4 3 2 1 0 Data Out 2 7 MSB Note: 1. Address bits A23,A22 is Don't Care. Read Data Bytes (READ) The device is first selected by driving Chip Select (S#) Low. The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, is shifted out on Serial Data Output (Q), each bit being shifted out, at a maximum frequency fR, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 4. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction.When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S#) High. Chip Select (S#) can be driven High at any time during data output. P/N: PM1167 7 REV. 1.2, JUN. 08, 2005 MX23L3254 Figure 5. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence and Data-Out Sequence S# 0 C Instruction 24 BIT ADDRESS 1 2 3 4 5 6 7 8 9 10 28 29 30 31 D 23 22 21 3 2 1 0 Q High Impedance S# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Dummy Byte D 7 6 5 4 3 2 1 0 DATA OUT 1 DATA OUT 2 1 0 7 MSB 6 5 4 3 2 1 0 7 MSB Q 7 MSB 6 5 4 3 2 Read Data Bytes at Higher Speed (FAST_READ) The device is first selected by driving Chip Select (S#) Low. The instruction code for the Read Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, is shifted out on Serial Data Output (Q), each bit being shifted out, at a maximum frequency fC, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 5. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving Chip Select (S#) High. Chip Select (S#) can be driven High at any time during data output. P/N: PM1167 8 REV. 1.2, JUN. 08, 2005 MX23L3254 POWER-UP AND POWER-DOWN At Power-up and Power-down, the device must not be selected (that is Chip Select (S#) must follow the voltage applied on VCC ) until VCC reaches the correct value: - VCC(min) at Power-up, and then for a further delay of tVSL - VSS at Power-down Usually a simple pull-up resistor on Chip Select (S#) can be used to insure safe and proper Power-up and Powerdown. To avoid data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less than the POR threshold value, VWI -- all operations are disabled, and the device does not respond to any instruction. These values are specified in Table 2. If the delay, tVSL, has elapsed, after VCC has risen above VCC (min), the device can be selected for READ instructions even if the tPUW delay is not yet fully elapsed. At Power-up, the device is in the following state: - The device is in the Standby mode. Normal precautions must be taken for supply rail decoupling, to stablise the VCC feed. Each device in a system should have the VCC rail decoupled by a suitable capacitor close to the package pins. (Generally, this capacitor is of the order of 0.1uF). At Power-down, when VCC drops from the operating voltage, to below the POR threshold value, VWI , all operations are disabled and the device does not respond to any instruction. Figure 6. Power-up Timing VCC VCC(max) Chip Selection Not Allowed VCC(min) Reset State of the Device VWI tPUW tVSL Read Access allowed Device fully accessible time P/N: PM1167 9 REV. 1.2, JUN. 08, 2005 MX23L3254 Table 2. Power-Up Timing Symbol tVSL1 VCC(min) to S# low Parameter Min. 30 Max. Unit us Note: 1. These parameters are characterized only. MAXIMUM RATING Stressing the device above the rating listed in the"Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Table 3. Absolute Maximum Ratings Symbol TSTG TLEAD VIO VCC VESD Storage Temperature Lead Temperature during Soldering 1 Input and Output Voltage (with respect to Ground) Supply Voltage Electrostatic Discharge Voltage (Human Body model) 3 - 0.6 - 0.6 - 2000 Parameter Min. - 65 Max. 150 260 2 4.0 4.0 2000 Unit ˚C ˚C V V V Note: 1. Compliant with the ECOPACK ® 7191395 specifiication for lead-free soldering processes 2. Not exceeding 250˚C for more than 30 seconds, and peaking at 260˚C 3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω) P/N: PM1167 10 REV. 1.2, JUN. 08, 2005 MX23L3254 DC AND AC PARAMETERS This section summarizes the operating and mea-surement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measurement Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 4. Operating Conditions Symbol VCC TA Supply Voltage Ambient Operating Temperature Parameter Min. 2.7 -25 Max. 3.6 85 Unit V ˚C Table 5. AC Measurement Conditions Symbol CL Load Capacitance Input Rise and Fall Times Input Pulse Voltages Input Timing Reference Voltages Output Timing Reference Voltages Note: 1. Output Hi-Z is defined as the point where data out is no longer driven. Parameter Min. 30 Max. Unit pF 5 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC V CC / 2 ns V V V Figure 7. AC Measurement I/O Waveform Input Levels 0.8VCC Input and Output Timing Reference Levels 0.7VCC 0.5VCC 0.3VCC 0.2VCC Table 6. Capacitance Symbol COUT CIN Parameter Output Capacitance (Q) Input Capacitance (other pins) Test Condition VOUT = 0V VIN = 0V Min. Max. 8 6 Unit pF pF Note: Sampled only, not 100% tested, at TA=25˚C and a frequency of 20 MHz. P/N: PM1167 11 REV. 1.2, JUN. 08, 2005 MX23L3254 Table 7. DC Characteristics Symbol ILI ILO ICC1 Parameter Input Leakage Current Output Leakage Current Standby Current S # = VCC, VIN = VSS or VCC C = 0.1VCC / 0.9.VCC at 50MHz, Q = open ICC2 Operating Current (READ) C = 0.1VCC / 0.9.VCC at 20MHz, Q = open Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 1.6mA IOH = -100 uA VCC- 0.2 - 0.5 0.7VCC 4 0.3VCC VCC+0.4 0.4 mA V V V V Test Condition (in addition to those in Table 8) Min. Max. ±2 ±2 50 8 Unit uA uA uA mA VIL VIH VOL VOH P/N: PM1167 12 REV. 1.2, JUN. 08, 2005 MX23L3254 Table 8. AC Characteristics Test conditions specified in Table 4 and Table 5 Symbol fC fR tCH 1 tCL 1 tCLCH 2 tCHCL 2 tSLCH tCHSL tDVCH tCHDX tCHSH tSHCH tSHSL tSHQZ 2 tCLQV tCLQX tHLCH tCHHH tHHCH tCHHL tHHQX 2 tHLQZ 2 tLZ tHZ tCSH tDIS tV tHO tDSU tDH tCSS tCLH tCLL Alt. fC Parameter Clock Frequency for the following instructions: FAST_READ Clock Frequency for READ instructions Clock High Time Clock Low Time Clock Rise Time3 (peak to peak) Clock Fall Time3 (peak to peak) S# Active Setup Time (relative to C) S# Not Active Hold Time (relative to C) Data In Setup Time Data In Hold Time S# Active Hold Time (relative to C) S# Not Active Setup Time (relative to C) S# Deselect Time Output Disable Time Clock Low to Output Valid Output Hold Time HOLD# Setup Time (relative to C) HOLD# Hold Time (relative to C) HOLD Setup Time (relative to C) HOLD Hold Time (relative to C) HOLD to Output Low-Z HOLD# to Output High-Z 0 5 5 5 5 8 8 Min. D.C. D.C. 9 9 0.1 0.1 5 5 2 5 5 5 100 8 8 Typ. Max. 50 20 Unit MHz MHz ns ns V/ns V/ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: 1. tCH + tCL must be greater than or equal to 1/ fC 2. Value guaranteed by characterization, not 100% tested in production. 3. Expressed as a slew-rate. P/N: PM1167 13 REV. 1.2, JUN. 08, 2005 MX23L3254 Figure 8. Serial Input Timing tSHSL S# tCHSL C tDVCH tCHDX D MSB IN tCLCH LSB IN tCHCL tSLCH tCHSH tSHCH Q High Impedance Figure 9. Hold Timing S# tHLCH tCHHL C tCHHH tHLQZ Q tHHQX tHHCH D HOLD# P/N: PM1167 14 REV. 1.2, JUN. 08, 2005 MX23L3254 Figure 10. Output Timing S# tCH C tCLQV tCLQX Q tQLQH tQHQL D ADDR.LSB IN tCLQV tCLQX tCL tSHQZ LSB OUT P/N: PM1167 15 REV. 1.2, JUN. 08, 2005 MX23L3254 PACKAGE INFORMATION P/N: PM1167 16 REV. 1.2, JUN. 08, 2005 MX23L3254 REVISION HISTORY Revision 1.0 1.1 1.2 Description 1. Removed "Preliminary" on page 1 1. Added "Industrial Grade" 1. Output timing waveform description modified Page P1 P1,11 P15 Date MAR/02/2005 MAR/09/2005 JUN/08/2005 P/N: PM1167 17 REV. 1.2, JUN. 08, 2005 M X23L3254 MACRONIX INTERNATIONAL CO., LTD. Headquarters: TEL:+886-3-578-6688 FAX:+886-3-563-2888 Europe Office : TEL:+32-2-456-8020 FAX:+32-2-456-8021 Hong Kong Office : TEL:+86-755-834-335-79 FAX:+86-755-834-380-78 Japan Office : Kawasaki Office : TEL:+81-44-246-9100 FAX:+81-44-246-9105 Osaka Office : TEL:+81-6-4807-5460 FAX:+81-6-4807-5461 Singapore Office : TEL:+65-6346-5505 FAX:+65-6348-8096 Taipei Office : TEL:+886-2-2509-3300 FAX:+886-2-2509-2200 MACRONIX AMERICA, INC. TEL:+1-408-262-8887 FAX:+1-408-262-8810 http : //www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.