MX25L12835E
MX25L12835E
HIGH PERFORMANCE
SERIAL FLASH SPECIFICATION
P/N: PM1676
1
REV. 1.3, MAY 28, 2012
MX25L12835E
Contents
1. FEATURES......................................................................................................................................................... 4
2. GENERAL DESCRIPTION................................................................................................................................ 6
Table 1. Additional Features ...................................................................................................................6
3. PIN CONFIGURATION....................................................................................................................................... 7
4. PIN DESCRIPTION............................................................................................................................................. 7
5. BLOCK DIAGRAM.............................................................................................................................................. 8
6. DATA PROTECTION........................................................................................................................................... 9
Table 2. Protected Area Sizes...............................................................................................................10
Table 3. 4K-bit Secured OTP Definition................................................................................................10
7. MEMORY ORGANIZATION...............................................................................................................................11
Table 4. Memory Organization.............................................................................................................. 11
8. DEVICE OPERATION....................................................................................................................................... 12
9. HOLD FEATURE............................................................................................................................................... 13
10. COMMAND DESCRIPTION............................................................................................................................ 14
Table 5. Command Sets........................................................................................................................14
10-1. Write Enable (WREN)...........................................................................................................................17
10-2. Write Disable (WRDI)............................................................................................................................18
10-3. Read Identification (RDID)....................................................................................................................19
10-4. Read Status Register (RDSR)..............................................................................................................20
10-5. Write Status Register (WRSR)..............................................................................................................22
Table 6. Protection Modes.....................................................................................................................23
10-6. Read Data Bytes (READ).....................................................................................................................25
10-7. Read Data Bytes at Higher Speed (FAST_READ)...............................................................................26
10-8. Dual Read Mode (DREAD)...................................................................................................................27
10-9. 2 x I/O Read Mode (2READ)................................................................................................................28
10-10. Quad Read Mode (QREAD).................................................................................................................29
10-11. 4 x I/O Read Mode (4READ)................................................................................................................30
10-12. Performance Enhance Mode................................................................................................................31
10-13. Performance Enhance Mode Reset (FFh)............................................................................................31
10-14. Burst Read............................................................................................................................................34
10-15. Sector Erase (SE).................................................................................................................................35
10-16. Block Erase (BE)..................................................................................................................................36
10-17. Block Erase (BE32K)............................................................................................................................37
10-18. Chip Erase (CE)....................................................................................................................................38
10-19. Page Program (PP)..............................................................................................................................39
10-20. 4 x I/O Page Program (4PP).................................................................................................................40
10-21. Continuously program mode (CP mode)..............................................................................................43
10-22. Deep Power-down (DP)........................................................................................................................45
10-23. Release from Deep Power-down (RDP), Read Electronic Signature (RES)........................................46
10-24. Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4)......................................48
10-25. ID Read.................................................................................................................................................49
Table 7. ID Definitions ..........................................................................................................................49
10-26. Enter Secured OTP (ENSO).................................................................................................................49
10-27. Exit Secured OTP (EXSO)....................................................................................................................49
10-28. Read Security Register (RDSCUR)......................................................................................................50
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REV. 1.3, MAY 28, 2012
MX25L12835E
Table 8. Security Register Definition.....................................................................................................51
10-29. Write Security Register (WRSCUR)......................................................................................................52
10-30. Write Protection Selection (WPSEL).....................................................................................................52
10-31. Single Block Lock/Unlock Protection (SBLK/SBULK)...........................................................................56
10-32. Read Block Lock Status (RDBLOCK)...................................................................................................59
10-33. Gang Block Lock/Unlock (GBLK/GBULK)............................................................................................60
10-34. Clear SR Fail Flags (CLSR)..................................................................................................................61
10-35. Enable SO to Output RY/BY# (ESRY)..................................................................................................61
10-36. Disable SO to Output RY/BY# (DSRY).................................................................................................61
10-37. No Operation (NOP).............................................................................................................................62
10-38. Software Reset (Reset-Enable (RSTEN) and Reset (RST))................................................................62
10-39. Read SFDP Mode (RDSFDP)...............................................................................................................63
Table 9. Signature and Parameter Identification Data Values ..............................................................64
Table 10. Parameter Table (0): JEDEC Flash Parameter Tables..........................................................65
Table 11. Parameter Table (1): Macronix Flash Parameter Tables........................................................67
11. POWER-ON STATE........................................................................................................................................ 69
12. ELECTRICAL SPECIFICATIONS................................................................................................................... 70
12-1. ABSOLUTE MAXIMUM RATINGS........................................................................................................70
12-2. CAPACITANCE TA = 25°C, f = 1.0 MHz...............................................................................................70
Table 12. DC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~
3.6V) .....................................................................................................................................................72
Table 13. AC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~
3.6V) .....................................................................................................................................................73
13. TIMING ANALYSIS......................................................................................................................................... 75
13-1. RESET..................................................................................................................................................77
Table 14. Reset Timing..........................................................................................................................77
Table 15. Power-Up Timing ..................................................................................................................78
13-2. INITIAL DELIVERY STATE...................................................................................................................78
14. OPERATING CONDITIONS............................................................................................................................ 79
15. ERASE AND PROGRAMMING PERFORMANCE......................................................................................... 81
16. DATA RETENTION......................................................................................................................................... 81
17. LATCH-UP CHARACTERISTICS................................................................................................................... 81
18. ORDERING INFORMATION........................................................................................................................... 82
19. PART NAME DESCRIPTION.......................................................................................................................... 83
20. PACKAGE INFORMATION............................................................................................................................. 84
21. REVISION HISTORY ...................................................................................................................................... 86
P/N: PM1676
3
REV. 1.3, MAY 28, 2012
MX25L12835E
128M-BIT [x 1/x 2/x 4] CMOS MXSMIOTM (SERIAL MULTI I/O) FLASH MEMORY
1. FEATURES
GENERAL
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
• 134,217,728 x 1 bit structure or 67,108,864 x 2 bits (two I/O mode) structure or 33,554,432 x 4 bits (four I/O
mode) structure
• 4096 Equal Sectors with 4K bytes each
- Any Sector can be erased individually
• 512 Equal Blocks with 32K bytes each
- Any Block can be erased individually
• 256 Equal Blocks with 64K bytes each
- Any Block can be erased individually
• Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
VCC = 2.7~3.6V
- Normal read
- 50MHz
- Fast read
- 1 I/O: 104MHz with 8 dummy cycles
- 2 I/O: 70MHz with 4 dummy cycles for 2READ instruction; 70MHz with 8 dummy cycles for DREAD
instruction
- 4 I/O: 70MHz with 6 dummy cycles for 4READ instruction; 70MHz with 8 dummy cycles for QREAD
instruction
- Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)
- Byte program time: 12us (typical)
- 8/16/32/64 byte Wrap-Around Burst Read Mode
- Continuously Program mode (automatically increase address under word program mode)
- Fast erase time: 60ms (typ.)/sector (4K-byte per sector) ; 0.7s(typ.) /block (64K-byte per block); 80s(typ.) /
chip
• Low Power Consumption
- Low active read current: 19mA(max.) at 104MHz, 15mA(max.) at 66MHz and 10mA(max.) at 33MHz
- Low active programming current: 25mA (max.)
- Low active erase current: 25mA (max.)
- Low standby current: 100uA (max.)
- Deep power down current: 40uA (max.)
• Minimum 100,000 erase/program cycles
• 20 years data retention
P/N: PM1676
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REV. 1.3, MAY 28, 2012
MX25L12835E
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- BP0-BP3 block group protect
- Flexible individual block protect when OTP WPSEL=1
- Additional 4K bits secured OTP for unique identifier
• Auto Erase and Auto Program Algorithms
- Automatically erases and verifies data at selected sector
- Automatically programs and verifies data at selected page by an internal algorithm that automatically times
the program pulse width (Any page to be programmed should have page in the erased state first.)
• Status Register Feature
• Electronic Identification
- JEDEC 1-byte Manufacturer ID and 2-byte Device ID
- RES command for 1-byte Device ID
- The REMS,REMS2, REMS4 commands for 1-byte Manufacturer ID and 1-byte Device ID
• Support Serial Flash Discoverable Parameters (SFDP) mode
HARDWARE FEATURES
• SCLK Input
- Serial clock input
• SI/SIO0
- Serial Data Input or Serial Data Input/Output for 2 x I/O mode and 4 x I/O mode
• SO/SIO1
- Serial Data Output or Serial Data Input/Output for 2 x I/O mode and 4 x I/O mode
• WP#/SIO2
- Hardware write protection or serial data Input/Output for 4 x I/O mode
• HOLD#/SIO3
- To pause the device without deselecting the device or serial data Input/Output for 4 x I/O mode
• RESET#
- Hardware Reset Pin
• PACKAGE
- 16-pin SOP (300mil)
- 8-WSON (8 x 6mm)
- All devices are RoHS Compliant
P/N: PM1676
5
REV. 1.3, MAY 28, 2012
MX25L12835E
2. GENERAL DESCRIPTION
MX25L12835E is 134,217,728 bits serial Flash memory, which is configured as 16,777,216 x 8 internally. When it
is in two or four I/O mode, the structure becomes 67,108,864 bits x 2 or 33,554,432 bits x 4. The MX25L12835E
features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three
bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the
device is enabled by CS# input.
MX25L12835E, MXSMIOTM (Serial Multi I/O) flash memory, provides sequential read operation on whole chip
and multi-I/O features.
When it is in dual I/O mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input
and data output. When it is in quad I/O mode, the SI pin, SO pin, WP# pin and HOLD# pin become SIO0 pin,
SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data Input/Output.
After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the
specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis, or word basis for Continuously Program mode, and erase command is executed on sector (4K-byte),
block (32K-byte/64K-byte), or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status
read command can be issued to detect completion status of a program or erase operation via WIP bit.
When the device is not in operation and CS# is high, it is put in standby mode and draws less than 100uA DC
current.
The MX25L12835E utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles.
Table 1. Additional Features
Additional
Features
Part
Name
MX25L12835E
Protection and Security
Flexible or
4K-bit
Individual block
secured
(or sector)
OTP
protection
V
V
Read Performance
1 I/O Read
(104 MHz)
2 I/O Read
(70 MHz)
4 I/O Read
(70 MHz)
Dual Read
(70 MHz)
Quad Read
(70 MHz)
V
V
V
V
V
Additional
Features
Part
Name
MX25L12835E
Identifier
RES
REMS
REMS2
REMS4
RDID
(command: AB hex) (command: 90 hex) (command: EF hex) (command: DF hex) (command: 9F hex)
17 (hex)
C2 17 (hex)
C2 17 (hex)
P/N: PM1676
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C2 17 (hex)
C2 20 18 (hex)
REV. 1.3, MAY 28, 2012
MX25L12835E
3. PIN CONFIGURATION
4. PIN DESCRIPTION
SYMBOL
DESCRIPTION
CS#
Chip Select
Serial Data Input (for 1xI/O)/ Serial
SI/SIO0 Data Input & Output (for 2xI/O or 4xI/O
mode)
Serial Data Output (for 1xI/O)/Serial
SO/SIO1 Data Input & Output (for 2xI/O or 4xI/O
mode)
SCLK
Clock Input
Write protection: connect to GND or
WP#/SIO2 Serial Data Input & Output (for 4xI/O
mode)
To pause the device without deselecting
HOLD#/
the device or Serial data Input/Output
SIO3
for 4 x I/O mode
RESET# Hardware Reset Pin
VCC
+ 3.3V Power Supply
GND
Ground
NC
No Connection
16-PIN SOP (300mil)
HOLD#/SIO3
VCC
RESET#
NC
NC
NC
CS#
SO/SIO1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SCLK
SI/SIO0
NC
NC
NC
NC
GND
WP#/SIO2
8-WSON (8x6mm)
CS#
SO/SIO1
WP#/SIO2
GND
1
2
3
4
8
7
6
5
VCC
HOLD#/SIO3
SCLK
SI/SIO0
Note:
1. The RESET# pin function is only available on
16-SOP package.
2. The HOLD# and RESET# pins are internal pull
high.
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REV. 1.3, MAY 28, 2012
MX25L12835E
5. BLOCK DIAGRAM
X-Decoder
Address
Generator
Memory Array
Page Buffer
SI/SIO0
Data
Register
Y-Decoder
SRAM
Buffer
Sense
Amplifier
CS#
WP#/SIO2
HOLD#/SIO3
RESET#
SCLK
Mode
Logic
State
Machine
HV
Generator
Clock Generator
Output
Buffer
SO/SIO1
P/N: PM1676
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REV. 1.3, MAY 28, 2012
MX25L12835E
6. DATA PROTECTION
MX25L12835E is designed to offer protection against accidental erasure or programming caused by spurious
system level signals that may exist during power transition. During power up the device automatically resets the
state machine in the standby mode. In addition, with its control register architecture, alteration of the memory
contents only occurs after successful completion of specific command sequences. The device also incorporates
several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or
system noise.
• Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
other command to change data. The WEL bit will return to reset stage under following situation:
- Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP, 4PP) command completion
- Continuously Program mode (CP) instruction completion
- Sector Erase (SE) command completion
- Block Erase (BE, BE32K) command completion
- Chip Erase (CE) command completion
- Single Block Lock/Unlock (SBLK/SBULK) instruction completion
- Gang Block Lock/Unlock (GBLK/GBULK) instruction completion
• Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from
writing all commands except Release from Deep Power Down mode command (RDP) and Read Electronic
Signature command (RES).
I. Block lock protection
- The Software Protected Mode (SPM) uses (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected as read only. The protected area definition is shown as table of "Table 2. Protected Area Sizes", the
protected areas are more flexible which may protect various areas by setting value of BP0-BP3 bits.
- The Hardware Protected Mode (HPM) uses WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and SRWD
bit. If the system goes into four I/O mode, the feature of HPM will be disabled.
- MX25L12835E provides individual block (or sector) write protect & unprotect. User may enter the mode with
WPSEL command and conduct individual block (or sector) write protect with SBLK instruction, or SBULK for
individual block (or sector) unprotect. Under the mode, user may conduct whole chip (all blocks) protect with
GBLK instruction and unlock the whole chip with GBULK instruction.
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REV. 1.3, MAY 28, 2012
MX25L12835E
Table 2. Protected Area Sizes
Status bit
BP3
BP2
BP1
BP0
0
0
0
0
0 (none)
0
0
0
1
1 (2 blocks, block 254th-255th)
0
0
1
0
2 (4 blocks, block 252nd-255th)
0
0
1
1
3 (8 blocks, block 248th-255th)
0
1
0
0
4 (16 blocks, block 240th-255th)
0
1
0
1
5 (32 blocks, block 224th-255th)
0
1
1
0
6 (64 blocks, block 192nd-255th)
0
1
1
1
7 (128 blocks, block 128th-255th)
1
0
0
0
8 (256 blocks, all)
1
0
0
1
9 (256 blocks, all)
1
0
1
0
10 (256 blocks, all)
1
0
1
1
11 (256 blocks, all)
1
1
0
0
12 (256 blocks, all)
1
1
0
1
13 (256 blocks, all)
1
1
1
0
14 (256 blocks, all)
1
1
1
1
15 (256 blocks, all)
Note: The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP3, BP2, BP1,
BP0) are 0.
II. Additional 4K-bit secured OTP for unique identifier: to provide 4K-bit One-Time Program area for setting
device unique serial number - Which may be set by factory or system maker.
- Security register bit 0 indicates whether the chip is locked by factory or not.
- To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with ENSO command), and
going through normal program procedure, and then exiting 4K-bit secured OTP mode by writing EXSO command.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register)
command to set customer lock-down bit1 as "1". Please refer to table of "Table 8. Security Register Definition" for security register bit definition and table of "Table 3. 4K-bit Secured OTP Definition" for address range
definition.
Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit Secured
OTP mode, array access is not allowed.
Table 3. 4K-bit Secured OTP Definition
Address range
Size
Standard Factory Lock
xxx000~xxx00F
128-bit
ESN (electrical serial number)
xxx010~xxx1FF
3968-bit
N/A
P/N: PM1676
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Customer Lock
Determined by customer
REV. 1.3, MAY 28, 2012
MX25L12835E
7. MEMORY ORGANIZATION
Table 4. Memory Organization
Block(64K-byte)
Block(32K-byte)
Sector
254
508
individual block
lock/unlock unit:64K-byte
507
253
506
FF8FFFh
4087
FF7000h
FF7FFFh
…
individual 16 sectors
lock/unlock unit:4K-byte
4080
FF0000h
FF0FFFh
4079
FEF000h
FEFFFFh
…
509
FF8000h
4072
FE8000h
FE8FFFh
4071
FE7000h
FE7FFFh
…
510
4088
4064
FE0000h
FE0FFFh
4063
FDF000h
FDFFFFh
…
255
FFFFFFh
4056
FD8000h
FD8FFFh
4055
FD7000h
FD7FFFh
4048
FD0000h
FD0FFFh
47
02F000h
02FFFFh
…
511
Address Range
FFF000h
…
4095
1
2
1
0
0
027FFFh
…
028FFFh
027000h
32
020000h
020FFFh
31
01F000h
01FFFFh
…
3
028000h
39
24
018000h
018FFFh
23
017000h
017FFFh
…
4
individual block
lock/unlock unit:64K-byte
40
16
010000h
010FFFh
15
00F000h
00FFFFh
…
2
8
008000h
008FFFh
7
007000h
007FFFh
000000h
000FFFh
individual 16 sectors
lock/unlock unit:4K-byte
…
5
…
individual block
lock/unlock unit:64K-byte
0
P/N: PM1676
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REV. 1.3, MAY 28, 2012
MX25L12835E
8. DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation.
2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby
mode until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z.
3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until
next CS# rising edge.
4. For standard single data rate serial mode, input data is latched on the rising edge of Serial Clock(SCLK) and
data shifts out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as Figure 1.
5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, RDSFDP, 2READ, DREAD,
4READ, QREAD, RDBLOCK, RES, REMS, REMS2, and REMS4 the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE, BE32K, HPM, CE, PP, CP, 4PP, RDP, DP, WPSEL, SBLK,
SBULK, GBLK, GBULK, ENSO, EXSO, WRSCUR, ESRY, DSRY and CLSR the CS# must go high exactly at
the byte boundary; otherwise, the instruction will be rejected and not executed.
6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglected and not affect the current operation of Write Status Register, Program, Erase.
Figure 1. Serial Modes Supported (for Normal Serial mode)
CPOL
CPHA
shift in
(Serial mode 0)
0
0
SCLK
(Serial mode 3)
1
1
SCLK
SI
shift out
MSB
SO
MSB
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while
not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial
mode is supported.
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REV. 1.3, MAY 28, 2012
MX25L12835E
9. HOLD FEATURE
HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop
the operation of write status register, programming, or erasing in progress.
The operation of HOLD requires Chip Select (CS#) keeping low and starts on falling edge of HOLD# pin signal
while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not
start until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while
Serial Clock(SCLK) signal is being low( if Serial Clock signal is not being low, HOLD operation will not end until
Serial Clock being low).
Figure 2. Hold Condition Operation
CS#
SCLK
HOLD#
Hold
Condition
(standard)
Hold
Condition
(non-standard)
The Serial Data Output (SO) is high impedance, both Serial Data Input (SI) and Serial Clock (SCLK) are don't
care during the HOLD operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal
logic of the device. To re-start communication with chip, the HOLD# must be at high and CS# must be at low.
Note: The HOLD feature is disabled during Quad I/O mode.
P/N: PM1676
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REV. 1.3, MAY 28, 2012
MX25L12835E
10. COMMAND DESCRIPTION
Table 5. Command Sets
Read Commands
I/O
Read Mode
1
SPI
1
SPI
1
SPI
Command
(byte)
READ
(normal read)
FAST READ (fast
read data)
RDSFDP
50
104
Clock rate
(MHz)
1st byte
2nd byte
3rd byte
4th byte
5th byte
Action
I/O
Read Mode
Command
(byte)
Clock rate
(MHz)
1st byte
2nd byte
3rd byte
4th byte
5th byte
Action
03 (hex)
AD1(8)
AD2(8)
AD3(8)
0B (hex)
AD1(8)
AD2(8)
AD3(8)
Dummy(8)
n bytes read out n bytes read out
until CS# goes
until CS# goes
high
high
4
SPI
4READ
(4 x I/O read
command) Note1
2
SPI
2READ
(2 x I/O read
command) Note1
2
SPI
DREAD
(1I / 2O read
command)
4
SPI
104
70
70
54
5A (hex)
AD1(8)
AD2(8)
AD3(8)
Dummy(8)
Read SFDP
mode
BB (hex)
AD1(4)
AD2(4)
AD3(4)
Dummy(4)
n bytes read out
by 2 x I/O until
CS# goes high
3B (hex)
AD1(8)
AD2(8)
AD3(8)
Dummy(8)
E7 (hex)
AD1(2)
AD2(2)
AD3(2)
Dummy(4)
Quad I/O read
with 4 dummy
cycles
W4READ
4
SPI
QREAD
70
70
EB (hex)
AD1(2)
AD2(2)
AD3(2)
Dummy(6)
Quad I/O read
with 6 dummy
cycles
6B (hex)
AD1(8)
AD2(8)
AD3(8)
Dummy(8)
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REV. 1.3, MAY 28, 2012
MX25L12835E
Other Commands
Command
(byte)
1st byte
2nd byte
3rd byte
4th byte
Action
Command
(byte)
1st byte
2nd byte
3rd byte
4th byte
Action
Command
(byte)
1st byte
2nd byte
3rd byte
4th byte
Action
WREN
WRDI
RDSR (read WRSR (write
4PP (quad
SE
BE 32K (block
(write enable) (write disable) status register) status register) page program) (sector erase) erase 32KB)
06 (hex)
04 (hex)
05 (hex)
01 (hex)
Values
38 (hex)
AD1
AD2
AD3
sets the (WEL) resets the to read out the to write new quad input to
write enable
(WEL) write values of the values of the program the
latch bit
enable latch status register status register selected page
bit
BE (block
erase 64KB)
CE (chip
erase)
PP (page
program)
CP (page
program)
D8 (hex)
60 or C7 (hex)
02 (hex)
AD (hex)
AD1
AD1
AD1
AD2
AD2
AD2
AD3
AD3
AD3
to erase the to erase whole to program the continuously
selected 64KB
chip
selected page
program
block
whole chip,
the address is
automatically
increase
REMS (read
electronic
manufacturer
& device ID)
AB (hex)
90 (hex)
x
x
x
x
x
ADD (Note 2)
to read out
output the
1-byte Device Manufacturer
ID
ID & Device ID
RES (read
electronic ID)
REMS2 (read
electronic
manufacturer
& device ID)
EF (hex)
x
x
ADD
output the
Manufacturer
ID & Device ID
DP (Deep
power down)
B9 (hex)
enters deep
power down
mode
20 (hex)
AD1
AD2
AD3
to erase the
selected
sector
52 (hex)
AD1
AD2
AD3
to erase the
selected 32KB
block
RDP (Release
RDID
from deep (read identificpower down)
ation)
AB (hex)
9F (hex)
release from
deep power
down mode
outputs
JEDEC
ID: 1-byte
Manufacturer
ID & 2-byte
Device ID
REMS4 (read
electronic
ENSO (enter
manufacturer secured OTP)
& device ID)
DF (hex)
B1 (hex)
x
x
ADD
output the
to enter the
Manufacturer 4K-bit secured
ID & device ID OTP mode
P/N: PM1676
15
REV. 1.3, MAY 28, 2012
MX25L12835E
Command
(byte)
1st byte
2nd byte
3rd byte
4th byte
Action
RDSCUR
WRSCUR
EXSO (exit
SBLK (single SBULK (single
(read security (write security
secured OTP)
block lock
block unlock)
register)
register)
C1 (hex)
2B (hex)
2F (hex)
36 (hex)
39 (hex)
AD1
AD1
AD2
AD2
AD3
AD3
to exit the 4K- to read value to set the lockindividual
individual
bit secured
of security
down bit as
block (64Kblock (64KOTP mode
register
"1" (once lock- byte) or sector byte) or sector
down, cannot (4K-byte) write
(4K-byte)
be update)
protect
unprotect
COMMAND
(byte)
GBULK (gang
block unlock)
NOP (No
Operation)
RSTEN
(Reset Enable)
RST (Reset
Memory)
1st byte
2nd byte
3rd byte
4th byte
Action
98 (hex)
00 (hex)
66 (hex)
99 (hex)
COMMAND
(byte)
1st byte
2nd byte
3rd byte
4th byte
Action
whole chip
unprotect
RDBLOCK
GBLK (gang
(block protect
block lock)
read)
3C (hex)
7E (hex)
AD1
AD2
AD3
read individual whole chip
block or sector write protect
write protect
status
WPSEL
ESRY (enable
SBL (Set Burst
(Write Protect SO to output
Length)
Selection)
RY/BY#)
77 (hex)
68 (hex)
70 (hex)
Value
to set Burst
length
to enter
to enable SO
and enable
to output RY/
individal block BY# during CP
protect mode
mode
DSRY (disable
CLSR (Clear
SO to output
SR Fail Flags)
RY/BY#)
80 (hex)
30 (hex)
to disable SO clear security
to output RY/ register bit 6
BY# during CP
and bit 5
mode
Note 1: The count base is 4-bit for ADD(2) and Dummy(2) because of 2 x I/O. And the MSB is on SI/SIO1 which is different
from 1 x I/O condition.
Note 2: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first.
Note 3: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the
hidden mode.
Note 4: RST command only executed if RSTEN command is executed first. Any intervening command will disable Reset.
P/N: PM1676
16
REV. 1.3, MAY 28, 2012
MX25L12835E
10-1.
Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP,
4PP, CP, SE, BE, BE32K, CE, WRSR, SBLK, SBULK, GBLK and GBULK, which are intended to change the device content, should be set every time after the WREN instruction setting the WEL bit.
The sequence of issuing WREN instruction is: CS# goes low→ sending WREN instruction code→ CS# goes
high.
Figure 3. Write Enable (WREN) Sequence (Command 06)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
SO
06h
High-Z
P/N: PM1676
17
REV. 1.3, MAY 28, 2012
MX25L12835E
10-2.
Write Disable (WRDI)
The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.
The sequence of issuing WRDI instruction is: CS# goes low→ sending WRDI instruction code→ CS# goes high.
The WEL bit is reset by following situations:
- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP, 4PP) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase (BE, BE32K) instruction completion
- Chip Erase (CE) instruction completion
- Continuously Program mode (CP) instruction completion
- Single Block Lock/Unlock (SBLK/SBULK) instruction completion
- Gang Block Lock/Unlock (GBLK/GBULK) instruction completion
Figure 4. Write Disable (WRDI) Sequence (Command 04)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
SO
04h
High-Z
P/N: PM1676
18
REV. 1.3, MAY 28, 2012
MX25L12835E
10-3.
Read Identification (RDID)
The RDID instruction is for reading the Manufacturer ID of 1-byte and followed by Device ID of 2-byte. The
Macronix Manufacturer ID is C2(hex), the memory type ID is 20(hex) as the first-byte Device ID, and the individual Device ID of second-byte ID are listed as table of "Table 7. ID Definitions".
The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code → 24-bits ID data
out on SO→ to end RDID operation can use CS# to high at any time during data out.
While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the
cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby
stage.
Figure 5. Read Identification (RDID) Sequence (Command 9F)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
28 29 30 31
SCLK
Command
SI
9Fh
Manufacturer Identification
SO
High-Z
7
6
5
3
MSB
2
1
Device Identification
0 15 14 13
3
2
1
0
MSB
P/N: PM1676
19
REV. 1.3, MAY 28, 2012
MX25L12835E
10-4.
Read Status Register (RDSR)
The RDSR instruction is for reading Status Register. The Read Status Register can be read at any time (even
in program/erase/write status register condition) and continuously. It is recommended to check the Write in
Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is
in progress.
The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register
data out on SO.
Figure 6. Read Status Register (RDSR) Sequence (Command 05)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
command
05h
SI
SO
High-Z
Status Register Out
7
6
5
4
3
2
1
Status Register Out
0
7
6
5
4
3
2
1
0
7
MSB
MSB
P/N: PM1676
20
REV. 1.3, MAY 28, 2012
MX25L12835E
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/
write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write
status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/
write status register cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch. When WEL bit sets to "1", which means the internal write enable latch is set, the device can accept
program/erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable
latch; the device will not accept program/erase/write status register instruction. The program/erase command will
be ignored and will reset WEL bit if it is applied to a protected memory area. To ensure both WIP bit & WEL bit are
both set to 0 and available for next program/erase/operations, WIP bit needs to be confirm to be 0 before polling
WEL bit. After WIP bit confirmed, WEL bit needs to be confirm to be 0.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area (as defined in Table 2. Protected Area Sizes) of the device to against the program/erase instruction
without hardware protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the
Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to
against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip Erase (CE) instructions (only if all
Block Protect bits set to 0, the CE instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as default.
Which is un-protected.
QE bit. The Quad Enable (QE) bit, non-volatile bit, while it is "0" (factory default), it performs non-Quad and WP#
is enable. While QE is "1", it performs Quad I/O mode and WP# is disabled. In the other word, if the system goes
into four I/O mode (QE=1), the feature of HPM will be disabled.
SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, default value is "0". SRWD bit is operated together with Write Protection (WP#/SIO2) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP#/SIO2 pin signal is low stage. In the hardware protection mode,
the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block
Protect bits (BP3, BP2, BP1, BP0) are read only. The SRWD bit defaults to be "0".
Status Register
bit7
SRWD
(status
register write
protect)
bit6
QE
(Quad
Enable)
bit5
BP3
(level of
protected
block)
bit4
BP2
(level of
protected
block)
bit3
BP1
(level of
protected
block)
bit2
BP0
(level of
protected
block)
1= Quad
1=status
Enable
register write
(note 1)
(note 1)
(note 1)
(note 1)
0=not Quad
disable
Enable
Non-volatile Non-volatile Non-volatile Non-volatile Non-volatile Non-volatile
bit
bit
bit
bit
bit
bit
bit1
bit0
WEL
WIP
(write enable
(write in
latch)
progress bit)
1=write
1=write
enable
operation
0=not write 0=not in write
enable
operation
volatile bit
volatile bit
Note: see the "Table 2. Protected Area Sizes" .
P/N: PM1676
21
REV. 1.3, MAY 28, 2012
MX25L12835E
10-5.
Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the
Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1, BP0) bits to define the protected area of memory (as shown in Table 2. Protected Area Sizes). The WRSR also can set or reset the Quad
enable (QE) bit and set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#/SIO2) pin signal, but has no effect on bit1(WEL) and bit0 (WIP) of the status register. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered.
The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register data on SI→ CS# goes high.
Figure 7. Write Status Register (WRSR) Sequence (Command 01)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
command
SI
SO
Status
Register In
01h
High-Z
7
6
5
4
3
2
1
0
MSB
P/N: PM1676
22
REV. 1.3, MAY 28, 2012
MX25L12835E
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The
Write in Progress (WIP) bit still can be checked out during the Write Status Register cycle is in progress. The
WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset.
Table 6. Protection Modes
Mode
Software protection
mode (SPM)
Hardware protection
mode (HPM)
Status register condition
Status register can be written
in (WEL bit is set to "1") and
the SRWD, BP0-BP3
bits can be changed
WP# and SRWD bit status
Memory
WP#=1 and SRWD bit=0, or
The protected area cannot
WP#=0 and SRWD bit=0, or
be programmed or erased.
WP#=1 and SRWD=1
The SRWD, BP0-BP3 of
status register bits cannot be
changed
WP#=0, SRWD bit=1
The protected area cannot
be programmed or erased.
Note: As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown
in Table 2. Protected Area Sizes.
As the table above showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode
(HPM):
Software Protected Mode (SPM):
- When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can
change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1,
BP0, is at software protected mode (SPM).
- When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values
of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software
protected mode (SPM)
Hardware Protected Mode (HPM):
- When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware protected mode (HPM). The data of the protected area is protected by software protected mode by BP3,
BP2, BP1, BP0 and hardware protected mode by the WP#/SIO2 to against data modification.
Note:
To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is
entered. If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via BP3, BP2, BP1, BP0.
If the system goes into four I/O mode, the feature of HPM will be disabled.
P/N: PM1676
23
REV. 1.3, MAY 28, 2012
MX25L12835E
Figure 8. WRSR flow
start
WREN command
RDSR command
WREN=1?
No
Yes
WRSR command
Write status register data
RDSR command
WIP=0?
No
Yes
RDSR command
Read WEL=0, BP[3:0], QE,
and SRWD data
Verify OK?
No
Yes
WRSR successfully
WRSR fail
P/N: PM1676
24
REV. 1.3, MAY 28, 2012
MX25L12835E
10-6.
Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out
on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole
memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached.
The sequence of issuing READ instruction is: CS# goes low→ sending READ instruction code→3-byte address
on SI →data out on SO→ to end READ operation can use CS# to high at any time during data out.
Figure 9. Read Data Bytes (READ) Sequence (Command 03)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
SI
03
24 ADD Cycles
A23 A22 A21
A3 A2 A1 A0
MSB
SO
Data Out 1
High-Z
Data Out 2
D7 D6 D5 D4 D3 D2 D1 D0 D7
MSB
P/N: PM1676
25
MSB
REV. 1.3, MAY 28, 2012
MX25L12835E
10-7.
Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and
data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be
at any location. The address is automatically increased to the next higher address after each byte data is shifted
out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to
0 when the highest address has been reached.
The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ instruction code→
3-byte address on SI→1-dummy byte (default) address on SI→ data out on SO→ to end FAST_READ operation
can use CS# to high at any time during data out.
In the performance-enhancing mode, P[7:4] must be toggling with P[3:0] ; likewise P[7:0]=A5h,5Ah,F0h or 0Fh
can make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with
P[3:0]; likewise P[7:0]=FFh,00h,AAh or 55h and afterwards CS# is raised and then lowered, the system then will
escape from performance enhance mode and return to normal operation.
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
Figure 10. Read at Higher Speed (FAST_READ) Sequence (Command 0B) (104MHz)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
SO
24 BIT ADDRESS
23 22 21
0Bh
3
2
1
0
High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Cycle
SI
7
6
5
4
3
2
1
0
DATA OUT 2
DATA OUT 1
SO
7
6
5
4
3
2
1
0
7
MSB
MSB
P/N: PM1676
26
6
5
4
3
2
1
0
7
MSB
REV. 1.3, MAY 28, 2012
MX25L12835E
10-8.
Dual Read Mode (DREAD)
The DREAD instruction enable double throughput of Serial Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at
a maximum frequency fT. The first address byte can be at any location. The address is automatically increased
to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single
DREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruction, the following data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing DREAD instruction is: CS# goes low → sending DREAD instruction → 3-byte address
on SI → 8-bit dummy cycle → data out interleave on SO1 & SO0 → to end DREAD operation can use CS# to
high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle.
Figure 11. Dual Read Mode Sequence (Command 3B)
CS#
0
1
2
3
4
5
6
7
8
…
Command
SI/SIO0
SO/SIO1
30 31 32
9
SCLK
3B
…
24 ADD Cycle
A23 A22
…
High Impedance
39 40 41 42 43 44 45
A1 A0
8 dummy
cycle
Data Out
1
Data Out
2
D6 D4 D2 D0 D6 D4
D7 D5 D3 D1 D7 D5
P/N: PM1676
27
REV. 1.3, MAY 28, 2012
MX25L12835E
10-9.
2 x I/O Read Mode (2READ)
The 2READ instruction enables Double Transfer Rate of Serial Flash in read mode. The address is latched on
rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at
a maximum frequency fT. The first address byte can be at any location. The address is automatically increased
to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single
2READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 24-bit address interleave on SIO1 & SIO0→ 4-bit dummy cycle on SIO1 & SIO0→ data out interleave on SIO1 & SIO0→ to end
2READ operation can use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
Figure 12. 2 x I/O Read Mode Sequence (Command BB)
CS#
0
1
2
3
4
5
6
7
8
SCLK
…
Command
SI/SIO0
SO/SIO1
18 19 20 21 22 23 24 25 26 27 28 29
9
BB(hex)
High Impedance
12 ADD Cycle
4 dummy
cycle
Data Out
1
Data Out
2
A22 A20
…
A2 A0 P2 P0
D6 D4 D2 D0 D6 D4
A23 A21
…
A3 A1 P3 P1
D7 D5 D3 D1 D7 D5
Note: SI/SIO0 or SO/SIO1 should be kept "0h" or "Fh" in the first two dummy cycles. In other words, P2=P0 or
P3=P1 is necessary.
P/N: PM1676
28
REV. 1.3, MAY 28, 2012
MX25L12835E
10-10. Quad Read Mode (QREAD)
The QREAD instruction enable quad throughput of Serial Flash in read mode. The address is latched on rising
edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a
maximum frequency fQ. The first address byte can be at any location. The address is automatically increased
to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single
QREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing QREAD instruction, the following data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing QREAD instruction is: CS# goes low→ sending QREAD instruction → 3-byte address
on SI → 8-bit dummy cycle → data out interleave on SO3, SO2, SO1 & SO0→ to end QREAD operation can
use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle.
Figure 13. Quad Read Mode Sequence (Command 6B)
CS#
0
1
2
3
4
5
6
7
8
SCLK
…
Command
SI/SO0
SO/SO1
WP#/SO2
HOLD#/SO3
29 30 31 32 33
9
6B
…
24 ADD Cycles
A23 A22
…
High Impedance
38 39 40 41 42
A2 A1 A0
8 dummy cycles
Data Data
Out 1 Out 2
Data
Out 3
D4 D0 D4 D0 D4
D5 D1 D5 D1 D5
High Impedance
D6 D2 D6 D2 D6
High Impedance
D7 D3 D7 D3 D7
P/N: PM1676
29
REV. 1.3, MAY 28, 2012
MX25L12835E
10-11. 4 x I/O Read Mode (4READ)
The 4READ instruction enables quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of
SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum
frequency fQ. The first address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 4READ
instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing 4READ instruction is: CS# goes low→ sending 4READ instruction→ 24-bit address interleave on SIO3, SIO2, SIO1 & SIO0→2+4 dummy cycles→data out interleave on SIO3, SIO2, SIO1 & SIO0→
to end 4READ operation can use CS# to high at any time during data out.
W4READ instruction (E7) is also available for 4 I/O read. The sequence is similar to 4READ, but with only 4
dummy cycles. The clock rate runs at 54MHz.
Figure 14. 4 x I/O Read Mode Sequence (Command EB)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
n
SCLK
8 Bit Instruction
SI/SIO0
SO/SIO1
WP#/SIO2
HOLD#/SIO3
6 Address cycles
Performance
enhance
indicator (Note)
4 dummy
cycles
Data Output
address
bit20, bit16..bit0
P4 P0
data
bit4, bit0, bit4....
High Impedance
address
bit21, bit17..bit1
P5 P1
data
bit5 bit1, bit5....
High Impedance
address
bit22, bit18..bit2
P6 P2
data
bit6 bit2, bit6....
High Impedance
address
bit23, bit19..bit3
P7 P3
data
bit7 bit3, bit7....
EBh
Note:
1. Hi-impedance is inhibited for the two clock cycles.
2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited.
P/N: PM1676
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REV. 1.3, MAY 28, 2012
MX25L12835E
Another sequence of issuing 4READ instruction especially useful in random access is : CS# goes low→ sending
4READ instruction→ 3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 →performance enhance toggling
bit P[7:0]→ 4 dummy cycles → data out still CS# goes high → CS# goes low (reduce 4 Read instruction) → 24bit random access address (Please refer to Figure 15 for 4 x I/O Read Enhance Performance Mode timing waveform).
In the performance-enhancing mode (Notes of Figure 15), P[7:4] must be toggling with P[3:0]; likewise
P[7:0]=A5h, 5Ah, F0h or 0Fh can make this mode continue and reduce the next 4READ instruction. Once P[7:4]
is no longer toggling with P[3:0]; likewise P[7:0]=FFh, 00h, AAh or 55h. These commands will reset the performance enhance mode. And afterwards CS# is raised and then lowered, the system then will return to normal operation.
While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle.
10-12. Performance Enhance Mode
The device could waive the command cycle bits if the two cycle bits after address cycle toggles. (Please note
Figure 15 4xI/O Read enhance performance mode sequence)
Please be noticed that “EBh” “E7h” commands support enhance mode. The performance enhance mode is not
supported in dual I/O mode.
After entering enhance mode, following CSB go high, the device will stay in the read mode and treat CSB go low
of the first clock as address instead of command cycle.
To exit enhance mode, a new fast read command whose first two dummy cycles is not toggle then exit. Or issue
”FFh” command to exit enhance mode.
10-13. Performance Enhance Mode Reset (FFh)
To conduct the Performance Enhance Mode Reset operation, FFh command code, 8 clocks, should be issued in
1I/O sequence.
If the system controller is being Reset during operation, the flash device will return to the standard SPI operation.
Upon Reset of main chip, SPI instruction would be issued from the system. Instructions like Read ID (9Fh) or
Fast Read (0Bh) would be issued.
P/N: PM1676
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REV. 1.3, MAY 28, 2012
MX25L12835E
Figure 15. 4 x I/O Read enhance performance Mode Sequence (Command EB)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
n
SCLK
8 Bit Instruction
WP#/SIO2
HOLD#/SIO3
Performance
enhance
indicator (Note)
4 dummy
cycles
Data Output
address
bit20, bit16..bit0
P4 P0
data
bit4, bit0, bit4....
High Impedance
address
bit21, bit17..bit1
P5 P1
data
bit5 bit1, bit5....
High Impedance
address
bit22, bit18..bit2
P6 P2
data
bit6 bit2, bit6....
High Impedance
address
bit23, bit19..bit3
P7 P3
data
bit7 bit3, bit7....
EBh
SI/SIO0
SO/SIO1
6 Address cycles
CS#
n+1
...........
n+7 ...... n+9
........... n+13
...........
SCLK
6 Address cycles
Performance
enhance
indicator (Note)
4 dummy
cycles
Data Output
SI/SIO0
address
bit20, bit16..bit0
P4 P0
data
bit4, bit0, bit4....
SO/SIO1
address
bit21, bit17..bit1
P5 P1
data
bit5 bit1, bit5....
WP#/SIO2
address
bit22, bit18..bit2
P6 P2
data
bit6 bit2, bit6....
HOLD#/SIO3
address
bit23, bit19..bit3
P7 P3
data
bit7 bit3, bit7....
Note: Performance enhance mode, if P7≠P3 & P6≠P2 & P5≠P1 & P4≠P0 (Toggling), ex: A5, 5A, 0F, if not using
performance enhance recommend to keep 1 or 0 in performance enhance indicator.
Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF
P/N: PM1676
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REV. 1.3, MAY 28, 2012
MX25L12835E
Figure 16. Performance Enhance Mode Reset for Fast Read Quad I/O
Mode Bit Reset
for Quad I/O
CS#
Mode 3
SCLK
０ 1
2
3
4
5
6
7
Mode ０
Mode 3
Mode ０
IO0
FFh
IO1
Don’t Care
IO2
Don’t Care
IO3
Don’t Care
P/N: PM1676
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REV. 1.3, MAY 28, 2012
MX25L12835E
10-14. Burst Read
To set the Burst length, following command operation is required
Issuing command: “77h” in the first Byte (8-clocks), following 4 clocks defining wrap around enable with “0h” and
disable with“1h”.
Next 4 clocks is to define wrap around depth. Definition as following table:
Data
1xh
1xh
1xh
1xh
Wrap Around
No
No
No
No
Wrap Depth
X
X
X
X
Data
00h
01h
02h
03h
Wrap Around
Yes
Yes
Yes
Yes
Wrap Depth
8-byte
16-byte
32-byte
64-byte
The wrap around unit is defined within the 256Byte page, with random initial address. It’s defined as “wraparound mode disable” for the default state of the device. To exit wrap around, it is required to issue another
“77” command in which data=‘1xh”. Otherwise, wrap around status will be retained until power down or reset
command. To change wrap around depth, it is requried to issue another “77” command in which data=“0xh”. SPI “EBh”
“E7h” support wrap around feature after wrap around enable. The Device ID default without Burst read.
Figure 17. Burst Read
CS#
0
1
2
1
1
0
3
4
5
6
7
8
9
0
0
0
0
H
H
10
11
12
13
H
L
L
14
15
SCLK
SIO
0
P/N: PM1676
34
H
L
L
REV. 1.3, MAY 28, 2012
MX25L12835E
10-15. Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used
for any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit
before sending the Sector Erase (SE). Any address of the sector (see Table 4. Memory Organization) is a valid
address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth
of address byte has been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing SE instruction is: CS# goes low → sending SE instruction code→ 3-byte address on SI
→CS# goes high.
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked out during the Sector Erase cycle is in progress. The WIP sets 1 during
the tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset.
If the sector is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected
(no change) and the WEL bit still be reset.
Figure 18. Sector Erase (SE) Sequence (Command 20)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
24 Bit Address
Command
SI
23 22
20h
2
1
0
MSB
P/N: PM1676
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REV. 1.3, MAY 28, 2012
MX25L12835E
10-16. Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for
64K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL)
bit before sending the Block Erase (BE). Any address of the block (see Table 4. Memory Organization) is a valid
address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth
of address byte has been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE instruction is: CS# goes low → sending BE instruction code → 3-byte address on
SI → CS# goes high.
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked out during the Sector Erase cycle is in progress. The WIP sets 1 during
the tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset.
If the block is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no
change) and the WEL bit still be reset.
Figure 19. Block Erase (BE) Sequence (Command D8)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
SI
24 Bit Address
23 22
D8h
2
1
0
MSB
P/N: PM1676
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REV. 1.3, MAY 28, 2012
MX25L12835E
10-17. Block Erase (BE32K)
The Block Erase (BE32) instruction is for erasing the data of the chosen block to be "1". The instruction is used
for 32K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable
Latch (WEL) bit before sending the Block Erase (BE32). Any address of the block (see Table 4. Memory Organization) is a valid address for Block Erase (BE32) instruction. The CS# must go high exactly at the byte boundary (the
latest eighth of address byte has been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE32 instruction is: CS# goes low → sending BE32 instruction code → 3-byte address
on SI → CS# goes high.
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked out during the Sector Erase cycle is in progress. The WIP sets 1 during
the tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset.
If the block is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no
change) and the WEL bit still be reset.
Figure 20. Block Erase 32KB (BE32K) Sequence (Command 52)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
SI
24 Bit Address
23 22
52h
2
1
0
MSB
P/N: PM1676
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REV. 1.3, MAY 28, 2012
MX25L12835E
10-18. Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS#
must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The sequence of issuing CE instruction is: CS# goes low → sending CE instruction code → CS# goes high.
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked out during the Chip Erase cycle is in progress. The WIP sets 1 during the
tCE timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
chip is protected the Chip Erase (CE) instruction will not be executed, but WEL will be reset.
Figure 21. Chip Erase (CE) Sequence (Command 60 or C7)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
60h or C7h
P/N: PM1676
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REV. 1.3, MAY 28, 2012
MX25L12835E
10-19. Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN)
instruction must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The
device programs only the last 256 data bytes sent to the device. If the entire 256 data bytes are going to be
programmed, A7-A0 (The eight least significant address bits) should be set to 0. If the eight least significant
address bits (A7-A0) are not all 0, all transmitted data going beyond the end of the current page are programmed
from the start address of the same page (from the address A7-A0 are all 0). If more than 256 bytes are sent to the
device, the data of the last 256-byte is programmed at the request page and previous data will be disregarded. If
less than 256 bytes are sent to the device, the data is programmed at the requested address of the page without
effect on other address of the same page.
The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on
SI→ at least 1-byte on data on SI→ CS# goes high.
The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte
boundary (the latest eighth bit of data being latched in), otherwise, the instruction will be rejected and will not be
executed.
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be checked out during the Page Program cycle is in progress. The WIP sets 1
during the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit
is reset. If the page is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be
protected (no change) and the WEL bit will still be reset.
Figure 22. Page Program (PP) Sequence (Command 02)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
1
0
7
6
5
3
2
1
0
2079
2
2078
3
2077
23 22 21
02h
SI
Data Byte 1
2076
24-Bit Address
2075
Command
4
1
0
MSB
MSB
2074
2073
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
2072
CS#
SCLK
Data Byte 2
SI
7
6
MSB
5
4
3
2
Data Byte 3
1
0
7
6
5
MSB
4
3
2
Data Byte 256
1
0
7
6
5
4
3
2
MSB
P/N: PM1676
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REV. 1.3, MAY 28, 2012
MX25L12835E
10-20. 4 x I/O Page Program (4PP)
The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN)
instruction must execute to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1"
before sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1,
SIO2, and SIO3, which can raise programmer performance and the effectiveness of application of lower clock
less than 70MHz. For system with faster clock, the Quad page program cannot provide more actual favors,
because the required internal page program time is far more than the time data flows in. Therefore, we suggest
that while executing this command (especially during sending data), user can slow the clock speed down to
70MHz below. The other function descriptions are as same as standard page program.
The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on
SIO[3:0]→ at least 1-byte on data on SIO[3:0]→ CS# goes high.
If the page is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no
change) and the WEL bit will still be reset.
Figure 23. 4 x I/O Page Program (4PP) Sequence (Command 38)
CS#
0
1
2
3
4
5
6
7
524 525
9 10 11 12 13 14 15 16 17
8
SCLK
…
Command
6 ADD cycles
Data
Byte 256
Data Data
Byte 1 Byte 2
A20 A16 A12 A8 A4 A0 D4 D0 D4 D0
…
D4 D0
SO/SIO1
A21 A17 A13 A9 A5 A1 D5 D1 D5 D1
…
D5 D1
WP#/SIO2
A22 A18 A14 A10 A6 A2 D6 D2 D6 D2
…
D6 D2
HOLD#/SIO3
A23 A19 A15 A11 A7 A3 D7 D3 D7 D3
…
D7 D3
SI/SIO0
38
P/N: PM1676
40
REV. 1.3, MAY 28, 2012
MX25L12835E
The Program/Erase function instruction function flow is as follows:
Figure 24. Program/Erase Flow(1) with read array data
Start
WREN command
RDSR command*
WREN=1?
No
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
No
WIP=0?
Yes
Read array data
(same address of PGM/ERS)
Verify OK?
No
Yes
Program/erase fail
Program/erase successfully
CLSR(30h) command
Program/erase
another block?
No
Yes
*
* Issue RDSR to check BP[3:0].
* If WPSEL=1, issue RDBLOCK to check the block status.
Program/erase completed
P/N: PM1676
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REV. 1.3, MAY 28, 2012
MX25L12835E
Figure 25. Program/Erase Flow(2) without read array data
Start
WREN command
RDSR command*
WREN=1?
No
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
No
WIP=0?
Yes
RDSCUR command
REGPFAIL/REGEFAIL=1?
Yes
No
Program/erase fail
Program/erase successfully
CLSR(30h) command
Program/erase
another block?
No
Yes
* Issue RDSR to check BP[3:0].
* If WPSEL=1, issue RDBLOCK to check the block status.
Program/erase completed
P/N: PM1676
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REV. 1.3, MAY 28, 2012
MX25L12835E
10-21. Continuously program mode (CP mode)
The CP mode may enhance program performance by automatically increasing address to the next higher address after each byte data has been programmed.
The Continuously program (CP) instruction is for multiple bytes program to Flash. A write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Continuously program (CP)
instruction. CS# requires to go high before CP instruction is executing. After CP instruction and address input,
two bytes of data is input sequentially from MSB(bit7) to LSB(bit0). The first byte data will be programmed to the
initial address range with A0=0 and second byte data with A0=1. If only one byte data is input, the CP mode will
not process. If more than two bytes data are input, the additional data will be ignored and only two byte data are
valid. Any byte to be programmed should be in the erase state (FF) first. It will not roll over during the CP mode,
once the last unprotected address has been reached, the chip will exit CP mode and reset write Enable Latch bit
(WEL) as "0" and CP mode bit as "0". Please check the WIP bit status if it is not in write progress before entering next valid instruction. During CP mode, the valid commands are CP command (AD hex), WRDI command (04
hex), RDSR command (05 hex), and RDSCUR command (2B hex). And the WRDI command is valid after completion of a CP programming cycle, which means the WIP bit=0.
The sequence of issuing CP instruction is : CS# goes low → sending CP instruction code → 3-byte address on
SI pin → two data bytes on SI → CS# goes high to low → sending CP instruction and then continue two data
bytes are programmed → CS# goes high to low → till last desired two data bytes are programmed → CS# goes
high to low →sending WRDI (Write Disable) instruction to end CP mode → send RDSR instruction to verify if
CP mode word program ends, or send RDSCUR to check bit4 to verify if CP mode ends.
Three methods to detect the completion of a program cycle during CP mode:
1) Software method-I: by checking WIP bit of Status Register to detect the completion of CP mode.
2) Software method-II: by waiting for a tBP time out to determine if it may load next valid command or not.
3) Hardware method: by writing ESRY (enable SO to output RY/BY#) instruction to detect the completion of a
program cycle during CP mode. The ESRY instruction must be executed before CP mode execution. Once
it is enable in CP mode, the CS# goes low will drive out the RY/BY# status on SO, "0" indicates busy stage,
"1" indicates ready stage, SO pin outputs tri-state if CS# goes high. DSRY (disable SO to output RY/BY#)
instruction to disable the SO to output RY/BY# and return to status register data output during CP mode.
Please note that the ESRY/DSRY commands are not accepted unless the completion of CP mode.
If the page is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no change) and the WEL bit will still be reset.
P/N: PM1676
43
REV. 1.3, MAY 28, 2012
MX25L12835E
Figure 26. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD)
CS#
0 1
6 7 8 9
30 31 31 32
47 48
0 1
6 7 8
20 21 22 23 24
0
7
0
7 8
SCLK
Command
SI
S0
AD (hex)
24-bit address
data in
Byte 0, Byte1
Valid
Command (1)
high impedance
data in
Byte n-1, Byte n
04 (hex)
05 (hex)
status (2)
Notes:
(1) During CP mode, the valid commands are CP command (AD hex), WRDI command (04 hex), RDSR
command (05 hex), RDSCUR command (2B hex), RSTEN command (66 hex) and RST command (99hex).
(2) Once an internal programming operation begins, CS# goes low will drive the status on the SO pin and CS#
goes high will return the SO pin to tri-state.
(3) To end the CP mode, either reaching the highest unprotected address or sending Write Disable (WRDI)
command (04 hex) may achieve it and then it is recommended to send RDSR command (05 hex) to verify if
CP mode is ended. Please be noticed that Software reset and Hardware reset can end the CP mode.
P/N: PM1676
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REV. 1.3, MAY 28, 2012
MX25L12835E
10-22. Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to entering the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down
mode requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is
not active and all Write/Program/Erase instructions are ignored. When CS# goes high, it's only in standby mode
not deep power-down mode. It's different from Standby mode.
The sequence of issuing DP instruction is: CS# goes low→ sending DP instruction code→ CS# goes high.
Once the DP instruction is set, all instructions will be ignored except the Release from Deep Power-down mode (RDP)
and Read Electronic Signature (RES) instruction. (those instructions allow the ID being reading out). When
Power-down, the deep power-down mode automatically stops, and when power-up, the device automatically is
in standby mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of
instruction code has been latched-in); otherwise, the instruction will not be executed. As soon as Chip Select (CS#)
goes high, a delay of tDP is required before entering the Deep Power-down mode and reducing the current to
ISB2.
Figure 27. Deep Power-down (DP) Sequence (Command B9)
CS#
0
1
2
3
4
5
6
tDP
7
SCLK
Command
SI
B9h
Stand-by Mode
P/N: PM1676
45
Deep Power-down Mode
REV. 1.3, MAY 28, 2012
MX25L12835E
10-23. Release from Deep Power-down (RDP), Read Electronic Signature (RES)
The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When
Chip Select (CS#) is driven High, the device is put in the standby Power mode. If the device was not previously in
the Deep Power-down mode, the transition to the standby Power mode is immediate. If the device was previously
in the Deep Power-down mode, though, the transition to the standby Power mode is delayed by tRES2, and Chip
Select (CS#) must remain High for at least tRES2(max), as specified in Table 13. AC CHARACTERISTICS. Once
in the standby mode, the device waits to be selected, so that it can receive, decode and execute instructions.
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as Table 7.
ID Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new
design, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to
be executed, only except the device is in progress of program/erase/write cycles; there's no effect on the current
program/erase/write cycles in progress.
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously
in Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high
at least tRES2(max). Once in the standby mode, the device waits to be selected, so it can receive, decode, and
execute instruction.
The RDP instruction is for releasing from Deep Power-down Mode.
Figure 28. Read Electronic Signature (RES) Sequence (Command AB)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38
SCLK
Command
SI
ABh
tRES2
3 Dummy Bytes
23 22 21
3
2
1
0
MSB
SO
Electronic Signature Out
High-Z
7
6
5
4
3
2
1
0
MSB
Deep Power-down Mode
P/N: PM1676
46
Stand-by Mode
REV. 1.3, MAY 28, 2012
MX25L12835E
Figure 29. Release from Deep Power-down (RDP) Sequence (Command AB)
CS#
0
1
2
3
4
5
6
tRES1
7
SCLK
Command
SI
SO
ABh
High-Z
Deep Power-down Mode
P/N: PM1676
47
Stand-by Mode
REV. 1.3, MAY 28, 2012
MX25L12835E
10-24. Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4)
The REMS, REMS2, and REMS4 instruction provides both the JEDEC assigned Manufacturer ID and the specific Device ID.
The instruction is initiated by driving the CS# pin low and shift the instruction code "90h", "DFh" or "EFh" followed by two dummy bytes and one byte address (A7~A0). After which, the Manufacturer ID for Macronix (C2h)
and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in
Figure 30. The Device ID values are listed in table of Table 7. ID Definitions. If the one-byte address is initially
set to 01h, then the Device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and
Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving
CS# high.
Figure 30. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF)
CS#
0 1 2 3 4 5 6 7 8 9 10
SCLK
Command
SI
SO
90
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
24 ADD Cycles
A23 A22 A21
A3 A2 A1 A0
Manufacturer ID
High-Z
Device ID
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
MSB
MSB
MSB
Notes:
1. A0=0 will output the Manufacturer ID first and A0=1 will output Device ID first. A1~A23 are don't care.
2. Instruction is either 90(hex) or EF(hex) or DF(hex).
P/N: PM1676
48
REV. 1.3, MAY 28, 2012
MX25L12835E
10-25. ID Read
The ID Read instruction identifies the devices as MX25L12835E and manufacturer as Macronix. The sequence
of issue ID instruction is CS# goes low→sending ID instruction→→Data out on SO→CS# goes high. Most
significant bit (MSB) first.
Immediately following the command cycle the device outputs data on the falling edge of the SCLK signal. The
data output stream is continuous until terminated by a low-tohigh transition of CS#. The device outputs three
bytes of data: manufacturer, device type, and device ID.
Table 7. ID Definitions
Command Type
RDID
manufacturer ID
C2
RES
REMS/REMS2/
REMS4
manufacturer ID
C2
MX25L12835E
memory type
20
electronic ID
17
device ID
17
memory density
18
10-26. Enter Secured OTP (ENSO)
The ENSO instruction is for entering the additional 4K-bit Secured OTP mode. The additional 4K-bit Secured
OTP is independent from main array, which may use to store unique serial number for system identifier. After
entering the Secured OTP mode, and then follow standard read or program procedure to read out the data or
update data. The Secured OTP data cannot be updated again once it is lock-down.
The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP
mode→ CS# goes high.
Please note that WRSR/WRSCUR/WPSEL/SBLK/GBLK/SBULK/GBULK/CE/BE/SE/BE32K commands are not
acceptable during the access of secure OTP region, once Security OTP is locked down, only read related commands are valid.
10-27. Exit Secured OTP (EXSO)
The EXSO instruction is for exiting the additional 4K-bit Secured OTP mode.
The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP
mode→ CS# goes high.
P/N: PM1676
49
REV. 1.3, MAY 28, 2012
MX25L12835E
10-28. Read Security Register (RDSCUR)
The RDSCUR instruction is for reading the value of Security Register. The Read Security Register can be read
at any time (even in program/erase/write status register/write security register condition) and continuously.
The sequence of issuing RDSCUR instruction is : CS# goes low→ sending RDSCUR instruction → Security
Register data out on SO→ CS# goes high.
Figure 31. Read Security Register (RDSCUR) Sequence (Command 2B)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
command
2B
SI
SO
High-Z
Security Register Out
7
6
5
4
3
2
1
Security Register Out
0
7
6
5
4
3
2
1
0
7
MSB
MSB
The definition of the Security Register is as below:
Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory before ex- factory
or not. When it is "0", it indicates non-factory lock; "1" indicates factory- lock.
Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for customer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 4K-bit Secured
OTP area cannot be updated any more. While it is in 4K-bit Secured OTP mode, array access is not allowed.
Continuously Program Mode (CP mode) bit. The Continuously Program Mode bit indicates the status of CP
mode, "0" indicates not in CP mode; "1" indicates in CP mode.
Program Fail Flag bit. While a program failure happened, the Program Fail Flag bit would be set. This bit will
also be set when the user attempts to program a protected main memory region or a locked OTP region. This bit
can indicate whether one or more of program operations fail, and can be reset by command CLSR (30h)
Erase Fail Flag bit. While an erase failure happened, the Erase Fail Flag bit would be set. This bit will also be
set when the user attempts to erase a protected main memory region or a locked OTP region. This bit can indicate whether one or more of erase operations fail, and can be reset by command CLSR (30h)
P/N: PM1676
50
REV. 1.3, MAY 28, 2012
MX25L12835E
Write Protection Select bit. The Write Protection Select bit indicates that WPSEL has been executed successfully. Once this bit has been set (WPSEL=1), all the blocks or sectors will be write-protected after the poweron every time. Once WPSEL has been set, it cannot be changed again, which means it's only for individual WP
mode.
Under the individual block protection mode (WPSEL=1), hardware protection is performed by driving WP#=0.
Once WP#=0, all array blocks/sectors are protected regardless of the contents of SRAM lock bits.
Table 8. Security Register Definition
bit7
bit6
bit5
bit4
Continuously
Program
mode
(CP mode)
WPSEL
E_FAIL
P_FAIL
0=normal
WP mode
0=normal
Erase
succeed
0=normal
Program
succeed
1=individual
1=indicate
WP mode
Erase failed
(default=0)
(default=0)
bit3
x
1=CP mode
(default=0)
x
bit1
bit0
LDSO
(lock-down
4K-bit
4K-bit Se- Secured OTP
cured OTP)
0 = not
lockdown
0=normal
Program
mode
1=indicate
Program
failed
(default=0)
bit2
reserved
reserved
0=
nonfactory
lock
1 = lockdown
(cannot
program/
erase
OTP)
1 = factory
lock
non-volatile
bit
volatile bit
volatile bit
volatile bit
volatile bit
volatile bit
non-volatile
bit
non-volatile
bit
OTP
Read Only
Read Only
Read Only
Read Only
Read Only
OTP
Read Only
P/N: PM1676
51
REV. 1.3, MAY 28, 2012
MX25L12835E
10-29. Write Security Register (WRSCUR)
The WRSCUR instruction is for changing the values of Security Register Bits. Unlike write status register, the
WREN instruction is not required before sending WRSCUR instruction. The WRSCUR instruction may change
the values of bit1 (LDSO bit) for customer to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is set
to "1", the Secured OTP area cannot be updated any more.
The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes
high.
The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
Figure 32. Write Security Register (WRSCUR) Sequence (Command 2F)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
SO
2F
High-Z
10-30. Write Protection Selection (WPSEL)
There are two write protection methods, (1) BP protection mode (2) individual block protection mode. If
WPSEL=0, flash is under BP protection mode. If WPSEL=1, flash is under individual block protection mode. The
default value of WPSEL is “0”. WPSEL command can be used to set WPSEL=1. Please note that WPSEL is an
OTP bit. Once WPSEL is set to 1, there is no chance to recovery WPSEL back to “0”. If the flash is put on
BP mode, the individual block protection mode is disabled. Contrarily, if flash is on the individual block protection
mode, the BP mode is disabled.
Every time after the system is powered-on, and the Security Register bit 7 is checked to be WPSEL=1,
all the blocks or sectors will be write protected by default. User may only unlock the blocks or sectors via
SBULK and GBULK instruction. Program or erase functions can only be operated after the Unlock instruction is
conducted.
BP protection mode, WPSEL=0:
ARRAY is protected by BP3~BP0 and BP3~BP0 bits are protected by “SRWD=1 and WP#=0”, where SRWD is
bit 7 of status register that can be set by WRSR command.
P/N: PM1676
52
REV. 1.3, MAY 28, 2012
MX25L12835E
Individual block protection mode, WPSEL=1:
Blocks are individually protected by their own SRAM lock bits which are set to “1” after power up. SBULK and
SBLK command can set SRAM lock bit to “0” and “1”. When the system accepts and executes WPSEL instruction, the bit 7 in security register will be set. It will activate SBLK, SBULK, RDBLOCK, GBLK, GBULK etc instructions to conduct block lock protection and replace the original Software Protect Mode (SPM) use (BP3~BP0)
indicated block methods. Under the individual block protection mode (WPSEL=1), hardware protection is performed by driving WP#=0. Once WP#=0, all array blocks/sectors are protected regardless of the contents of
SRAM lock bits.
The sequence of issuing WPSEL instruction is: CS# goes low → sending WPSEL instruction to enter the individual block protect mode → CS# goes high.
Figure 33. Write Protection Selection (WPSEL) Sequence (Command 68)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
68
WPSEL instruction function flow is as follows:
Figure 34. BP and SRWD if WPSEL=0
WPB pin
BP3
BP2
BP1
BP0
SRWD
64KB
64KB
64KB
(1) BP3~BP0 is used to define the protection group region.
(The protected area size see Table 2. Protected Area Sizes)
(2) “SRWD=1 and WPB=0” is used to protect BP3~BP0. In this
case, SRWD and BP3~BP0 of status register bits can not be
changed by WRSR
.
.
.
64KB
P/N: PM1676
53
REV. 1.3, MAY 28, 2012
MX25L12835E
Figure 35. The individual block lock mode is effective after setting WPSEL=1
SRAM
SRAM
…
…
TOP 4KBx16
Sectors
4KB
4KB
4KB
SRAM
SRAM
…
64KB
SRAM
…
……
Uniform
64KB blocks
64KB
4KB
SRAM
…
…
Bottom
4KBx16
Sectors
4KB
SRAM
• Power-Up: All SRAM bits=1 (all blocks are default protected).
All arrays cannot be programmed/erased
• SBLK/SBULK(36h/39h):
- SBLK(36h) : Set SRAM bit=1 (protect) : array can not be
programmed /erased
- SBULK(39h): Set SRAM bit=0 (unprotect): array can be
programmed /erased
- All top 4KBx16 sectors and bottom 4KBx16 sectors
and other 64KB uniform blocks can be protected and
unprotected SRAM bits individually by SBLK/SBULK
command set.
• GBLK/ GBULK(7Eh/98h):
- GBLK(7Eh):Set all SRAM bits=1,whole chip are protected
and cannot be programmed / erased.
- GBULK(98h):Set all SRAM bits=0,whole chip are
unprotected and can be programmed / erased.
- All sectors and blocks SRAM bits of whole chip can be
protected and unprotected at one time by GBLK/GBULK
command set.
• RDBLOCK(3Ch):
- use RDBLOCK mode to check the SRAM bits status after
SBULK /SBLK/GBULK/GBLK command set.
SBULK / SBLK / GBULK / GBLK / RDBLOCK
P/N: PM1676
54
REV. 1.3, MAY 28, 2012
MX25L12835E
Figure 36. WPSEL Flow
start
RDSCUR(2Bh) command
Yes
WPSEL=1?
No
WPSEL disable,
block protected by BP[3:0]
WPSEL(68h) command
RDSR command
WIP=0?
No
Yes
RDSCUR(2Bh) command
WPSEL=1?
No
Yes
WPSEL set successfully
WPSEL set fail
WPSEL enable.
Block protected by individual lock
(SBLK, SBULK, … etc).
P/N: PM1676
55
REV. 1.3, MAY 28, 2012
MX25L12835E
10-31. Single Block Lock/Unlock Protection (SBLK/SBULK)
These instructions are only effective after WPSEL was executed. The SBLK instruction is for write protection a
specified block(or sector) of memory, using A23-A16 or (A23-A12) address bits to assign a 64Kbytes block (or
4K bytes sector) to be protected as read only. The SBULK instruction will cancel the block (or sector) write protection state. This feature allows user to stop protecting the entire block (or sector) through the chip unprotect
command (GBULK).
The WREN (Write Enable) instruction is required before issuing SBLK/SBULK instruction.
The sequence of issuing SBLK/SBULK instruction is: CS# goes low → send SBLK/SBULK (36h/39h) instruction
→ send 3 address bytes assign one block (or sector) to be protected on SI pin → CS# goes high.
The CS# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not be executed.
Figure 37. Single Block Lock/Unlock Protection (SBLK/SBULK) Sequence (Command 36/39)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
24 Bit Address
Cycles
Command
SI
36/39
A23 A22
A2 A1 A0
MSB
P/N: PM1676
56
REV. 1.3, MAY 28, 2012
MX25L12835E
SBLK/SBULK instruction function flow is as follows:
Figure 38. Block Lock Flow
Start
RDSCUR(2Bh) command
WPSEL=1?
No
WPSEL command
Yes
WREN command
SBLK command
( 36h + 24bit address )
RDSR command
WIP=0?
No
Yes
RDBLOCK command
( 3Ch + 24bit address )
Data = FFh ?
No
Yes
Block lock successfully
Lock another block?
Block lock fail
Yes
No
Block lock completed
P/N: PM1676
57
REV. 1.3, MAY 28, 2012
MX25L12835E
Figure 39. Block Unlock Flow
start
RDSCUR(2Bh) command
WPSEL=1?
No
WPSEL command
Yes
WREN command
SBULK command
( 39h + 24bit address )
RDSR command
No
WIP=0?
Yes
Unlock another block?
Yes
Unlock block completed
P/N: PM1676
58
REV. 1.3, MAY 28, 2012
MX25L12835E
10-32. Read Block Lock Status (RDBLOCK)
This instruction is only effective after WPSEL was executed. The RDBLOCK instruction is for reading the status
of protection lock of a specified block(or sector), using A23-A16 (or A23-A12) address bits to assign a 64K bytes
block (4K bytes sector) and read protection lock status bit which the first byte of Read-out cycle. The status bit
is"1" to indicate that this block has been protected, that user can read only but cannot write/program /erase this
block. The status bit is "0" to indicate that this block hasn't be protected, and user can read and write this block.
The sequence of issuing RDBLOCK instruction is: CS# goes low → send RDBLOCK (3Ch) instruction → send
3 address bytes to assign one block on SI pin → read block's protection lock status bit on SO pin → CS# goes
high.
Figure 40. Read Block Protection Lock Status (RDBLOCK) Sequence (Command 3C)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
SI
3C
24 ADD Cycles
A23 A22 A21
A3 A2 A1 A0
MSB
SO
Block Protection Lock status out
High-Z
D7 D6 D5 D4 D3 D2 D1 D0
MSB
P/N: PM1676
59
REV. 1.3, MAY 28, 2012
MX25L12835E
10-33. Gang Block Lock/Unlock (GBLK/GBULK)
These instructions are only effective after WPSEL was executed. The GBLK/GBULK instruction is for enable/
disable the lock protection block of the whole chip.
The WREN (Write Enable) instruction is required before issuing GBLK/GBULK instruction.
The sequence of issuing GBLK/GBULK instruction is: CS# goes low → send GBLK/GBULK (7Eh/98h) instruction → CS# goes high.
The CS# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed.
Figure 41. Gang Block Lock/Unlock (GBLK/GBULK) Sequence (Command 7E/98)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
7E/98
P/N: PM1676
60
REV. 1.3, MAY 28, 2012
MX25L12835E
10-34. Clear SR Fail Flags (CLSR)
The CLSR instruction is for resetting the Program/Erase Fail Flag bit of Security Register. It should be executed
before program/erase another block during programming/erasing flow without read array data.
The sequence of issuing CLSR instruction is: CS# goes low → send CLSR instruction code → CS# goes high.
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
10-35. Enable SO to Output RY/BY# (ESRY)
The ESRY instruction is for outputting the ready/busy status to SO during CP mode.
The sequence of issuing ESRY instruction is: CS# goes low → sending ESRY instruction code → CS# goes
high.
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
10-36. Disable SO to Output RY/BY# (DSRY)
The DSRY instruction is for resetting ESRY during CP mode. The ready/busy status will not output to SO after
DSRY issued.
The sequence of issuing DSRY instruction is: CS# goes low → send DSRY instruction code → CS# goes high.
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
P/N: PM1676
61
REV. 1.3, MAY 28, 2012
MX25L12835E
10-37. No Operation (NOP)
The No Operation command only cancels a Reset Enable command. NOP has no impact on any other
command.
10-38. Software Reset (Reset-Enable (RSTEN) and Reset (RST))
The Reset operation is used as a system (software) reset that puts the device in normal operating Ready mode.
This operation consists of two commands: Reset-Enable (RSTEN) and Reset (RST).
To reset the device, the host drives CS# low, sends the Reset-Enable command (66H), and drives CS# high.
Next, the host drives CS# low again, sends the Reset command (99H), and drives CS# high.
The Reset operation requires the Reset-Enable command followed by the Reset command. Any command other
than the Reset command after the Reset-Enable command will disable the Reset-Enable.
A successful command execution will reset the device to SPI stand-by read mode, which are their respective
default states. A device reset during an active Program or Erase operation aborts the operation, which can cause
the data of the targeted address range to be corrupted or lost. Depending on the prior operation, the reset timing
may vary. Recovery from a Write operation requires more latency time than recovery from other operations.
Figure 42. Software Reset Recovery
Stand-by Mode
CS#
66
99
tRCR
tRCP
tRCE
Mode
tRCR: 200ns (Recovery Time from Read)
tRCP: 20us (Recovery Time from Program)
tRCE: 12ms (Recovery Time from Erase)
P/N: PM1676
62
REV. 1.3, MAY 28, 2012
MX25L12835E
10-39. Read SFDP Mode (RDSFDP)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the
functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These
parameter tables can be interrogated by host system software to enable adjustments needed to accommodate
divergent features from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC
Standard, JESD68 on CFI.
The sequence of issuing RDSFDP instruction is CS# goes low→send RDSFDP instruction (5Ah)→send 3
address bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP operation
can use CS# to high at any time during data out. (Please refer to Figure 43. Read Serial Flash Discoverable
Parameter (RDSFDP) Sequence)
SFDP is a standard of JEDEC. JESD216. v1.0.
Figure 43. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence (Command 5A)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
SO
24 BIT ADDRESS
23 22 21
5Ah
3
2
1
0
High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Cycle
SI
7
6
5
4
3
2
1
0
DATA OUT 2
DATA OUT 1
SO
7
6
5
4
3
2
1
0
7
MSB
MSB
P/N: PM1676
63
6
5
4
3
2
1
0
7
MSB
REV. 1.3, MAY 28, 2012
MX25L12835E
Table 9. Signature and Parameter Identification Data Values
Description
SFDP Signature
Comment
Fixed: 50444653h
Add (h) DW Add
Data
(Byte)
(Bit)
(h/b) note1
00h
07:00
53h
Data
(h)
53h
01h
15:08
46h
46h
02h
23:16
44h
44h
03h
31:24
50h
50h
SFDP Minor Revision Number
Start from 00h
04h
07:00
00h
00h
SFDP Major Revision Number
Start from 01h
05h
15:08
01h
01h
Number of Parameter Headers
Start from 01h
06h
23:16
01h
01h
07h
31:24
FFh
FFh
00h: it indicates a JEDEC
specified header.
08h
07:00
00h
00h
Start from 00h
09h
15:08
00h
00h
Start from 01h
0Ah
23:16
01h
01h
How many DWORDs in the
Parameter table
0Bh
31:24
09h
09h
0Ch
07:00
30h
30h
0Dh
15:08
00h
00h
0Eh
23:16
00h
00h
0Fh
31:24
FFh
FFh
it indicates Macronix manufacturer
ID
10h
07:00
C2h
C2h
Start from 00h
11h
15:08
00h
00h
Start from 01h
12h
23:16
01h
01h
How many DWORDs in the
Parameter table
13h
31:24
04h
04h
14h
07:00
60h
60h
15h
15:08
00h
00h
16h
23:16
00h
00h
17h
31:24
FFh
FFh
Unused
ID number (JEDEC)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length
(in double word)
Parameter Table Pointer (PTP)
First address of JEDEC Flash
Parameter table
Unused
ID number
(Macronix manufacturer ID)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length
(in double word)
Parameter Table Pointer (PTP)
First address of Macronix Flash
Parameter table
Unused
P/N: PM1676
64
REV. 1.3, MAY 28, 2012
MX25L12835E
Table 10. Parameter Table (0): JEDEC Flash Parameter Tables
Description
Comment
Block/Sector Erase sizes
00: Reserved, 01: 4KB erase,
10: Reserved,
11: not suport 4KB erase
Write Granularity
Write Enable Instruction
Requested for Writing to Volatile
Status Registers
Add (h) DW Add
Data
(Byte)
(Bit)
(h/b) note1
01:00
01b
0: 1Byte, 1: 64Byte or larger
02
1b
0: Nonvolatitle status bit
1: Volatitle status bit
(BP status register bit)
03
0b
30h
0: use 50h opcode,
1: use 06h opcode
Write Enable Opcode Select for
Note: If target flash status register
Writing to Volatile Status Registers
is nonvolatile, then bits 3 and 4
must be set to 00b.
Contains 111b and can never be
Unused
changed
4KB Erase Opcode
31h
Data
(h)
E5h
04
0b
07:05
111b
15:08
20h
16
1b
18:17
00b
19
0b
20
1b
20h
(1-1-2) Fast Read(Note2)
0=not support 1=support
Address Bytes Number used in
addressing flash array
Double Transfer Rate (DTR)
Clocking
00: 3Byte only, 01: 3 or 4Byte,
10: 4Byte only, 11: Reserved
(1-2-2) Fast Read
0=not support 1=support
(1-4-4) Fast Read
0=not support 1=support
21
1b
(1-1-4) Fast Read
0=not support 1=support
22
1b
23
1b
33h
31:24
FFh
37h:34h
31:00
07FFFFFFh
0=not support 1=support
32h
Unused
Unused
Flash Memory Density
(1-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
states (Note3)
Clocks) not support
(1-4-4) Fast Read Number of
000b: Mode Bits not support
Mode Bits (Note4)
38h
(1-4-4) Fast Read Opcode
39h
(1-1-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
states
Clocks) not support
(1-1-4) Fast Read Number of
000b: Mode Bits not support
Mode Bits
3Ah
(1-1-4) Fast Read Opcode
3Bh
P/N: PM1676
65
04:00
0 0100b
07:05
010b
15:08
EBh
20:16
0 1000b
23:21
000b
31:24
6Bh
F1h
FFh
44h
EBh
08h
6Bh
REV. 1.3, MAY 28, 2012
MX25L12835E
Description
Comment
(1-1-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy
states
Clocks) not support
(1-1-2) Fast Read Number of
000b: Mode Bits not support
Mode Bits
Add (h) DW Add
Data
(Byte)
(Bit)
(h/b) note1
3Ch
(1-1-2) Fast Read Opcode
3Dh
(1-2-2) Fast Read Number of Wait 0 0000b: Wait states(Dummy
states
Clocks) not support
(1-2-2) Fast Read Number of
000b: Mode Bits not support
Mode Bits
3Eh
(1-2-2) Fast Read Opcode
3Fh
(2-2-2) Fast Read
0=not support 1=support
Unused
(4-4-4) Fast Read
0=not support 1=support
40h
Unused
04:00
0 1000b
07:05
000b
15:08
3Bh
20:16
0 0100b
23:21
000b
31:24
BBh
00
0b
03:01
111b
04
0b
07:05
111b
Data
(h)
08h
3Bh
04h
BBh
EEh
Unused
43h : 41h
31:08
FFFFFFh
0xFFh
Unused
45h:44h
15:00
FFFFh
0xFFh
20:16
0 0000b
23:21
000b
(2-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy
states
Clocks) not support
(2-2-2) Fast Read Number of
000b: Mode Bits not support
Mode Bits
46h
(2-2-2) Fast Read Opcode
47h
31:24
FFh
FFh
49h:48h
15:00
FFFFh
0xFFh
20:16
0 0000b
23:21
000b
Unused
00h
(4-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
states
Clocks) not support
(4-4-4) Fast Read Number of
000b: Mode Bits not support
Mode Bits
4Ah
(4-4-4) Fast Read Opcode
4Bh
31:24
FFh
FFh
4Ch
07:00
0Ch
0Ch
4Dh
15:08
20h
20h
4Eh
23:16
0Fh
0Fh
4Fh
31:24
52h
52h
50h
07:00
10h
10h
51h
15:08
D8h
D8h
52h
23:16
00h
00h
53h
31:24
FFh
FFh
Sector Type 1 Size
Sector/block size = 2^N bytes
(Note5)
0x00b: this sector type don't exist
Sector Type 1 erase Opcode
Sector Type 2 Size
Sector/block size = 2^N bytes
0x00b: this sector type don't exist
Sector Type 2 erase Opcode
Sector Type 3 Size
Sector/block size = 2^N bytes
0x00b: this sector type don't exist
Sector Type 3 erase Opcode
Sector Type 4 Size
Sector/block size = 2^N bytes
0x00b: this sector type don't exist
Sector Type 4 erase Opcode
P/N: PM1676
66
00h
REV. 1.3, MAY 28, 2012
MX25L12835E
Table 11. Parameter Table (1): Macronix Flash Parameter Tables
Description
Comment
Add (h) DW Add
Data
(Byte)
(Bit)
(h/b) note1
Data
(h)
Vcc Supply Maximum Voltage
2000h=2.000V
2700h=2.700V
3600h=3.600V
61h:60h
15:00
3600h
3600h
Vcc Supply Minimum Voltage
1650h=1.650V
2250h=2.250V
2350h=2.350V
2700h=2.700V
63h:62h
31:16
2700h
2700h
HW Reset# pin
0=not support 1=support
00
1b
HW Hold# pin
0=not support 1=support
01
1b
Deep Power Down Mode
0=not support 1=support
02
1b
SW Reset
0=not support 1=support
03
1b
SW Reset Opcode
Should be issue Reset Enable
(66h) before Reset cmd.
Program Suspend/Resume
0=not support 1=support
12
0b
Erase Suspend/Resume
0=not support 1=support
13
0b
14
1b
15
1b
66h
23:16
77h
77h
67h
31:24
64h
64h
65h:64h
Unused
Wrap-Around Read mode
0=not support 1=support
Wrap-Around Read mode Opcode
11:04
1001 1001b C99Fh
(99h)
Wrap-Around Read data length
08h:support 8B wrap-around read
16h:8B&16B
32h:8B&16B&32B
64h:8B&16B&32B&64B
Individual block lock
0=not support 1=support
00
1b
Individual block lock bit
(Volatile/Nonvolatile)
0=Volatile 1=Nonvolatile
01
0b
09:02
0011 0110b
(36h)
10
0b
11
1b
Individual block lock Opcode
Individual block lock Volatile
protect bit default protect status
0=protect 1=unprotect
Secured OTP
0=not support 1=support
Read Lock
0=not support 1=support
12
0b
Permanent Lock
0=not support 1=support
13
0b
Unused
15:14
11b
Unused
31:16
FFh
P/N: PM1676
67
6Bh:68h
C8D9h
FFh
REV. 1.3, MAY 28, 2012
MX25L12835E
Note 1: h/b is hexadecimal or binary.
Note 2: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x),
address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1), (2-2-2),
and (4-4-4)
Note 3: Wait States is required dummy clock cycles after the address bits or optional mode bits.
Note 4: Mode Bits is optional control bits that follow the address bits. These bits are driven by the system
controller if they are specified. (eg,read performance enhance toggling bits)
Note 5: 4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h
Note 6: 0xFFh means all data is blank ("1b").
P/N: PM1676
68
REV. 1.3, MAY 28, 2012
MX25L12835E
11. POWER-ON STATE
The device is at below states when power-up:
- Standby mode (please note it is not Deep Power-down mode)
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage unless the VCC achieves below correct level:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal Power-on Reset (POR) circuit may protect the device from data corruption and inadvertent data
change during power up state.
For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is
not guaranteed. The read, write, erase, and program command should be sent after the time delay:
- tVSL after VCC reached VCC minimum level
The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended. (generally around 0.1uF)
P/N: PM1676
69
REV. 1.3, MAY 28, 2012
MX25L12835E
12. ELECTRICAL SPECIFICATIONS
12-1.
ABSOLUTE MAXIMUM RATINGS
RATING
VALUE
Ambient Operating Temperature
Industrial grade
-40°C to 85°C
Storage Temperature
-65°C to 150°C
Applied Input Voltage
-0.5V to 4.6V
Applied Output Voltage
-0.5V to 4.6V
VCC to Ground Potential
-0.5V to 4.6V
NOTICE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage
to the device. This is stress rating only and functional operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended period may affect reliability.
2. Specifications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see
the figures below.
Figure 45. Maximum Positive Overshoot Waveform
Figure 44. Maximum Negative Overshoot Waveform
20ns
20ns
20ns
Vcc + 2.0V
Vss
Vcc
Vss-2.0V
20ns
12-2.
20ns
20ns
CAPACITANCE TA = 25°C, f = 1.0 MHz
Symbol Parameter
CIN
COUT
Min.
Typ.
Max.
Unit
Input Capacitance
20
pF
VIN = 0V
Output Capacitance
20
pF
VOUT = 0V
P/N: PM1676
70
Conditions
REV. 1.3, MAY 28, 2012
MX25L12835E
Figure 46. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL
Input timing reference level
0.8VCC
0.2VCC
0.7VCC
0.3VCC
Output timing reference level
AC
Measurement
Level
0.5VCC
Note: Input pulse rise and fall time are
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