MX25L1673E
MX25L1673E
HIGH PERFORMANCE
SERIAL FLASH SPECIFICATION
P/N: PM1912
1
REV. 1.2, JAN. 14, 2014
MX25L1673E
Contents
1. FEATURES......................................................................................................................................................... 4
2. GENERAL DESCRIPTION................................................................................................................................ 6
Table 1. Additional Feature......................................................................................................................6
3. PIN CONFIGURATION....................................................................................................................................... 7
4. PIN DESCRIPTION............................................................................................................................................. 7
5. BLOCK DIAGRAM.............................................................................................................................................. 8
6. DATA PROTECTION........................................................................................................................................... 9
Table 2. Protected Area Sizes...............................................................................................................10
Table 3. 512-bit Secured OTP Definition...............................................................................................10
7. MEMORY ORGANIZATION...............................................................................................................................11
Table 4. Memory Organization.............................................................................................................. 11
8. DEVICE OPERATION....................................................................................................................................... 12
9. COMMAND DESCRIPTION.............................................................................................................................. 13
Table 5. Command Sets........................................................................................................................13
9-1. Write Enable (WREN)...........................................................................................................................15
9-2. Write Disable (WRDI)............................................................................................................................16
9-3. Read Identification (RDID)....................................................................................................................17
9-4. Read Status Register (RDSR)..............................................................................................................18
9-5. Write Status Register (WRSR)..............................................................................................................20
Table 6. Protection Modes.....................................................................................................................21
9-6. Read Data Bytes (READ).....................................................................................................................23
9-7. Read Data Bytes at Higher Speed (FAST_READ)...............................................................................24
9-8. Dual Read Mode (DREAD)...................................................................................................................25
9-9. 2 x I/O Read Mode (2READ)................................................................................................................26
9-10. Quad Read Mode (QREAD).................................................................................................................27
9-11. 4 x I/O Read Mode (4READ)................................................................................................................28
9-12. Performance Enhance Mode................................................................................................................29
9-13. Performance Enhance Mode Reset (FFh)............................................................................................29
9-14. Sector Erase (SE).................................................................................................................................32
9-15. Block Erase (BE)..................................................................................................................................33
9-16. Chip Erase (CE)....................................................................................................................................34
9-17. Page Program (PP)..............................................................................................................................35
9-18. 4 x I/O Page Program (4PP).................................................................................................................36
9-19. Deep Power-down (DP)........................................................................................................................37
9-20. Release from Deep Power-down (RDP), Read Electronic Signature (RES)........................................38
9-21. Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4)......................................40
9-22. ID Read.................................................................................................................................................41
Table 7. ID Definitions ..........................................................................................................................41
9-23. Enter Secured OTP (ENSO).................................................................................................................41
9-24. Exit Secured OTP (EXSO)....................................................................................................................41
9-25. Read Security Register (RDSCUR)......................................................................................................42
Table 8. Security Register Definition.....................................................................................................42
9-26. Write Security Register (WRSCUR)......................................................................................................43
9-27. Read SFDP Mode (RDSFDP)...............................................................................................................44
Table 9. Signature and Parameter Identification Data Values ..............................................................45
P/N: PM1912
2
REV. 1.2, JAN. 14, 2014
MX25L1673E
Table 10. Parameter Table (0): JEDEC Flash Parameter Tables..........................................................46
Table 11. Parameter Table (1): Macronix Flash Parameter Tables........................................................48
10. POWER-ON STATE........................................................................................................................................ 50
11. ELECTRICAL SPECIFICATIONS................................................................................................................... 51
11-1. Absolute Maximum Ratings..................................................................................................................51
11-2. Capacitance..........................................................................................................................................51
Table 12. DC Characteristics.................................................................................................................53
Table 13. AC Characteristics.................................................................................................................54
12. TIMING ANALYSIS......................................................................................................................................... 55
Table 14. Power-Up Timing ..................................................................................................................56
12-1. Initial Delivery State..............................................................................................................................56
13. OPERATING CONDITIONS............................................................................................................................ 57
14. ERASE AND PROGRAMMING PERFORMANCE......................................................................................... 59
15. DATA RETENTION......................................................................................................................................... 59
16. LATCH-UP CHARACTERISTICS................................................................................................................... 59
17. ORDERING INFORMATION........................................................................................................................... 60
18. PART NAME DESCRIPTION.......................................................................................................................... 61
19. REVISION HISTORY ...................................................................................................................................... 64
P/N: PM1912
3
REV. 1.2, JAN. 14, 2014
MX25L1673E
16M-BIT [x 1/x 2/x 4] CMOS MXSMIO® (SERIAL MULTI I/O) FLASH MEMORY
1. FEATURES
GENERAL
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
• 16,777,216 x 1 bit structure or 8,388,608 x 2 bits (two I/O read mode) structure or 4,194,304 x 4 bits (four I/O
read mode) structure
• 512 Equal Sectors with 4K byte each
- Any Sector can be erased individually
• 32 Equal Blocks with 64K byte each
- Any Block can be erased individually
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
• Permanent fixed QE bit, QE =1 and 4 I/O mode is enabled
PERFORMANCE
• High Performance
- Fast read
- 1 I/O: 104MHz with 8 dummy cycles
- 2 I/O: 85MHz with 4 dummy cycles
- 4 I/O: 85MHz with 6 dummy cycles
- Fast access time: 104MHz serial clock
- Serial clock of four I/O read mode : 85MHz, which is equivalent to 340MHz
- Fast program time: 0.6ms(typ.) and 3ms(max.)/page (256-byte per page)
- Byte program time: 9us (typical)
- Fast erase time: 40ms (typ.)/sector (4K-byte per sector) ; 0.4s(typ.) /block (64K-byte per block); 5s(typ.) /chip
• Low Power Consumption
- Low active read current: 25mA(max.) at 104MHz and 10mA(max.) at 33MHz
- Low active programming current: 15mA (typ.)
- Low active sector erase current: 9mA (typ.)
- Low standby current: 15uA (typ.)
• Typical 100,000 erase/program cycles
• 20 years data retention
P/N: PM1912
4
REV. 1.2, JAN. 14, 2014
MX25L1673E
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block lock protection
The BP0-BP3 status bit defines the size of the area to be software protection against program and erase
instructions
- Additional 512-bit secured OTP for unique identifier
• Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected sector
- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse widths (Any page to be programed should have page in the erased state first)
• Status Register Feature
• Electronic Identification
- JEDEC 1-byte manufacturer ID and 2-byte device ID
- RES command for 1-byte Device ID
- Both REMS,REMS2 and REMS4 commands for 1-byte manufacturer ID and 1-byte device ID
• Support Serial Flash Discoverable Parameters (SFDP) mode
HARDWARE FEATURES
• SCLK Input
- Serial clock input
• SI/SIO0
- Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
• SO/SIO1
- Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
• SIO2
- Serial data Input/Output for 4 x I/O read mode
• SIO3
- Serial data Input/Output for 4 x I/O read mode
• PACKAGE
- 8-pin SOP (200mil)
- 8-WSON (6x5mm)
- All devices are RoHS Compliant & Halogen-free.
P/N: PM1912
5
REV. 1.2, JAN. 14, 2014
MX25L1673E
2. GENERAL DESCRIPTION
The MX25L1673E are 16,777,216 bit serial Flash memory, which is configured as 2,097,152 x 8 internally. When it
is in two or four I/O read mode, the structure becomes 8,388,608 bits x 2 or 4,194,304 bits x 4. The MX25L1673E
feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus
signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device
is enabled by CS# input.
When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input
and data output. When it is in four I/O read mode, the SI pin, SO pin become SIO0 pin and SIO1 pin, SIO2 pin and
SIO3 pin for address/dummy bits input and data Input/Output.
The MX25L1673E provides sequential read operation on whole chip.
After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis, and erase command is executes on sector (4K-byte), or block (64K-byte), or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
Advanced security features enhance the protection and security functions, please see security features section for
more details.
When the device is not in operation and CS# is high, it is put in standby mode.
The MX25L1673E utilizes Macronix proprietary memory cell, which reliably stores memory contents even after
100,000 program and erase cycles.
Table 1. Additional Feature
Protection and
Security
Additional
Features Flexible
Block
512-bit
Part
Protection secured
Name
(BP0OTP
BP3)
MX25L1673E
P/N: PM1912
V
V
Read
Performance
2 I/O
Read
4 I/O
Read
V
V
Identifier
RES
REMS
REMS2
REMS4
RDID
(command: (command: (command: (command: (command:
AB hex)
90 hex)
EF hex)
DF hex)
9F hex)
24 (hex)
6
C2 24 (hex) C2 24 (hex) C2 24 (hex) C2 24 15
(if ADD=0) (if ADD=0) (if ADD=0)
(hex)
REV. 1.2, JAN. 14, 2014
MX25L1673E
3. PIN CONFIGURATION
4. PIN DESCRIPTION
8-PIN SOP (200mil)
CS#
SO/SIO1
SIO2
GND
SYMBOL
CS#
1
2
3
4
8
7
6
5
VCC
SIO3
SCLK
SI/SIO0
SI/SIO0
SO/SIO1
SCLK
8-WSON (6x5mm)
CS#
SO/SIO1
SIO2
GND
P/N: PM1912
1
2
3
4
8
7
6
5
SIO2
VCC
SIO3
SCLK
SI/SIO0
SIO3
VCC
GND
7
DESCRIPTION
Chip Select
Serial Data Input (for 1 x I/O)/ Serial
Data Input & Output (for 2xI/O or 4xI/
O read mode)
Serial Data Output (for 1 x I/O)/
Serial Data Input & Output (for 2xI/O
or 4xI/O read mode)
Clock Input
Serial Data Input & Output (for 4xI/O
read mode)
Serial Data Input & Output (for 4xI/O
read mode)
+ 3.3V Power Supply
Ground
REV. 1.2, JAN. 14, 2014
MX25L1673E
5. BLOCK DIAGRAM
X-Decoder
Address
Generator
Memory Array
Page Buffer
SI/SIO0
Data
Register
Y-Decoder
SRAM
Buffer
Sense
Amplifier
CS#
SIO2
SIO3
SCLK
Mode
Logic
State
Machine
Clock Generator
Output
Buffer
SO/SIO1
P/N: PM1912
HV
Generator
8
REV. 1.2, JAN. 14, 2014
MX25L1673E
6. DATA PROTECTION
During power transition, there may be some false system level signals which result in inadvertent erasure or programming. The device is designed to protect itself from these accidental write cycles.
The state machine will be reset as standby mode automatically during power up. In addition, the control register architecture of the device constrains that the memory contents can only be changed after specific command sequences have completed successfully.
In the following, there are several features to protect the system from the accidental write cycles during VCC powerup and power-down or from system noise.
• Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
other command to change data. The WEL bit will return to reset stage under following situation:
- Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP, 4PP) command completion
- Sector Erase (SE) command completion
- Block Erase (BE) command completion
- Chip Erase (CE) command completion
• Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from
writing all commands except Release from deep power down mode command (RDP) and Read Electronic Signature command (RES).
• Advanced Security Features: there are some protection and securuity features which protect content from inadvertent write and hostile access.
I. Block lock protection
- The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected
as read only. The proected area definition is shown as table of "Protected Area Sizes", the protected areas are
more flexible which may protect various area by setting value of BP0-BP3 bits.
Please refer to table of "protected area sizes".
P/N: PM1912
9
REV. 1.2, JAN. 14, 2014
MX25L1673E
Table 2. Protected Area Sizes
Status bit
BP3
BP2
BP1
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
BP0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Protect Level
16Mb
0 (none)
1 (1block, protected block 31th)
2 (2blocks, protected block 30th-31th)
3 (4blocks, protected block 28th-31th)
4 (8blocks, protected block 24th-31th)
5 (16blocks, protected block 16th-31th)
6 (32blocks, protected all)
7 (32blocks, protected all)
8 (32blocks, protected all)
9 (32blocks, protected all)
10 (16blocks, protected block 0th-15th)
11 (24blocks, protected block 0th-23th)
12 (28blocks, protected block 0th-27th)
13 (30blocks, protected block 0th-29th)
14 (31blocks, protected block 0th-30th)
15 (32blocks, protected all)
II. Additional 512-bit secured OTP for unique identifier: to provide 512-bit one-time program area for setting device unique serial number - Which may be set by factory or system customer. Please refer to "Table 3. 512-bit
Secured OTP Definition"
- Security register bit 0 indicates whether the chip is locked by factory or not.
- To program the 512-bit secured OTP by entering 512-bit secured OTP mode (with ENSO command), and going
through normal program procedure, and then exiting 512-bit secured OTP mode by writing EXSO command.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register) command to set customer lock-down bit1 as "1". Please refer to table of "security register definition" for security register bit definition and table of "512-bit secured OTP definition" for address range definition.
- Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 512-bit secured
OTP mode, array access is not allowed.
Table 3. 512-bit Secured OTP Definition
Address range
Size
Standard Factory Lock
xxxx00~xxxx0F
128-bit
ESN (electrical serial number)
xxxx10~xxxx3F
384-bit
N/A
P/N: PM1912
10
Customer Lock
Determined by customer
REV. 1.2, JAN. 14, 2014
MX25L1673E
7. MEMORY ORGANIZATION
Table 4. Memory Organization
Block
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
P/N: PM1912
Sector
511
:
496
495
:
480
479
:
464
463
:
448
447
:
432
431
:
416
415
:
400
399
:
384
383
:
368
367
:
352
351
:
336
335
:
320
319
:
304
303
:
288
287
:
272
271
:
256
Block
Address Range
1FF000h
1FFFFFh
:
:
1F0000h
1F0FFFh
1EF000h
1EFFFFh
:
:
1E0000h
1E0FFFh
1DF000h
1DFFFFh
:
:
1D0000h
1D0FFFh
1CF000h
1CFFFFh
:
:
1C0000h
1C0FFFh
1BF000h
1BFFFFh
:
:
1B0000h
1B0FFFh
1AF000h
1AFFFFh
:
:
1A0000h
1A0FFFh
19F000h
19FFFFh
:
:
190000h
190FFFh
18F000h
18FFFFh
:
:
180000h
180FFFh
17F000h
17FFFFh
:
:
170000h
170FFFh
16F000h
16FFFFh
:
:
160000h
160FFFh
15F000h
15FFFFh
:
:
150000h
150FFFh
14F000h
14FFFFh
:
:
140000h
140FFFh
13F000h
13FFFFh
:
:
130000h
130FFFh
12F000h
12FFFFh
:
:
120000h
120FFFh
11F000h
11FFFFh
:
:
110000h
110FFFh
10F000h
10FFFFh
:
:
100000h
100FFFh
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
11
Sector
255
:
240
239
:
224
223
:
208
207
:
192
191
:
176
175
:
160
159
:
144
143
:
128
127
:
112
111
:
96
95
:
80
79
:
64
63
:
48
47
:
32
31
:
16
15
:
2
1
0
Address Range
0FF000h
0FFFFFh
:
:
0F0000h
0F0FFFh
0EF000h
0EFFFFh
:
:
0E0000h
0E0FFFh
0DF000h
0DFFFFh
:
:
0D0000h
0D0FFFh
0CF000h
0CFFFFh
:
:
0C0000h
0C0FFFh
0BF000h
0BFFFFh
:
:
0B0000h
0B0FFFh
0AF000h
0AFFFFh
:
:
0A0000h
0A0FFFh
09F000h
09FFFFh
:
:
090000h
090FFFh
08F000h
08FFFFh
:
:
080000h
080FFFh
07F000h
07FFFFh
:
:
070000h
070FFFh
06F000h
06FFFFh
:
:
060000h
060FFFh
05F000h
05FFFFh
:
:
050000h
050FFFh
04F000h
04FFFFh
:
:
040000h
040FFFh
03F000h
03FFFFh
:
:
030000h
030FFFh
02F000h
02FFFFh
:
:
020000h
020FFFh
01F000h
01FFFFh
:
:
010000h
010FFFh
00F000h
00FFFFh
:
:
002000h
002FFFh
001000h
001FFFh
000000h
000FFFh
REV. 1.2, JAN. 14, 2014
MX25L1673E
8. DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation.
2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode
until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z.
3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until
next CS# rising edge.
4. For standard single data rate serial mode, input data is latched on the rising edge of Serial Clock(SCLK) and
data shifts out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as "Figure 1.
Serial Modes Supported (for Normal Serial mode)" .
5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, RDSFDP, 2READ, DREAD,
4READ, QREAD, RES, REMS, REMS2, and REMS4 the shifted-in instruction sequence is followed by a dataout sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN,
WRDI, WRSR, SE, BE, CE, PP, 4PP, RDP, DP, ENSO, EXSO,and WRSCUR, the CS# must go high exactly at
the byte boundary; otherwise, the instruction will be rejected and not executed.
6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglected and not affect the current operation of Write Status Register, Program, Erase.
Figure 1. Serial Modes Supported (for Normal Serial mode)
CPOL
CPHA
shift in
(Serial mode 0)
0
0
SCLK
(Serial mode 3)
1
1
SCLK
SI
shift out
MSB
SO
MSB
Note:
CPOL indicates clock polarity of Serial master,
-CPOL=1 for SCLK high while idle,
-CPOL=0 for SCLK low while not transmitting.
CPHA indicates clock phase.
The combination of CPOL bit and CPHA bit decides which Serial mode is supported.
P/N: PM1912
12
REV. 1.2, JAN. 14, 2014
MX25L1673E
9. COMMAND DESCRIPTION
Table 5. Command Sets
Read Commands
Command
(byte)
READ (read
data)
1st byte
03 (hex)
AD1
(A23-A16)
AD2
(A15-A8)
AD3
(A7-A0)
2nd byte
3rd byte
4th byte
5th byte
Action
P/N: PM1912
n bytes read
out until CS#
goes high
DREAD
QREAD
FAST READ
RDSFDP
2READ (2 x I/O
4READ (4 x I/O
(1I / 2O read
(1I / 4O read
(fast read data) (Read SFDP) read command)
read command)
command)
command)
0B (hex)
5A (hex)
BB (hex)
3B (hex)
EB (hex)
6B (hex)
AD1
AD1
ADD
AD1
ADD & Dummy
AD1
AD2
AD2
ADD & Dummy
AD2
Dummy
AD2
AD3
AD3
Dummy
n bytes read
out until CS#
goes high
Dummy
Read SFDP
mode
AD3
n bytes
read out
by 2 x I/O until
CS# goes high
13
Dummy
AD3
n bytes read
out by 4 x I/O
until CS# goes
high
Dummy
REV. 1.2, JAN. 14, 2014
MX25L1673E
Other Commands
Command
(byte)
WREN (write
enable)
WRDI
(write disable)
1st byte
06 (hex)
04 (hex)
RDID
RDSR (read
WRSR (write
4PP (quad
(read identificstatus register) status register) page program)
ation)
9F (hex)
05 (hex)
2nd byte
01 (hex)
38 (hex)
20 (hex)
Values
AD1
AD1
3rd byte
AD2
4th byte
Action
SE (sector
erase)
sets the (WEL)
resets the
outputs JEDEC to read out the to write new
write enable
(WEL) write
ID: 1-byte
values of the
values of the
latch bit
enable latch bit Manufact-urer status register status register
ID & 2-byte
Device ID
AD3
quad input to
to erase the
program the selected sector
selected page
Command
(byte)
BE (block
erase)
CE (chip erase)
PP (page
program)
DP (Deep
power down)
RDP (Release
from deep
power down)
RES (read
electronic ID)
1st byte
D8 (hex)
60 or C7 (hex)
02 (hex)
B9 (hex)
AB (hex)
AB (hex)
FFh (hex)
2nd byte
AD1
AD1
x
x
3rd byte
AD2
AD2
x
x
x
to read out
1-byte Device
ID
x
All these
commands
FFh, 00h, AAh
or 55h will
escape the
performance
enhance mode
4th byte
AD3
AD3
to erase the to erase whole to program the
selected block
chip
selected page
enters deep
power down
mode
release from
deep power
down mode
REMS4 (read
ID for 4x I/O
mode)
ENSO (enter
secured OTP)
EXSO (exit
secured OTP)
RDSCUR
(read security
register)
WRSCUR
(write security
register)
DF (hex)
B1 (hex)
C1 (hex)
2B (hex)
2F (hex)
Action
REMS (read
REMS2 (read
Command
electronic
ID for 2x I/O
(byte)
manufacturer &
mode)
device ID)
1st byte
90 (hex)
EF (hex)
2nd byte
x
X
x
3rd byte
x
X
x
4th byte
Action
Release Read
Enhanced
ADD (Note3)
ADD (Note3)
ADD (Note3)
to enter the to exit the 512- to read value of to set the lockoutput the
output the
output the
Manufacturer Manufacturer Manufacturer 512-bit secured bit secured security register down bit as
ID & Device ID ID & Device ID ID & Device ID
OTP mode
OTP mode
"1" (once lockdown, cannot
be update)
Note 3: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first.
Note 4: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden mode.
P/N: PM1912
14
REV. 1.2, JAN. 14, 2014
MX25L1673E
9-1.
Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP,
4PP, SE, BE, CE, and WRSR, which are intended to change the device content, should be set every time after the
WREN instruction setting the WEL bit.
The sequence of issuing WREN instruction is: CS# goes low→ sending WREN instruction code→ CS# goes high.
The SIO[3:1] are don't care in this mode.
Figure 2. Write Enable (WREN) Sequence (Command 06)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
SO
P/N: PM1912
06h
High-Z
15
REV. 1.2, JAN. 14, 2014
MX25L1673E
9-2.
Write Disable (WRDI)
The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.
The sequence of issuing WRDI instruction is: CS# goes low→ sending WRDI instruction code→ CS# goes high.
The WEL bit is reset by following situations:
- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP, 4PP) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase (BE) instruction completion
- Chip Erase (CE) instruction completion
Figure 3. Write Disable (WRDI) Sequence (Command 04)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
SO
P/N: PM1912
04h
High-Z
16
REV. 1.2, JAN. 14, 2014
MX25L1673E
9-3.
Read Identification (RDID)
The RDID instruction is for reading the Manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Macronix Manufacturer ID is C2(hex), the memory type ID is as the first-byte Device ID, and the individual Device ID of
second-byte ID are listed as table of "Table 7. ID Definitions".
The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code → 24-bits ID data out
on SO→ to end RDID operation can use CS# to high at any time during data out.
While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.
Figure 4. Read Identification (RDID) Sequence (Command 9F)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
28 29 30 31
SCLK
Command
SI
9Fh
Manufacturer Identification
SO
High-Z
7
6
5
3
MSB
P/N: PM1912
2
1
Device Identification
0 15 14 13
3
2
1
0
MSB
17
REV. 1.2, JAN. 14, 2014
MX25L1673E
9-4.
Read Status Register (RDSR)
The RDSR instruction is for reading Status Register. The Read Status Register can be read at any time (even in
program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP)
bit before sending a new instruction when a program, erase, or write status register operation is in progress.
The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register
data out on SO.
The SIO[3:1] are don't care when during this mode.
Figure 5. Read Status Register (RDSR) Sequence (Command 05)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
command
05h
SI
SO
High-Z
Status Register Out
7
6
5
4
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
P/N: PM1912
3
Status Register Out
18
REV. 1.2, JAN. 14, 2014
MX25L1673E
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write
status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status
register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status
register cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable
latch. When WEL bit sets to "1", which means the internal write enable latch is set, the device can accept program/
erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. The program/erase command will be ignored and
will reset WEL bit if it is applied to a protected memory area. To ensure both WIP bit & WEL bit are both set to 0 and
available for next program/erase/operations, WIP bit needs to be confirm to be 0 before polling WEL bit. After WIP bit
confirmed, WEL bit needs to be confirm to be 0.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area (as
defined in "Table 2. Protected Area Sizes") of the device to against the program/erase instruction without hardware
protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register
(WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP),
Sector Erase (SE), Block Erase (BE) and Chip Erase (CE) instructions (only if all Block Protect bits set to 0, the CE
instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as default. Which is un-protected.
QE bit. The Quad Enable (QE) bit, a non-volatile bit which is permanently set to "1". The flash always performs
Quad I/O mode.
SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, default value is "0".
Status Register
bit7
bit6
SRWD (status
register write
protect)
QE
(Quad
Enable)
1=status
register write
disable
1=Quad
Enable
0=status
register write
enable
Non-volatile
bit
bit5
BP3
(level of
protected
block)
bit4
BP2
(level of
protected
block)
bit3
BP1
(level of
protected
block)
bit2
BP0
(level of
protected
block)
(Note)
(Note)
(Note)
(Note)
Non-volatile
bit
Non-volatile
bit
Non-volatile
bit
Non-volatile
bit
bit1
bit0
WEL
WIP
(write enable
(write in
latch)
progress bit)
1=write
enable
0=not write
enable
1=write
operation
0=not in write
operation
volatile bit
volatile bit
Note: See the "Table 2. Protected Area Sizes".
P/N: PM1912
19
REV. 1.2, JAN. 14, 2014
MX25L1673E
9-5.
Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the
Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1, BP0) bits to define the protected area of memory (as shown in "Table 2. Protected Area Sizes"). The WRSR can reset the Status Register
Write Disable (SRWD) bit, but has no effect on bit1 (WEL) and bit0 (WIP) of the status register.
The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register
data on SI→ CS# goes high.
Figure 6. Write Status Register (WRSR) Sequence (Command 01)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
command
SI
SO
P/N: PM1912
01
High-Z
Status
Register In
7
6
5
4
3
2
1
0
MSB
20
REV. 1.2, JAN. 14, 2014
MX25L1673E
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be checked out during the Write Status Register cycle is in progress. The WIP sets 1
during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL)
bit is reset.
Table 6. Protection Modes
Mode
Software protection
mode (SPM)
Status register condition
SRWD bit status
Memory
Status register can be written
in (WEL bit is set to "1") and
the SRWD, BP0-BP3
bits can be changed
SRWD bit=0
The protected area cannot
be programmed or erased.
Note: As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in
"Table 2. Protected Area Sizes".
Software Protected Mode (SPM):
- When SRWD bit=0, the WREN instruction may set the WEL bit and can change the values of SRWD, BP3,
BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM).
P/N: PM1912
21
REV. 1.2, JAN. 14, 2014
MX25L1673E
Figure 7. WRSR flow
start
WREN command
RDSR command
WEL=1?
No
Yes
WRSR command
Write status register data
RDSR command
WIP=0?
No
Yes
RDSR command
Read WEL=0, BP[3:0], QE,
and SRWD data
Verify OK?
No
Yes
WRSR successfully
P/N: PM1912
WRSR fail
22
REV. 1.2, JAN. 14, 2014
MX25L1673E
9-6.
Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on
the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address
is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can
be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been
reached.
The sequence of issuing READ instruction is: CS# goes low→ sending READ instruction code→3-byte address on
SI →data out on SO→ to end READ operation can use CS# to high at any time during data out.
Figure 8. Read Data Bytes (READ) Sequence (Command 03)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
SI
03
24 ADD Cycles
A23 A22 A21
A3 A2 A1 A0
MSB
SO
Data Out 1
High-Z
D7 D6 D5 D4 D3 D2 D1 D0 D7
MSB
P/N: PM1912
Data Out 2
23
MSB
REV. 1.2, JAN. 14, 2014
MX25L1673E
9-7.
Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and
data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at
any location. The address is automatically increased to the next higher address after each byte data is shifted out,
so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when
the highest address has been reached.
The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ instruction code→
3-byte address on SI→1-dummy byte (default) address on SI→ data out on SO→ to end FAST_READ operation
can use CS# to high at any time during data out.
In the performance-enhancing mode, P[7:4] must be toggling with P[3:0] ; likewise P[7:0]=A5h,5Ah,F0h or 0Fh can
make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0]; likewise P[7:0]=FFh,00h,AAh or 55h and afterwards CS# is raised and then lowered, the system then will escape from
performance enhance mode and return to normal operation.
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle.
Figure 9. Read at Higher Speed (FAST_READ) Sequence (Command 0B) (104MHz)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
SO
24 BIT ADDRESS
23 22 21
0Bh
3
2
1
0
High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Cycle
SI
7
6
5
4
3
2
1
0
DATA OUT 2
DATA OUT 1
SO
7
6
4
3
2
1
0
7
MSB
MSB
P/N: PM1912
5
24
6
5
4
3
2
1
0
7
MSB
REV. 1.2, JAN. 14, 2014
MX25L1673E
9-8.
Dual Read Mode (DREAD)
The DREAD instruction enable double throughput of Serial Flash in read mode. The address is latched on rising
edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruction, the following data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing DREAD instruction is: CS# goes low → sending DREAD instruction → 3-byte address on
SI → 8-bit dummy cycle → data out interleave on SO1 & SO0 → to end DREAD operation can use CS# to high at
any time during data out.
While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
Figure 10. Dual Read Mode Sequence (Command 3B)
CS#
0
1
2
3
4
5
6
7
8
…
Command
SI/SIO0
SO/SIO1
P/N: PM1912
30 31 32
9
SCLK
3B
…
24 ADD Cycle
A23 A22
…
High Impedance
39 40 41 42 43 44 45
A1 A0
8 dummy
cycle
Data Out
1
Data Out
2
D6 D4 D2 D0 D6 D4
D7 D5 D3 D1 D7 D5
25
REV. 1.2, JAN. 14, 2014
MX25L1673E
9-9.
2 x I/O Read Mode (2READ)
The 2READ instruction enables Double Transfer Rate of Serial Flash in read mode. The address is latched on rising
edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 24-bit address interleave on SIO1 & SIO0→ 4-bit dummy cycles on SIO1 & SIO0→ data out interleave on SIO1 & SIO0→ to end
2READ operation can use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
Figure 11. 2 x I/O Read Mode Sequence (Command BB)
CS#
0
1
2
3
4
5
6
7
8
SCLK
…
Command
SI/SIO0
SO/SIO1
18 19 20 21 22 23 24 25 26 27 28 29
9
BB(hex)
High Impedance
12 ADD Cycle
4 dummy
cycle
Data Out
1
Data Out
2
A22 A20
…
A2 A0 P2 P0
D6 D4 D2 D0 D6 D4
A23 A21
…
A3 A1 P3 P1
D7 D5 D3 D1 D7 D5
Note: SI/SIO0 or SO/SIO1 should be kept "0h" or "Fh" in the first two dummy cycles. In other words, P2=P0 or
P3=P1 is necessary.
P/N: PM1912
26
REV. 1.2, JAN. 14, 2014
MX25L1673E
9-10.
Quad Read Mode (QREAD)
The QREAD instruction enable quad throughput of Serial Flash in read mode. The address is latched on rising edge
of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum
frequency fQ. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single QREAD instruction.
The address counter rolls over to 0 when the highest address has been reached. Once writing QREAD instruction,
the following data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing QREAD instruction is: CS# goes low→ sending QREAD instruction → 3-byte address on
SI → 8-bit dummy cycle → data out interleave on SO3, SO2, SO1 & SO0→ to end QREAD operation can use
CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
Figure 12. Quad Read Mode Sequence (Command 6B)
CS#
0
1
2
3
4
5
6
7
8
SCLK
…
Command
SI/SO0
SO/SO1
SO2
SO3
P/N: PM1912
29 30 31 32 33
9
6B
…
24 ADD Cycles
A23 A22
…
High Impedance
38 39 40 41 42
A2 A1 A0
8 dummy cycles
Data Data
Out 1 Out 2
Data
Out 3
D4 D0 D4 D0 D4
D5 D1 D5 D1 D5
High Impedance
D6 D2 D6 D2 D6
High Impedance
D7 D3 D7 D3 D7
27
REV. 1.2, JAN. 14, 2014
MX25L1673E
9-11.
4 x I/O Read Mode (4READ)
The 4READ instruction enables quad throughput of Serial Flash in read mode. The address is latched on rising
edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ. The first address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing 4READ instruction is: CS# goes low→ sending 4READ instruction→ 24-bit address interleave on SIO3, SIO2, SIO1 & SIO0→ 2+4 dummy cycles→ data out interleave on SIO3, SIO2, SIO1 & SIO0→ to
end 4READ operation can use CS# to high at any time during data out.
Figure 13. 4 x I/O Read Mode Sequence (Command EB)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
n
SCLK
8 Bit Instruction
SI/SIO0
SO/SIO1
SIO2
SIO3
6 Address cycles
Performance
enhance
indicator (Note)
4 dummy
cycles
Data Output
address
bit20, bit16..bit0
P4 P0
data
bit4, bit0, bit4....
High Impedance
address
bit21, bit17..bit1
P5 P1
data
bit5 bit1, bit5....
High Impedance
address
bit22, bit18..bit2
P6 P2
data
bit6 bit2, bit6....
High Impedance
address
bit23, bit19..bit3
P7 P3
data
bit7 bit3, bit7....
EB(hex)
Note:
1. Hi-impedance is inhibited for the two clock cycles.
2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited.
P/N: PM1912
28
REV. 1.2, JAN. 14, 2014
MX25L1673E
Another sequence of issuing 4READ instruction especially useful in random access is : CS# goes low→ sending
4READ instruction→ 3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 →performance enhance toggling bit
P[7:0]→ 4 dummy cycles→ data out until CS# goes high → CS# goes low (reduce 4 Read instruction) → 24-bit random access address (Please refer to "Figure 14. 4 x I/O Read enhance performance Mode Sequence (Command
EB)" ).
In the performance-enhancing mode (Notes of "Figure 14. 4 x I/O Read enhance performance Mode Sequence
(Command EB)"), P[7:4] must be toggling with P[3:0]; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh can make this mode
continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0]; likewise P[7:0]=FFh,
00h, AAh or 55h. These commands will reset the performance enhance mode. And afterwards CS# is raised and
then lowered, the system then will return to normal operation.
While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
9-12.
Performance Enhance Mode
The device could waive the command cycle bits if the two cycle bits after address cycle toggles. (Please note "Figure 14. 4 x I/O Read enhance performance Mode Sequence (Command EB)")
Please be noticed that “EBh” and “E7h” commands support enhance mode. The performance enhance mode is not
supported in dual I/O mode.
After entering enhance mode, following CSB go high, the device will stay in the read mode and treat CSB go low of
the first clock as address instead of command cycle.
To exit enhance mode, a new fast read command whose first two dummy cycles is not toggle then exit. Or issue
”FFh” command to exit enhance mode.
9-13.
Performance Enhance Mode Reset (FFh)
To conduct the Performance Enhance Mode Reset operation, FFh command code, 8 clocks, should be issued in 1I/
O sequence.
If the system controller is being Reset during operation, the flash device will return to the standard operation.
Upon Reset of main chip, Instruction would be issued from the system. Instructions like Read ID (9Fh) or Fast Read
(0Bh) would be issued.
The SIO[3:1] are don't care when during this mode.
P/N: PM1912
29
REV. 1.2, JAN. 14, 2014
MX25L1673E
Figure 14. 4 x I/O Read enhance performance Mode Sequence (Command EB)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
n
SCLK
8 Bit Instruction
SIO2
SIO3
Performance
enhance
indicator (Note)
4 dummy
cycles
Data Output
address
bit20, bit16..bit0
P4 P0
data
bit4, bit0, bit4....
High Impedance
address
bit21, bit17..bit1
P5 P1
data
bit5 bit1, bit5....
High Impedance
address
bit22, bit18..bit2
P6 P2
data
bit6 bit2, bit6....
High Impedance
address
bit23, bit19..bit3
P7 P3
data
bit7 bit3, bit7....
EB(hex)
SI/SIO0
SO/SIO1
6 Address cycles
CS#
n+1
...........
n+7 ...... n+9
........... n+13
...........
SCLK
6 Address cycles
Performance
enhance
indicator (Note)
4 dummy
cycles
Data Output
SI/SIO0
address
bit20, bit16..bit0
P4 P0
data
bit4, bit0, bit4....
SO/SIO1
address
bit21, bit17..bit1
P5 P1
data
bit5 bit1, bit5....
SIO2
address
bit22, bit18..bit2
P6 P2
data
bit6 bit2, bit6....
SIO3
address
bit23, bit19..bit3
P7 P3
data
bit7 bit3, bit7....
Note: Performance enhance mode, if P7=P3 & P6=P2 & P5=P1 & P4=P0 (Toggling), ex: A5, 5A, 0F
Note:
Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF
1. Performance enhance mode, if P7≠P3 & P6≠P2 & P5≠P1 & P4≠P0 (Toggling), ex: A5, 5A, 0F, if not using
performance enhance recommend to keep 1 or 0 in performance enhance indicator.
Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF
P/N: PM1912
30
REV. 1.2, JAN. 14, 2014
MX25L1673E
Figure 15. Performance Enhance Mode Reset for Fast Read Quad I/O
Mode Bit Reset
for Quad I/O
CS#
Mode 3
SCLK
P/N: PM1912
０ 1
2
3
4
5
6
Mode ０
7
Mode 3
Mode ０
SIO0
FFh
SIO1
Don’t Care
SIO2
Don’t Care
SIO3
Don’t Care
31
REV. 1.2, JAN. 14, 2014
MX25L1673E
9-14.
Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for
any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before
sending the Sector Erase (SE). Any address of the sector (see "Table 4. Memory Organization" ) is a valid address
for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address
byte has been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing SE instruction is: CS# goes low → sending SE instruction code→ 3-byte address on SI
→CS# goes high.
The SIO[3:1] are don't care when during this mode.
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked out during the Sector Erase cycle is in progress. The WIP sets 1 during the tSE
timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page
is protected by BP3, BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the page.
Figure 16. Sector Erase (SE) Sequence (Command 20)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
24 Bit Address
Command
SI
23 22
20h
2
1
0
MSB
P/N: PM1912
32
REV. 1.2, JAN. 14, 2014
MX25L1673E
9-15.
Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for
64K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL)
bit before sending the Block Erase (BE). Any address of the block (see "Table 4. Memory Organization" ) is a valid
address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of
address byte has been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE instruction is: CS# goes low → sending BE instruction code → 3-byte address on SI →
CS# goes high.
The SIO[3:1] are don't care when during this mode.
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked out during the Sector Erase cycle is in progress. The WIP sets 1 during the tBE
timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page
is protected by BP3, BP2, BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the page.
Figure 17. Block Erase (BE) Sequence (Command D8)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
SI
24 Bit Address
23 22
D8h
2
1
0
MSB
P/N: PM1912
33
REV. 1.2, JAN. 14, 2014
MX25L1673E
9-16.
Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must go
high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The sequence of issuing CE instruction is: CS# goes low → sending CE instruction code → CS# goes high.
The SIO[3:1] are don't care when during this mode.
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE
timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is
protected, the Chip Erase (CE) instruction will not be executed, but WEL will be reset.
Figure 18. Chip Erase (CE) Sequence (Command 60 or C7)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
P/N: PM1912
60h or C7h
34
REV. 1.2, JAN. 14, 2014
MX25L1673E
9-17.
Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction
must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device programs
only the last 256 data bytes sent to the device. The last address byte (the 8 least significant address bits, A7-A0)
should be set to 0 for 256 bytes page program. If A7-A0 are not all zero, transmitted data that exceed page length
are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently selected page. If the
data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the request page and previous
data will be disregarded. If the data bytes sent to the device has not exceeded 256, the data will be programmed at
the request address of the page. There will be no effort on the other data bytes of the same page.
The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→ at
least 1-byte on data on SI→ CS# goes high.
The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte
boundary (the latest eighth bit of data being latched in), otherwise, the instruction will be rejected and will not be
executed.
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked out during the Page Program cycle is in progress. The WIP sets 1 during
the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If
the page is protected by BP3~0, the array data will be protected (no change) and the WEL bit will still be reset.
The SIO[3:1] are don't care when during this mode.
Figure 19. Page Program (PP) Sequence (Command 02)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
1
0
7
6
5
3
2
1
0
2079
2
2078
3
2077
23 22 21
02h
SI
Data Byte 1
2076
24-Bit Address
2075
Command
4
1
0
MSB
MSB
2074
2073
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
2072
CS#
SCLK
Data Byte 2
SI
7
6
MSB
P/N: PM1912
5
4
3
2
Data Byte 3
1
0
7
6
5
MSB
4
3
2
Data Byte 256
1
0
7
6
5
4
3
2
MSB
35
REV. 1.2, JAN. 14, 2014
MX25L1673E
9-18.
4 x I/O Page Program (4PP)
The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN)
instruction must execute to set the Write Enable Latch (WEL) bit. The Quad Page Programming takes four pins:
SIO0, SIO1, SIO2, and SIO3, which can raise programmer performance and the effectiveness of application of
lower clock less than 85MHz. For system with faster clock, the Quad page program cannot provide more actual
favors, because the required internal page program time is far more than the time data flows in. Therefore, we
suggest that while executing this command (especially during sending data), user can slow the clock speed down to
85MHz below. The other function descriptions are as same as standard page program.
The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on
SIO[3:0]→ at least 1-byte on data on SIO[3:0]→ CS# goes high.
If the page is protected by BP3~0, the array data will be protected (no change) and the WEL bit will still be reset.
Figure 20. 4 x I/O Page Program (4PP) Sequence (Command 38)
CS#
0
1
2
3
4
5
6
7
8
SCLK
…
Command
6 ADD cycles
Data
Byte 256
Data Data
Byte 1 Byte 2
A20 A16 A12 A8 A4 A0 D4 D0 D4 D0
…
D4 D0
SO/SIO1
A21 A17 A13 A9 A5 A1 D5 D1 D5 D1
…
D5 D1
SIO2
A22 A18 A14 A10 A6 A2 D6 D2 D6 D2
…
D6 D2
SIO3
A23 A19 A15 A11 A7 A3 D7 D3 D7 D3
…
D7 D3
SI/SIO0
P/N: PM1912
524 525
9 10 11 12 13 14 15 16 17
38
36
REV. 1.2, JAN. 14, 2014
MX25L1673E
9-19.
Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to entering the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode
requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instructions are ignored. When CS# goes high, it's only in standby mode not deep
power-down mode. It's different from Standby mode.
The sequence of issuing DP instruction is: CS# goes low→ sending DP instruction code→ CS# goes high.
The SIO[3:1] are don't care when during this mode.
Once the DP instruction is set, all instructions will be ignored except the Release from Deep Power-down mode (RDP)
and Read Electronic Signature (RES) instruction. (those instructions allow the ID being reading out). When Powerdown, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby
mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction
code has been latched-in); otherwise, the instruction will not be executed. As soon as Chip Select (CS#) goes high,
a delay of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2.
Figure 21. Deep Power-down (DP) Sequence (Command B9)
CS#
0
1
2
3
4
5
6
7
tDP
SCLK
Command
SI
B9h
Stand-by Mode
P/N: PM1912
37
Deep Power-down Mode
REV. 1.2, JAN. 14, 2014
MX25L1673E
9-20.
Release from Deep Power-down (RDP), Read Electronic Signature (RES)
The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip
Select (CS#) is driven High, the device is put in the standby Power mode. If the device was not previously in the
Deep Power-down mode, the transition to the standby Power mode is immediate. If the device was previously in the
Deep Power-down mode, though, the transition to the standby Power mode is delayed by tRES2, and Chip Select
(CS#) must remain High for at least tRES2(max), as specified in "Table 13. AC Characteristics". Once in the standby mode, the device waits to be selected, so that it can receive, decode and execute instructions.
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as "Table 7.
ID Definitions". This is not the same as RDID instruction. It is not recommended to use for new design. For new
design, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be
executed, only except the device is in progress of program/erase/write cycles; there's no effect on the current program/erase/write cycles in progress.
The SIO[3:1] are don't care when during this mode.
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously
in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in
Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least
tRES2(max). Once in the standby mode, the device waits to be selected, so it can receive, decode, and execute
instruction.
The RDP instruction is for releasing from Deep Power-down Mode.
Figure 22. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38
SCLK
Command
SI
ABh
tRES2
3 Dummy Bytes
23 22 21
3
2
1
0
MSB
SO
Electronic Signature Out
High-Z
7
6
5
4
3
2
1
0
MSB
Deep Power-down Mode
P/N: PM1912
38
Stand-by Mode
REV. 1.2, JAN. 14, 2014
MX25L1673E
Figure 23. Release from Deep Power-down (RDP) Sequence (Command AB)
CS#
0
1
2
3
4
5
6
tRES1
7
SCLK
Command
SI
SO
ABh
High-Z
Deep Power-down Mode
P/N: PM1912
39
Stand-by Mode
REV. 1.2, JAN. 14, 2014
MX25L1673E
9-21.
Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4)
The REMS, REMS2, and REMS4 instruction provides both the JEDEC assigned Manufacturer ID and the specific
Device ID.
The instruction is initiated by driving the CS# pin low and shift the instruction code "90h", "DFh" or "EFh" followed
by two dummy bytes and one byte address (A7~A0). After which, the Manufacturer ID for Macronix (C2h) and the
Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in the figure below. The Device ID values are listed in "Table 7. ID Definitions". If the one-byte address is initially set to 01h, then
the Device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be
read continuously, alternating from one to the other. The instruction is completed by driving CS# high.
Figure 24. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF)
CS#
0 1 2 3 4 5 6 7 8 9 10
SCLK
Command
SI
SO
90
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
24 ADD Cycles
A23 A22 A21
A3 A2 A1 A0
Manufacturer ID
High-Z
Device ID
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
MSB
MSB
MSB
Notes:
1. A0=0 will output the Manufacturer ID first and A0=1 will output Device ID first. A1~A23 are don't care.
2. Instruction is either 90(hex) or EF(hex) or DF(hex).
P/N: PM1912
40
REV. 1.2, JAN. 14, 2014
MX25L1673E
9-22.
ID Read
User can execute this ID Read instruction to identify the Device ID and Manufacturer ID. The sequence of issue ID
instruction is CS# goes low→sending ID instruction→→Data out on SO→CS# goes high. Most significant bit (MSB)
first.
After the command cycle, the device will immediately output data on the falling edge of SCLK. The manufacturer ID,
memory type, and device ID data byte will be output continuously, until the CS# goes high.
Table 7. ID Definitions
RDID Command
manufacturer ID
C2
memory type
24
electronic ID
24
device ID
24
RES Command
REMS/REMS2/REMS4/
Command
9-23.
manufacturer ID
C2
memory density
15
Enter Secured OTP (ENSO)
The ENSO instruction is for entering the additional 512-bit secured OTP mode. The additional 512-bit secured OTP
is independent from main array, which may use to store unique serial number for system identifier. After entering
the Secured OTP mode, and then follow standard read or program, procedure to read out the data or update data.
The Secured OTP data cannot be updated again once it is lock-down.
The sequence of issuing ENSO instruction is: CS# goes low→sending ENSO instruction to enter Secured OTP
mode→ CS# goes high.
Please note that WRSR/WRSCUR commands are not acceptable during the access of secure OTP region, once
se- curity OTP is lock down, only read related commands are valid.
9-24.
Exit Secured OTP (EXSO)
The EXSO instruction is for exiting the additional 512-bit secured OTP mode.
The sequence of issuing EXSO instruction is: CS# goes low→sending EXSO instruction to exit Secured OTP
mode→CS# goes high.
P/N: PM1912
41
REV. 1.2, JAN. 14, 2014
MX25L1673E
9-25.
Read Security Register (RDSCUR)
The RDSCUR instruction is for reading the value of Security Register. The Read Security Register can be read at
any time (even in program/erase/write status register/write security register condition) and continuously.
The sequence of issuing RDSCUR instruction is : CS# goes low→ sending RDSCUR instruction → Security Register data out on SO→ CS# goes high.
The SIO[3:1] are don't care when during this mode.
Figure 25. Read Security Register (RDSCUR) Sequence (Command 2B)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
command
2B
SI
Security Register Out
High-Z
SO
7
6
5
4
3
2
1
Security Register Out
0
7
6
5
4
3
2
1
0
7
MSB
MSB
The definition of the Security Register is as below:
Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory before ex- factory or
not. When it is "0", it indicates non- factory lock; "1" indicates factory- lock.
Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for customer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 512-bit Secured OTP
area cannot be update any more. While it is in 512-bit secured OTP mode, main array access is not allowed.
Table 8. Security Register Definition
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
x
x
x
x
x
x
LDSO
(indicate if
lock-down
Secured OTP
indicator bit
0 = non-factory
lock
1 = factory
lock
non-volatile bit
reserved
reserved
reserved
reserved
reserved
reserved
0 = not lock-down
1 = lock-down
(cannot
program/erase
OTP)
volatile bit
volatile bit
volatile bit
volatile bit
volatile bit
volatile bit
non-volatile bit
P/N: PM1912
42
REV. 1.2, JAN. 14, 2014
MX25L1673E
9-26.
Write Security Register (WRSCUR)
The WRSCUR instruction is for changing the values of Security Register Bits. The WREN instruction is required before sending WRSCUR instruction. The WRSCUR instruction may change the values of bit1 (LDSO bit) for customer
to lock-down the Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area cannot be updated any
more.
The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high.
The SIO[3:1] are don't care when during this mode.
The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
Figure 26. Write Security Register (WRSCUR) Sequence (Command 2F)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
SO
P/N: PM1912
2F
High-Z
43
REV. 1.2, JAN. 14, 2014
MX25L1673E
9-27.
Read SFDP Mode (RDSFDP)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional
and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables
can be interrogated by host system software to enable adjustments needed to accommodate divergent features
from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on
CFI.
The sequence of issuing RDSFDP instruction is same as CS# goes low→send RDSFDP instruction (5Ah)→send 3
address bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP operation can
use CS# to high at any time during data out.
SFDP is a JEDEC Standard. JESD216.
Figure 27. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
SO
24 BIT ADDRESS
23 22 21
5Ah
3
2
1
0
High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Cycle
SI
7
6
5
4
3
2
1
0
DATA OUT 2
DATA OUT 1
SO
7
6
P/N: PM1912
5
4
3
2
1
0
7
MSB
MSB
44
6
5
4
3
2
1
0
7
MSB
REV. 1.2, JAN. 14, 2014
MX25L1673E
Table 9. Signature and Parameter Identification Data Values
SFDP Table below is for MX25L1673EM2I-10G and MX25L1673EZNI-10G
Description
SFDP Signature
Comment
Fixed: 50444653h
Add (h)
(Byte)
00h
DW Add Data (h/b)
(Bit)
(Note1)
07:00
53h
Data
(h)
53h
01h
15:08
46h
46h
02h
23:16
44h
44h
03h
31:24
50h
50h
SFDP Minor Revision Number
Start from 00h
04h
07:00
00h
00h
SFDP Major Revision Number
Start from 01h
This number is 0-based. Therefore,
0 indicates 1 parameter header.
05h
15:08
01h
01h
06h
23:16
01h
01h
07h
31:24
FFh
FFh
00h: it indicates a JEDEC specified
header.
08h
07:00
00h
00h
Start from 00h
09h
15:08
00h
00h
Start from 01h
0Ah
23:16
01h
01h
How many DWORDs in the
Parameter table
0Bh
31:24
09h
09h
0Ch
07:00
30h
30h
0Dh
15:08
00h
00h
0Eh
23:16
00h
00h
0Fh
31:24
FFh
FFh
it indicates Macronix manufacturer
ID
10h
07:00
C2h
C2h
Start from 00h
11h
15:08
00h
00h
Start from 01h
12h
23:16
01h
01h
How many DWORDs in the
Parameter table
13h
31:24
04h
04h
14h
07:00
60h
60h
15h
15:08
00h
00h
16h
23:16
00h
00h
17h
31:24
FFh
FFh
Number of Parameter Headers
Unused
ID number (JEDEC)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length
(in double word)
Parameter Table Pointer (PTP)
First address of JEDEC Flash
Parameter table
Unused
ID number
(Macronix manufacturer ID)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length
(in double word)
Parameter Table Pointer (PTP)
First address of Macronix Flash
Parameter table
Unused
P/N: PM1912
45
REV. 1.2, JAN. 14, 2014
MX25L1673E
Table 10. Parameter Table (0): JEDEC Flash Parameter Tables
SFDP Table below is for MX25L1673EM2I-10G and MX25L1673EZNI-10G
Description
Comment
Block/Sector Erase sizes
00: Reserved, 01: 4KB erase,
10: Reserved,
11: not support 4KB erase
Write Granularity
0: 1Byte, 1: 64Byte or larger
Write Enable Instruction Required 0: not required
1: required 00h to be written to the
for Writing to Volatile Status
status register
Registers
Add (h)
(Byte)
01:00
01b
02
1b
03
0b
30h
0: use 50h opcode,
1: use 06h opcode
Write Enable Opcode Select for
Note: If target flash status register is
Writing to Volatile Status Registers
nonvolatile, then bits 3 and 4 must
be set to 00b.
Contains 111b and can never be
Unused
changed
4KB Erase Opcode
DW Add Data (h/b)
(Bit)
(Note1)
31h
E5h
04
0b
07:05
111b
15:08
20h
16
1b
18:17
00b
19
0b
20
1b
(1-1-2) Fast Read (Note2)
0=not support 1=support
Address Bytes Number used in
addressing flash array
Double Transfer Rate (DTR)
Clocking
00: 3Byte only, 01: 3 or 4Byte,
10: 4Byte only, 11: Reserved
(1-2-2) Fast Read
0=not support 1=support
(1-4-4) Fast Read
0=not support 1=support
21
1b
(1-1-4) Fast Read
0=not support 1=support
22
1b
23
1b
33h
31:24
FFh
37h:34h
31:00
0=not support 1=support
32h
Unused
Unused
Flash Memory Density
(1-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
states (Note3)
Clocks) not support
(1-4-4) Fast Read Number of
000b: Mode Bits not support
Mode Bits (Note4)
38h
(1-4-4) Fast Read Opcode
39h
(1-1-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
states
Clocks) not support
(1-1-4) Fast Read Number of
000b: Mode Bits not support
Mode Bits
3Ah
(1-1-4) Fast Read Opcode
3Bh
P/N: PM1912
46
Data
(h)
20h
F1h
FFh
00FF FFFFh
04:00
0 0100b
07:05
010b
15:08
EBh
20:16
0 1000b
23:21
000b
31:24
6Bh
44h
EBh
08h
6Bh
REV. 1.2, JAN. 14, 2014
MX25L1673E
SFDP Table below is for MX25L1673EM2I-10G and MX25L1673EZNI-10G
Description
Comment
(1-1-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy
states
Clocks) not support
(1-1-2) Fast Read Number of
000b: Mode Bits not support
Mode Bits
Add (h)
(Byte)
3Ch
(1-1-2) Fast Read Opcode
3Dh
(1-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy
states
Clocks) not support
(1-2-2) Fast Read Number of
000b: Mode Bits not support
Mode Bits
3Eh
(1-2-2) Fast Read Opcode
3Fh
(2-2-2) Fast Read
0=not support 1=support
Unused
(4-4-4) Fast Read
0=not support 1=support
40h
Unused
DW Add Data (h/b)
(Bit)
(Note1)
04:00
0 1000b
07:05
000b
15:08
3Bh
20:16
0 0100b
23:21
000b
31:24
BBh
00
0b
03:01
111b
04
0b
07:05
111b
Data
(h)
08h
3Bh
04h
BBh
EEh
Unused
43h:41h
31:08
FFh
FFh
Unused
45h:44h
15:00
FFh
FFh
20:16
0 0000b
23:21
000b
(2-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy
states
Clocks) not support
(2-2-2) Fast Read Number of
000b: Mode Bits not support
Mode Bits
46h
(2-2-2) Fast Read Opcode
47h
31:24
FFh
FFh
49h:48h
15:00
FFh
FFh
20:16
0 0000b
23:21
000b
Unused
00h
(4-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
states
Clocks) not support
(4-4-4) Fast Read Number of
000b: Mode Bits not support
Mode Bits
4Ah
(4-4-4) Fast Read Opcode
4Bh
31:24
FFh
FFh
4Ch
07:00
0Ch
0Ch
4Dh
15:08
20h
20h
4Eh
23:16
10h
10h
4Fh
31:24
D8h
D8h
50h
07:00
00h
00h
51h
15:08
FFh
FFh
52h
23:16
00h
00h
53h
31:24
FFh
FFh
Sector Type 1 Size
Sector/block size = 2^N bytes (Note5)
0x00b: this sector type doesn't exist
Sector Type 1 erase Opcode
Sector Type 2 Size
Sector/block size = 2^N bytes
0x00b: this sector type doesn't exist
Sector Type 2 erase Opcode
Sector Type 3 Size
Sector/block size = 2^N bytes
0x00b: this sector type doesn't exist
Sector Type 3 erase Opcode
Sector Type 4 Size
Sector/block size = 2^N bytes
0x00b: this sector type doesn't exist
Sector Type 4 erase Opcode
P/N: PM1912
47
00h
REV. 1.2, JAN. 14, 2014
MX25L1673E
Table 11. Parameter Table (1): Macronix Flash Parameter Tables
SFDP Table below is for MX25L1673EM2I-10G and MX25L1673EZNI-10G
Description
Comment
Add (h) DW Add
(Byte)
(Bit)
Data (h/b)
(Note1)
Data
(h)
Vcc Supply Maximum Voltage
2000h=2.000V
2700h=2.700V
3600h=3.600V
61h:60h
07:00
15:08
00h
36h
00h
36h
Vcc Supply Minimum Voltage
1650h=1.650V
2250h=2.250V
2350h=2.350V
2700h=2.700V
63h:62h
23:16
31:24
00h
27h
00h
27h
H/W Reset# pin
0=not support 1=support
00
0b
H/W Hold# pin
0=not support 1=support
01
0b
Deep Power Down Mode
0=not support 1=support
02
1b
S/W Reset
0=not support 1=support
03
0b
S/W Reset Opcode
Reset Enable (66h) should be
issued before Reset Opcode
11:04
1111 1111b
(FFh)
Program Suspend/Resume
0=not support 1=support
12
0b
Erase Suspend/Resume
0=not support 1=support
13
0b
14
1b
15
0b
66h
23:16
FFh
FFh
67h
31:24
FFh
FFh
65h:64h
Unused
Wrap-Around Read mode
0=not support 1=support
Wrap-Around Read mode Opcode
Wrap-Around Read data length
08h:support 8B wrap-around read
16h:8B&16B
32h:8B&16B&32B
64h:8B&16B&32B&64B
Individual block lock
0=not support 1=support
00
0b
Individual block lock bit
(Volatile/Nonvolatile)
0=Volatile 1=Nonvolatile
01
1b
09:02
1111 1111b
(FFh)
10
1b
11
1b
Individual block lock Opcode
4FF4h
Individual block lock Volatile
protect bit default protect status
0=protect 1=unprotect
Secured OTP
0=not support 1=support
Read Lock
0=not support 1=support
12
0b
Permanent Lock
0=not support 1=support
13
0b
Unused
15:14
11b
Unused
31:16
FFh
FFh
31:00
FFh
FFh
Unused
6Bh:68h
6Fh:6Ch
CFFEh
MX25L1673EM2I-10G-SFDP_2014-01-14
P/N: PM1912
48
REV. 1.2, JAN. 14, 2014
MX25L1673E
Note 1: h/b is hexadecimal or binary.
Note 2: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x),
address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1), (2-2-2),
and (4-4-4)
Note 3: Wait States is required dummy clock cycles after the address bits or optional mode bits.
Note 4: Mode Bits is optional control bits that follow the address bits. These bits are driven by the system controller
if they are specified. (eg,read performance enhance toggling bits)
Note 5: 4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h
Note 6: All unused and undefined area data is blank FFh.
P/N: PM1912
49
REV. 1.2, JAN. 14, 2014
MX25L1673E
10. POWER-ON STATE
The device is at below states when power-up:
- Standby mode (please note it is not Deep Power-down mode)
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage unless the VCC achieves below correct
level:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal Power-on Reset (POR) circuit may protect the device from data corruption and inadvertent data change
during power up state.
For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not
guaranteed. The read, write, erase, and program command should be sent after the time delay:
- tVSL after VCC reached VCC minimum level
The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended.
(generally around 0.1uF)
P/N: PM1912
50
REV. 1.2, JAN. 14, 2014
MX25L1673E
11. ELECTRICAL SPECIFICATIONS
11-1.
Absolute Maximum Ratings
Rating
Value
Ambient Operating Temperature
Industrial grade
-40°C to 85°C
Storage Temperature
-65°C to 150°C
Applied Input Voltage
-0.5V to 4.6V
Applied Output Voltage
-0.5V to 4.6V
VCC to Ground Potential
-0.5V to 4.6V
NOTICE:
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended period may affect reliability.
2. Specifications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see the
figures below.
Figure 28. Maximum Negative Overshoot Waveform
Figure 29. Maximum Positive Overshoot Waveform
20ns
20ns
20ns
Vcc + 2.0V
Vss
Vcc
Vss-2.0V
20ns
11-2.
20ns
20ns
Capacitance
TA = 25°C, f = 1.0 MHz
Symbol Parameter
CIN
COUT
P/N: PM1912
Min.
Typ.
Max.
Unit
Input Capacitance
6
pF
VIN = 0V
Output Capacitance
8
pF
VOUT = 0V
51
Conditions
REV. 1.2, JAN. 14, 2014
MX25L1673E
Figure 30. Input Test Waveforms and Measurement Level
Input timing reference level
0.8VCC
0.2VCC
0.7VCC
0.3VCC
Output timing reference level
AC
Measurement
Level
0.5VCC
Note: Input pulse rise and fall time are
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