MX25L25635EZNI-12G

MX25L25635E MX25L25635E HIGH PERFORMANCE SERIAL FLASH SPECIFICATION P/N: PM1532 REV. 1.3, FEB. 10, 2012 1 MX25L25635E Contents FEATURES................................................................................................................................................................... 5 GENERAL DESCRIPTION.......................................................................................................................................... 7 Table 1. Additional Features ............................................................................................................................... 7 PIN CONFIGURATION................................................................................................................................................. 8 PIN DESCRIPTION....................................................................................................................................................... 8 BLOCK DIAGRAM........................................................................................................................................................ 9 DATA PROTECTION................................................................................................................................................... 10 Table 2. Protected Area Sizes........................................................................................................................... 11 Table 3. 4K-bit Secured OTP Definition............................................................................................................. 11 Memory Organization................................................................................................................................................ 12 Table 4. Memory Organization......................................................................................................................... 12 DEVICE OPERATION................................................................................................................................................. 13 Figure 1. Serial Modes Supported (for Normal Serial mode)............................................................................ 13 HOLD FEATURES...................................................................................................................................................... 14 Figure 2. Hold Condition Operation . ................................................................................................................ 14 COMMAND DESCRIPTION........................................................................................................................................ 15 Table 5. Command Sets.................................................................................................................................... 15 (1) Write Enable (WREN).................................................................................................................................. 17 (2) Write Disable (WRDI)................................................................................................................................... 17 (3) Read Identification (RDID)........................................................................................................................... 17 (4) Read Status Register (RDSR)..................................................................................................................... 18 (5) Write Status Register (WRSR)..................................................................................................................... 19 Protection Modes.............................................................................................................................................. 19 (6) Enter 4-byte mode (EN4B).......................................................................................................................... 20 (7) Exit 4-byte mode (EX4B)............................................................................................................................. 20 (8) Read Data Bytes (READ)............................................................................................................................ 20 (9) Read Data Bytes at Higher Speed (FAST_READ)...................................................................................... 20 (10) 2 x I/O Read Mode (2READ)..................................................................................................................... 21 (11) Dual Read Mode (DREAD)........................................................................................................................ 21 (12) 4 x I/O Read Mode (4READ)..................................................................................................................... 21 (13) Quad Read Mode (QREAD)...................................................................................................................... 22 (14) Sector Erase (SE)...................................................................................................................................... 22 (15) Block Erase (BE)....................................................................................................................................... 23 (16) Block Erase (BE32K)................................................................................................................................. 23 (17) Chip Erase (CE)......................................................................................................................................... 24 (18) Page Program (PP)................................................................................................................................... 24 (19) 4 x I/O Page Program (4PP)...................................................................................................................... 24 Program/Erase Flow(1) - verify by reading array data...................................................................................... 26 Program/Erase Flow(2) - verify by reading program/erase fail flag bit.............................................................. 27 (20) Continuously program mode (CP mode)................................................................................................... 28 (21) Deep Power-down (DP)............................................................................................................................. 29 (22) Release from Deep Power-down (RDP), Read Electronic Signature (RES)............................................. 29 (23) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4)........................................... 29 Table 6. ID Definitions ...................................................................................................................................... 30 P/N: PM1532 REV. 1.3, FEB. 10, 2012 2 MX25L25635E (24) Enter Secured OTP (ENSO)...................................................................................................................... 30 (25) Exit Secured OTP (EXSO)......................................................................................................................... 30 (26) Read Security Register (RDSCUR)........................................................................................................... 30 Security Register Definition............................................................................................................................... 31 (27) Write Security Register (WRSCUR)........................................................................................................... 31 (28) Write Protection Selection (WPSEL).......................................................................................................... 32 BP and SRWD if WPSEL=0.............................................................................................................................. 32 The individual block lock mode is effective after setting WPSEL=1.................................................................. 33 WPSEL Flow..................................................................................................................................................... 34 (29) Single Block Lock/Unlock Protection (SBLK/SBULK)................................................................................ 35 Block Lock Flow................................................................................................................................................ 35 Block Unlock Flow............................................................................................................................................. 36 (30) Read Block Lock Status (RDBLOCK)........................................................................................................ 37 (31) Gang Block Lock/Unlock (GBLK/GBULK)................................................................................................. 37 (32) Clear SR Fail Flags (CLSR)....................................................................................................................... 37 (33) Enable SO to Output RY/BY# (ESRY)....................................................................................................... 37 (34) Disable SO to Output RY/BY# (DSRY)...................................................................................................... 37 (35) Read SFDP Mode (RDSFDP).................................................................................................................... 38 Read Serial Flash Discoverable Parameter (RDSFDP) Sequence................................................................... 38 Table a. Signature and Parameter Identification Data Values .......................................................................... 39 Table b. Parameter Table (0): JEDEC Flash Parameter Tables........................................................................ 40 Table c. Parameter Table (1): Macronix Flash Parameter Tables...................................................................... 42 POWER-ON STATE.................................................................................................................................................... 44 ELECTRICAL SPECIFICATIONS............................................................................................................................... 45 ABSOLUTE MAXIMUM RATINGS.................................................................................................................... 45 Figure 3. Maximum Negative Overshoot Waveform......................................................................................... 45 CAPACITANCE TA = 25°C, f = 1.0 MHz............................................................................................................ 45 Figure 4. Maximum Positive Overshoot Waveform........................................................................................... 45 Figure 5. OUTPUT LOADING.......................................................................................................................... 46 Table 7. DC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V) .. 47 Table 8. AC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V) .48 Timing Analysis......................................................................................................................................................... 50 Figure 6. Serial Input Timing............................................................................................................................. 50 Figure 7. Output Timing..................................................................................................................................... 50 Figure 8. Hold Timing........................................................................................................................................ 51 Figure 9. WP# Setup Timing and Hold Timing during WRSR when SRWD=1.................................................. 51 Figure 10. Write Enable (WREN) Sequence (Command 06)............................................................................ 52 Figure 11. Write Disable (WRDI) Sequence (Command 04)............................................................................. 52 Figure 12. Read Identification (RDID) Sequence (Command 9F)..................................................................... 53 Figure 13. Read Status Register (RDSR) Sequence (Command 05)............................................................... 53 Figure 14. Write Status Register (WRSR) Sequence (Command 01)............................................................... 53 Figure 15. Read Data Bytes (READ) Sequence (Command 03)...................................................................... 54 Figure 16. Read at Higher Speed (FAST_READ) Sequence (Command 0B).................................................. 54 Figure 17. 2 x I/O Read Mode Sequence (Command BB)................................................................................ 55 Figure 18. Dual Read Mode Sequence (Command 3B)................................................................................... 55 Figure 19. 4 x I/O Read Mode Sequence (Command EB)................................................................................ 56 P/N: PM1532 REV. 1.3, FEB. 10, 2012 3 MX25L25635E Figure 20. Quad Read Mode Sequence (Command 6B).................................................................................. 56 Figure 21. 4 x I/O Read Enhance Performance Mode Sequence (Command EB)........................................... 57 Figure 22. Sector Erase (SE) Sequence (Command 20).................................................................................. 58 Figure 23. Block Erase (BE/EB32K) Sequence (Command D8/52).................................................................. 58 Figure 24. Chip Erase (CE) Sequence (Command 60 or C7)........................................................................... 58 Figure 25. Page Program (PP) Sequence (Command 02)............................................................................... 59 Figure 26. 4 x I/O Page Program (4PP) Sequence (Command 38).................................................................. 59 Figure 27. Continuously Program (CP) Mode Sequence with Hardware Detection (Command AD)................ 60 Figure 28. Deep Power-down (DP) Sequence (Command B9)........................................................................ 61 Figure 29. Read Electronic Signature (RES) Sequence (Command AB).......................................................... 61 Figure 30. Release from Deep Power-down (RDP) Sequence (Command AB)............................................... 61 Figure 31. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF).......... 62 Figure 32. Write Protection Selection (WPSEL) Sequence (Command 68)...................................................... 62 Figure 33. Single Block Lock/Unlock Protection (SBLK/SBULK) Sequence (Command 36/39)....................... 63 Figure 34. Read Block Protection Lock Status (RDBLOCK) Sequence (Command 3C).................................. 63 Figure 35. Gang Block Lock/Unlock (GBLK/GBULK) Sequence (Command 7E/98)........................................ 63 RESET........................................................................................................................................................................ 64 Figure 36. RESET Timing.................................................................................................................................. 64 Table 9. Reset Timing........................................................................................................................................ 64 Figure 37. Power-up Timing.............................................................................................................................. 65 Table 10. Power-Up Timing............................................................................................................................... 65 INITIAL DELIVERY STATE............................................................................................................................... 65 OPERATING CONDITIONS........................................................................................................................................ 66 Figure 38. AC Timing at Device Power-Up........................................................................................................ 66 Figure 39. Power-Down Sequence................................................................................................................... 67 ERASE AND PROGRAMMING PERFORMANCE..................................................................................................... 68 DATA RETENTION..................................................................................................................................................... 68 LATCH-UP CHARACTERISTICS............................................................................................................................... 68 ORDERING INFORMATION....................................................................................................................................... 69 PART NAME DESCRIPTION...................................................................................................................................... 70 PACKAGE INFORMATION......................................................................................................................................... 71 REVISION HISTORY ................................................................................................................................................. 73 P/N: PM1532 REV. 1.3, FEB. 10, 2012 4 MX25L25635E 256M-BIT [x 1/x 2/x 4] CMOS MXSMIOTM (SERIAL MULTI I/O) FLASH MEMORY FEATURES GENERAL • Serial Peripheral Interface compatible -- Mode 0 and Mode 3 • 268,435,456 x 1 bit structure or 134,217,728 x 2 bits (two I/O mode) structure or 67,108,864 x 4 bits (four I/O mode) structure • 8192 Equal Sectors with 4K bytes each - Any Sector can be erased individually • 1024 Equal Blocks with 32K bytes each - Any Block can be erased individually • 512 Equal Blocks with 64K bytes each - Any Block can be erased individually • Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations • Latch-up protected to 100mA from -1V to Vcc +1V PERFORMANCE • High Performance VCC = 2.7~3.6V - Normal read - 50MHz - Fast read - 1 I/O: 80MHz with 8 dummy cycles - 2 I/O: 70MHz with 4 dummy cycles - 4 I/O: 70MHz with 6 dummy cycles - Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page) - Byte program time: 9us (typical) - Continuously Program mode (automatically increase address under word program mode) - Fast erase time: 60ms (typ.)/sector (4K-byte per sector) ; 0.5s(typ.) /block (32K-byte per block); 0.7s(typ.) /block (64K-byte per block); 160s(typ.) /chip • Low Power Consumption - Low active read current: 45mA(max.) at 80MHz, 40mA(max.) at 70MHz and 30mA(max.) at 50MHz - Low active programming current: 25mA (max.) - Low active erase current: 25mA (max.) - Standby current: 200uA (max.) - Deep power down current: 80uA (max.) • Typical 100,000 erase/program cycles SOFTWARE FEATURES • Input Data Format - 1-byte Command code • Advanced Security Features - BP0-BP3 block group protect - Flexible individual block protect when OTP WPSEL=1 P/N: PM1532 REV. 1.3, FEB. 10, 2012 5 MX25L25635E - Additional 4K bits secured OTP for unique identifier • Auto Erase and Auto Program Algorithms - Automatically erases and verifies data at selected sector - Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse width (Any page to be programed should have page in the erased state first.) • Status Register Feature • Electronic Identification - JEDEC 1-byte Manufacturer ID and 2-byte Device ID - RES command for 1-byte Device ID - Both REMS,REMS2, REMS4 commands for 1-byte Manufacturer ID and 1-byte Device ID • Support Serial Flash Discoverable Parameters (SFDP) mode HARDWARE FEATURES • SCLK Input - Serial clock input • SI/SIO0 - Serial Data Input or Serial Data Input/Output for 2 x I/O mode and 4 x I/O mode • SO/SIO1 - Serial Data Output or Serial Data Input/Output for 2 x I/O mode and 4 x I/O mode • WP#/SIO2 - Hardware write protection or serial data Input/Output for 4 x I/O mode • HOLD#/SIO3 - HOLD# pin or serial data Input/Output for 4 x I/O mode, an internal weak pull up on the pin - The weak pull up on the HOLD# pin will be disabled after QE bit is enabled, until next power-on cycle starts. - HOLD# function is only available on 16 SOP package • RESET# - Hardware reset pin • PACKAGE - 16-pin SOP (300mil) - 8 WSON (8x6mm) - All devices are RoHS Compliant P/N: PM1532 REV. 1.3, FEB. 10, 2012 6 MX25L25635E GENERAL DESCRIPTION MX25L25635E is 268,435,456 bits serial Flash memory, which is configured as 33,554,432 x 8 internally. When it is in two or four I/O mode, the structure becomes 134,217,728 bits x 2 or 67,108,864 bits x 4. The MX25L25635E features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input. MX25L25635E, MXSMIOTM (Serial Multi I/O) flash memory, provides sequential read operation on whole chip and multi-I/O features. When it is in dual I/O mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and data output. When it is in quad I/O mode, the SI pin, SO pin, WP# pin and HOLD# pin become SIO0 pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data Input/Output. After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256 bytes) basis, or word basis for Continuously Program mode, and erase command is executes on sector (4K-byte), block (32K-byte/64K-byte), or whole chip basis. To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. When the device is not in operation and CS# is high, it is put in standby mode and draws less than 200uA DC current. The MX25L25635E utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles. Table 1. Additional Features Additional Features Part Name MX25L25635E Protection and Security Read Performance Flexible or Individual block (or sector) protection 4K-bit secured OTP 1 I/O Read (80 MHz) 2 I/O Read (70 MHz) 4 I/O Read (70 MHz) V V V V V Additional Features Part Name MX25L25635E Identifier RES REMS REMS2 REMS4 RDID (command: AB hex) (command: 90 hex) (command: EF hex) (command: DF hex) (command: 9F hex) 18 (hex) C2 18 (hex) C2 18 (hex) P/N: PM1532 C2 18 (hex) C2 20 19 (hex) REV. 1.3, FEB. 10, 2012 7 MX25L25635E PIN CONFIGURATION PIN DESCRIPTION 16-PIN SOP (300mil) HOLD#/SIO3 VCC RESET# NC NC NC CS# SO/SIO1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SYMBOL DESCRIPTION CS# Chip Select Serial Data Input (for 1xI/O)/ Serial Data SI/SIO0 Input & Output (for 2xI/O or 4xI/O mode) Serial Data Output (for 1xI/O)/Serial SO/SIO1 Data Input & Output (for 2xI/O or 4xI/O mode) SCLK Clock Input Write protection: connect to GND or WP#/SIO2 Serial Data Input & Output (for 4xI/O mode) HOLD#(1,2)/ HOLD# pin or Serial Data Input & Output SIO3 (for 4xI/O mode) VCC + 3.3V Power Supply GND Ground RESET#(3) Hardware Reset Pin, Active low NC No Connection SCLK SI/SIO0 NC NC NC NC GND WP#/SIO2 8-WSON (8x6mm) * CS# SO/SIO1 WP#/SIO2 GND 1 2 3 4 8 7 6 5 VCC RESET#/SIO3 SCLK SI/SIO0 Note: (1). HOLD# function is only available on 16-SOP package. (2). The weak pull up on the HOLD#����������������� ���������������������� pin will be disabled after QE bit is enabled, until next power-on cycle starts. (3). RESET# pin has internal pull up. P/N: PM1532 REV. 1.3, FEB. 10, 2012 8 MX25L25635E BLOCK DIAGRAM X-Decoder Address Generator Memory Array Page Buffer SI/SIO0 Data Register Y-Decoder SRAM Buffer Sense Amplifier CS# WP#/SIO2 HOLD#/SIO3 RESET# SCLK Mode Logic State Machine HV Generator Clock Generator Output Buffer SO/SIO1 P/N: PM1532 REV. 1.3, FEB. 10, 2012 9 MX25L25635E DATA PROTECTION MX25L25635E is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the standby mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise. • Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary. • Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other command to change data. The WEL bit will return to reset stage under following situation: - Power-up - Reset# Pin driven low - Write Disable (WRDI) command completion - Write Status Register (WRSR) command completion - Page Program (PP, 4PP) command completion - Continuously Program mode (CP) instruction completion - Sector Erase (SE) command completion - Block Erase (BE, BE32K) command completion - Chip Erase (CE) command completion - Single Block Lock/Unlock (SBLK/SBULK) instruction completion - Gang Block Lock/Unlock (GBLK/GBULK) instruction completion - Write Security Register (WRSCUR) instruction completion - Write Protection Selection (WPSEL) instruction completion • Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing all commands except Release from Deep Power Down mode command (RDP) and Read Electronic Signature command (RES). I. Block lock protection - The Software Protected Mode (SPM) uses (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected as read only. The protected area definition is shown as table of "Protected Area Sizes", the protected areas are more flexible which may protect various area by setting value of BP0-BP3 bits. Please refer to table of "Protected Area Sizes". - The Hardware Protected Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and SRWD bit. If the system goes into four I/O mode, the feature of HPM will be disabled. - MX25L25635E provide individual block (or sector) write protect & unprotect. User may enter the mode with WPSEL command and conduct individual block (or sector) write protect with SBLK instruction, or SBULK for individual block (or sector) unprotect. Under the mode, user may conduct whole chip (all blocks) protect with GBLK instruction and unlock the whole chip with GBULK instruction. P/N: PM1532 REV. 1.3, FEB. 10, 2012 10 MX25L25635E Table 2. Protected Area Sizes Status bit Protection Area BP3 BP2 BP1 BP0 256Mb 0 0 0 0 0 (none) 0 0 0 1 1 (2 blocks, block 510th-511th) 0 0 1 0 2 (4 blocks, block 508th-511th) 0 0 1 1 3 (8 blocks, block 504th-511th) 0 1 0 0 4 (16 blocks, block 496th-511th) 0 1 0 1 5 (32 blocks, block 480th-511th) 0 1 1 0 6 (64 blocks, block 448nd-511th) 0 1 1 1 7 (128 blocks, block 384th-511th) 1 0 0 0 8 (256 blocks, block 256th-511th) 1 0 0 1 9 (512 blocks, all) 1 0 1 0 10 (512 blocks, all) 1 0 1 1 11 (512 blocks, all) 1 1 0 0 12 (512 blocks, all) 1 1 0 1 13 (512 blocks, all) 1 1 1 0 14 (512 blocks, all) 1 1 1 1 15 (512 blocks, all) Note: The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP3, BP2, BP1, BP0) are 0. II. Additional 4K-bit secured OTP for unique identifier: to provide 4K-bit One-Time Program area for setting device unique serial number - Which may be set by factory or system maker. Please refer to Table 3. 4K-bit Secured OTP Definition. - Security register bit 0 indicates whether the chip is locked by factory or not. - To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with ENSO command), and going through normal program procedure, and then exiting 4K-bit secured OTP mode by writing EXSO command. - Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register) command to set customer lock-down bit1 as "1". Please refer to table of "Security Register Definition" for security register bit definition and table of "4K-bit Secured OTP Definition" for address range definition. - Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit Secured OTP mode, array access is not allowed. Table 3. 4K-bit Secured OTP Definition Address range Size Standard Factory Lock xxx000~xxx00F 128-bit ESN (electrical serial number) xxx010~xxx1FF 3968-bit N/A P/N: PM1532 Customer Lock Determined by customer REV. 1.3, FEB. 10, 2012 11 MX25L25635E Memory Organization Table 4. Memory Organization Sector … 8183 1FF7000h 1FF7FFFh … 1FF0FFFh 1FEF000h 1FEFFFFh … 1FE8FFFh 1FE7000h 1FE7FFFh … 1FE0000h 1FE0FFFh 8159 1FDF000h 1FDFFFFh … … 8160 1019 509 … 1FE8000h 8167 … 8168 1020 individual block lock/unlock unit:64K-byte … 1FF0000h 8175 … 8176 1021 8152 1FD8000h 1FD8FFFh 8151 1FD7000h 1FD7FFFh … … … 1018 individual 16 sectors lock/unlock unit:4K-byte … … 1FF8FFFh … 1FF8000h 1022 510 1FFFFFFh 8184 1023 511 Address Range 1FFF000h … 8191 … Block(64K-byte) Block(32K-byte) 8144 1FD0000h 1FD0FFFh 47 002F000h 002FFFFh 0020000h 0020FFFh 31 001F000h 001FFFFh 0018000h 0018FFFh 23 0017000h 0017FFFh … 2 24 P/N: PM1532 8 0008000h 0008FFFh 7 0007000h 0007FFFh … … 000FFFFh … 0010FFFh 000F000h … 0 0010000h 15 … 0 16 … 1 … 1 … 32 … … 0027FFFh … 0028FFFh 027000h … 3 0028000h 39 … 4 individual block lock/unlock unit:64K-byte 40 … 2 … … 5 … individual block lock/unlock unit:64K-byte 0 0000000h 0000FFFh individual 16 sectors lock/unlock unit:4K-byte REV. 1.3, FEB. 10, 2012 12 MX25L25635E DEVICE OPERATION 1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation. 2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z. 3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next CS# rising edge. 4. For standard single data rate serial mode, input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as Figure 1. 5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, RDSFDP, 2READ, DREAD, 4READ, QREAD, RDBLOCK, RES, REMS, REMS2, and REMS4 the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE, BE32K, HPM, CE, PP, CP, 4PP, RDP, DP, WPSEL, SBLK, SBULK, GBLK, GBULK, ENSO, EXSO, WRSCUR, EN4B, EX4B, ENPLM, EXPLM, ESRY, DSRY and CLSR the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglected and not affect the current operation of Write Status Register, Program, Erase. Figure 1. Serial Modes Supported (for Normal Serial mode) CPOL CPHA shift in (Serial mode 0) 0 0 SCLK (Serial mode 3) 1 1 SCLK SI shift out MSB SO MSB Note: CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is supported. P/N: PM1532 REV. 1.3, FEB. 10, 2012 13 MX25L25635E HOLD FEATURES HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the operation of write status register, programming, or erasing in progress. The operation of HOLD requires Chip Select(CS#) keeping low and starts on falling edge of HOLD# pin signal while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Serial Clock(SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not end until Serial Clock being low), see Figure 2. Figure 2. Hold Condition Operation CS# SCLK HOLD# Hold Condition (standard) Hold Condition (non-standard) The Serial Data Output (SO) is high impedance, both Serial Data Input (SI) and Serial Clock (SCLK) are don't care during the HOLD operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and CS# must be at low. Note 1: The HOLD feature is disabled during Quad I/O mode in 16-SOP package. P/N: PM1532 REV. 1.3, FEB. 10, 2012 14 MX25L25635E COMMAND DESCRIPTION Table 5. Command Sets RDSR WRSR COMMAND WREN (write WRDI (write RDID (read (read status (write status (byte) enable) disable) identification) register) register) Command 06 04 9F 05 01 (hex) Input Data(8) Cycles Dummy Cycles sets the resets the outputs to read out to write new (WEL) write (WEL) write JEDEC the values values to enable latch enable latch ID: 1-byte of the status the status bit bit Manufacturer register register Action ID & 2-byte Device ID COMMAND (byte) Command (hex) Input Cycles Dummy Cycles Action 2READ (2 FAST READ RDSFDP x I/O read (fast read (Read SFDP) command) data) Note1 B7 E9 03 ADD(24) to enter to exit 4-byte n bytes read 4-byte mode mode and out until CS# and set clear 4BYTE goes high 4BYTE bit as bit to be "0" "1" DREAD (1I 2O read) 4READ (4 x I/O read command) QREAD (1I 4O read) 4PP (quad page program) SE (sector erase) 0B 5A BB 3B EB 6B 38 20 ADD(24) ADD(24) ADD(12) ADD(24) ADD(6)+ indicator(2) ADD(24) ADD(6)+ Data(512) ADD(24) 8 8 4 8 4 8 n bytes read Read SFDP n bytes read n bytes read n bytes read n bytes read quad input to erase the out until CS# mode out by 2 x I/ out by Dual out by 4 x I/ out by Quad to program selected goes high O until CS# output until O until CS# output until the selected sector goes high CS# goes goes high CS# goes page high high COMMAND BE (block BE 32K (block (byte) erase 64KB) erase 32KB) Command (hex) Input Cycles Dummy Cycles EN4B (enter EX4B (exit READ (read 4-byte mode) 4-byte mode) data) D8 52 ADD(24) ADD(24) CP RDP (Continuously DP (Deep (Release RES (read program power down) from deep electronic ID) mode) power down) CE (chip erase) PP (Page program) 60 or C7 02 AD ADD(24)+ Data(2048) ADD(24)+ Data(16) B9 AB AB 24 to erase the selected 64KB block to erase the selected 32KB block to erase whole chip to program the selected page Action P/N: PM1532 continously enters deep release from to read out program power down deep power 1-byte Device whole mode down mode ID chip, the address is automatically increase REV. 1.3, FEB. 10, 2012 15 MX25L25635E REMS (read REMS2 (read REMS4 (read RDSCUR COMMAND electronic ENSO (enter EXSO (exit ID for 2x I/O ID for 4x I/O (read security (byte) manufacturer & secured OTP) secured OTP) mode) mode) register) device ID) Command 90 EF DF B1 C1 2B (hex) Input ADD(8) ADD(8) ADD(8) Cycles Dummy 16 16 16 Cycles output the output the output the to enter the to exit the to read value of Manufacturer Manufacturer Manufact4K-bit Secured 4K-bit Secured security register ID & Device ID ID & Device ID urer ID & OTP mode OTP mode device ID Action COMMAND (byte) Command (hex) Input Cycles Dummy Cycles Action COMMAND (byte) Command (hex) Input Cycles Dummy Cycles Action ESRY (enable DSRY (disable HPM (High CLSR (Clear SO to output SO to output Perform-ance SR Fail Flags) RY/BY#) RY/BY#) Enable Mode) 70 80 30 to enable SO to disable SO clear security to output RY/ to output RY/ register bit 6 BY# during CP BY# during CP and bit 5 mode mode RDBLOCK (block protect read) GBLK (gang block lock) GBULK (gang block unlock) 3C 7E 98 whole chip write protect whole chip unprotect A3 WRSCUR (write security register) 2F to set the lockdown bit as "1" (once lockdown, cannot be updated) WPSEL (write protection selection) SBLK (single block lock) *Note 2 SBULK (single block unlock) 68 36 39 ADD(24) ADD(24) Quad I/O high to enter and individual block individual block Perform-ance enable individal (64K-byte) or (64K-byte) or mode block protect sector (4K-byte) sector (4K-byte) mode write protect unprotect ADD(24) read individual block or sector write protect status Note 1: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden mode. Note 2: In individual block write protection mode, all blocks/sectors is locked as defualt. Note 3: The number in parentheses afer "ADD" or "Data" stands for how many clock cycles it has. For example, "Data(8)" represents there are 8 clock cycles for the data in. Please note the number after "ADD" are based on 3-byte address mode, for 4-byte address mode, which will be increased. P/N: PM1532 REV. 1.3, FEB. 10, 2012 16 MX25L25635E (1) Write Enable (WREN) The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP, CP, SE, BE, BE32K, CE, WRSR, WRSCUR, WPSEL, SBLK, SBULK, GBLK and GBULK, which are intended to change the device content, should be set every time after the WREN instruction setting the WEL bit. The sequence of issuing WREN instruction is: CS# goes low→ sending WREN instruction code→ CS# goes high. (Please refer to Figure 10) (2) Write Disable (WRDI) The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit. The sequence of issuing WRDI instruction is: CS# goes low→ sending WRDI instruction code→ CS# goes high. (Please refer to Figure 11) The WEL bit is reset by following situations: - Power-up - Reset# pin driven low - Write Disable (WRDI) instruction completion - Write Status Register (WRSR) instruction completion - Page Program (PP, 4PP) instruction completion - Sector Erase (SE) instruction completion - Block Erase (BE, BE32K) instruction completion - Chip Erase (CE) instruction completion - Continuously Program mode (CP) instruction completion - Single Block Lock/Unlock (SBLK/SBULK) instruction completion - Gang Block Lock/Unlock (GBLK/GBULK) instruction completion - Write Security Register (WRSCUR) instruction completion - Write Protection Selection (WPSEL) instruction completion (3) Read Identification (RDID) The RDID instruction is for reading the Manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC Manufacturer ID is C2(hex), the memory type ID is 20(hex) as the first-byte Device ID, and the individual Device ID of second-byte ID are listed as table of "ID Definitions". (Please refer to Table 6) The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code → 24-bits ID data out on SO→ to end RDID operation can use CS# to high at any time during data out. (Please refer to Figure 12) While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage. P/N: PM1532 REV. 1.3, FEB. 10, 2012 17 MX25L25635E (4) Read Status Register (RDSR) The RDSR instruction is for reading Status Register. The Read Status Register can be read at any time (even in program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in progress. The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register data out on SO (Please refer to Figure 13). The definition of the status register bits is as below: WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch. When WEL bit sets to "1", which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. The program/erase command will be ignored and will reset WEL bit if it is applied to a protected memory area. BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area (as defined in Table 2) of the device to against the program/erase instruction without hardware protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip Erase (CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed). QE bit. The Quad Enable (QE) bit, non-volatile bit, while it is "0" (factory default), it performs non-Quad and WP#, HOLD#, RESET# are enable. While QE is "1", it performs Quad I/O mode and WP#, HOLD#, RESET# are disabled. In the other word, if the system goes into four I/O mode (QE=1), the feature of HPM and HOLD (16SOP package) or RESET (8 WSON package) will be disabled. SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, default value is "0". SRWD bit is operated together with Write Protection (WP#/SIO2) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are read only. Status Register bit7 bit6 SRWD (status register write protect) QE (Quad Enable) 1= Quad 1=status Enable register write 0=not Quad disable Enable Non-volatile Non-volatile bit bit bit5 BP3 (level of protected block) bit4 BP2 (level of protected block) bit3 BP1 (level of protected block) bit2 BP0 (level of protected block) (note 1) (note 1) (note 1) (note 1) Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit bit1 bit0 WEL WIP (write enable (write in latch) progress bit) 1=write 1=write enable operation 0=not write 0=not in write enable operation volatile bit volatile bit Note 1: see the Table 2 "Protected Area Size" in page 11. P/N: PM1532 REV. 1.3, FEB. 10, 2012 18 MX25L25635E (5) Write Status Register (WRSR) The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1, BP0) bits to define the protected area of memory (as shown in Table 2). The WRSR also can set or reset the Quad enable (QE) bit and set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#/SIO2) pin signal, but has no effect on bit1(WEL) and bit0 (WIP) of the status register. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered. If Reset# goes low while Write Status Register (WRSR) execution is on going, the operation of WRSR will finish after tw timing before entering Reset mode. The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register data on SI→ CS# goes high. (Please refer to Figure 14) The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset. Protection Modes Mode Software protection mode (SPM) Hardware protection mode (HPM) Status register condition WP# and SRWD bit status Memory Status register can be written in (WEL bit is set to "1") and the SRWD, BP0-BP3 bits can be changed WP#=1 and SRWD bit=0, or WP#=0 and SRWD bit=0, or WP#=1 and SRWD=1 The protected area cannot be program or erase. The SRWD, BP0-BP3 of status register bits cannot be changed WP#=0, SRWD bit=1 The protected area cannot be program or erase. Note: As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in Table 2. As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM). Software Protected Mode (SPM): - When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM). - When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM) Hardware Protected Mode (HPM): - When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2, BP1, BP0 and hardware protected mode by the WP#/SIO2 to against data modification. Note: To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is entered. If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via BP3, BP2, BP1, BP0. If the system goes into four I/O mode, the feature of HPM will be disabled. P/N: PM1532 REV. 1.3, FEB. 10, 2012 19 MX25L25635E (6) Enter 4-byte mode (EN4B) The EN4B instruction enables accessing the address length of 32-bit for the memory area of higher density (larger than 128Mb). The device default is in 24-bit address mode; after sending out the EN4B instruction, the bit2 (4BTYE bit) of security register will be automatically set to "1" to indicate the 4-byte address mode has been enabled. Once the 4-byte address mode is enabled, the address length becomes 32-bit instead of the default 24-bit. There are three methods to exit the 4-byte mode: writing exit 4-byte mode (EX4B) instruction, Hardware Reset or power-off. All instructions are accepted normally, and just the address bit is changed from 24-bit to 32-bit. The sequence of issuing EN4B instruction is: CS# goes low → sending EN4B instruction to enter 4-byte mode( automatically set 4BYTE bit as "1") → CS# goes high. (7) Exit 4-byte mode (EX4B) The EX4B instruction is executed to exit the 4-byte address mode and return to the default 3-bytes address mode. After sending out the EX4B instruction, the bit2 (4BTYE bit) of security register will be cleared to be "1" to indicate the exit of the 4-byte address mode. Once exiting the 4-byte address mode, the address length will return to 24-bit. The sequence of issuing EX4B instruction is: CS# goes low → sending EX4B instruction to exit 4-byte mode (automatically clear the 4BYTE bit to be "0") → CS# goes high. (8) Read Data Bytes (READ) The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached. The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B) Mode section. The sequence of issuing READ instruction is: CS# goes low → sending READ instruction code→ 3-byte or 4-byte address (depending on mode state) on SI → data out on SO → to end READ operation can use CS# to high at any time during data out. (Please refer to Figure 15) (9) Read Data Bytes at Higher Speed (FAST_READ) The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has been reached. The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B) Mode section. The sequence of issuing FAST_READ instruction is: CS# goes low → sending FAST_READ instruction code → 3-byte or 4-byte address (depending on mode state) on SI → 1-dummy byte (default) address on SI → data out on P/N: PM1532 REV. 1.3, FEB. 10, 2012 20 MX25L25635E SO → to end FAST_READ operation can use CS# to high at any time during data out. (Please refer to Figure 16) While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. (10) 2 x I/O Read Mode (2READ) The 2READ instruction enables Double throughput of Serial Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit. The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B) Mode section. The sequence of issuing 2READ instruction is: CS# goes low → sending 2READ instruction → 3-byte or 4-byte address (depending on mode state) interleave on SIO1 & SIO0 → 4-bit dummy cycle on SIO1 & SIO0 → data out interleave on SIO1 & SIO0 → to end 2READ operation can use CS# to high at any time during data out (Please refer to Figure 17 for 2 x I/O Read Mode Timing Waveform). While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. (11) Dual Read Mode (DREAD) The DREAD instruction enable double throughput of Serial Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruction, the following data out will perform as 2-bit instead of previous 1-bit. The sequence of issuing DREAD instruction is: CS# goes low → sending DREAD instruction → 3-byte or 4-byte address on SI → 8-bit dummy cycle → data out interleave on SO1 & SO0 → to end DREAD operation can use CS# to high at any time during data out (Please refer to Figure 18 for Dual Read Mode Timing Waveform). While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. (12) 4 x I/O Read Mode (4READ) The 4READ instruction enables quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit. P/N: PM1532 REV. 1.3, FEB. 10, 2012 21 MX25L25635E The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B) Mode section. The sequence of issuing 4READ instruction is: CS# goes low → sending 4READ instruction → 3-byte or 4-byte address (depending on mode state) interleave on SIO3, SIO2, SIO1 & SIO0 → 6 dummy cycles → data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end 4READ operation can use CS# to high at any time during data out (Please refer to Figure 19 for 4 x I/O Read Mode Timing Waveform). Another sequence of issuing 4 READ instruction especially useful in random access is : CS# goes low→ sending 4 READ instruction → 3-byte or 4-byte address (depending on mode state) interleave on SIO3, SIO2, SIO1 & SIO0 → performance enhance toggling bit P[7:0]→ 4 dummy cycles → data out still CS# goes high → CS# goes low (reduce 4 Read instruction) → 3-byte or 4-byte address (depending on mode state) random access address (Please refer to Figure 21 for 4x I/O Read Enhance Performance Mode timing waveform). In the performance-enhancing mode (the waveform figure), P[7:4] must be toggling with P[3:0] ; likewise P[7:0]=A5h,5Ah,F0h or 0Fh can make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0]; likewise P[7:0]=FFh,00h,AAh or 55h. These commands will reset the performance enhance mode. And afterwards CS# is raised and then lowered, the system then will return to normal operation. While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. (13) Quad Read Mode (QREAD) The QREAD instruction enable quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status register must be set to "1" before sending the QREAD. The address is latched on rising edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single QREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing QREAD instruction, the following data out will perform as 4-bit instead of previous 1-bit. The sequence of issuing QREAD instruction is: CS# goes low→ sending QREAD instruction → 3-byte or 4-byte address on SI → 8-bit dummy cycle → data out interleave on SO3, SO2, SO1 & SO0→ to end QREAD operation can use CS# to high at any time during data out (Please refer to Figure 20 for Quad Read Mode Timing Waveform). While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. (14) Sector Erase (SE) The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector (Table of memory organization) is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The default mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode. If RESET# goes low while Sector Erase (SE) execution is on going, the operation of SE will finish after tSE timing before entering Reset mode. P/N: PM1532 REV. 1.3, FEB. 10, 2012 22 MX25L25635E The sequence of issuing SE instruction is: CS# goes low → sending SE instruction code→ 3-byte or 4-byte address (depending on mode state) on SI → CS# goes high. (Please refer to Figure 22) The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the sector is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no change) and the WEL bit still be reset. (15) Block Erase (BE) The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 64K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (Table of memory organization) is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The default mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode. The sequence of issuing BE instruction is: CS# goes low → sending BE instruction code → 3-byte or 4-byte address (depending on mode state) on SI → CS# goes high. (Please refer to Figure 23) The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the block is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no change) and the WEL bit still be reset. (16) Block Erase (BE32K) The Block Erase (BE32) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 32K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE32). Any address of the block (Table of memory organization) is a valid address for Block Erase (BE32) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The default mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode. If RESET# goes low while Block Erase (BE32K) execution is on going, the operation of BE32K will finish after tBE (32KB) timing before entering Reset mode. The sequence of issuing BE32 instruction is: CS# goes low → sending BE32 instruction code → 3-byte or 4-byte address (depending on mode state) on SI → CS# goes high. (Please refer to Figure 23) The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the block is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no change) and the WEL bit still be reset. P/N: PM1532 REV. 1.3, FEB. 10, 2012 23 MX25L25635E (17) Chip Erase (CE) The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. The sequence of issuing CE instruction is: CS# goes low → sending CE instruction code → CS# goes high. (Please refer to Figure 24) The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is protected the Chip Erase (CE) instruction will not be executed, but WEL will be reset. (18) Page Program (PP) The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device programs only the last 256 data bytes sent to the device. If the entire 256 data bytes are going to be programmed, A7-A0 (The eight least significant address bits) should be set to 0. If the eight least significant address bits (A7-A0) are not all 0, all transmitted data going beyond the end of the current page are programmed from the start address of the same page (from the address A7-A0 are all 0). If more than 256 bytes are sent to the device, the data of the last 256-byte is programmed at the request page and previous data will be disregarded. If less than 256 bytes are sent to the device, the data is programmed at the requested address of the page without effect on other address of the same page. The default mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode. The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte or 4-byte address (depending on mode state) on SI→ at least 1-byte on data on SI→ CS# goes high. (Please refer to Figure 25) The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte boundary (the latest eighth bit of data being latched in), otherwise, the instruction will be rejected and will not be executed. The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no change) and the WEL bit will still be reset. (19) 4 x I/O Page Program (4PP) The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1" before sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1, SIO2, and SIO3, which can raise programer performance and and the effectiveness of application of lower clock less than 20MHz. For system with faster clock, the Quad page program cannot provide more actual favors, because P/N: PM1532 REV. 1.3, FEB. 10, 2012 24 MX25L25635E the required internal page program time is far more than the time data flows in. Therefore, we suggest that while executing this command (especially during sending data), user can slow the clock speed down to 20MHz below. The other function descriptions are as same as standard page program. The default mode is 3-byte address, to access higher address( 4-byte address) which requires to enter the 4-byte address read mode. The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte or 4-byte address (depending on mode state) on SIO[3:0]→ at least 1-byte on data on SIO[3:0]→ CS# goes high. (���������� Please refer to Figure 26) If the page is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no change) and the WEL bit will still be reset. P/N: PM1532 REV. 1.3, FEB. 10, 2012 25 MX25L25635E The Program/Erase function instruction function flow is as follows: Program/Erase Flow(1) - verify by reading array data Start WREN command RDSR command* WREN=1? No Yes Program/erase command Write program data/address (Write erase address) RDSR command No WIP=0? Yes Read array data (same address of PGM/ERS) Verify OK? No Yes Program/erase fail Program/erase successfully CLSR(30h) command Program/erase another block? No Yes * * Issue RDSR to check BP[3:0]. * If WPSEL=1, issue RDBLOCK to check the block status. Program/erase completed P/N: PM1532 REV. 1.3, FEB. 10, 2012 26 MX25L25635E Program/Erase Flow(2) - verify by reading program/erase fail flag bit Start WREN command RDSR command* WREN=1? No Yes Program/erase command Write program data/address (Write erase address) RDSR command No WIP=0? Yes RDSCUR command REGPFAIL/REGEFAIL=1? Yes No Program/erase fail Program/erase successfully CLSR(30h) command Program/erase Yes another block? No * Issue RDSR to check BP[3:0]. * If WPSEL=1, issue RDBLOCK to check the block status. Program/erase completed P/N: PM1532 REV. 1.3, FEB. 10, 2012 27 MX25L25635E (20) Continuously program mode (CP mode) The CP mode may enhance program performance by automatically increasing address to the next higher address after each byte data has been programmed. The Continuously program (CP) instruction is for multiple byte program to Flash. A write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Continuously program (CP) instruction. CS# requires to go high before CP instruction is executing. After CP instruction and address input, two bytes of data is input sequentially from MSB(bit7) to LSB(bit0). The first byte data will be programmed to the initial address range with A0=0 and second byte data with A0=1. If only one byte data is input, the CP mode will not process. If more than two bytes data are input, the additional data will be ignored and only two byte data are valid. Any byte to be programmed should be in the erase state (FF) first. It will not roll over during the CP mode, once the last unprotected address has been reached, the chip will exit CP mode and reset write Enable Latch bit (WEL) as "0" and CP mode bit as "0". Please check the WIP bit status if it is not in write progress before entering next valid instruction. During CP mode, the valid commands are CP command (AD hex), WRDI command (04 hex), RDSR command (05 hex), and RDSCUR command (2B hex). And the WRDI command is valid after completion of a CP programming cycle, which means the WIP bit=0. The default mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode. The sequence of issuing CP instruction is : CS# goes low → sending CP instruction code → 3-byte or 4-byte address (depending on mode state) on SI pin → two data bytes on SI → CS# goes high to low → sending CP instruction and then continue two data bytes are programmed → CS# goes high to low → till last desired two data bytes are programmed → CS# goes high to low → sending WRDI (Write Disable) instruction to end CP mode → send RDSR instruction to verify if CP mode word program ends, or send RDSCUR to check bit4 to verify if CP mode ends. (Please refer to Figure 27 of CP mode timing waveform) Three methods to detect the completion of a program cycle during CP mode: 1) Software method-I: by checking WIP bit of Status Register to detect the completion of CP mode. 2) Software method-II: by waiting for a tBP time out to determine if it may load next valid command or not. 3) Hardware method: by writing ESRY (enable SO to output RY/BY#) instruction to detect the completion of a program cycle during CP mode. The ESRY instruction must be executed before CP mode execution. Once it is enable in CP mode, the CS# goes low will drive out the RY/BY# status on SO, "0" indicates busy stage, "1" indicates ready stage, SO pin outputs tri-state if CS# goes high. DSRY (disable SO to output RY/BY#) instruction to disable the SO to output RY/BY# and return to status register data output during CP mode. Please note that the ESRY/DSRY command are not accepted unless the completion of CP mode. If the page is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no change) and the WEL bit will still be reset. P/N: PM1532 REV. 1.3, FEB. 10, 2012 28 MX25L25635E (21) Deep Power-down (DP) The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to entering the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep power-down mode. It's different from Standby mode. The sequence of issuing DP instruction is: CS# goes low→ sending DP instruction code→ CS# goes high. (Please refer to Figure 28) Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP) and Read Electronic Signature (RES) instruction. (those instructions allow the ID being reading out). When Powerdown, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2. (22) Release from Deep Power-down (RDP), Read Electronic Signature (RES) The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip Select (CS#) is driven High, the device is put in the standby Power mode. If the device was not previously in the Deep Power-down mode, the transition to the standby Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the standby Power mode is delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2(max), as specified in Table 8. Once in the standby mode, the device waits to be selected, so that it can receive, decode and execute instructions. Reset# pin goes low will release the Flash from deep power down mode. RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new design, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device is in progress of program/erase/write cycles; there's no effect on the current program/erase/write cycles in progress. The sequence is shown as Figure 29, 30. The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction. The RDP instruction is for releasing from Deep Power-down Mode. (23) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4) The REMS, REMS2, and REMS4 instruction provides both the JEDEC assigned Manufacturer ID and the specific Device ID. The instruction is initiated by driving the CS# pin low and shift the instruction code "90h", "DFh" or "EFh" followed by two dummy bytes and one bytes address (A7~A0). After which, the Manufacturer ID for MXIC (C2h) and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 28. The Device ID values are listed in table of ID Definitions. If the one-byte address is initially set to 01h, then the Device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high. P/N: PM1532 REV. 1.3, FEB. 10, 2012 29 MX25L25635E Table 6. ID Definitions Command Type RDID manufacturer ID C2 RES REMS/REMS2/REMS4 manufacturer ID C2 MX25L25635E memory type 20 electronic ID 18 device ID 18 memory density 19 (24) Enter Secured OTP (ENSO) The ENSO instruction is for entering the additional 4K-bit Secured OTP mode. The additional 4K-bit Secured OTP is independent from main array, which may use to store unique serial number for system identifier. After entering the Secured OTP mode, and then follow standard read or program, procedure to read out the data or update data. The Secured OTP data cannot be updated again once it is lock-down. The sequence of issuing ENSO instruction is: CS# goes low → sending ENSO instruction to enter Secured OTP mode → CS# goes high. Please note that WRSR/WRSCUR/WPSEL/SBLK/GBLK/SBULK/GBULK/CE/BE/SE/BE32K commands are not acceptable during the access of secure OTP region, once Security OTP is lock down, only read related commands are valid. (25) Exit Secured OTP (EXSO) The EXSO instruction is for exiting the additional 4K-bit Secured OTP mode. The sequence of issuing EXSO instruction is: CS# goes low → sending EXSO instruction to exit Secured OTP mode → CS# goes high. (26) Read Security Register (RDSCUR) The RDSCUR instruction is for reading the value of Security Register. The Read Security Register can be read at any time (even in program/erase/write status register/write security register condition) and continuously. The sequence of issuing RDSCUR instruction is : CS# goes low → sending RDSCUR instruction → Security Register data out on SO → CS# goes high. The definition of the Security Register is as below: Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory before ex- factory or not. When it is "0", it indicates non-factory lock; "1" indicates factory- lock. Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for customer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 4K-bit Secured OTP area cannot be update any more. While it is in 4K-bit Secured OTP mode, array access is not allowed. 4BYTE Indicator bit. By writing EN4B instruction, the 4BYTE bit may be set to "1" to access the address length of 32-bit for higher density (large than 128Mb) memory area. The default state is "0", which means the mode of 24-bit address. The 4BYTE bit may be clear by power off or writing EX4B instruction to reset the state to be "0". P/N: PM1532 REV. 1.3, FEB. 10, 2012 30 MX25L25635E Continuously Program Mode (CP mode) bit. The Continuously Program Mode bit indicates the status of CP mode, "0" indicates not in CP mode; "1" indicates in CP mode. Program Fail Flag bit. While a program failure happened, the Program Fail Flag bit would be set. This bit will also be set when the user attempts to program a protected main memory region or a locked OTP region. This bit can indicate whether one or more of program operations fail, and can be reset by command CLSR (30h) Erase Fail Flag bit. While a erase failure happened, the Erase Fail Flag bit would be set. This bit will also be set when the user attempts to erase a protected main memory region or a locked OTP region. This bit can indicate whether one or more of erase operations fail, and can be reset by command CLSR (30h) Write Protection Select bit. The Write Protection Select bit indicates that WPSEL has been executed successfully. Once this bit has been set (WPSEL=1), all the blocks or sectors will be write-protected after the power-on every time. Once WPSEL has been set, it cannot be changed again, which means it's only for individual WP mode. Under the individual block protection mode (WPSEL=1), hardware protection is performed by driving WP#=0. Once WP#=0 all array blocks/sectors are protected regardless of the contents of SRAM lock bits. Security Register Definition bit7 bit6 bit5 bit4 WPSEL E_FAIL P_FAIL Continuously Program mode (CP mode) 0=normal WP mode 1=individual WP mode (default=0) 0=normal Erase succeed 1=indicate Erase failed (default=0) 0=normal Program succeed 1=indicate Program failed (default=0) non-volatile bit volatile bit OTP Read Only bit3 bit2 bit1 bit0 LDSO (lock-down 4K-bit 4K-bit Se- Secured OTP cured OTP) 0 = not lockdown 0= 1 = locknonfactory down lock (cannot 1 = factory program/ lock erase OTP) x 4BYTE 0=normal Program mode 1=CP mode (default=0) reserved 0=3-byte address mode, 1=4-byte address mode (default=0) volatile bit volatile bit volatile bit volatile bit non-volatile bit non-volatile bit Read Only Read Only Read Only Read Only OTP Read Only (27) Write Security Register (WRSCUR) The WRSCUR instruction is for changing the values of Security Register Bits. The WRSCUR instruction may change the values of bit1 (LDSO bit) for customer to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area cannot be updated any more. The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high. The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. P/N: PM1532 REV. 1.3, FEB. 10, 2012 31 MX25L25635E (28) Write Protection Selection (WPSEL) There are two write protection methods, (1) BP protection mode (2) individual block protection mode. If WPSEL=0, flash is under BP protection mode . If WPSEL=1, flash is under individual block protection mode. The default value of WPSEL is “0”. WPSEL command can be used to set WPSEL=1. Please note that WPSEL is an OTP bit. Once WPSEL is set to 1, there is no chance to recovery WPSEL back to “0”. If the flash is put on BP mode, the individual block protection mode is disabled. Contrarily, if flash is on the individual block protection mode, the BP mode is disabled. Every time after the system is powered-on, and the Security Register bit 7 is checked to be WPSEL=1, all the blocks or sectors will be write protected by default. User may only unlock the blocks or sectors via SBULK and GBULK instruction. Program or erase functions can only be operated after the Unlock instruction is conducted. BP protection mode, WPSEL=0: ARRAY is protected by BP3~BP0 and BP3~BP0 bits are protected by “SRWD=1 and WP#=0”, where SRWD is bit 7 of status register that can be set by WRSR command. Individual block protection mode, WPSEL=1: Blocks are individually protected by their own SRAM lock bits which are set to “1” after power up. SBULK and SBLK command can set SRAM lock bit to “0” and “1”. When the system accepts and executes WPSEL instruction, the bit 7 in security register will be set. It will activate SBLK, SBULK, RDBLOCK, GBLK, GBULK etc instructions to conduct block lock protection and replace the original Software Protect Mode (SPM) use (BP3~BP0) indicated block methods. Under the individual block protection mode (WPSEL=1), hardware protection is performed by driving WP#=0. Once WP#=0 all array blocks/sectors are protected regardless of the contents of SRAM lock bits. The sequence of issuing WPSEL instruction is: CS# goes low → sending WPSEL instruction to enter the individual block protect mode → CS# goes high. WPSEL instruction function flow is as follows: BP and SRWD if WPSEL=0 WPB pin BP3 BP2 BP1 BP0 SRWD 64KB 64KB 64KB (1) BP3~BP0 is used to define the protection group region. (The protected area size see Table2) (2) “SRWD=1 and WPB=0” is used to protect BP3~BP0. In this case, SRWD and BP3~BP0 of status register bits can not be changed by WRSR . . . 64KB P/N: PM1532 REV. 1.3, FEB. 10, 2012 32 MX25L25635E The individual block lock mode is effective after setting WPSEL=1 SRAM SRAM … … TOP 4KBx16 Sectors 4KB 4KB 4KB SRAM SRAM … 64KB SRAM … …… Uniform 64KB blocks 64KB 4KB SRAM … … Bottom 4KBx16 Sectors 4KB SRAM • Power-Up: All SRAM bits=1 (all blocks are default protected). All array cannot be programmed/erased • SBLK/SBULK(36h/39h): - SBLK(36h) : Set SRAM bit=1 (protect) : array can not be programmed /erased - SBULK(39h): Set SRAM bit=0 (unprotect): array can be programmed /erased - All top 4KBx16 sectors and bottom 4KBx16 sectors and other 64KB uniform blocks can be protected and unprotected SRAM bits individually by SBLK/SBULK command set. • GBLK/ GBULK(7Eh/98h): - GBLK(7Eh):Set all SRAM bits=1,whole chip are protected and cannot be programmed / erased. - GBULK(98h):Set all SRAM bits=0,whole chip are unprotected and can be programmed / erased. - All sectors and blocks SRAM bits of whole chip can be protected and unprotected at one time by GBLK/GBULK command set. • RDBLOCK(3Ch): - use RDBLOCK mode to check the SRAM bits status after SBULK /SBLK/GBULK/GBLK command set. SBULK / SBLK / GBULK / GBLK / RDBLOCK P/N: PM1532 REV. 1.3, FEB. 10, 2012 33 MX25L25635E WPSEL Flow start RDSCUR(2Bh) command Yes WPSEL=1? No WPSEL disable, block protected by BP[3:0] WPSEL(68h) command RDSR command WIP=0? No Yes RDSCUR(2Bh) command WPSEL=1? No Yes WPSEL set successfully WPSEL set fail WPSEL enable. Block protected by individual lock (SBLK, SBULK, … etc). P/N: PM1532 REV. 1.3, FEB. 10, 2012 34 MX25L25635E (29) Single Block Lock/Unlock Protection (SBLK/SBULK) These instructions are only effective after WPSEL was executed. The SBLK instruction is for write protection a specified block(or sector) of memory, using address bits to assign a 64Kbyte block (or 4K bytes sector) to be protected as read only. The SBULK instruction will cancel the block (or sector) write protection state. This feature allows user to stop protecting the entire block (or sector) through the chip unprotect command (GBULK). The default mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode. The WREN (Write Enable) instruction is required before issuing SBLK/SBULK instruction. The sequence of issuing SBLK/SBULK instruction is: CS# goes low → send SBLK/SBULK (36h/39h) instruction → send 3-byte or 4-byte address (depending on mode state) assign one block (or sector) to be protected on SI pin → CS# goes high. (Please refer to Figure 33) The CS# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not be executed. SBLK/SBULK instruction function flow is as follows: Block Lock Flow Start RDSCUR(2Bh) command WPSEL=1? No WPSEL command Yes WREN command SBLK command ( 36h address ) RDSR command WIP=0? No Yes RDBLOCK command ( 3Ch address ) Data = FFh ? No Yes Block lock successfully Lock another block? Block lock fail Yes No Block lock completed P/N: PM1532 REV. 1.3, FEB. 10, 2012 35 MX25L25635E Block Unlock Flow start RDSCUR(2Bh) command WPSEL=1? No WPSEL command Yes WREN command SBULK command ( 39h address ) RDSR command No WIP=0? Yes Unlock another block? Yes Unlock block completed? P/N: PM1532 REV. 1.3, FEB. 10, 2012 36 MX25L25635E (30) Read Block Lock Status (RDBLOCK) This instruction is only effective after WPSEL was executed. The RDBLOCK instruction is for reading the status of protection lock of a specified block(or sector), using address bits to assign a 64K bytes block (4K bytes sector) and read protection lock status bit which the first byte of Read-out cycle. The status bit is"1" to indicate that this block has be protected, that user can read only but cannot write/program /erase this block. The status bit is "0" to indicate that this block hasn't be protected, and user can read and write this block. The default mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode. The sequence of issuing RDBLOCK instruction is: CS# goes low → send RDBLOCK (3Ch) instruction → send 3-byte or 4-byte address (depending on mode state) to assign one block on SI pin → read block's protection lock status bit on SO pin → CS# goes high. (Please refer to Figure 34) (31) Gang Block Lock/Unlock (GBLK/GBULK) These instructions are only effective after WPSEL was executed. The GBLK/GBULK instruction is for enable/disable the lock protection block of the whole chip. The WREN (Write Enable) instruction is required before issuing GBLK/GBULK instruction. The sequence of issuing GBLK/GBULK instruction is: CS# goes low → send GBLK/GBULK (7Eh/98h) instruction → CS# goes high. (Please refer to Figure 35) The CS# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed. (32) Clear SR Fail Flags (CLSR) The CLSR instruction is for resetting the Program/Erase Fail Flag bit of Security Register. It should be executed before program/erase another block during programming/erasing flow without read array data. The sequence of issuing CLSR instruction is: CS# goes low → send CLSR instruction code → CS# goes high. The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. (33) Enable SO to Output RY/BY# (ESRY) The ESRY instruction is for outputting the ready/busy status to SO during CP mode. The sequence of issuing ESRY instruction is: CS# goes low → sending ESRY instruction code → CS# goes high. The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. (34) Disable SO to Output RY/BY# (DSRY) The DSRY instruction is for resetting ESRY during CP mode. The ready/busy status will not output to SO after DSRY issued. The sequence of issuing DSRY instruction is: CS# goes low → send DSRY instruction code → CS# goes high. The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. P/N: PM1532 REV. 1.3, FEB. 10, 2012 37 MX25L25635E (35) Read SFDP Mode (RDSFDP) The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on CFI. The sequence of issuing RDSFDP instruction is CS# goes low→send RDSFDP instruction (5Ah)→send 3 address bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP operation can use CS# to high at any time during data out. SFDP is a standard of JEDEC. JESD216. v1.0. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI SO 24 BIT ADDRESS 23 22 21 5Ah 3 2 1 0 High-Z CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Cycle SI 7 6 5 4 3 2 1 0 DATA OUT 2 DATA OUT 1 SO 7 6 5 4 3 2 1 0 7 MSB MSB P/N: PM1532 6 5 4 3 2 1 0 7 MSB REV. 1.3, FEB. 10, 2012 38 MX25L25635E Table a. Signature and Parameter Identification Data Values Description SFDP Signature Comment Fixed: 50444653h Add (h) DW Add Data (h/b) (Byte) (Bit) (Note1) 00h 07:00 53h Data (h) 53h 01h 15:08 46h 46h 02h 23:16 44h 44h 03h 31:24 50h 50h SFDP Minor Revision Number Start from 00h 04h 07:00 00h 00h SFDP Major Revision Number Start from 01h 05h 15:08 01h 01h Number of Parameter Headers Start from 01h 06h 23:16 01h 01h 07h 31:24 FFh FFh 00h: it indicates a JEDEC specified header. 08h 07:00 00h 00h Start from 00h 09h 15:08 00h 00h Start from 01h 0Ah 23:16 01h 01h How many DWORDs in the Parameter table 0Bh 31:24 09h 09h 0Ch 07:00 30h 30h 0Dh 15:08 00h 00h 0Eh 23:16 00h 00h 0Fh 31:24 FFh FFh it indicates Macronix manufacturer ID 10h 07:00 C2h C2h Start from 00h 11h 15:08 00h 00h Start from 01h 12h 23:16 01h 01h How many DWORDs in the Parameter table 13h 31:24 04h 04h 14h 07:00 60h 60h 15h 15:08 00h 00h 16h 23:16 00h 00h 17h 31:24 FFh FFh Unused ID number (JEDEC) Parameter Table Minor Revision Number Parameter Table Major Revision Number Parameter Table Length (in double word) Parameter Table Pointer (PTP) First address of JEDEC Flash Parameter table Unused ID number (Macronix manufacturer ID) Parameter Table Minor Revision Number Parameter Table Major Revision Number Parameter Table Length (in double word) Parameter Table Pointer (PTP) First address of Macronix Flash Parameter table Unused P/N: PM1532 REV. 1.3, FEB. 10, 2012 39 MX25L25635E Table b. Parameter Table (0): JEDEC Flash Parameter Tables Description Comment Block/Sector Erase sizes 00: Reserved, 01: 4KB erase, 10: Reserved, 11: not suport 4KB erase Write Granularity Write Enable Instruction Requested for Writing to Volatile Status Registers Add (h) DW Add Data (h/b) (Byte) (Bit) (Note1) 01:00 01b 0: 1Byte, 1: 64Byte or larger 02 1b 0: Nonvolatitle status bit 1: Volatitle status bit (BP status register bit) 03 0b 30h 0: use 50h opcode, 1: use 06h opcode Write Enable Opcode Select for Note: If target flash status register is Writing to Volatile Status Registers nonvolatile, then bits 3 and 4 must be set to 00b. Contains 111b and can never be Unused changed 4KB Erase Opcode 31h Data (h) E5h 04 0b 07:05 111b 15:08 20h 16 1b 18:17 01b 19 0b 20 1b 20h (1-1-2) Fast Read (Note2) 0=not support 1=support Address Bytes Number used in addressing flash array Double Transfer Rate (DTR) Clocking 00: 3Byte only, 01: 3 or 4Byte, 10: 4Byte only, 11: Reserved (1-2-2) Fast Read 0=not support 1=support (1-4-4) Fast Read 0=not support 1=support 21 1b (1-1-4) Fast Read 0=not support 1=support 22 1b 23 1b 33h 31:24 FFh 37h:34h 31:00 0FFFFFFFh 0=not support 1=support 32h Unused Unused Flash Memory Density (1-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states (Note3) Clocks) not support (1-4-4) Fast Read Number of 000b: Mode Bits not support Mode Bits (Note4) 38h (1-4-4) Fast Read Opcode 39h (1-1-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (1-1-4) Fast Read Number of 000b: Mode Bits not support Mode Bits 3Ah (1-1-4) Fast Read Opcode 3Bh P/N: PM1532 04:00 0 0100b 07:05 010b 15:08 EBh 20:16 0 1000b 23:21 000b 31:24 6Bh F3h FFh 44h EBh 08h 6Bh REV. 1.3, FEB. 10, 2012 40 MX25L25635E Description Comment (1-1-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (1-1-2) Fast Read Number of 000b: Mode Bits not support Mode Bits Add (h) DW Add Data (h/b) (Byte) (Bit) (Note1) 3Ch (1-1-2) Fast Read Opcode 3Dh (1-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (1-2-2) Fast Read Number of 000b: Mode Bits not support Mode Bits 3Eh (1-2-2) Fast Read Opcode 3Fh (2-2-2) Fast Read 0=not support 1=support Unused (4-4-4) Fast Read 0=not support 1=support 40h Unused 04:00 0 1000b 07:05 000b 15:08 3Bh 20:16 0 0100b 23:21 000b 31:24 BBh 00 0b 03:01 111b 04 0b 07:05 111b Data (h) 08h 3Bh 04h BBh EEh Unused 43h:41h 31:08 0xFFh 0xFFh Unused 45h:44h 15:00 0xFFh 0xFFh 20:16 0 000b 23:21 000b (2-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (2-2-2) Fast Read Number of 000b: Mode Bits not support Mode Bits 46h (2-2-2) Fast Read Opcode 47h 31:24 FFh FFh 49h:48h 15:00 0xFFh 0xFFh 20:16 0 0000b 23:21 000b Unused 00h (4-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (4-4-4) Fast Read Number of 000b: Mode Bits not support Mode Bits 4Ah (4-4-4) Fast Read Opcode 4Bh 31:24 FFh FFh 4Ch 07:00 0Ch 0Ch 4Dh 15:08 20h 20h 4Eh 23:16 0Fh 0Fh 4Fh 31:24 52h 52h 50h 07:00 10h 10h 51h 15:08 D8h D8h 52h 23:16 00h 00h 53h 31:24 FFh FFh Sector Type 1 Size Sector/block size = 2^N bytes (Note5) 0x00b: this sector type doesn't exist Sector Type 1 erase Opcode Sector Type 2 Size Sector/block size = 2^N bytes 0x00b: this sector type doesn't exist Sector Type 2 erase Opcode Sector Type 3 Size Sector/block size = 2^N bytes 0x00b: this sector type doesn't exist Sector Type 3 erase Opcode Sector Type 4 Size Sector/block size = 2^N bytes 0x00b: this sector type doesn't exist Sector Type 4 erase Opcode P/N: PM1532 00h REV. 1.3, FEB. 10, 2012 41 MX25L25635E Table c. Parameter Table (1): Macronix Flash Parameter Tables Description Comment Add (h) DW Add Data (h/b) (Byte) (Bit) (Note1) Data (h) Vcc Supply Maximum Voltage 2000h=2.000V 2700h=2.700V 3600h=3.600V 61h:60h 07:00 15:08 00h 36h 00h 36h Vcc Supply Minimum Voltage 1650h=1.650V 2250h=2.250V 2350h=2.350V 2700h=2.700V 63h:62h 23:16 31:24 00h 27h 00h 27h HW Reset# pin 0=not support 1=support 00 1b HW Hold# pin 0=not support 1=support 01 1b Deep Power Down Mode 0=not support 1=support 02 1b SW Reset 0=not support 1=support 03 0b SW Reset Opcode Reset Enable (66h) should be issued 65h:64h before Reset command 11:04 1111 1111b (FFh) Program Suspend/Resume 0=not support 1=support 12 0b Erase Suspend/Resume 0=not support 1=support 13 0b 14 1b 15 0b 66h 23:16 FFh FFh 67h 31:24 FFh FFh Unused Wrap-Around Read mode 0=not support 1=support Wrap-Around Read mode Opcode Wrap-Around Read data length 08h:support 8B wrap-around read 16h:8B&16B 32h:8B&16B&32B 64h:8B&16B&32B&64B Individual block lock 0=not support 1=support 00 1b Individual block lock bit (Volatile/Nonvolatile) 0=Volatile 1=Nonvolatile 01 0b 09:02 0011 0110b (36h) 10 0b 11 1b Individual block lock Opcode 4FF7h Individual block lock Volatile protect bit default protect status 0=protect 1=unprotect Secured OTP 0=not support 1=support Read Lock 0=not support 1=support 12 0b Permanent Lock 0=not support 1=support 13 0b Unused 15:14 11b Unused 31:16 0xFFh 0xFFh 31:00 0xFFh 0xFFh Unused 6Bh:68h 6Fh:6Ch P/N: PM1532 C8D9 REV. 1.3, FEB. 10, 2012 42 MX25L25635E Note 1: h/b is hexadecimal or binary. Note 2: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x), address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1), (2-2-2), and (4-4-4) Note 3: Wait States is required dummy clock cycles after the address bits or optional mode bits. Note 4: Mode Bits is optional control bits that follow the address bits. These bits are driven by the system controller if they are specified. (eg,read performance enhance toggling bits) Note 5: 4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h Note 6: 0xFFh means all data is blank ("1b"). P/N: PM1532 REV. 1.3, FEB. 10, 2012 43 MX25L25635E POWER-ON STATE The device is at below states when power-up: - Standby mode ( please note it is not Deep Power-down mode) - Write Enable Latch (WEL) bit is reset - 3-byte address mode The device must not be selected during power-up and power-down stage unless the VCC achieves below correct level: - VCC minimum at power-up stage and then after a delay of tVSL - GND at power-down Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level. An internal Power-on Reset (POR) circuit may protect the device from data corruption and inadvertent data change during power up state. For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The read, write, erase, and program command should be sent after the time delay: - tVSL after VCC reached VCC minimum level The device can accept read command after VCC reached VCC minimum and a time delay of tVSL. Please refer to the figure of "Power-up Timing". Note: - To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended. (generally around 0.1uF) P/N: PM1532 REV. 1.3, FEB. 10, 2012 44 MX25L25635E ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Rating Value Ambient Operating Temperature Industrial grade -40°C to 85°C Storage Temperature -55°C to 125°C Applied Input Voltage -0.5V to 4.6V Applied Output Voltage -0.5V to 4.6V VCC to Ground Potential -0.5V to 4.6V NOTICE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. 2. Specifications contained within the following tables are subject to change. 3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see Figure 3, 4. Figure 4. Maximum Positive Overshoot Waveform Figure 3. Maximum Negative Overshoot Waveform 20ns 20ns 20ns Vss Vcc + 2.0V Vss-2.0V Vcc 20ns 20ns 20ns CAPACITANCE TA = 25°C, f = 1.0 MHz Symbol Parameter CIN COUT Min. Typ. Max. Unit Input Capacitance 30 pF VIN = 0V Output Capacitance 30 pF VOUT = 0V P/N: PM1532 Conditions REV. 1.3, FEB. 10, 2012 45 MX25L25635E Figure 5. OUTPUT LOADING DEVICE UNDER 2.7K ohm TEST CL 6.2K ohm +3.3V DIODES=IN3064 OR EQUIVALENT CL=30/15pF Including jig capacitance P/N: PM1532 REV. 1.3, FEB. 10, 2012 46 MX25L25635E Table 7. DC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V) Symbol Parameter Notes Min. Max. Units Test Conditions VCC = VCC Max, VIN = VCC or GND, HOLD# = VCC VCC = VCC Max, VOUT = VCC or GND ILI Input Load Current 1 ±4 uA ILO Output Leakage Current 1 ±4 uA ISB1 VCC Standby Current 1 200 uA VIN = VCC or GND, CS# = VCC, HOLD# = VCC ISB2 Deep Power-down Current 80 uA VIN = VCC or GND, CS# = VCC, HOLD# = VCC 45 mA f=80MHz, fQ=70MHz (4 x I/O read) SCLK=0.1VCC/0.9VCC, SO=Open 40 mA fT=70MHz (2 x I/O read) SCLK=0.1VCC/0.9VCC, SO=Open 30 mA f=50MHz, SCLK=0.1VCC/0.9VCC, SO=Open 25 mA Program in Progress, CS# = VCC 40 mA Program status register in progress, CS#=VCC 1 25 mA Erase in Progress, CS#=VCC 1 40 mA Erase in Progress, CS#=VCC 0.8 V ICC1 VCC Read VIL VCC Program Current (PP) VCC Write Status Register (WRSR) Current VCC Sector Erase Current (SE) VCC Chip Erase Current (CE) Input Low Voltage VIH Input High Voltage VOL Output Low Voltage VOH Output High Voltage ICC2 ICC3 ICC4 ICC5 1 1 -0.5 0.7VCC VCC+0.4 0.4 VCC-0.2 P/N: PM1532 V V IOL = 1.6mA V IOH = -100uA REV. 1.3, FEB. 10, 2012 47 MX25L25635E Table 8. AC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V) Symbol Alt. Parameter fSCLK fC fRSCLK fR fT fQ fTSCLK f4PP Min. Clock Frequency for the following instructions: FAST_READ, RDSFDP, PP, SE, BE, CE, DP, RES, RDP, WREN, WRDI, RDID, RDSR, WRSR tCLH Clock High Time tCL(1) tCLL Clock Low Time Fast_Read Read Fast_Read Read tCLCH(2) Clock Rise Time (3) (peak to peak) tCHCL(2) Clock Fall Time (3) (peak to peak) tSLCH tCSS CS# Active Setup Time (relative to SCLK) tCHSL CS# Not Active Hold Time (relative to SCLK) tDVCH tDSU Data In Setup Time tCHDX tDH Data In Hold Time tCHSH CS# Active Hold Time (relative to SCLK) tSHCH CS# Not Active Setup Time (relative to SCLK) tSHSL(3) tCSH CS# Deselect Time tSHQZ(2) tDIS Output Disable Time tV Clock Low to Output Valid VCC=2.7V~3.6V Loading: 15pF Loading: 30pF tHO Output Hold Time HOLD# Setup Time (relative to SCLK) HOLD# Hold Time (relative to SCLK) HOLD Setup Time (relative to SCLK) HOLD Hold Time (relative to SCLK) tHHQX(2) tLZ tHLQZ(2) tHZ HOLD# to Output High-Z tWHSL(4) tSHWL(4) tDP(2) Loading: 15pF Loading: 30pF VCC=3.0V~3.6V tCLQX tHLCH tCHHH tHHCH tCHHL Unit 80 MHz 50 70 70 20 5.5 9 5.5 9 0.1 0.1 8 5 2 5 5 8 15 MHz MHz MHz MHz ns ns ns ns V/ns V/ns ns ns ns ns ns ns ns 100 ns Clock Frequency for READ instructions Clock Frequency for 2READ/DREAD instructions Clock Frequency for 4READ/QREAD instructions Clock Frequency for 4PP (Quad page program) tCH(1) tCLQV Max. D.C. Read Write/Erase/ Program 2.7V-3.6V 3.0V-3.6V 1 I/O 2 I/O & 4 I/O 2 I/O & 4 I/O 1 I/O 2 I/O & 4 I/O 2 I/O & 4 I/O 2.7V-3.6V 3.0V-3.6V 2.7V-3.6V 3.0V-3.6V HOLD to Output Low-Z Write Protect Setup Time Write Protect Hold Time CS# High to Deep Power-down Mode P/N: PM1532 2 8 5 8 5 20 100 Typ. 12 10 12 12 15 12 12 13 12 10 12 10 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns us REV. 1.3, FEB. 10, 2012 48 MX25L25635E Symbol tRES1(2) tRES2(2) tW tBP tPP tSE tBE tBE tCE tWPS tWSR Alt. Parameter CS# High to Standby Mode without Electronic Signature Read CS# High to Standby Mode with Electronic Signature Read Write Status Register Cycle Time Byte-Program Page Program Cycle Time Sector Erase Cycle Time (4KB) Block Erase Cycle Time (32KB) Block Erase Cycle Time (64KB) Chip Erase Cycle Time Write Protection Selection Time Write Security Register Time Min. Typ. 40 9 1.4 60 0.5 0.7 160 Max. 100 100 100 300 5 300 2 2 400 1 1 Unit us us ms us ms ms s s s ms ms Notes: 1. tCH + tCL must be greater than or equal to 1/ fC. 2. Value guaranteed by characterization, not 100% tested in production. 3.Only applicable as a constraint for a WRSR instruction when SRWD is set at 1. P/N: PM1532 REV. 1.3, FEB. 10, 2012 49 MX25L25635E Timing Analysis Figure 6. Serial Input Timing tSHSL CS# tCHSL tSLCH tCHSH tSHCH SCLK tDVCH tCHCL tCHDX tCLCH LSB MSB SI High-Z SO Figure 7. Output Timing CS# tCH SCLK tCLQV tCLQX tCL tCLQV tSHQZ tCLQX LSB SO tQLQH tQHQL SI ADDR.LSB IN P/N: PM1532 REV. 1.3, FEB. 10, 2012 50 MX25L25635E Figure 8. Hold Timing CS# tHLCH tCHHL tHHCH SCLK tCHHH tHLQZ tHHQX SO HOLD# * SI is "don't care" during HOLD operation. Figure 9. WP# Setup Timing and Hold Timing during WRSR when SRWD=1 WP# tSHWL tWHSL CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK 01 SI SO High-Z P/N: PM1532 REV. 1.3, FEB. 10, 2012 51 MX25L25635E Figure 10. Write Enable (WREN) Sequence (Command 06) CS# 0 1 2 3 4 5 6 7 5 6 7 SCLK Command SI 06 High-Z SO Figure 11. Write Disable (WRDI) Sequence (Command 04) CS# 0 1 2 3 4 SCLK Command SI 04 High-Z SO P/N: PM1532 REV. 1.3, FEB. 10, 2012 52 MX25L25635E Figure 12. Read Identification (RDID) Sequence (Command 9F) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31 SCLK Command SI 9F Manufacturer Identification High-Z SO Device Identification D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 MSB D3 D2 D1 D0 MSB Figure 13. Read Status Register (RDSR) Sequence (Command 05) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK command 05 SI SO Status Register Out High-Z D7 D6 D5 D4 D3 D2 D1 D0 MSB Figure 14. Write Status Register (WRSR) Sequence (Command 01) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK SI SO command Status Register In 01 D7 D6 D5 D4 D3 D2 D1 D0 MSB High-Z P/N: PM1532 REV. 1.3, FEB. 10, 2012 53 MX25L25635E Figure 15. Read Data Bytes (READ) Sequence (Command 03) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK Command 24 ADD Cycles (Note) 03 SI A23 A22 A21 A3 A2 A1 A0 MSB Data Out 1 High-Z SO Data Out 2 D7 D6 D5 D4 D3 D2 D1 D0 D7 MSB MSB Note: Please note the above address cycles are based on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. Figure 16. Read at Higher Speed (FAST_READ) Sequence (Command 0B) CS# 0 1 2 3 4 5 6 7 8 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 9 10 SCLK Command SI SO 0B 24 ADD Cycles 8 Dummy Cycles (Note) A23 A22 A21 A3 A2 A1 A0 Data Out 1 High-Z Data Out 2 D7 D6 D5 D4 D3 D2 D1 D0 D7 MSB Note: Please note the above address cycles are based on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. P/N: PM1532 REV. 1.3, FEB. 10, 2012 54 MX25L25635E Figure 17. 2 x I/O Read Mode Sequence (Command BB) CS# 0 1 2 3 4 5 6 7 8 SCLK  12 ADD Cycle (Note 2) Command BB(hex) SI/SIO0 SO/SIO1 18 19 20 21 22 23 24 25 26 27 28 29 9 High Impedance 4 dummy cycle Data Out 1 Data Out 2 A22 A20  A2 A0 P2 P0 D6 D4 D2 D0 D6 D4 A23 A21  A3 A1 P3 P1 D7 D5 D3 D1 D7 D5 Note: 1. SI/SIO0 or SO/SIO1 should be kept "0h" or "Fh" in the first two dummy cycles. In other words, P2=P0 or P3=P1 is necessary. 2. Please note the above address cycles are based on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. Figure 18. Dual Read Mode Sequence (Command 3B) CS# 0 1 2 3 4 5 6 7 8 SCLK  Command SI/SIO0 SO/SIO1 30 31 32 9 3B  24 ADD Cycle A22 A21  High Impedance 39 40 41 42 43 44 45 A2 A0 8 dummy cycle Data Out 1 Data Out 2 D6 D4 D2 D0 D6 D4 D7 D5 D3 D1 D7 D5 P/N: PM1532 REV. 1.3, FEB. 10, 2012 55 MX25L25635E Figure 19. 4 x I/O Read Mode Sequence (Command EB) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 SCLK Command EB SI/SIO0 SO/SIO1 WP#/SIO2 HOLD#/SIO3 6 ADD Cycles (Note 3) High Impedance High Impedance High Impedance Performance Enhance Indicator (Note1, 2) 4 dummy cycles Data Data Out 1 Out 2 Data Out 3 A20 A16 A12 A8 A4 A0 P4 P0 D4 D0 D4 D0 D4 A21 A17 A13 A9 A5 A1 P5 P1 D5 D1 D5 D1 D5 A22 A18 A14 A10 A6 A2 P6 P2 D6 D2 D6 D2 D6 A23 A19 A15 A11 A7 A3 P7 P3 D7 D3 D7 D3 D7 Note: 1. Hi-impedance is inhibited for the two clock cycles. 2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) will result in entering the performance enhance mode. 3. Please note the above address cycles are based on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. Figure 20. Quad Read Mode Sequence (Command 6B) CS# 0 1 2 3 4 5 6 7 8 … Command SI/SIO0 SO/SIO1 WP#/SIO2 HOLD#/SIO3 29 30 31 32 33 9 SCLK 6B … 24 ADD Cycles A23 A22 … High Impedance 38 39 40 41 42 A2 A1 A0 8 dummy cycles Data Data Out 1 Out 2 Data Out 3 D4 D0 D4 D0 D4 D5 D1 D5 D1 D5 High Impedance D6 D2 D6 D2 D6 High Impedance D7 D3 D7 D3 D7 P/N: PM1532 REV. 1.3, FEB. 10, 2012 56 MX25L25635E Figure 21. 4 x I/O Read Enhance Performance Mode Sequence (Command EB) CS# 0 1 SCLK SI/SIO0 SO/SIO1 WP#/SIO2 HOLD#/SIO3 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 n+1    n+9  n+7 n+13   4 dummy cycles Command 6 ADD Cycles (Note 3) EB A20 A16 A12 A8 A4 A0 P4 P0 D4 D0 D4 D0 A20  A0 P4 P0 D4 D0 D4 D0 D4 A21 A17 A13 A9 A5 A1 P5 P1 D5 D1 D5 D1 A21  A1 P5 P1 D5 D1 D5 D1 D5 A22 A18 A14 A10 A6 A2 P6 P2 D6 D2 D6 D2 A22  A2 P6 P2 D6 D2 D6 D2 D6 A23 A19 A15 A11 A7 A3 P7 P3 D7 D3 D7 D3 A23  A3 P7 P3 D7 D3 D7 D3 D7 High Impedance High Impedance High Impedance Performance enhance indicator (Note) Data Data Out 1 Out 2 6 ADD Cycles Performance enhance indicator (Note) 4 dummy cycles Data Data Out 1 Out 2 Data Out 3 Note: 1. Performance enhance mode, if P7≠P3 & P6≠P2 & P5≠P1 & P4≠P0 (Toggling), ex: A5, 5A, 0F 2. Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF 3. Please note the above address cycles are based on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. P/N: PM1532 REV. 1.3, FEB. 10, 2012 57 MX25L25635E Figure 22. Sector Erase (SE) Sequence (Command 20) CS# 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK … 24 ADD Cycles (Note) Command SI … A23 A22 20 A2 A1 A0 MSB Note: Please note the above address cycles are based on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. Figure 23. Block Erase (BE/EB32K) Sequence (Command D8/52) CS# 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK 24 ADD Cycles (Note) Command SI D8/52 A23 A22 A2 A1 A0 MSB Note: Please note the above address cycles are based on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. Figure 24. Chip Erase (CE) Sequence (Command 60 or C7) CS# 0 1 2 3 4 5 6 7 SCLK Command SI 60 or C7 P/N: PM1532 REV. 1.3, FEB. 10, 2012 58 MX25L25635E Figure 25. Page Program (PP) Sequence (Command 02) 2079 2078 2077 2076 2075 2074 28 29 30 31 32 33 34 35 36 37 38 39 2073 0 1 2 3 4 5 6 7 8 9 10 2072 CS# SCLK Command 02 SI 24 ADD Cycles (Note) A23 A22 A21 A3 A2 A1 A0 Data Byte 1 Data Byte 256 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 MSB MSB Note: Please note the above address cycles are based on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. Figure 26. 4 x I/O Page Program (4PP) Sequence (Command 38) CS# 0 1 2 3 4 5 6 7 8 524 525 9 10 11 12 13 14 15 16 17 SCLK  Command 6 ADD cycles (Note) Data Byte 256 Data Data Byte 1 Byte 2 A20 A16 A12 A8 A4 A0 D4 D0 D4 D0  D4 D0 SO/SIO1 A21 A17 A13 A9 A5 A1 D5 D1 D5 D1  D5 D1 WP#/SIO2 A22 A18 A14 A10 A6 A2 D6 D2 D6 D2  D6 D2 HOLD#/SIO3 A23 A19 A15 A11 A7 A3 D7 D3 D7 D3  D7 D3 SI/SIO0 38 Note: Please note the above address cycles are based on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. P/N: PM1532 REV. 1.3, FEB. 10, 2012 59 MX25L25635E Figure 27. Continuously Program (CP) Mode Sequence with Hardware Detection (Command AD) CS# 0 1 30 31 31 32 6 7 8 9 47 48 0 1 6 7 8 20 21 22 23 24 0 7 0 7 8 SCLK Command SI S0 AD (hex) 24-bit address (Note 4) data in Byte 0, Byte1 Valid Command (Note 1) high impedance data in Byte n-1, Byte n 04 (hex) 05 (hex) status (Note 2) Note: 1. During CP mode, the valid commands are CP command (AD hex), WRDI command (04 hex), RDSR command (05 hex), and RDSCUR command (2B hex). 2. Once an internal programming operation begins, CS# goes low will drive the status on the SO pin and CS# goes high will return the SO pin to tri-state. 3. To end the CP mode, either reaching the highest unprotected address or sending Write Disable (WRDI) command (04 hex) may achieve it and then it is recommended to send RDSR command (05 hex) to verify if CP mode is ended. 4. Please note the above address cycles are based on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. P/N: PM1532 REV. 1.3, FEB. 10, 2012 60 MX25L25635E Figure 28. Deep Power-down (DP) Sequence (Command B9) CS# 0 1 2 3 4 5 6 tDP 7 SCLK Command B9 SI Deep Power-down Mode Stand-by Mode Figure 29. Read Electronic Signature (RES) Sequence (Command AB) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK Command SI tRES2 24 Dummy Cycles 23 22 21 AB … 3 2 1 0 MSB Electronic Signature Out High-Z SO D7 D6 D5 D4 D3 D2 D1 D0 MSB Deep Power-down Mode Stand-by Mode Figure 30. Release from Deep Power-down (RDP) Sequence (Command AB) CS# 0 1 2 3 4 5 6 tRES1 7 SCLK Command SI SO AB High-Z Deep Power-down Mode P/N: PM1532 Stand-by Mode REV. 1.3, FEB. 10, 2012 61 MX25L25635E Figure 31. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF) CS# 0 1 2 3 4 5 6 7 8 9 10 SCLK Command SI SO 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 2 Dummy Bytes 15 14 13 90 ADD (1) 3 2 1 0 7 6 5 4 3 2 1 0 Manufacturer ID High-Z Device ID D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 MSB MSB MSB Notes: 1. A0=0 will output the Manufacturer ID first and A0=1 will output Device ID first. A1~A23 is don't care. 2. Instruction is either 90(hex) or EF(hex) or DF(hex). Figure 32. Write Protection Selection (WPSEL) Sequence (Command 68) CS# 0 1 2 3 4 5 6 7 SCLK Command SI 68 P/N: PM1532 REV. 1.3, FEB. 10, 2012 62 MX25L25635E Figure 33. Single Block Lock/Unlock Protection (SBLK/SBULK) Sequence (Command 36/39) CS# 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK 24 Bit Address Cycles (Note) Command SI 36/39 A23 A22 A2 A1 A0 MSB Note: Please note the above address cycles are based on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. Figure 34. Read Block Protection Lock Status (RDBLOCK) Sequence (Command 3C) CS# 0 1 2 3 4 5 6 7 8 28 29 30 31 32 33 34 35 36 37 38 39 9 10 SCLK Command SI 3C 24 ADD Cycles (Note) A23 A22 A21 A3 A2 A1 A0 MSB SO Block Protection Lock status out High-Z D7 D6 D5 D4 D3 D2 D1 D0 MSB Note: Please note the above address cycles are based on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. Figure 35. Gang Block Lock/Unlock (GBLK/GBULK) Sequence (Command 7E/98) CS# 0 1 2 3 4 5 6 7 SCLK Command SI 7E/98 P/N: PM1532 REV. 1.3, FEB. 10, 2012 63 MX25L25635E RESET Driving the RESET# pin low for a period of tRLRH or longer will reset the device. After reset cycle, the device is at the following states: - Standby mode - All the volatile bits such as WEL/WIP/SRAM lock bit will return to the default status as power on. - 3-byte address mode If the device is under programming or erasing, driving the RESET# pin low will also terminate the operation and data could be lost. During the resetting cycle, the SO data becomes high impedance and the current will be reduced to minimum. Figure 36. RESET Timing CS# tRHSL SCLK tRH tRS RESET# tRLRH Table 9. Reset Timing Symbol tRLRH tRS tRH tRHSL Alt. Parameter Reset Pulse Width Reset Setup Time Reset Hold Time Reset Recovery Time (During instruction decoding) Reset Recovery Time (For Read operation) Reset Recovery Time (For Erase or Program operation) Min. 10 15 15 30 30 300 tSE Reset Recovery Time (For SE/4KB Sector Erase operation) (1) tBE Reset Recovery Time (For BE32K/32KB Block Erase (32KB) operation) (1) tW Reset Recovery Time (for WRSR operation) (1) Typ. Max. Unit us ns ns us us us ms s ms Notes: 1. See Table 8 for tSE/tBE (32KB)/tW data. P/N: PM1532 REV. 1.3, FEB. 10, 2012 64 MX25L25635E Figure 37. Power-up Timing VCC VCC(max) Chip Selection is Not Allowed VCC(min) tVSL Device is fully accessible time Note: VCC (max.) is 3.6V and VCC (min.) is 2.7V. Table 10. Power-Up Timing Symbol tVSL(1) Parameter VCC(min) to CS# low Min. 300 Max. Unit us Note: 1. The parameter is characterized only. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). P/N: PM1532 REV. 1.3, FEB. 10, 2012 65 MX25L25635E OPERATING CONDITIONS At Device Power-Up and Power-Down AC timing illustrated in Figure 38 and Figure 39 are for the supply voltages and the control signals at device powerup and power-down. If the timing in the figures is ignored, the device will not operate correctly. During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL. Figure 38. AC Timing at Device Power-Up VCC VCC(min) GND tVR tSHSL CS# tSLCH tCHSL tSHCH tCHSH SCLK tDVCH tCHCL tCHDX LSB IN MSB IN SI High Impedance SO Symbol tVR tCLCH Parameter VCC Rise Time Notes 1 Min. 20 Max. 500000 Unit us/V Notes : 1. Sampled, not 100% tested. 2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "AC CHARACTERISTICS" table. P/N: PM1532 REV. 1.3, FEB. 10, 2012 66 MX25L25635E Figure 39. Power-Down Sequence During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation. VCC CS# SCLK P/N: PM1532 REV. 1.3, FEB. 10, 2012 67 MX25L25635E ERASE AND PROGRAMMING PERFORMANCE Parameter Typ. (1) Max. (2) Unit Write Status Register Cycle Time 40 100 ms Sector Erase Time (4KB) 60 300 ms Block Erase Time (64KB) 0.7 2 s Block Erase Time (32KB) 0.5 2 s Chip Erase Time 160 400 s 9 300 us 1.4 5 ms Byte Program Time (via page program command) Page Program Time Erase/Program Cycle 100,000 cycles Note: 1. Typical program and erase time assumes the following conditions: 25°C, 3.3V, and checker board pattern. 2. Under worst conditions of 85°C and 2.7V. 3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming command. DATA RETENTION Parameter Condition Min. Data retention 55˚C 20 Max. Unit years LATCH-UP CHARACTERISTICS Input Voltage with respect to GND on all power pins, SI, CS# Input Voltage with respect to GND on SO Current Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. P/N: PM1532 Min. -1.0V -1.0V -100mA Max. 2 VCCmax VCC + 1.0V +100mA REV. 1.3, FEB. 10, 2012 68 MX25L25635E ORDERING INFORMATION MX25L25635EMI-12G CLOCK (MHz) 80 MX25L25635EZNI-12G 80 PART NO. TEMPERATURE PACKAGE Remark -40°C~85°C 16-SOP (300mil) RoHS Compliant -40°C~85°C 8-WSON (8x6mm) RoHS Compliant P/N: PM1532 REV. 1.3, FEB. 10, 2012 69 MX25L25635E PART NAME DESCRIPTION MX 25 L 25635E M I 12 G OPTION: G: RoHS Compliant SPEED: 12: 80MHz TEMPERATURE RANGE: I: Industrial (-40° C to 85° C) PACKAGE: M: 300mil 16-SOP ZN: 8x6mm 8-WSON DENSITY & MODE: 25635E: 256Mb Quad I/O standard type TYPE: L: 3V DEVICE: 25: Serial Flash P/N: PM1532 REV. 1.3, FEB. 10, 2012 70 MX25L25635E PACKAGE INFORMATION P/N: PM1532 REV. 1.3, FEB. 10, 2012 71 MX25L25635E P/N: PM1532 REV. 1.3, FEB. 10, 2012 72 MX25L25635E REVISION HISTORY Revision No. Description Page Date 0.01 1. Changed title from "Advanced Information" to "Preliminary". P5 NOV/18/2009 2. Rename CFI to DMC. P6,13,16,37 3. Added DMC contents. P37~39 4. Added HOLD# pin condition for ILI/ISB1/ISB2, P43 revised VCC read test conditions and deleted notes of typical values. 5. Revised GBLK from 78h to 7Eh. P32 6. Revised Figure number in NOTICE. P41 7. Revised Figure 17. 2 x I/O Read Mode Sequence. P51 8. Added HOLD# in 4 x I/O Sequence. P51-52,54 9. Deleted CF (hex). P60 10. Added VCC and CS# ramp up example in device power-up P63 11. Deleted chip programming time evaluation conditions P64 0.02 1. Modified DMC table: 1Ch data from 28h to 30h P37 JAN/19/2010 0.03 1. Added Hardware Reset (RESET#) function P6,8,10,19,23 APR/13/2010 P28,44,59 2. Removed Parallel mode feature P43,44 3. Modified Figure 35. and Table 10. Power-up Timing P60 4. Modified Figure 36. AC Timing at Device Power-Up P61 5. Added Figure 37. Power-Down Sequence P62 6. Added 8-WSON package information P6,8,14,18,39 P63,64 7. Added "DREAD" & "QREAD" information P13,15,21,22, P45,52,53 1.0 1. Removed DMC sequence description & content table P6,13,16 JUL/01/2010 2. Removed command WREN in WPSEL and WRSCUR flows P31,32,34 3. Revised EN4B description P20 4. Removed "Preliminary" P5 1.1 1. Modified tCLQV for Table 8. AC CHARACTERISTICS P42 MAR/22/2011 2. Modified description for RoHS compliance P6,64 3. Modified CIN/COUT(max.) from 6/8(pF) to 30/30(pF) P39 1.2 1. Modified Figure 36. RESET Timing P58 DEC/29/2011 2. Modified ILO test conditions from VIN to VOUT P41 3. Changed ordering information format P63 4. Added HOLD# pin description P6,8 5. Modified Figure 39. Power-Down Sequence P61 6. Modified tRHSL spec from max. to min. P58 7. Modified Power-up Timing & table P59 1.3 1. Added Read SFDP (RDSFDP) Mode P6,13,15, FEB/10/2012 P38~43,48 P/N: PM1532 REV. 1.3, FEB. 10, 2012 73 MX25L25635E Except for customized products which has been expressly identified in the applicable agreement, Macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. 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For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 74