MX25L3233F
MX25L3233F
3V, 32M-BIT [x 1/x 2/x 4]
CMOS MXSMIO® (SERIAL MULTI I/O)
FLASH MEMORY
Key Features
• Hold Feature
• Multi I/O Support - Single I/O, Dual I/O and Quad I/O
• Auto Erase and Auto Program Algorithms
• Program Suspend/Resume & Erase Suspend/Resume
P/N: PM2113
1
Rev. 1.6, March 10, 2017
MX25L3233F
Contents
1. FEATURES......................................................................................................................................................... 5
2. GENERAL DESCRIPTION................................................................................................................................ 6
3. PIN CONFIGURATION....................................................................................................................................... 7
4. PIN DESCRIPTION............................................................................................................................................. 7
5. BLOCK DIAGRAM.............................................................................................................................................. 8
6. DATA PROTECTION........................................................................................................................................... 9
Table 1. Protected Area Sizes...............................................................................................................10
Table 2. 4K-bit Secured OTP Definition................................................................................................ 11
7. MEMORY ORGANIZATION.............................................................................................................................. 12
Table 3. Memory Organization..............................................................................................................12
8. DEVICE OPERATION....................................................................................................................................... 13
9. HOLD FEATURE............................................................................................................................................... 14
10. COMMAND DESCRIPTION............................................................................................................................ 16
Table 4. Command Sets........................................................................................................................16
10-1. Write Enable (WREN)...........................................................................................................................19
10-2. Write Disable (WRDI)............................................................................................................................20
10-3. Read Identification (RDID)....................................................................................................................21
10-4. Read Status Register (RDSR)..............................................................................................................22
10-5. Read Configuration Register (RDCR)...................................................................................................23
Table 5. Status Register........................................................................................................................24
Table 6. Configuration Register.............................................................................................................25
Table 7. Dummy Cycle and Frequency Table........................................................................................25
10-6. Write Status Register (WRSR)..............................................................................................................26
Table 8. Protection Modes.....................................................................................................................27
10-7. Read Data Bytes (READ).....................................................................................................................29
10-8. Read Data Bytes at Higher Speed (FAST_READ)...............................................................................30
10-9. Dual Read Mode (DREAD)...................................................................................................................31
10-10. 2 x I/O Read Mode (2READ)................................................................................................................32
10-11. Quad Read Mode (QREAD).................................................................................................................33
10-12. 4 x I/O Read Mode (4READ)................................................................................................................34
10-13. Performance Enhance Mode................................................................................................................36
10-14. Burst Read............................................................................................................................................37
10-15. Sector Erase (SE).................................................................................................................................38
10-16. Block Erase (BE)..................................................................................................................................39
10-17. Block Erase (BE32K)............................................................................................................................40
10-18. Chip Erase (CE)....................................................................................................................................41
10-19. Page Program (PP)..............................................................................................................................42
10-20. 4 x I/O Page Program (4PP).................................................................................................................43
10-21. Deep Power-down (DP)........................................................................................................................46
10-22. Release from Deep Power-down (RDP), Read Electronic Signature (RES)........................................47
10-23. Read Electronic Manufacturer ID & Device ID (REMS)........................................................................49
Table 9. ID Definitions ..........................................................................................................................50
10-24. Enter Secured OTP (ENSO).................................................................................................................50
10-25. Exit Secured OTP (EXSO)....................................................................................................................50
10-26. Read Security Register (RDSCUR)......................................................................................................51
Table 10. Security Register Definition...................................................................................................52
10-27. Write Security Register (WRSCUR)......................................................................................................53
P/N: PM2113
2
Rev. 1.6, March 10, 2017
MX25L3233F
10-28. Program Suspend and Erase Suspend................................................................................................54
Table 11. Readable Area of Memory While a Program or Erase Operation is Suspended...................54
Table 12. Acceptable Commands During Program/Erase Suspend after tPSL/tESL............................54
Table 13. Acceptable Commands During Suspend (tPSL/tESL not required).......................................55
10-29. Program Resume and Erase Resume..................................................................................................56
10-30. No Operation (NOP).............................................................................................................................57
10-31. Software Reset (Reset-Enable (RSTEN) and Reset (RST))................................................................57
10-32. Read SFDP Mode (RDSFDP)...............................................................................................................58
Table 14. Signature and Parameter Identification Data Values ............................................................59
Table 15. Parameter Table (0): JEDEC Flash Parameter Tables..........................................................60
Table 16. Parameter Table (1): Macronix Flash Parameter Tables.......................................................62
11. POWER-ON STATE........................................................................................................................................ 64
12. Electrical Specifications............................................................................................................................... 65
12-1. Absolute Maximum Ratings..................................................................................................................65
12-2. Capacitance TA = 25°C, f = 1.0 MHz....................................................................................................65
Table 17. DC Characteristics.................................................................................................................67
Table 18. AC Characteristics.................................................................................................................68
13. TIMING ANALYSIS......................................................................................................................................... 70
14. OPERATING CONDITIONS............................................................................................................................ 72
Table 19. Power-Up/Down Voltage and Timing.....................................................................................74
14-1. Initial Delivery State..............................................................................................................................74
15. ERASE AND PROGRAMMING PERFORMANCE......................................................................................... 75
16. DATA RETENTION......................................................................................................................................... 75
17. LATCH-UP CHARACTERISTICS................................................................................................................... 75
18. ORDERING INFORMATION........................................................................................................................... 76
19. PART NAME DESCRIPTION.......................................................................................................................... 77
20. PACKAGE INFORMATION............................................................................................................................. 78
20-1. 8-pin SOP (150mil)...............................................................................................................................78
20-2. 8-pin SOP (200mil)...............................................................................................................................79
20-3. 8-land USON (4x3mm).........................................................................................................................80
20-4. 16-pin SOP (300mil).............................................................................................................................81
20-5. 8-WSON (6x5mm)................................................................................................................................82
21. REVISION HISTORY ...................................................................................................................................... 83
P/N: PM2113
3
Rev. 1.6, March 10, 2017
MX25L3233F
Figures
Figure 1. Serial Modes Supported (for Normal Serial mode)........................................................................................................13
Figure 2. Hold Condition Operation .............................................................................................................................................14
Figure 3. Write Enable (WREN) Sequence (Command 06h).......................................................................................................19
Figure 4. Write Disable (WRDI) Sequence (Command 04h).......................................................................................................20
Figure 5. Read Identification (RDID) Sequence (Command 9Fh)...............................................................................................21
Figure 6. Read Status Register (RDSR) Sequence (Command 05h)..........................................................................................22
Figure 7. Read Configuration Register (RDCR) Sequence..........................................................................................................23
Figure 8. Write Status Register (WRSR) Sequence (Command 01h).........................................................................................26
Figure 9. WRSR flow....................................................................................................................................................................28
Figure 10. Read Data Bytes (READ) Sequence (Command 03h)...............................................................................................29
Figure 11. Read at Higher Speed (FAST_READ) Sequence (Command 0Bh)...........................................................................30
Figure 12. Dual Read Mode Sequence (Command 3Bh).............................................................................................................31
Figure 13. 2 x I/O Read Mode Sequence (Command BBh).........................................................................................................32
Figure 14. Quad Read Mode Sequence (Command 6Bh)............................................................................................................33
Figure 15. 4 x I/O Read Mode Sequence (Command EBh).........................................................................................................34
Figure 16. 4 x I/O Read enhance performance Mode Sequence (Command EBh) (SPI Mode)..................................................36
Figure 17. Burst Read...................................................................................................................................................................37
Figure 18. Sector Erase (SE) Sequence (Command 20h)..........................................................................................................38
Figure 19. Block Erase (BE) Sequence (Command D8h)...........................................................................................................39
Figure 20. Block Erase 32KB (BE32K) Sequence (Command 52h)...........................................................................................40
Figure 21. Chip Erase (CE) Sequence (Command 60h or C7h).................................................................................................41
Figure 22. Page Program (PP) Sequence (Command 02h)........................................................................................................42
Figure 23. 4 x I/O Page Program (4PP) Sequence (Command 38h)..........................................................................................43
Figure 24. Program/Erase Flow(1) with read array data...............................................................................................................44
Figure 25. Program/Erase Flow(2) without read array data..........................................................................................................45
Figure 26. Deep Power-down (DP) Sequence (Command B9h).................................................................................................46
Figure 27. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command ABh).......................47
Figure 28. Release from Deep Power-down (RDP) Sequence....................................................................................................48
Figure 29. Read Electronic Manufacturer & Device ID (REMS) Sequence..................................................................................49
Figure 30. Read Security Register (RDSCUR) Sequence (Command 2Bh)................................................................................51
Figure 31. Write Security Register (WRSCUR) Sequence (Command 2Fh) (SPI mode).............................................................53
Figure 32. Suspend to Read Latency...........................................................................................................................................55
Figure 33. Resume to Suspend Latency......................................................................................................................................55
Figure 34. Suspend to Program Latency......................................................................................................................................56
Figure 35. Resume to Read Latency............................................................................................................................................56
Figure 36. Software Reset Recovery............................................................................................................................................57
Figure 37. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence.............................................................................58
Figure 38. Maximum Negative Overshoot Waveform...................................................................................................................65
Figure 39. Maximum Positive Overshoot Waveform.....................................................................................................................65
Figure 40. Input Test Waveforms and Measurement Level..........................................................................................................66
Figure 41. Output Loading............................................................................................................................................................66
Figure 42. SCLK TIMING DEFINITION........................................................................................................................................66
Figure 43. Serial Input Timing.......................................................................................................................................................70
Figure 44. Output Timing..............................................................................................................................................................70
Figure 45. Hold Timing..................................................................................................................................................................71
Figure 46. WP# Setup Timing and Hold Timing during WRSR when SRWD=1...........................................................................71
Figure 47. AC Timing at Device Power-Up...................................................................................................................................72
Figure 48. Power-Down Sequence...............................................................................................................................................73
Figure 49. Power-up Timing..........................................................................................................................................................73
Figure 50. Power Up/Down and Voltage Drop..............................................................................................................................74
P/N: PM2113
4
Rev. 1.6, March 10, 2017
MX25L3233F
32M-BIT [x 1 / x 2 / x 4] CMOS MXSMIO® (SERIAL MULTI I/O)
FLASH MEMORY
1. FEATURES
- 1-byte Command code
• Advanced Security Features
- Block Lock Protection
The BP0-BP3 and T/B status bits define the site of the
area to be protected against program and erase instructions.
• Additional 4K bits secured OTP
- Features unique identifier
- Factory locked identifiable and customer lockable
• Auto Erase and Auto Program Algorithms
- Automatically erases and verifies data at selected
sector
- Automatically programs and verifies data at selected page by an internal algorithm that automatically
times the program pulse width (Any page to be programmed should have page in the erased state first.)
• Status Register Feature
• Command Reset
• Program/Erase Suspend
• Program/Erase Resume
• Electronic Identification
GENERAL
• Supports Serial Peripheral Interface -- Mode 0 and
Mode 3
• 33,554,432 x 1 bit structure
or 16,777,216 x 2 bits (two I/O read mode) structure
or 8,388,608 x 4 bits (four I/O mode) structure
• 1024 Equal Sectors with 4K bytes each
- Any Sector can be erased individually
• 128 Equal Blocks with 32K bytes each
- Any Block can be erased individually
• 64 Equal Blocks with 64K bytes each
- Any Block can be erased individually
• Power Supply Operation
- 2.65 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
VCC = 2.65 to 3.6V
- Normal read
- 50MHz
- Fast read
- FAST_READ, DREAD, QREAD:
133MHz with 8 dummy cycles
- 2READ:
104MHz with 4 dummy cycle,
133MHz with 8 dummy cycle
- 4READ:
104MHz with 6 dummy cycle,
133MHz with 10 dummy cycle
- Configurable dummy cycle number for 2READ
and 4READ operation
- 8/16/32/64 byte Wrap-Around Burst Read Mode
• Low Power Consumption
• Typical 100,000 erase/program cycles
• 20 years data retention
- JEDEC 1-byte Manufacturer ID and 2-byte Device
ID
- RES command for 1-byte Device ID
• Support Serial Flash Discoverable Parameters (SFDP)
mode
- All devices are RoHS Compliant and Halogenfree
KEY FEATURES
• Input Data Format
P/N: PM2113
5
Rev. 1.6, March 10, 2017
MX25L3233F
2. GENERAL DESCRIPTION
MX25L3233F is 32Mb bits Serial NOR Flash memory, which is configured as 4,194,304 x 8 internally. When it is
in four I/O mode, the structure becomes 8,388,608 bits x 4. When it is in two I/O mode, the structure becomes
16,777,216 bits x 2.
MX25L3233F features a serial peripheral interface and software protocol allowing operation on a simple 3-wire
bus while it is in single I/O mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a
serial data output (SO). Serial access to the device is enabled by CS# input.
MX25L3233F, MXSMIO® (Serial Multi I/O) flash memory, provides sequential read operation on the whole chip
and multi-I/O features.
When it is in quad I/O mode, the SI pin, SO pin, WP# pin and HOLD# pin become SIO0 pin, SIO1 pin, SIO2 pin
and SIO3 pin for address/dummy bits input and data Input/Output.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the
specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis. Erase command is executed on 4K-byte sector, 32K-byte/64K-byte block, or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status
read command can be issued to detect completion status of a program or erase operation via WIP bit.
When the device is not in operation and CS# is high, it is put in standby mode.
The MX25L3233F utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after
100,000 program and erase cycles.
P/N: PM2113
6
Rev. 1.6, March 10, 2017
MX25L3233F
3. PIN CONFIGURATION
4. PIN DESCRIPTION
SYMBOL
DESCRIPTION
CS#
Chip Select
Serial Data Input (for 1xI/O)/ Serial Data
SI/SIO0 Input & Output (for 2xI/O mode and 4xI/
O mode)
Serial Data Output (for 1xI/O)/Serial
SO/SIO1 Data Input & Output (for 2xI/O mode
and 4xI/O mode)
SCLK
Clock Input
Write protection Active Low or Serial
WP#/SIO2
Data Input & Output (for 4xI/O mode)
To pause the device without deselecting
HOLD#/
the device or Serial data Input/Output
SIO3
for 4 x I/O mode
VCC
+ 3.0V Power Supply
GND
Ground
NC
No Connection
8-PIN SOP (150mil)/8-PIN SOP (200mil)
CS#
SO/SIO1
WP#/SIO2
GND
1
2
3
4
8
7
6
5
VCC
HOLD#/SIO3
SCLK
SI/SIO0
8-LAND USON (4x3mm)
1
2
3
4
CS#
SO/SIO1
WP#/SIO2
GND
8
7
6
5
VCC
HOLD#/SIO3
SCLK
SI/SIO0
Note:
1. The pin of HOLD#/SIO3 or WP#/SIO2 will remain
internal pull up function while this pin is not
physically connected in system configuration.
However, the internal pull up function will be
disabled if the system has physical connection to
HOLD#/SIO3 or WP#/SIO2 pin.
8-WSON (6x5mm)
CS#
SO/SIO1
WP#/SIO2
GND
1
2
3
4
VCC
HOLD#/SIO3
SCLK
SI/SIO0
8
7
6
5
16-PIN SOP (300mil)
HOLD#/SIO3
VCC
NC
NC
NC
NC
CS#
SO/SIO1
P/N: PM2113
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SCLK
SI/SIO0
NC
NC
NC
NC
GND
WP#/SIO2
7
Rev. 1.6, March 10, 2017
MX25L3233F
5. BLOCK DIAGRAM
X-Decoder
Address
Generator
SI/SIO0
SO/SIO1
SIO2 *
SIO3 *
WP# *
HOLD# *
RESET# *
CS#
SCLK
Memory Array
Y-Decoder
Data
Register
Sense
Amplifier
SRAM
Buffer
Mode
Logic
State
Machine
HV
Generator
Clock Generator
Output
Buffer
* Depends on part number options.
P/N: PM2113
8
Rev. 1.6, March 10, 2017
MX25L3233F
6. DATA PROTECTION
During power transition, there may be some false system level signals which result in inadvertent erasure or programming. The device is designed to protect itself from these accidental write cycles.
The state machine will be reset as standby mode automatically during power up. In addition, the control register
architecture of the device constrains that the memory contents can only be changed after specific command sequences have completed successfully.
In the following, there are several features to protect the system from the accidental write cycles during VCC
power-up and power-down or from system noise.
• Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
other command to change data.
• Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from
writing all commands except Release from Deep Power Down mode command (RDP) and Read Electronic
Signature command (RES).
I. Block lock protection
- The Software Protected Mode (SPM) uses (TB, BP3, BP2, BP1, BP0) bits to allow part of memory to be
protected as read only. The protected area definition is shown as table of "Table 1. Protected Area Sizes", the
protected areas are more flexible which may protect various areas by setting value of TB, BP0-BP3 bits.
- The Hardware Protected Mode (HPM) uses WP#/SIO2 to protect the (BP3, BP2, BP1, BP0, TB) bits and
SRWD bit.
P/N: PM2113
9
Rev. 1.6, March 10, 2017
MX25L3233F
Table 1. Protected Area Sizes
Protected Area Sizes (TB bit = 0)
Status bit
BP3
BP2
BP1
BP0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Protected Area Sizes (TB bit = 1)
Status bit
BP3
BP2
BP1
BP0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Protect Level
32Mb
0 (none)
1 (1block, block 63rd)
2 (2blocks, block 62nd-63rd)
3 (4blocks, block 60th-63rd)
4 (8blocks, block 56th-63rd)
5 (16blocks, block 48th-63rd)
6 (32blocks, block 32nd-63rd)
7 (64blocks, protect all)
8 (64blocks, protect all)
9 (64blocks, protect all)
10 (64blocks, protect all)
11 (64blocks, protect all)
12 (64blocks, protect all)
13 (64blocks, protect all)
14 (64blocks, protect all)
15 (64blocks, protect all)
Protect Level
32Mb
0 (none)
1 (1block, block 0th)
2 (2blocks, block 0th-1st)
3 (4blocks, block 0th-3rd)
4 (8blocks, block 0th-7th)
5 (16blocks, block 0th-15th)
6 (32blocks, block 0th-31st)
7 (64blocks, protect all)
8 (64blocks, protect all)
9 (64blocks, protect all)
10 (64blocks, protect all)
11 (64blocks, protect all)
12 (64blocks, protect all)
13 (64blocks, protect all)
14 (64blocks, protect all)
15 (64blocks, protect all)
Note: The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP3, BP2, BP1,
BP0) are 0.
P/N: PM2113
10
Rev. 1.6, March 10, 2017
MX25L3233F
II. Additional 4K-bit secured OTP for unique identifier: to provide 4K-bit One-Time Program area for setting
device unique serial number - Which may be set by factory or system maker.
- Security register bit 0 indicates whether the chip is locked by factory or not.
- To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with ENSO command), and
going through normal program procedure, and then exiting 4K-bit secured OTP mode by writing EXSO command.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register)
command to set customer lock-down bit1 as "1". Please refer to "Table 10. Security Register Definition" for
security register bit definition and "Table 2. 4K-bit Secured OTP Definition" for address range definition.
Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit Secured
OTP mode, array access is not allowed.
Table 2. 4K-bit Secured OTP Definition
P/N: PM2113
Address range
Size
Standard Factory Lock
Customer Lock
xxx000~xxx1FF
4096-bit
Determined by Factory
Determined by customer
11
Rev. 1.6, March 10, 2017
MX25L3233F
7. MEMORY ORGANIZATION
Table 3. Memory Organization
Block(64K-byte) Block(32K-byte)
Sector (4K-byte)
61
122
5
2
4
3
1
2
1
0
0
…
3F0FFFh
3EF000h
3EFFFFh
…
3F0000h
1007
3E8000h
3E8FFFh
999
3E7000h
3E7FFFh
…
1000
3E0000h
3E0FFFh
991
3DF000h
3DFFFFh
…
992
984
3D8000h
3D8FFFh
983
3D7000h
3D7FFFh
976
3D0000h
3D0FFFh
47
02F000h
02FFFFh
…
123
1008
…
124
3F7FFFh
40
028000h
028FFFh
39
027000h
027FFFh
…
62
3F8FFFh
3F7000h
32
020000h
020FFFh
31
01F000h
01FFFFh
…
125
3F8000h
1015
24
018000h
018FFFh
23
017000h
017FFFh
16
010000h
010FFFh
15
00F000h
00FFFFh
…
126
1016
…
63
8
008000h
008FFFh
7
007000h
007FFFh
000000h
000FFFh
0
P/N: PM2113
3FFFFFh
…
127
Address Range
3FF000h
…
1023
12
Rev. 1.6, March 10, 2017
MX25L3233F
8. DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation.
2. When incorrect command is inputted to this device, it enters standby mode and remains in standby mode until next CS# falling edge. In standby mode, SO pin of the device is High-Z.
3. When correct command is inputted to this device, it enters active mode and remains in active mode until next
CS# rising edge.
4. For standard single data rate serial mode, input data is latched on the rising edge of Serial Clock(SCLK) and
data is shifted out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as "Figure 1.
Serial Modes Supported (for Normal Serial mode)".
5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, RDSFDP, 4READ, QREAD,
2READ, DREAD, RDCR, RES, and REMS the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN,
WRDI, WRSR, SE, BE, BE32K, CE, PP, 4PP, Suspend, Resume, NOP, RSTEN, RST, ENSO, EXSO, WRSCUR, the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not
executed.
6. While a Write Status Register, Program, or Erase operation is in progress, access to the memory array is neglected and will not affect the current operation of Write Status Register, Program, Erase.
Figure 1. Serial Modes Supported (for Normal Serial mode)
CPOL
CPHA
shift in
(Serial mode 0)
0
0
SCLK
(Serial mode 3)
1
1
SCLK
SI
shift out
MSB
SO
MSB
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while
not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial
mode is supported.
P/N: PM2113
13
Rev. 1.6, March 10, 2017
MX25L3233F
9. HOLD FEATURE
HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop
the operation of write status register, programming, or erasing in progress.
The operation of HOLD requires Chip Select (CS#) keeping low and starts on falling edge of HOLD# pin signal
while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not
start until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while
Serial Clock(SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not end until
Serial Clock being low).
≈
SI/SIO0
≈ ≈
SO/SIO1
(internal)
SO/SIO1
(External)
Don’t care
Valid Data
Valid Data
High_Z
P/N: PM2113
Bit 6
Bit 5
Bit 6
≈
≈ ≈
SO/SIO1
(internal)
SO/SIO1
(External)
High_Z
Bit 7
Bit 5
≈
≈
SI/SIO0
≈
HOLD#
≈ ≈
SCLK
Valid Data
Bit 6
Bit 7
CS#
Don’t care
Bit 7
≈
HOLD#
≈ ≈
SCLK
≈
CS#
≈
Figure 2. Hold Condition Operation
Don’t care
Valid Data
Bit 7
Bit 7
Valid Data
Bit 6
High_Z
Bit 5
Bit 6
14
Don’t care
Bit 5
Valid Data
Bit 4
High_Z
Bit 3
Bit 4
Bit 3
Rev. 1.6, March 10, 2017
MX25L3233F
During the HOLD operation, the Serial Data Output (SO) is high impedance when Hold# pin goes low and will
keep high impedance until Hold# pin goes high. The Serial Data Input (SI) is don't care if both Serial Clock (SCLK)
and Hold# pin goes low and will keep the state until SCLK goes low and Hold# pin goes high. If Chip Select (CS#)
drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with
chip, the HOLD# must be at high and CS# must be at low.
Note: The HOLD feature is disabled during Quad I/O mode.
P/N: PM2113
15
Rev. 1.6, March 10, 2017
MX25L3233F
10. COMMAND DESCRIPTION
Table 4. Command Sets
Read Commands
I/O
1
1
2
2
4
4
Command
READ
(normal read)
03 (hex)
FAST READ
(fast read
data)
0B (hex)
2READ
(2 x I/O read
command)
BB (hex)
DREAD
(1I / 2O read
command)
3B (hex)
4READ
(4 x I/O read
command)
EB (hex)
QREAD
(1I/4O read
command)
6B (hex)
1st byte
2nd byte
A[23:16]
A[23:16]
A[23:16]
A[23:16]
A[23:16]
A[23:16]
3rd byte
A[15:8]
A[15:8]
A[15:8]
A[15:8]
A[15:8]
A[15:8]
4th byte
A[7:0]
A[7:0]
A[7:0]
A[7:0]
A[7:0]
A[7:0]
5th byte
Action
n bytes read
out until CS#
goes high
Dummy(8)
Dummy*
Dummy(8)
Dummy*
n bytes read n bytes read n bytes read
Quad I/O
read with
out until CS# out by 2 x I/O out by Dual
goes high until CS# goes Output until
configurable
high
CS# goes high dummy cycles
Dummy(8)
Note: *Dummy cycle number will be different, depending on the bit6 (DC) setting of Configuration Register.
Please refer to "Table 6. Configuration Register".
P/N: PM2113
16
Rev. 1.6, March 10, 2017
MX25L3233F
Other Commands
Command
1st byte
2nd byte
3rd byte
4th byte
Action
Command
1st byte
2nd byte
3rd byte
4th byte
Action
Command
1st byte
2nd byte
3rd byte
4th byte
Action
P/N: PM2113
WRSR
(write status/
4PP (quad
SE
configuration page program) (sector erase)
register)
06 (hex)
04 (hex)
05 (hex)
15 (hex)
01 (hex)
38 (hex)
20 (hex)
Values
A[23:16]
A[23:16]
Values
A[15:8]
A[15:8]
A[7:0]
A[7:0]
sets the (WEL) resets the to read out the to read out the to write new quad input to to erase the
selected
write enable
(WEL) write values of the values of the values of the program the
sector
latch bit
enable latch status register configuration configuration/ selected page
bit
register
status register
RDCR (read
WREN
WRDI
RDSR (read
configuration
(write enable) (write disable) status register)
register)
BE 32K
(block erase
32KB)
BE
(block erase
64KB)
CE
(chip erase)
PP
(page
program)
RDP (Release
DP (Deep
from deep
power down)
power down)
52 (hex)
D8 (hex)
60 or C7 (hex)
02 (hex)
B9 (hex)
A[23:16]
A[23:16]
A[23:16]
A[15:8]
A[15:8]
A[15:8]
A[7:0]
A[7:0]
A[7:0]
to erase the
to erase the to erase whole to program the enters deep
chip
selected page power down
selected 32KB selected 64KB
block
mode
block
PGM/ERS
Resume
(Resumes
Program/
Erase)
7A/30 (hex)
RDID
RES (read
(read identificelectronic ID)
ation)
9F (hex)
to continue
outputs
performing the
JEDEC
suspended
ID: 1-byte
program/erase Manufacturer
sequence
ID & 2-byte
Device ID
AB (hex)
PGM/ERS
Suspend
(Suspends
Program/
Erase)
75/B0 (hex)
release from program/erase
deep power
operation is
down mode
interrupted
by suspend
command
REMS (read
electronic
ENSO (enter
manufacturer secured OTP)
& device ID)
AB (hex)
90 (hex)
B1 (hex)
x
x
x
x
x
ADD
output the
to enter the
to read out
1-byte Device Manufacturer 4K-bit secured
ID
ID & Device ID OTP mode
17
Rev. 1.6, March 10, 2017
MX25L3233F
Command
(byte)
1st byte
2nd byte
3rd byte
4th byte
5th byte
Action
Command
(byte)
1st byte
2nd byte
3rd byte
4th byte
5th byte
RDSCUR
WRSCUR
EXSO (exit
RSTEN
(read security (write security
secured OTP)
(Reset Enable)
register)
register)
C1 (hex)
2B (hex)
2F (hex)
66 (hex)
to exit the
to read value to set the lock4K-bit secured of security
down bit as
register
"1" (once lockOTP mode
down, cannot
be update)
RST
(Reset
Memory)
99 (hex)
(Note 2)
RDSFDP
5A (hex)
A[23:16]
A[15:8]
A[7:0]
Dummy(8)
n bytes read
out until CS#
goes high
SBL (Set Burst
Length)
C0/77 (hex)
Value
to set Burst
length
NOP
(No
Operation)
00 (hex)
Action
Note 1: It is not recommended to adopt any other code not in the command definition table, which will potentially enter
the hidden mode.
Note 2: The RSTEN command must be executed before executing the RST command. If any other command is issued
in-between RSTEN and RST, the RST command will be ignored.
P/N: PM2113
18
Rev. 1.6, March 10, 2017
MX25L3233F
10-1.
Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP,
4PP, SE, BE, BE32K, CE, and WRSR which are intended to change the device content, should be set every time
after the WREN instruction setting the WEL bit.
The sequence of issuing WREN instruction is: CS# goes low→ sending WREN instruction code→ CS# goes
high.
The SIO[3:1] are don't care.
Figure 3. Write Enable (WREN) Sequence (Command 06h)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
06h
High-Z
SO
P/N: PM2113
19
Rev. 1.6, March 10, 2017
MX25L3233F
10-2.
Write Disable (WRDI)
The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.
The sequence of issuing WRDI instruction is: CS# goes low→ sending WRDI instruction code→ CS# goes high.
The WEL bit is reset by following situations:
- Power-up
- WRDI command completion
- WRSR command completion
- PP command completion
- 4PP command completion
- SE command completion
- BE32K command completion
- BE command completion
- CE command completion
- PGM/ERS Suspend command completion
- Softreset command completion
- WRSCUR command completion
Figure 4. Write Disable (WRDI) Sequence (Command 04h)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
04h
High-Z
SO
P/N: PM2113
20
Rev. 1.6, March 10, 2017
MX25L3233F
10-3.
Read Identification (RDID)
The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Macronix Manufacturer ID and Device ID are listed as table of "Table 9. ID Definitions".
The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code → 24-bits ID data
out on SO→ to end RDID operation can use CS# to high at any time during data out.
While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the
cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby
stage.
Figure 5. Read Identification (RDID) Sequence (Command 9Fh)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
28 29 30 31
SCLK
Command
SI
9Fh
Manufacturer Identification
SO
High-Z
7
6
5
MSB
P/N: PM2113
3
2
1
Device Identification
0 15 14 13
3
2
1
0
MSB
21
Rev. 1.6, March 10, 2017
MX25L3233F
10-4.
Read Status Register (RDSR)
The RDSR instruction is for reading Status Register. The Read Status Register can be read at any time (even
in program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in
progress.
The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register
data out on SO.
The SIO[3:1] are don't care.
Figure 6. Read Status Register (RDSR) Sequence (Command 05h)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
command
05h
SI
SO
High-Z
Status Register Out
7
6
5
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
P/N: PM2113
4
Status Register Out
22
Rev. 1.6, March 10, 2017
MX25L3233F
10-5.
Read Configuration Register (RDCR)
The RDCR instruction is for reading Configuration Register Bits. The Read Configuration Register can be read
at any time (even in program/erase/write configuration register condition). It is recommended to check the Write
in Progress (WIP) bit before sending a new instruction when a program, erase, or write configuration register
operation is in progress.
The sequence of issuing RDCR instruction is: CS# goes low→ sending RDCR instruction code→ Configuration
Register data out on SO.
The SIO[3:1] are don't care.
Figure 7. Read Configuration Register (RDCR) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
Mode 0
command
15h
SI
SO
High-Z
Configuration register Out
7
6
5
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
P/N: PM2113
4
Configuration register Out
23
Rev. 1.6, March 10, 2017
MX25L3233F
Status Register
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/
write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write
status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/
write status register cycle.
WEL bit. The Write Enable Latch (WEL) bit is a volatile bit that is set to “1” by the WREN instruction. WEL needs
to be set to “1” before the device can accept program and erase instructions, otherwise the program and erase
instructions are ignored. WEL automatically clears to “0” when a program or erase operation completes. To ensure that both WIP and WEL are “0” and the device is ready for the next program or erase operation, it is recommended that WIP be confirmed to be “0” before checking that WEL is also “0”. If a program or erase instruction is
applied to a protected memory area, the instruction will be ignored and WEL will clear to “0”.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area (as defined in "Table 1. Protected Area Sizes") of the device to against the program/erase instruction
without hardware protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the
Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to
against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip Erase (CE) instructions (only if all
Block Protect bits set to 0, the CE instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as default.
Which is un-protected.
QE bit. The Quad Enable (QE) bit is a non-volatile bit with a factory default of “0”. When QE is “0”, Quad mode
commands are ignored; pins WP#/SIO2 and HOLD#/SIO3 function as WP# and HOLD#, respectively. When QE is “1”,
Quad mode is enabled and Quad mode commands are supported along with Single and Dual mode commands.
Pins WP#/SIO2 and HOLD#/SIO3 function as SIO2 and SIO3, respectively, and their alternate pin functions are
disabled. Enabling Quad mode also disables the HPM and HOLD features.
SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, default value is "0". SRWD bit is operated together with Write Protection (WP#/SIO2) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP#/SIO2 pin signal is low stage. In the hardware protection mode,
the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block
Protect bits (BP3, BP2, BP1, BP0) are read only. The SRWD bit defaults to be "0".
Table 5. Status Register
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SRWD
BP3
BP2
BP1
BP0
QE
WEL
WIP
(status
(level of
(level of
(level of
(level of
(Quad
(write enable
(write in
register write
protected
protected
protected
protected
Enable)
latch)
progress bit)
protect)
block)
block)
block)
block)
1=status
register write 1= Quad
1=write
1=write
disabled
Enable
enable
operation
(note 1)
(note 1)
(note 1)
(note 1)
0=status
0=not Quad
0=not write 0=not in write
register write
Enable
enable
operation
enabled
Non-volatile Non-volatile Non-volatile Non-volatile Non-volatile Non-volatile
volatile bit
volatile bit
bit
bit
bit
bit
bit
bit
Note 1: Please refer to the "Table 1. Protected Area Sizes".
P/N: PM2113
24
Rev. 1.6, March 10, 2017
MX25L3233F
Configuration Register
The Configuration Register is able to change the default status of Flash memory. Flash memory will be configured
after the CR bit is set.
ODS bit
The output driver strength ODS bit are volatile bits, which indicate the output driver level of the device. The
Output Driver Strength is defaulted=1 when delivered from factory. To write the ODS bit requires the Write Status
Register (WRSR) instruction to be executed.
TB bit
The Top/Bottom (TB) bit is a OTP bit. The Top/Bottom (TB) bit is used to configure the Block Protect area by BP
bit (BP3, BP2, BP1, BP0), starting from TOP or Bottom of the memory array. The TB bit is defaulted as “0”, which
means Top area protect. When it is set as “1”, the protect area will change to Bottom area of the memory device.
To write the TB bit requires the Write Status Register (WRSR) instruction to be executed.
Table 6. Configuration Register
bit7
bit6
bit5
DC
Reserved
(Dummy
Reserved
Cycle)
bit4
Reserved
x
2READ/
4READ
Dummy
Cycle
x
x
x
volatile
x
x
bit3
TB
(top/bottom
selected)
0=Top area
protect
1=Bottom
area protect
(Default=0)
OTP
bit2
bit1
bit0
Reserved
Reserved
ODS
x
x
0, Output driver
strength=1
1, Output driver
strength=1/4
(Default=0)
x
x
volatile
Note: Refer to "Table 7. Dummy Cycle and Frequency Table", with "Don't Care" on other Reserved Configuration
Registers.
Table 7. Dummy Cycle and Frequency Table
2READ
4READ
P/N: PM2113
DC
Numbers of Dummy
Cycles
Freq. (MHz)
0 (default)
4
104
1
8
133
0 (default)
6
104
1
10
133
25
Rev. 1.6, March 10, 2017
MX25L3233F
10-6.
Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits and Configuration Register Bits. Before sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the
Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3,
BP2, BP1, BP0) bits to define the protected area of memory (as shown in "Table 1. Protected Area Sizes"). The
WRSR also can set or reset the Quad enable (QE) bit and set or reset the Status Register Write Disable (SRWD)
bit in accordance with Write Protection (WP#/SIO2) pin signal, but has no effect on bit1(WEL) and bit0 (WIP) of
the status register. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered.
The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register data on SI→ CS# goes high.
Figure 8. Write Status Register (WRSR) Sequence (Command 01h)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Mode 0
SI
SO
P/N: PM2113
command
01h
High-Z
Status
Register In
7
6
5
4
3
2
Configuration
Register In
1
0 15 14 13 12 11 10 9
8
MSB
26
Rev. 1.6, March 10, 2017
MX25L3233F
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The
Write in Progress (WIP) bit still can be checked out during the Write Status Register cycle is in progress. The
WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset.
Table 8. Protection Modes
Mode
Software protection
mode (SPM)
Hardware protection
mode (HPM)
Status register condition
Status register can be written
in (WEL bit is set to "1") and
the SRWD, BP0-BP3
bits can be changed
WP# and SRWD bit status
Memory
WP#=1 and SRWD bit=0, or
The protected area cannot
WP#=0 and SRWD bit=0, or
be programmed or erased.
WP#=1 and SRWD=1
The SRWD, BP0-BP3, TB of
status register bits cannot be
changed
WP#=0, SRWD bit=1
The protected area cannot
be programmed or erased.
Note: As defined by the values in the Block Protect (BP3, BP2, BP1, BP0, TB) bits of the Status Register, as
shown in "Table 1. Protected Area Sizes".
As the table above showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode
(HPM):
Software Protected Mode (SPM):
- When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can
change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1,
BP0, is at software protected mode (SPM).
- When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values
of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software
protected mode (SPM)
Hardware Protected Mode (HPM):
- When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware protected mode (HPM). The data of the protected area is protected by software protected mode by BP3,
BP2, BP1, BP0, TB and hardware protected mode by the WP#/SIO2 to against data modification.
Note:
To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is
entered. If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via BP3, BP2, BP1, BP0, TB.
If the system goes into four I/O mode, the feature of HPM will be disabled.
P/N: PM2113
27
Rev. 1.6, March 10, 2017
MX25L3233F
Figure 9. WRSR flow
start
WREN command
RDSR command
WEL=1?
No
Yes
WRSR command
Write status register data
RDSR command
WIP=0?
No
Yes
RDSR command
Read WEL=0, BP[3:0], QE,
and SRWD data
Verify OK?
No
Yes
WRSR successfully
P/N: PM2113
WRSR fail
28
Rev. 1.6, March 10, 2017
MX25L3233F
10-7.
Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out
on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole
memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached.
The sequence of issuing READ instruction is: CS# goes low→ sending READ instruction code→3-byte address
on SI →data out on SO→ to end READ operation can use CS# to high at any time during data out.
Figure 10. Read Data Bytes (READ) Sequence (Command 03h)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
SI
03
24 ADD Cycles
A23 A22 A21
A3 A2 A1 A0
MSB
SO
Data Out 1
High-Z
D7 D6 D5 D4 D3 D2 D1 D0 D7
MSB
P/N: PM2113
Data Out 2
29
MSB
Rev. 1.6, March 10, 2017
MX25L3233F
10-8.
Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and
data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be
at any location. The address is automatically increased to the next higher address after each byte data is shifted
out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to
0 when the highest address has been reached.
The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ instruction code→
3-byte address on SI→1-dummy byte (default) address on SI→ data out on SO→ to end FAST_READ operation can use CS# to high at any time during data out. (Please refer to "Figure 11. Read at Higher Speed (FAST_
READ) Sequence (Command 0Bh)")
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
Figure 11. Read at Higher Speed (FAST_READ) Sequence (Command 0Bh)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
SO
24 BIT ADDRESS
23 22 21
0Bh
3
2
1
0
High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Cycle
SI
7
6
5
4
3
2
1
0
DATA OUT 2
DATA OUT 1
SO
7
6
4
3
2
1
0
7
MSB
MSB
P/N: PM2113
5
30
6
5
4
3
2
1
0
7
MSB
Rev. 1.6, March 10, 2017
MX25L3233F
10-9.
Dual Read Mode (DREAD)
The DREAD instruction enable double throughput of Serial NOR Flash in read mode. The address is latched on
rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at
a maximum frequency fT. The first address byte can be at any location. The address is automatically increased
to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single
DREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruction, the following data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing DREAD instruction is: CS# goes low → sending DREAD instruction → 3-byte address
on SI → 8-bit dummy cycle → data out interleave on SO1 & SO0 → to end DREAD operation can use CS# to
high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle.
Figure 12. Dual Read Mode Sequence (Command 3Bh)
CS#
0
1
2
3
4
5
6
7
8
…
Command
SI/SIO0
SO/SIO1
P/N: PM2113
30 31 32
9
SCLK
3B
…
24 ADD Cycle
A23 A22
…
High Impedance
39 40 41 42 43 44 45
A1 A0
8 dummy
cycle
Data Out
1
Data Out
2
D6 D4 D2 D0 D6 D4
D7 D5 D3 D1 D7 D5
31
Rev. 1.6, March 10, 2017
MX25L3233F
10-10. 2 x I/O Read Mode (2READ)
The 2READ instruction enables Double Transfer Rate of Serial NOR Flash in read mode. The address is latched
on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK
at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased
to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single
2READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 24-bit address interleave on SIO1 & SIO0→ 4 dummy cycles(default) on SIO1 & SIO0→ data out interleave on SIO1 & SIO0→ to
end 2READ operation can use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
Figure 13. 2 x I/O Read Mode Sequence (Command BBh)
CS#
0
1
2
3
4
5
6
7
8
SCLK
…
Command
SI/SIO0
SO/SIO1
18 19 20 21 22 23 24 25 26 27 28 29
9
BB(hex)
High Impedance
12 ADD Cycle
Configurable
Dummy cycles
Data Out
1
Data Out
2
A22 A20
…
A2 A0 P2 P0
D6 D4 D2 D0 D6 D4
A23 A21
…
A3 A1 P3 P1
D7 D5 D3 D1 D7 D5
Note: SI/SIO0 or SO/SIO1 should be kept "0h" or "Fh" in the first two dummy cycles. In other words, P2=P0 or
P3=P1 is necessary.
P/N: PM2113
32
Rev. 1.6, March 10, 2017
MX25L3233F
10-11. Quad Read Mode (QREAD)
The QREAD instruction enable quad throughput of Serial NOR Flash in read mode. A Quad Enable (QE) bit of
status Register must be set to "1" before sending the QREAD instruction. The address is latched on rising edge
of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum
frequency fQ. The first address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single QREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing QREAD
instruction, the following data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing QREAD instruction is: CS# goes low→ sending QREAD instruction → 3-byte address
on SI → 8-bit dummy cycle → data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end QREAD operation can
use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle.
Figure 14. Quad Read Mode Sequence (Command 6Bh)
CS#
0
1
2
3
4
5
6
7
8
SCLK
…
Command
SI/SIO0
SO/SIO1
WP#/SIO2
HOLD#/SIO3
P/N: PM2113
29 30 31 32 33
9
6B
…
24 ADD Cycles
A23 A22
High Impedance
…
38 39 40 41 42
A2 A1 A0
8 dummy cycles
Data Data
Out 1 Out 2
Data
Out 3
D4 D0 D4 D0 D4
D5 D1 D5 D1 D5
High Impedance
D6 D2 D6 D2 D6
High Impedance
D7 D3 D7 D3 D7
33
Rev. 1.6, March 10, 2017
MX25L3233F
10-12. 4 x I/O Read Mode (4READ)
The 4READ instruction enables quad throughput of Serial NOR Flash in read mode. A Quad Enable (QE) bit of
status Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge
of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum
frequency fQ. The first address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 4READ
instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing 4READ instruction is: CS# goes low→ sending 4READ instruction→ 24-bit address interleave on SIO3, SIO2, SIO1 & SIO0→2+4 dummy cycles (default) →data out interleave on SIO3, SIO2, SIO1
& SIO0→ to end 4READ operation can use CS# to high at any time during data out. (Please refer to the figure
below)
Figure 15. 4 x I/O Read Mode Sequence (Command EBh)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
n
SCLK
8 Bit Instruction
6 Address cycles
Configurable
Dummy cycles
(Note 3)
Performance
Data Output
enhance indicator
(Note 1 & 2)
SI/SIO0
SO/SIO1
WP#/SIO2
HOLD#/SIO3
address
bit20, bit16..bit0
P4 P0
data
bit4, bit0, bit4....
High Impedance
address
bit21, bit17..bit1
P5 P1
data
bit5 bit1, bit5....
High Impedance
address
bit22, bit18..bit2
P6 P2
data
bit6 bit2, bit6....
High Impedance
address
bit23, bit19..bit3
P7 P3
data
bit7 bit3, bit7....
EBh
Notes:
1. Hi-impedance is inhibited for the two clock cycles.
2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited.
3. The Configurable Dummy Cycle is set by Configuration Register Bit. Please see "Dummy Cycle and Frequency Table"
P/N: PM2113
34
Rev. 1.6, March 10, 2017
MX25L3233F
Another sequence of issuing 4READ instruction especially useful in random access is: CS# goes low→send
4READ instruction→3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0→performance enhance toggling
bit P[7:0]→4 dummy cycles →data out until CS# goes high → CS# goes low (The following 4READ instruction is
not allowed, hence 8 cycles of 4READ can be saved comparing to normal 4READ mode) → 24-bit random access address (Please refer to "Figure 16. 4 x I/O Read enhance performance Mode Sequence (Command EBh) (SPI
Mode)" ).
In the performance-enhancing mode (Notes of "Figure 16. 4 x I/O Read enhance performance Mode Sequence
(Command EBh) (SPI Mode)"), P[7:4] must be toggling with P[3:0]; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh can
make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0];
likewise P[7:0]=FFh, 00h, AAh or 55h. These commands will reset the performance enhance mode. And afterwards CS# is raised and then lowered, the system then will return to normal operation.
While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle.
P/N: PM2113
35
Rev. 1.6, March 10, 2017
MX25L3233F
10-13. Performance Enhance Mode
The device could waive the command cycle bits if the two cycle bits after address cycle toggles. (Please note
"Figure 16. 4 x I/O Read enhance performance Mode Sequence (Command EBh) (SPI Mode)")
Performance enhance mode is supported for 4READ mode.
“EBh” commands support enhance mode.
After entering enhance mode, following CS# go high, the device will stay in the read mode and treat CS# go low
of the first clock as address instead of command cycle.
To exit enhance mode, a new fast read command whose first two dummy cycles is not toggle then exit. Or issue
”FFh” data cycles to exit enhance mode.
Figure 16. 4 x I/O Read enhance performance Mode Sequence (Command EBh) (SPI Mode)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
n
SCLK
8 Bit Instruction
WP#/SIO2
HOLD#/SIO3
Configurable
Dummy cycles
(Note 2)
Performance
enhance
indicator (Note1)
Data Output
address
bit20, bit16..bit0
P4 P0
data
bit4, bit0, bit4....
High Impedance
address
bit21, bit17..bit1
P5 P1
data
bit5 bit1, bit5....
High Impedance
address
bit22, bit18..bit2
P6 P2
data
bit6 bit2, bit6....
High Impedance
address
bit23, bit19..bit3
P7 P3
data
bit7 bit3, bit7....
EBh
SI/SIO0
SO/SIO1
6 Address cycles
CS#
n+1
...........
n+7 ...... n+9
........... n+13
...........
SCLK
6 Address cycles
Configurable
Dummy cycles
(Note 2)
Data Output
Performance
enhance
indicator (Note1)
SI/SIO0
address
bit20, bit16..bit0
P4 P0
data
bit4, bit0, bit4....
SO/SIO1
address
bit21, bit17..bit1
P5 P1
data
bit5 bit1, bit5....
WP#/SIO2
address
bit22, bit18..bit2
P6 P2
data
bit6 bit2, bit6....
HOLD#/SIO3
address
bit23, bit19..bit3
P7 P3
data
bit7 bit3, bit7....
Note:
1. Performance enhance mode, if P7≠P3 & P6≠P2 & P5≠P1 & P4≠P0 (Toggling), ex: A5, 5A, 0F, if not using
performance enhance recommend to keep 1 or 0 in performance enhance indicator.
Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF.
2. The Configurable Dummy Cycle is set by Configuration Register Bit. Please see "Dummy Cycle and
Frequency Table"
P/N: PM2113
36
Rev. 1.6, March 10, 2017
MX25L3233F
10-14. Burst Read
The Burst Read feature allows applications to fill a cache line with a fixed length of data without using multiple
read commands. Burst Read is disabled by default at power-up or reset. Burst Read is enabled by setting
the Burst Length. When the Burst Length is set, reads will wrap on the selected boundary (8/16/32/64-bytes)
containing the initial target address. For example if an 8-byte Wrap Depth is selected, reads will wrap on the
8-byte-page-aligned boundary containing the initial read address.
To set the Burst Length, drive CS# low → send SET BURST LENGTH instruction code → send WRAP CODE →
drive CS# high. Refer to the table below for valid 8-bit Wrap Codes and their corresponding Wrap Depth.
Data
00h
01h
02h
03h
1xh
Wrap Around
Yes
Yes
Yes
Yes
No
Wrap Depth
8-byte
16-byte
32-byte
64-byte
X
Once Burst Read is enabled, it will remain enabled until the device is power-cycled or reset. The 4READ read
command supports the wrap around feature after Burst Read is enabled. To change the wrap depth, resend the
Burst Read instruction with the appropriate Wrap Code. To disable Burst Read, send the Burst Read instruction
with Wrap Code 1xh. “EBh" supports wrap around feature after wrap around is enabled.
Figure 17. Burst Read
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9
D7
D6
10
11
12
13
14
15
SCLK
Mode 0
SIO
P/N: PM2113
77h
37
D5
D4
D3
D2
D1
D0
Rev. 1.6, March 10, 2017
MX25L3233F
10-15. Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used
for any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit
before sending the Sector Erase (SE). Any address of the sector (Please refer to "Table 3. Memory Organization" ) is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary
(the least significant bit of the address has been latched-in); otherwise, the instruction will be rejected and not
executed.
The sequence of issuing SE instruction is: CS# goes low → sending SE instruction code→ 3-byte address on SI
→CS# goes high.
The SIO[3:1] are don't care.
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets during the tSE
timing, and clears when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the
sector is protected by BP3~0, the array data will be protected (no change) and the WEL bit still be reset.
Figure 18. Sector Erase (SE) Sequence (Command 20h)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
24 Bit Address
Command
SI
23 22
20h
2
1
0
MSB
P/N: PM2113
38
Rev. 1.6, March 10, 2017
MX25L3233F
10-16. Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for
64K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable
Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (Please refer to "Table 3. Memory Organization") is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte
boundary (the least significant bit of address byte has been latched-in); otherwise, the instruction will be rejected
and not executed.
The sequence of issuing BE instruction is: CS# goes low → sending BE instruction code → 3-byte address on
SI → CS# goes high.
The SIO[3:1] are don't care.
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets during the tBE
timing, and clears when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the
block is protected by BP3~0, the array data will be protected (no change) and the WEL bit still be reset.
Figure 19. Block Erase (BE) Sequence (Command D8h)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
SI
24 Bit Address
23 22
D8h
2
1
0
MSB
P/N: PM2113
39
Rev. 1.6, March 10, 2017
MX25L3233F
10-17. Block Erase (BE32K)
The Block Erase (BE32K) instruction is for erasing the data of the chosen block to be "1". The instruction is used
for 32K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable
Latch (WEL) bit before sending the Block Erase (BE32K). Any address of the block (Please refer to "Table 3.
Memory Organization" ) is a valid address for Block Erase (BE32K) instruction. The CS# must go high exactly at
the byte boundary (the least significant bit of address byte has been latched-in); otherwise, the instruction will be
rejected and not executed.
The sequence of issuing BE32K instruction is: CS# goes low → sending BE32K instruction code → 3-byte address on SI → CS# goes high.
The SIO[3:1] are don't care.
The self-timed Block Erase Cycle time (tBE32K) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets during the
tBE32K timing, and clears 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is
cleared. If the block is protected by BP3~0, the array data will be protected (no change) and the WEL bit still be
reset.
Figure 20. Block Erase 32KB (BE32K) Sequence (Command 52h)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
SI
24 Bit Address
23 22
52h
2
1
0
MSB
P/N: PM2113
40
Rev. 1.6, March 10, 2017
MX25L3233F
10-18. Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The
CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The sequence of issuing CE instruction is: CS# goes low → sending CE instruction code → CS# goes high.
The SIO[3:1] are don't care.
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Chip Erase cycle is in progress. The WIP sets during the tCE
timing, and clears when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the
chip is protected the Chip Erase (CE) instruction will not be executed, but WEL will be reset.
Figure 21. Chip Erase (CE) Sequence (Command 60h or C7h)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
P/N: PM2113
60h or C7h
41
Rev. 1.6, March 10, 2017
MX25L3233F
10-19. Page Program (PP)
The Page Program (PP) instruction is for programming memory bits to "0". One to 256 bytes can be sent to the
device to be programmed. A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL)
bit before sending the Page Program (PP). If more than 256 data bytes are sent to the device, only the last 256
data bytes will be accepted and the previous data bytes will be disregarded. The Page Program instruction
requires that all the data bytes fall within the same 256-byte page. The low order address byte A[7:0] specifies
the starting address within the selected page. Bytes that will cross a page boundary will wrap to the beginning of
the selected page. The device can accept (256 minus A[7:0]) data bytes without wrapping. If 256 data bytes are
going to be programmed, A[7:0] should be set to 0.
The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on
SI→ at least 1-byte on data on SI→ CS# goes high.
The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte
boundary (the latest eighth bit of data being latched in), otherwise, the instruction will be rejected and will not be
executed.
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Page Program cycle is in progress. The WIP sets during the
tPP timing, and clears when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is cleared.
If the page is protected by BP3~0, the array data will be protected (no change) and the WEL bit will still be reset.
The SIO[3:1] are don't care.
Figure 22. Page Program (PP) Sequence (Command 02h)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
1
0
7
6
5
3
2
1
0
2079
2
2078
3
2077
23 22 21
02h
SI
Data Byte 1
2076
24-Bit Address
2075
Command
4
1
0
MSB
MSB
2074
2073
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
2072
CS#
SCLK
Data Byte 2
SI
7
6
MSB
P/N: PM2113
5
4
3
2
Data Byte 3
1
0
7
6
5
MSB
4
3
2
Data Byte 256
1
0
7
6
5
4
3
2
MSB
42
Rev. 1.6, March 10, 2017
MX25L3233F
10-20. 4 x I/O Page Program (4PP)
The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN)
instruction must be executed to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set
to "1" before sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0,
SIO1, SIO2, and SIO3, which can raise programmer performance and the effectiveness of application of lower
clock less than f4PP. For system with faster clock, the Quad page program cannot provide more performance,
because the required internal page program time is far more than the time data flows in. Therefore, we suggest
that while executing this command (especially during sending data), user can slow the clock speed down to f4PP
below. The other function descriptions are as same as standard page program.
The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on
SIO[3:0]→ at least 1-byte on data on SIO[3:0]→ CS# goes high.
If the page is protected by BP3~0, the array data will be protected (no change) and the WEL bit will still be reset.
Figure 23. 4 x I/O Page Program (4PP) Sequence (Command 38h)
CS#
0
1
2
3
4
5
6
7
8
SCLK
…
Command
SI/SIO0
SO/SIO1
WP#/SIO2
HOLD#/SIO3
P/N: PM2113
524 525
9 10 11 12 13 14 15 16 17
38
6 ADD cycles
Data
Byte 256
Data Data
Byte 1 Byte 2
A20 A16 A12 A8 A4 A0 D4 D0 D4 D0
…
D4 D0
A21 A17 A13 A9 A5 A1 D5 D1 D5 D1
…
D5 D1
A22 A18 A14 A10 A6 A2 D6 D2 D6 D2
…
D6 D2
A23 A19 A15 A11 A7 A3 D7 D3 D7 D3
…
D7 D3
43
Rev. 1.6, March 10, 2017
MX25L3233F
The Program/Erase function instruction function flow is as follows:
Figure 24. Program/Erase Flow(1) with read array data
Start
WREN command
RDSR command*
No
WEL=1?
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
No
WIP=0?
Yes
Read array data
(same address of PGM/ERS)
Verify OK?
No
Yes
Program/erase fail
Program/erase successfully
Program/erase
another block?
No
Yes
*
* Issue RDSR to check BP[3:0].
Program/erase completed
P/N: PM2113
44
Rev. 1.6, March 10, 2017
MX25L3233F
Figure 25. Program/Erase Flow(2) without read array data
Start
WREN command
RDSR command*
No
WEL=1?
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
No
WIP=0?
Yes
RDSCUR command
Yes
P_FAIL/E_FAIL=1?
No
Program/erase fail
Program/erase successfully
Program/erase
Yes
another block?
* Issue RDSR to check BP[3:0].
No
Program/erase completed
P/N: PM2113
45
Rev. 1.6, March 10, 2017
MX25L3233F
10-21. Deep Power-down (DP)
The Deep Power-down (DP) instruction places the device into a minimum power consumption state, Deep Power-down mode, in which the quiescent current is reduced from ISB1 to ISB2.
The sequence of issuing DP instruction: CS# goes low→ send DP instruction code→ CS# goes high. The CS#
must go high at the byte boundary (after exactly eighth bits of the instruction code have been latched-in); otherwise the instruction will not be executed. SIO[3:1] are "don't care".
After CS# goes high there is a delay of tDP before the device transitions from Stand-by mode to Deep Powerdown mode and before the current reduces from ISB1 to ISB2. Once in Deep Power-down mode, all instructions
will be ignored except Release from Deep Power-down (RDP).
The device exits Deep Power-down mode and returns to Stand-by mode if it receives a Release from Deep
Power-down (RDP) instruction, power-cycle, or reset. Please refer to "Figure 28. Release from Deep Powerdown (RDP) Sequence".
Figure 26. Deep Power-down (DP) Sequence (Command B9h)
CS#
0
1
2
3
4
5
6
7
tDP
SCLK
Command
SI
B9h
Stand-by Mode
P/N: PM2113
46
Deep Power-down Mode
Rev. 1.6, March 10, 2017
MX25L3233F
10-22. Release from Deep Power-down (RDP), Read Electronic Signature (RES)
The Release from Deep Power-down (RDP) instruction is completed by driving Chip Select (CS#) High. When
Chip Select (CS#) is driven High, the device is put in the standby Power mode. If the device was not previously in
the Deep Power-down mode, the transition to the standby Power mode is immediate. If the device was previously
in the Deep Power-down mode, though, the transition to the standby Power mode is delayed by tRES2, and Chip
Select (CS#) must remain High for at least tRES2(max), as specified in "Table 18. AC Characteristics". Once in
the standby mode, the device waits to be selected, so that it can receive, decode and execute instructions.
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as "Table 9.
ID Definitions". This is not the same as RDID instruction. It is not recommended to use for new design. For new
design, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to
be executed, only except the device is in progress of program/erase/write cycles; there's no effect on the current
program/erase/write cycles in progress.
The SIO[3:1] are don't care when during this mode.
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously
in Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high
at least tRES2(max). Once in the standby mode, the device waits to be selected, so it can receive, decode, and
execute instruction.
The RDP instruction is for releasing from Deep Power-down Mode.
Figure 27. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command
ABh)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38
SCLK
Command
SI
ABh
tRES2
3 Dummy Bytes
23 22 21
3
2
1
0
MSB
SO
Electronic Signature Out
High-Z
7
6
5
4
3
2
1
0
MSB
Deep Power-down Mode
P/N: PM2113
47
Stand-by Mode
Rev. 1.6, March 10, 2017
MX25L3233F
Figure 28. Release from Deep Power-down (RDP) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
tRES1
7
SCLK
Mode 0
Command
SI
SO
ABh
High-Z
Deep Power-down Mode
P/N: PM2113
48
Stand-by Mode
Rev. 1.6, March 10, 2017
MX25L3233F
10-23. Read Electronic Manufacturer ID & Device ID (REMS)
The REMS instruction returns both the JEDEC assigned manufacturer ID and the device ID. The Device ID values are listed in "Table 9. ID Definitions".
The REMS instruction is initiated by driving the CS# pin low and sending the instruction code "90h" followed by
two dummy bytes and one address byte (A7~A0). After which the manufacturer ID for Macronix (C2h) and the
device ID are shifted out on the falling edge of SCLK with the most significant bit (MSB) first. If the address byte
is 00h, the manufacturer ID will be output first, followed by the device ID. If the address byte is 01h, then the device ID will be output first, followed by the manufacturer ID. While CS# is low, the manufacturer and device IDs
can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high.
Figure 29. Read Electronic Manufacturer & Device ID (REMS) Sequence
CS#
SCLK
Mode 3
0
1
2
Mode 0
3
4
5
6
7
8
Command
SI
9 10
2 Dummy Bytes
15 14 13
90h
3
2
1
0
High-Z
SO
CS#
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
ADD (1)
SI
7
6
5
4
3
2
1
0
Manufacturer ID
SO
7
6
MSB
5
4
3
2
1
Device ID
0
7
MSB
6
5
4
3
2
1
0
7
MSB
Notes: (1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first.
P/N: PM2113
49
Rev. 1.6, March 10, 2017
MX25L3233F
Table 9. ID Definitions
Command Type
RDID
Manufacturer ID
C2
RES
REMS
Manufacturer ID
C2
MX25L3233F
Memory Type
20
Electronic ID
15
Device ID
15
Memory Density
16
10-24. Enter Secured OTP (ENSO)
The ENSO instruction is for entering the additional 4K-bit Secured OTP mode. While the device is in 4K-bit Secured OTP mode, array access is not available. The additional 4K-bit Secured OTP is independent from main array, and may be used to store unique serial number for system identifier. After entering the Secured OTP mode,
follow standard read or program procedure to read out the data or update data. The Secured OTP data cannot
be updated again once it is lock-down.
The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP
mode→ CS# goes high.
The SIO[3:1] are don't care.
Please note that WRSR/WRSCUR/CE/BE/SE/BE32K commands are not acceptable during the access of secure
OTP region, once Security OTP is locked down, only read related commands are valid.
10-25. Exit Secured OTP (EXSO)
The EXSO instruction is for exiting the additional 4K-bit Secured OTP mode.
The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP
mode→ CS# goes high.
The SIO[3:1] are don't care.
P/N: PM2113
50
Rev. 1.6, March 10, 2017
MX25L3233F
10-26. Read Security Register (RDSCUR)
The RDSCUR instruction is for reading the value of Security Register. The Read Security Register can be read
at any time (even in program/erase/write status register/write security register condition) and continuously.
The sequence of issuing RDSCUR instruction is: CS# goes low→ sending RDSCUR instruction → Security Register data out on SO→ CS# goes high.
The SIO[3:1] are don't care.
Figure 30. Read Security Register (RDSCUR) Sequence (Command 2Bh)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
command
2B
SI
SO
High-Z
Security Register Out
7
6
5
4
3
2
1
Security Register Out
0
7
6
5
4
3
2
1
0
7
MSB
MSB
The definition of the Security Register is as below:
Secured OTP Indicator bit. The Secured OTP indicator bit shows the Secured OTP area is locked by factory or
not. When it is "0", it indicates non-factory lock; "1" indicates factory- lock.
Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for customer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 4K-bit Secured
OTP area cannot be updated any more.
Program Suspend Status bit. Program Suspend Bit (PSB) indicates the status of Program Suspend operation.
Users may use PSB to identify the state of flash memory. After the flash memory is suspended by Program Suspend command, PSB is set to "1". PSB is cleared to "0" after program operation resumes.
Erase Suspend Status bit. Erase Suspend Bit (ESB) indicates the status of Erase Suspend operation. Users
may use ESB to identify the state of flash memory. After the flash memory is suspended by Erase Suspend command, ESB is set to "1". ESB is cleared to "0" after erase operation resumes.
P/N: PM2113
51
Rev. 1.6, March 10, 2017
MX25L3233F
Program Fail Flag bit. While a program failure happened, the Program Fail Flag bit would be set. If the program
operation fails on a protected memory region or locked OTP region, this bit will also be set. This bit can be the
failure indication of one or more program operations. This fail flag bit will be cleared automatically after the next
successful program operation.
Erase Fail Flag bit. While an erase failure happened, the Erase Fail Flag bit would be set. If the erase operation fails on a protected memory region or locked OTP region, this bit will also be set. This bit can be the failure
indication of one or more erase operations. This fail flag bit will be cleared automatically after the next successful
erase operation.
Table 10. Security Register Definition
bit7
Reserved
bit6
bit5
E_FAIL
P_FAIL
0=normal
Erase
succeed
0=normal
Program
succeed
1=indicate
Erase failed
(default=0)
1=indicate
Program
failed
(default=0)
non-volatile
bit
volatile bit
volatile bit
Reserved
Read Only
Read Only
Reserved
P/N: PM2113
bit4
bit3
bit2
Reserved
ESB (Erase
Suspend
status)
PSB
(Program
Suspend
status)
0=Erase
is not
suspended
0=Program
is not
suspended
volatile bit
volatile bit
Read Only
Read Only
Reserved
volatile bit
bit1
bit0
LDSO
Secured OTP
(lock-down 4K- Indicator bit
bit Secured
(4K-bit
OTP)
Secured OTP)
0 = not
lockdown
0 = nonfactory
lock
1 = lock-down
(cannot
1=Erase is 1=Program
program/erase
suspended is suspended
OTP)
(default=0) (default=0)
52
1 = factory
lock
non-volatile bit non-volatile bit
OTP
Read Only
Rev. 1.6, March 10, 2017
MX25L3233F
10-27. Write Security Register (WRSCUR)
The WRSCUR instruction is for changing the values of Security Register Bits. Unlike write status register, the
WREN instruction is required before sending WRSCUR instruction. The WRSCUR instruction may change the
values of bit1 (LDSO bit) for customer to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is set to
"1", the Secured OTP area cannot be updated any more.
The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes
high.
The SIO[3:1] are don't care.
The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
Figure 31. Write Security Register (WRSCUR) Sequence (Command 2Fh) (SPI mode)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
SO
P/N: PM2113
2F
High-Z
53
Rev. 1.6, March 10, 2017
MX25L3233F
10-28. Program Suspend and Erase Suspend
The Suspend instruction interrupts a Page Program, Sector Erase, or Block Erase operation to allow access to
the memory array. After the program or erase operation has entered the suspended state, the memory array can
be read except for the page being programmed or the sector or block being erased ("Table 11. Readable Area of
Memory While a Program or Erase Operation is Suspended").
Table 11. Readable Area of Memory While a Program or Erase Operation is Suspended
Suspended Operation
Readable Region of Memory Array
Page Program
All but the Page being programmed
Sector Erase (4KB)
All but the 4KB Sector being erased
Block Erase (32KB)
All but the 32KB Block being erased
Block Erase (64KB)
All but the 64KB Block being erased
When the serial flash receives the Suspend instruction, there is a latency of tPSL or tESL ("Figure 32. Suspend
to Read Latency") before the Write Enable Latch (WEL) bit clears to “0” and the PSB or ESB sets to “1”, after
which the device is ready to accept one of the commands listed in "Table 12. Acceptable Commands During Program/Erase Suspend after tPSL/tESL" (e.g. FAST READ). Refer to "Table 18. AC Characteristics" for tPSL and
tESL timings. "Table 13. Acceptable Commands During Suspend (tPSL/tESL not required)" lists the commands
for which the tPSL and tESL latencies do not apply. For example, RDSR, RDSCUR, RSTEN, and RST can be issued at any time after the Suspend instruction.
Security Register bit 2 (PSB) and bit 3 (ESB) can be read to check the suspend status. The PSB (Program Suspend Bit) sets to “1” when a program operation is suspended. The ESB (Erase Suspend Bit) sets to “1” when an
erase operation is suspended. The PSB or ESB clears to “0” when the program or erase operation is resumed.
Table 12. Acceptable Commands During Program/Erase Suspend after tPSL/tESL
Command Name
Command Code
READ
03h
FAST READ
0Bh
DREAD
3Bh
QREAD
6Bh
2READ
BBh
4READ
EBh
RDSFDP
5Ah
RDID
9Fh
REMS
90h
ENSO
B1h
EXSO
C1h
SBL
C0h or 77h
WREN
06h
RESUME
7Ah or 30h
PP
02h
4PP
38h
P/N: PM2113
Suspend Type
Program Suspend
Erase Suspend
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
54
Rev. 1.6, March 10, 2017
MX25L3233F
Table 13. Acceptable Commands During Suspend (tPSL/tESL not required)
Command Name
Command Code
WRDI
04h
RDSR
05h
RDCR
15h
RDSCUR
2Bh
RES
ABh
RSTEN
66h
RST
99h
NOP
00h
Suspend Type
Program Suspend
Erase Suspend
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Figure 32. Suspend to Read Latency
CS#
Suspend Command
tPSL / tESL
Read Command
tPSL: Program Latency
tESL: Erase Latency
Figure 33. Resume to Suspend Latency
CS#
Resume Command
tPRS / tERS
Suspend
Command
tPRS: Program Resume to another Suspend
tERS: Erase Resume to another Suspend
P/N: PM2113
55
Rev. 1.6, March 10, 2017
MX25L3233F
10-28-1.
Program Suspend
The “Erase Suspend to Program” feature allows Page Programming while an erase operation is suspended.
Page Programming is permitted in any unprotected memory except within the sector of a suspended Sector
Erase operation or within the block of a suspended Block Erase operation. The Write Enable (WREN) instruction
must be issued before any Page Program instruction.
A Page Program operation initiated within a suspended erase cannot itself be suspended and must be allowed
to finish before the suspended erase can be resumed. The Status Register can be polled to determine the status
of the Page Program operation. The WEL and WIP bits of the Status Register will remain “1” while the Page
Program operation is in progress and will both clear to “0” when the Page Program operation completes.
Figure 34. Suspend to Program Latency
CS#
Suspend Command
tPSL / tESL
Program Command
tPSL: Program Latency
tESL: Erase Latency
10-29. Program Resume and Erase Resume
The Resume instruction resumes a suspended Page Program, Sector Erase, or Block Erase operation. Before
issuing the Resume instruction to restart a suspended erase operation, make sure that there is no Page Program
operation in progress.
Immediately after the serial flash receives the Resume instruction, the WEL and WIP bits are set to “1” and the
PSB or ESB is cleared to “0”. The program or erase operation will continue until finished ("Figure 35. Resume to
Read Latency") or until another Suspend instruction is received. A resume-to-suspend latency of tPRS or tERS
must be observed before issuing another Suspend instruction ("Figure 33. Resume to Suspend Latency").
Please note that the Resume instruction will be ignored if the serial flash is in “Performance Enhance Mode”.
Make sure the serial flash is not in “Performance Enhance Mode” before issuing the Resume instruction.
Figure 35. Resume to Read Latency
CS#
P/N: PM2113
Resume Command
tSE/tBE/tBE32K/tPP
Read Command
56
Rev. 1.6, March 10, 2017
MX25L3233F
10-30. No Operation (NOP)
The "No Operation" command is only able to terminate the Reset Enable (RSTEN) command and will not affect
any other command.
10-31. Software Reset (Reset-Enable (RSTEN) and Reset (RST))
The Software Reset operation combines two instructions: Reset-Enable (RSTEN) command and Reset (RST)
command. It returns the device to a standby mode. All the volatile bits and settings will be cleared then, which
makes the device return to the default status as power on.
To execute Reset command (RST), the Reset-Enable (RSTEN) command must be executed first to perform the
Reset operation. If there is any other command to interrupt after the Reset-Enable command, the Reset-Enable
will be invalid.
If the Reset command is executed during program or erase operation, the operation will be disabled, the data under processing could be damaged or lost.
The reset time is different depending on the last operation. Longer latency time is required to recover from a program operation than from other operations.
Figure 36. Software Reset Recovery
Stand-by Mode
CS#
66
99
tRCR
tRCP
tRCE
Mode
P/N: PM2113
57
Rev. 1.6, March 10, 2017
MX25L3233F
10-32. Read SFDP Mode (RDSFDP)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the
functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These
parameter tables can be interrogated by host system software to enable adjustments needed to accommodate
divergent features from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC
Standard, JESD68 on CFI.
The sequence of issuing RDSFDP instruction is CS# goes low→send RDSFDP instruction (5Ah)→send 3
address bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP operation
can use CS# to high at any time during data out.
SFDP is a JEDEC Standard, JESD216.
Figure 37. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
SO
24 BIT ADDRESS
23 22 21
5Ah
3
2
1
0
High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Cycle
SI
7
6
5
4
3
2
1
0
DATA OUT 2
DATA OUT 1
SO
7
6
MSB
P/N: PM2113
58
5
4
3
2
1
0
7
MSB
6
5
4
3
2
1
0
7
MSB
Rev. 1.6, March 10, 2017
MX25L3233F
Table 14. Signature and Parameter Identification Data Values
SFDP Table (JESD216) below is for MX25L3233FM1I-08G, MX25L3233FZBI-08G, MX25L3233FM2I-08G,
MX25L3233FMI-08G, MX25L3233FZNI-08G, MX25L3233FM1I-08Q, MX25L3233FZBI-08Q, MX25L3233FM2I08Q, MX25L3233FMI-08Q and MX25L3233FZNI-08Q
Description
SFDP Signature
Comment
Fixed: 50444653h
Add (h) DW Add Data (h/b) Data
(Byte)
(Bit)
(Note1)
(h)
00h
07:00
53h
53h
01h
15:08
46h
46h
02h
23:16
44h
44h
03h
31:24
50h
50h
SFDP Minor Revision Number
Start from 00h
04h
07:00
00h
00h
SFDP Major Revision Number
Start from 01h
This number is 0-based. Therefore,
0 indicates 1 parameter header.
05h
15:08
01h
01h
06h
23:16
01h
01h
07h
31:24
FFh
FFh
00h: it indicates a JEDEC specified
header.
08h
07:00
00h
00h
Start from 00h
09h
15:08
00h
00h
Start from 01h
0Ah
23:16
01h
01h
How many DWORDs in the
Parameter table
0Bh
31:24
09h
09h
0Ch
07:00
30h
30h
0Dh
15:08
00h
00h
0Eh
23:16
00h
00h
0Fh
31:24
FFh
FFh
it indicates Macronix manufacturer
ID
10h
07:00
C2h
C2h
Start from 00h
11h
15:08
00h
00h
Start from 01h
12h
23:16
01h
01h
How many DWORDs in the
Parameter table
13h
31:24
04h
04h
14h
07:00
60h
60h
15h
15:08
00h
00h
16h
23:16
00h
00h
17h
31:24
FFh
FFh
Number of Parameter Headers
Unused
ID number (JEDEC)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length
(in double word)
Parameter Table Pointer (PTP)
First address of JEDEC Flash
Parameter table
Unused
ID number
(Macronix manufacturer ID)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length
(in double word)
Parameter Table Pointer (PTP)
First address of Macronix Flash
Parameter table
Unused
P/N: PM2113
59
Rev. 1.6, March 10, 2017
MX25L3233F
Table 15. Parameter Table (0): JEDEC Flash Parameter Tables
SFDP Table below is for MX25L3233FM1I-08G, MX25L3233FZBI-08G, MX25L3233FM2I-08G, MX25L3233FMI08G, MX25L3233FZNI-08G, MX25L3233FM1I-08Q, MX25L3233FZBI-08Q, MX25L3233FM2I-08Q,
MX25L3233FMI-08Q and MX25L3233FZNI-08Q
Description
Comment
Block/Sector Erase sizes
00: Reserved, 01: 4KB erase,
10: Reserved,
11: not support 4KB erase
Write Granularity
0: 1Byte, 1: 64Byte or larger
Write Enable Instruction Required 0: not required
1: required 00h to be written to the
for Writing to Volatile Status
status register
Registers
Add (h) DW Add Data (h/b)
(Byte)
(Bit)
(Note1)
01b
02
1b
03
0b
30h
0: use 50h opcode,
1: use 06h opcode
Write Enable Opcode Select for
Note: If target flash status register is
Writing to Volatile Status Registers
nonvolatile, then bits 3 and 4 must
be set to 00b.
Contains 111b and can never be
Unused
changed
4KB Erase Opcode
01:00
31h
Data
(h)
E5h
04
0b
07:05
111b
15:08
20h
16
1b
18:17
00b
19
0b
20
1b
20h
(1-1-2) Fast Read (Note2)
0=not support 1=support
Address Bytes Number used in
addressing flash array
Double Transfer Rate (DTR)
Clocking
00: 3Byte only, 01: 3 or 4Byte,
10: 4Byte only, 11: Reserved
(1-2-2) Fast Read
0=not support 1=support
(1-4-4) Fast Read
0=not support 1=support
21
1b
(1-1-4) Fast Read
0=not support 1=support
22
1b
23
1b
33h
31:24
FFh
37h:34h
31:00
01FF FFFFh
0=not support 1=support
32h
Unused
Unused
Flash Memory Density
(1-4-4) Fast Read Number of Wait
states (Note3)
(1-4-4) Fast Read Number of
Mode Bits (Note4)
0 0000b: Not supported; 0 0100b: 4
0 0110b: 6; 0 1000b: 8
Mode Bits:
000b: Not supported; 010b: 2 bits
(1-4-4) Fast Read Opcode
(1-1-4) Fast Read Number of Wait
states
(1-1-4) Fast Read Number of
Mode Bits
39h
0 0000b: Not supported; 0 0100b: 4
0 0110b: 6; 0 1000b: 8
Mode Bits:
000b: Not supported; 010b: 2 bits
(1-1-4) Fast Read Opcode
P/N: PM2113
38h
3Ah
3Bh
60
04:00
0 0100b
07:05
010b
15:08
EBh
20:16
0 1000b
23:21
000b
31:24
6Bh
F1h
FFh
44h
EBh
08h
6Bh
Rev. 1.6, March 10, 2017
MX25L3233F
SFDP Table below is for MX25L3233FM1I-08G, MX25L3233FZBI-08G, MX25L3233FM2I-08G, MX25L3233FMI08G, MX25L3233FZNI-08G, MX25L3233FM1I-08Q, MX25L3233FZBI-08Q, MX25L3233FM2I-08Q,
MX25L3233FMI-08Q and MX25L3233FZNI-08Q
Add (h) DW Add Data (h/b) Data
Description
Comment
(Byte)
(Bit)
(Note1)
(h)
(1-1-2) Fast Read Number of Wait 0 0000b: Not supported; 0 0100b: 4
04:00
0 1000b
states
0 0110b: 6; 0 1000b: 8
3Ch
08h
(1-1-2) Fast Read Number of
Mode Bits:
07:05
000b
Mode Bits
000b: Not supported; 010b: 2 bits
(1-1-2) Fast Read Opcode
(1-2-2) Fast Read Number of Wait
states
(1-2-2) Fast Read Number of
Mode Bits
3Dh
0 0000b: Not supported; 0 0100b: 4
0 0110b: 6; 0 1000b: 8
Mode Bits:
000b: Not supported; 010b: 2 bits
(1-2-2) Fast Read Opcode
(2-2-2) Fast Read
3Fh
0=not support 1=support
Unused
(4-4-4) Fast Read
3Eh
0=not support 1=support
40h
Unused
15:08
3Bh
20:16
0 0100b
23:21
000b
31:24
BBh
00
0b
03:01
111b
04
0b
07:05
111b
3Bh
04h
BBh
EEh
Unused
43h:41h
31:08
FFh
FFh
Unused
45h:44h
15:00
FFh
FFh
20:16
0 0000b
23:21
000b
47h
31:24
FFh
FFh
49h:48h
15:00
FFh
FFh
20:16
0 0000b
23:21
000b
4Bh
31:24
FFh
FFh
4Ch
07:00
0Ch
0Ch
4Dh
15:08
20h
20h
4Eh
23:16
0Fh
0Fh
4Fh
31:24
52h
52h
50h
07:00
10h
10h
51h
15:08
D8h
D8h
52h
23:16
00h
00h
53h
31:24
FFh
FFh
(2-2-2) Fast Read Number of Wait
states
(2-2-2) Fast Read Number of
Mode Bits
0 0000b: Not supported; 0 0100b: 4
0 0110b: 6; 0 1000b: 8
Mode Bits:
000b: Not supported; 010b: 2 bits
(2-2-2) Fast Read Opcode
Unused
(4-4-4) Fast Read Number of Wait
states
(4-4-4) Fast Read Number of
Mode Bits
0 0000b: Not supported; 0 0100b: 4
0 0110b: 6; 0 1000b: 8
Mode Bits:
000b: Not supported; 010b: 2 bits
(4-4-4) Fast Read Opcode
Sector Type 1 Size
Sector/block size = 2^N bytes (Note5)
0Ch: 4KB; 0Fh: 32KB; 10h: 64KB
Sector Type 1 erase Opcode
Sector Type 2 Size
Sector/block size = 2^N bytes
00h: N/A; 0Fh: 32KB; 10h: 64KB
Sector Type 2 erase Opcode
Sector Type 3 Size
Sector/block size = 2^N bytes
00h: N/A; 0Fh: 32KB; 10h: 64KB
Sector Type 3 erase Opcode
Sector Type 4 Size
00h: N/A, This sector type doesn't
exist
Sector Type 4 erase Opcode
P/N: PM2113
61
46h
4Ah
00h
00h
Rev. 1.6, March 10, 2017
MX25L3233F
Table 16. Parameter Table (1): Macronix Flash Parameter Tables
SFDP Table below is for MX25L3233FM1I-08G, MX25L3233FZBI-08G, MX25L3233FM2I-08G, MX25L3233FMI08G, MX25L3233FZNI-08G, MX25L3233FM1I-08Q, MX25L3233FZBI-08Q, MX25L3233FM2I-08Q,
MX25L3233FMI-08Q and MX25L3233FZNI-08Q
Add (h) DW Add Data (h/b) Data
Description
Comment
(Byte)
(Bit)
(Note1)
(h)
2000h=2.000V
07:00
00h
00h
Vcc Supply Maximum Voltage
2700h=2.700V
61h:60h
15:08
36h
36h
3600h=3.600V
1650h=1.650V, 1750h=1.750V
2250h=2.250V, 2300h=2.300V
23:16
50h
50h
Vcc Supply Minimum Voltage
63h:62h
2350h=2.350V, 2650h=2.650V
31:24
26h
26h
2700h=2.700V
H/W Reset# pin
0=not support 1=support
00
0b
H/W Hold# pin
0=not support 1=support
01
1b
Deep Power Down Mode
0=not support 1=support
02
1b
S/W Reset
0=not support 1=support
03
1b
S/W Reset Opcode
Reset Enable (66h) should be
issued before Reset Opcode
Program Suspend/Resume
0=not support 1=support
12
1b
Erase Suspend/Resume
0=not support 1=support
13
1b
14
1b
15
1b
66h
23:16
77h
77h
67h
31:24
64h
64h
65h:64h
Unused
Wrap-Around Read mode
0=not support 1=support
Wrap-Around Read mode Opcode
11:04
1001 1001b
F99Eh
(99h)
Wrap-Around Read data length
08h:support 8B wrap-around read
16h:8B&16B
32h:8B&16B&32B
64h:8B&16B&32B&64B
Individual block lock
0=not support 1=support
00
0b
Individual block lock bit
(Volatile/Nonvolatile)
0=Volatile 1=Nonvolatile
01
1b
09:02
1111 1111b
(FFh)
10
1b
11
1b
Individual block lock Opcode
Individual block lock Volatile
protect bit default protect status
0=protect 1=unprotect
Secured OTP
0=not support 1=support
Read Lock
0=not support 1=support
12
0b
Permanent Lock
0=not support 1=support
13
0b
Unused
15:14
11b
Unused
31:16
FFh
FFh
31:00
FFh
FFh
Unused
6Bh:68h
6Fh:6Ch
CFFEh
MX25L3233FM1I-08G-SFDP_2016-10-11,SF10
P/N: PM2113
62
Rev. 1.6, March 10, 2017
MX25L3233F
Notes:
1: h/b is hexadecimal or binary.
2: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode
(x), address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-11), (2-2-2), and (4-4-4)
3: Wait States is required dummy clock cycles after the address bits or optional mode bits.
4: Mode Bits is optional control bits that follow the address bits. These bits are driven by the system
controller if they are specified. (eg, read performance enhance toggling bits)
5: 4KB=2^0Ch, 32KB=2^0Fh, 64KB=2^10h
6: All unused and undefined area data is blank FFh for SFDP Tables that are defined in Parameter
Identification Header. All other areas beyond defined SFDP Table are reserved by Macronix.
P/N: PM2113
63
Rev. 1.6, March 10, 2017
MX25L3233F
11. POWER-ON STATE
The device is at the following states after power-up:
- Standby mode
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage until the VCC reaches the following
levels:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal Power-on Reset (POR) circuit may protect the device from data corruption and inadvertent data
change during power up state.
For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is
not guaranteed. The read, write, erase, and program command should be sent after the time delay:
- tVSL after VCC reached VCC minimum level
The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended. (generally around 0.1uF)
P/N: PM2113
64
Rev. 1.6, March 10, 2017
MX25L3233F
12. Electrical Specifications
12-1.
Absolute Maximum Ratings
RATING
VALUE
Ambient Operating Temperature
Industrial grade
-40°C to 85°C
Storage Temperature
-65°C to 150°C
Applied Input Voltage
-0.5V to 4.6V
Applied Output Voltage
-0.5V to 4.6V
VCC to Ground Potential
-0.5V to 4.6V
NOTICE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage
to the device. This is stress rating only and functional operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended period may affect reliability.
2. Specifications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see
the figures below.
Figure 38. Maximum Negative Overshoot Waveform
20ns
Figure 39. Maximum Positive Overshoot Waveform
20ns
20ns
Vss
Vcc + 2.0V
Vss-2.0V
Vcc
20ns
20ns
12-2.
Capacitance TA = 25°C, f = 1.0 MHz
Symbol Parameter
CIN
COUT
P/N: PM2113
20ns
Min.
Typ.
Max.
Unit
Input Capacitance
6
pF
VIN = 0V
Output Capacitance
8
pF
VOUT = 0V
65
Conditions
Rev. 1.6, March 10, 2017
MX25L3233F
Figure 40. Input Test Waveforms and Measurement Level
Input timing reference level
0.8VCC
0.2VCC
Output timing reference level
0.7VCC
0.3VCC
AC
Measurement
Level
0.5VCC
Note: Input pulse rise and fall time are
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