MX25L3255DXCI-10G

MX25L3255D MX25L3255D SECURE SERIAL FLASH SPECIFICATION P/N: PM1431 REV. 1.1, SEP. 09, 2010 1 MX25L3255D Contents FEATURES................................................................................................................................................................... 5 GENERAL DESCRIPTION.......................................................................................................................................... 7 Table 1. Additional Feature Comparison............................................................................................................. 7 PIN CONFIGURATIONS .............................................................................................................................................. 8 PIN DESCRIPTION....................................................................................................................................................... 8 BLOCK DIAGRAM........................................................................................................................................................ 9 DATA PROTECTION................................................................................................................................................... 10 Table 2. 4K-bit Secured OTP Definition............................................................................................................. 11 Memory Organization................................................................................................................................................ 12 Table 3. Memory Organization......................................................................................................................... 12 DEVICE OPERATION................................................................................................................................................. 14 Figure 1. Serial Modes Supported.................................................................................................................... 14 COMMAND DESCRIPTION........................................................................................................................................ 15 Table 4. Command Set...................................................................................................................................... 15 (1) Write Enable (WREN).................................................................................................................................. 17 (2) Write Disable (WRDI)................................................................................................................................... 17 (3) Read Identification (RDID)........................................................................................................................... 17 (4) Read Status Register (RDSR)..................................................................................................................... 17 (5) Block Write Lock Protection (BLOCKP)....................................................................................................... 18 (6) Read Block Write Lock status (RDBLOCK)................................................................................................. 18 (7) Chip Unprotect (UNLOCK).......................................................................................................................... 19 (8) Read Data Bytes (READ)............................................................................................................................ 19 (9) Read Data Bytes at Higher Speed (FAST_READ)...................................................................................... 19 (10) 2 x I/O Read Mode (2READ)..................................................................................................................... 19 (11) Dual Read Mode (DREAD)........................................................................................................................ 20 (12) 4 x I/O Read Mode (4READ)..................................................................................................................... 20 (13) Quad Read Mode (QREAD)...................................................................................................................... 20 (14) Sector Erase (SE)...................................................................................................................................... 21 (15) Block Erase (BE)....................................................................................................................................... 21 (16) Chip Erase (CE)......................................................................................................................................... 21 (17) Page Program (PP)................................................................................................................................... 22 (18) 4 x I/O Page Program (4PP)...................................................................................................................... 22 (19) Continuously program mode (CP mode)................................................................................................... 22 (20) Deep Power-down (DP)............................................................................................................................. 23 (21) Release from Deep Power-down (RDP), Read Electronic Signature (RES)............................................. 23 (22) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4)........................................... 24 Table 5. ID Definitions ...................................................................................................................................... 24 (23) Enter Secured OTP (ENSO)...................................................................................................................... 25 (24) Exit Secured OTP (EXSO)......................................................................................................................... 25 P/N: PM1431 REV. 1.1, SEP. 09, 2010 2 MX25L3255D (25) Read Security Register (RDSCUR)........................................................................................................... 25 Table 6. Security Register Definition................................................................................................................. 26 (26) Write Security Register (WRSCUR)........................................................................................................... 26 POWER-ON STATE.................................................................................................................................................... 27 ELECTRICAL SPECIFICATIONS............................................................................................................................... 28 ABSOLUTE MAXIMUM RATINGS.................................................................................................................... 28 Figure 2.Maximum Negative Overshoot Waveform.......................................................................................... 28 CAPACITANCE TA = 25°C, f = 1.0 MHz............................................................................................................ 28 Figure 3. Maximum Positive Overshoot Waveform........................................................................................... 28 Figure 4. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL............................................................. 29 Figure 5. OUTPUT LOADING.......................................................................................................................... 29 Table 7. DC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V) .. 30 Table 8. AC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V) .31 Timing Analysis......................................................................................................................................................... 32 Figure 6. Serial Input Timing............................................................................................................................. 32 Figure 7. Output Timing..................................................................................................................................... 32 Figure 8. WP# Setup Timing and Hold Timing ................................................................................................. 33 Figure 9. Write Enable (WREN) Sequence (Command 06).............................................................................. 33 Figure 10. Write Disable (WRDI) Sequence (Command 04)............................................................................. 33 Figure 11. Read Identification (RDID) Sequence (Command 9F)..................................................................... 34 Figure 12. Read Status Register (RDSR) Sequence (Command 05)............................................................... 34 Figure 13. Block Write Lock Protection (BLOCKP) Sequence (Command E2)................................................ 34 Figure 14. Chip Unprotect (UNLOCK) Sequence (Command F3)................................................................... 35 Figure 15. Read Data Bytes (READ) Sequence (Command 03)..................................................................... 35 Figure 16. Read Block Protection Lock Status (RDBLOCK) Sequence (Command FB)................................. 35 Figure 17. Read at Higher Speed (FAST_READ) Sequence (Command 0B)................................................. 36 Figure 18. 2 x I/O Read Mode Sequence (Command BB)................................................................................ 36 Figure 19. Dual Read Mode Sequence (Command 3B)................................................................................... 37 Figure 20. 4 x I/O Read Mode Sequence (Command EB)................................................................................ 37 Figure 21. 4 x I/O Read enhance performance Mode Sequence (Command EB)............................................ 38 Figure 22. Quad Read Mode Sequence (Command 6B).................................................................................. 39 Figure 23. Page Program (PP) Sequence (Command 02).............................................................................. 40 Figure 24. 4 x I/O Page Program (4PP) Sequence (Command 38)................................................................. 40 Figure 25. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD).................. 41 Figure 26. Sector Erase (SE) Sequence (Command 20)................................................................................. 41 Figure 27. Block Erase (BE) Sequence (Command D8).................................................................................. 41 Figure 28. Chip Erase (CE) Sequence (Command 60 or C7).......................................................................... 42 Figure 29. Deep Power-down (DP) Sequence (Command B9)....................................................................... 42 Figure 30. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB). .......................................................................................................................................................................... 42 Figure 31. Release from Deep Power-down (RDP) Sequence (Command AB).............................................. 43 Figure 32. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF)......... 43 P/N: PM1431 REV. 1.1, SEP. 09, 2010 3 MX25L3255D Figure 33. Power-up Timing.............................................................................................................................. 44 Table 9. Power-Up Timing ................................................................................................................................ 44 INITIAL DELIVERY STATE............................................................................................................................... 44 OPERATING CONDITIONS........................................................................................................................................ 45 Figure 34. AC Timing at Device Power-Up........................................................................................................ 45 Figure 35. Power-Down Sequence................................................................................................................... 46 ERASE AND PROGRAMMING PERFORMANCE..................................................................................................... 47 DATA RETENTION..................................................................................................................................................... 47 LATCH-UP CHARACTERISTICS............................................................................................................................... 47 ORDERING INFORMATION....................................................................................................................................... 48 PART NAME DESCRIPTION...................................................................................................................................... 49 PACKAGE INFORMATION......................................................................................................................................... 50 REVISION HISTORY ................................................................................................................................................. 52 P/N: PM1431 REV. 1.1, SEP. 09, 2010 4 MX25L3255D 32M-BIT [x 1/x 2/x4] CMOS MXSMIOTM (SERIAL MULTI I/O) FLASH MEMORY FEATURES GENERAL • Serial Peripheral Interface compatible -- Mode 0 and Mode 3 • 33,554,432 x 1 bit structure or 16,772,216 x 2 bits (two I/O read mode) structure or 8,388,608 x 4 bits (four I/O read mode) structure • 1024 Equal Sectors with 4K byte each - Any Sector can be erased individually • 64 Equal Blocks with 64K byte each - Any Block can be erased individually • Single Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations • Latch-up protected to 100mA from -1V to Vcc +1V PERFORMANCE • High Performance - Fast read - 1 I/O: 104MHz with 8 dummy cycles - 4 I/O: 75MHz with 6 dummy cycles for 4READ; 75MHz with 8 dummy cycles for QREAD - 2 I/O: 75MHz with 4 dummy cycles for 2READ; 75MHz with 8 dummy cycles for DREAD - Fast access time: 104MHz serial clock - Serial clock of four I/O read mode : 75MHz, which is equivalent to 300MHz - Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page) - Byte program time: 9us (typical) - Continuously program mode (automatically increase address under word program mode) - Fast erase time: 60ms (typ.)/sector (4K-byte per sector) ; 0.7s(typ.) /block (64K-byte per block); 25s(typ.) /chip • Low Power Consumption - Low active read current: 25mA(max.) at 104MHz, 20mA(max.) at 66MHz and 10mA(max.) at 33MHz - Low active programming current: 20mA (max.) - Low active erase current: 20mA (max.) - Low standby current: 20uA (max.) • Typical 100,000 erase/program cycles • 20 years data retention SOFTWARE FEATURES • Input Data Format - 1-byte Command code • Advanced Security Features - Block Write Lock protection - Additional 4K-bit secured OTP for unique identifier - Permanent lock - Read protection function • Auto Erase and Auto Program Algorithm - Automatically erases and verifies data at selected sector - Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (Any page to be programed should have page in the erased state first) P/N: PM1431 REV. 1.1, SEP. 09, 2010 5 MX25L3255D • Status Register Feature • Electronic Identification - JEDEC 1-byte manufacturer ID and 2-byte device ID - RES command for 1-byte Device ID - Both REMS,REMS2 and REMS4 commands for 1-byte manufacturer ID and 1-byte device ID HARDWARE FEATURES • SCLK Input - Serial clock input • SI/SIO0 - Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode • SO/SIO1 - Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode • WP#/SIO2 - Hardware write protection or serial data Input/Output for 4 x I/O read mode • NC/SIO3 - NC pin or serial data Input/Output for 4 x I/O read mode • PACKAGE - 8-pin SOP (200mil) - 24-ball BGA - All Pb-free devices are RoHS Compliant Please contact Macronix sales for specific information regarding this Advanced Security Features P/N: PM1431 REV. 1.1, SEP. 09, 2010 6 MX25L3255D GENERAL DESCRIPTION The MX25L3255D are 33,554,432 bit serial Flash memory, which is configured as 4,194,304 x 8 internally. When it is in two or four I/O read mode, the structure becomes 16,772,216 bits x 2 or 8,388,608 bits x 4. The MX25L3255D feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input. When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# pin and NC pin become SIO0 pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output. The MX25L3255D provides sequential read operation on whole chip. After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256 bytes) basis, or word basis for Continuously program mode, and erase command is executes on sector (4K-byte), or block (64K-byte), or whole chip basis. To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. Advanced security features enhance the protection and security functions, please contact Macronix sales for more details. When the device is not in operation and CS# is high, it is put in standby mode and draws less than 20uA DC current. The MX25L3255D utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles. Table 1. Additional Feature Comparison Part Name MX25L3255D MX25L3235D Read Performance Protection and Security Additional Features Permanent Lock V Each 4K-bit WP# Read Block secured Hardware ProtectProtection OTP Protection ion V V V V V V P/N: PM1431 2 I/O Read (75 MHz) 4 I/O Read (75 MHz) V V V V Identifier REMS/2/4 RES RDID (command: (command: (command: 90/EF/0F 90 hex) 9F hex) hex) C2 9E 16 9E (hex) C2 9E (hex) (hex) C2 5E 16 5E (hex) C2 5E (hex) (hex) REV. 1.1, SEP. 09, 2010 7 MX25L3255D PIN CONFIGURATIONS PIN DESCRIPTION SYMBOL CS# 8-PIN SOP (200mil) CS# SO/SIO1 WP#/SIO2 GND 1 2 3 4 8 7 6 5 SI/SIO0 VCC NC/SIO3 SCLK SI/SIO0 SO/SIO1 SCLK WP#/SIO2 NC/SIO3 VCC GND DESCRIPTION Chip Select Serial Data Input (for 1 x I/O)/ Serial Data Input & Output (for 2xI/O or 4xI/ O read mode) Serial Data Output (for 1 x I/O)/ Serial Data Input & Output (for 2xI/O or 4xI/ O read mode) Clock Input Write protection: connect to GND or Serial Data Input & Output (for 4xI/O read mode) NC pin (Not connect) or Serial Data Input & Output (for 4xI/O read mode) + 3.3V Power Supply Ground 24-ball BGA 4 NC VCC NC/SIO3 NC NC NC GND NC SI/SIO0 NC NC NC SCLK CS# SO/SIO1 NC NC NC NC NC NC NC NC A B C D E WP#/SIO2 3 2 1 P/N: PM1431 F REV. 1.1, SEP. 09, 2010 8 MX25L3255D BLOCK DIAGRAM X-Decoder Address Generator Memory Array Page Buffer SI/SIO0 Data Register Y-Decoder SRAM Buffer CS# WP#/SIO2 NC/SIO3 SCLK Mode Logic State Machine Sense Amplifier HV Generator Clock Generator Output Buffer SO/SIO1 P/N: PM1431 REV. 1.1, SEP. 09, 2010 9 MX25L3255D DATA PROTECTION MX25L3255D is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the standby mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise. • Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary. • Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other command to change data. The WEL bit will return to reset stage under following situation: - Power-up - Write Disable (WRDI) command completion - Page Program (PP) command completion - Continuously Program mode (CP) instruction completion - Sector Erase (SE) command completion - Block Erase (BE) command completion - Chip Erase (CE) command completion • Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing all commands except Release from deep power down mode command (RDP) and Read Electronic Signature command (RES). • Advanced Security Features: there are some protection and securuity features which protect content from inadvertent write and hostile access. I. Block Write Lock protection - The Software Protected Mode (SPM) use A23-A16 address bits to allow a block (64K Byte) of memory to be protected as read only through the Block Write Lock protection command (BLOCKP). This feature allows user to unprotect the entice chip through the chip unprotect command (UNLOCK). - The Hardware Protected Mode (HPM) use WP#/SIO2 to protect the Block. If WP#/SIO2=VIL (input Low), all blocks of memory to be protected as read only. If WP#/SIO2=VIH (input High), all blocks depends on whether they were last Lock or Unlock. If the system goes into four I/O read mode, the feature of HPM will be disabled. P/N: PM1431 REV. 1.1, SEP. 09, 2010 10 MX25L3255D II. Additional 4K-bit secured OTP for unique identifier: to provide 4K-bit one-time program area for setting device unique serial number - Which may be set by factory or system customer. Please refer to table 2. 4K-bit secured OTP definition. - Security register bit 0 indicates whether the chip is locked by factory or not. - To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with ENSO command), and going through normal program procedure, and then exiting 4K-bit secured OTP mode by writing EXSO command. - Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register) command to set customer lock-down bit1 as "1". Please refer to table of "security register definition" for security register bit definition and table of "4K-bit secured OTP definition" for address range definition. - Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit secured OTP mode, array access is not allowed. Table 2. 4K-bit Secured OTP Definition Address range Size Standard Factory Lock xxx000~xxx00F 128-bit ESN (electrical serial number) xxx010~xxx1FF 3968-bit N/A P/N: PM1431 Customer Lock Determined by customer REV. 1.1, SEP. 09, 2010 11 MX25L3255D Memory Organization Table 3. Memory Organization Block 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 Sector 1023 : 1008 1007 : 992 991 : 976 975 : 960 959 : 944 943 : 928 927 : 912 911 : 896 895 : 880 879 : 864 863 : 848 847 : 832 831 : 816 815 : 800 799 : 784 783 : 768 Block Address Range 3FF000h 3FFFFFh : : 3F0000h 3F0FFFh 3EF000h 3EFFFFh : : 3E0000h 3E0FFFh 3DF000h 3DFFFFh : : 3D0000h 3D0FFFh 3CF000h 3CFFFFh : : 3C0000h 3C0FFFh 3BF000h 3BFFFFh : : 3B0000h 3B0FFFh 3AF000h 3AFFFFh : : 3A0000h 3A0FFFh 39F000h 39FFFFh : : 390000h 390FFFh 38F000h 38FFFFh : : 380000h 380FFFh 37F000h 37FFFFh : : 370000h 370FFFh 36F000h 36FFFFh : : 360000h 360FFFh 35F000h 35FFFFh : : 350000h 350FFFh 34F000h 34FFFFh : : 340000h 340FFFh 33F000h 33FFFFh : : 330000h 330FFFh 32F000h 32FFFFh : : 320000h 320FFFh 31F000h 31FFFFh : : 310000h 310FFFh 30F000h 30FFFFh : : 300000h 300FFFh 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 P/N: PM1431 Sector 767 : 752 751 : 736 735 : 720 719 : 704 703 : 688 687 : 672 671 : 656 655 : 640 639 : 624 623 : 608 607 : 592 591 : 576 575 : 560 559 : 544 543 : 528 527 : 512 Address Range 2FF000h 2FFFFFh : : 2F0000h 2F0FFFh 2EF000h 2EFFFFh : : 2E0000h 2E0FFFh 2DF000h 2DFFFFh : : 2D0000h 2D0FFFh 2CF000h 2CFFFFh : : 2C0000h 2C0FFFh 2BF000h 2BFFFFh : : 2B0000h 2B0FFFh 2AF000h 2AFFFFh : : 2A0000h 2A0FFFh 29F000h 29FFFFh : : 290000h 290FFFh 28F000h 28FFFFh : : 280000h 280FFFh 27F000h 27FFFFh : : 270000h 270FFFh 26F000h 26FFFFh : : 260000h 260FFFh 25F000h 25FFFFh : : 250000h 250FFFh 24F000h 24FFFFh : : 240000h 240FFFh 23F000h 23FFFFh : : 230000h 230FFFh 22F000h 22FFFFh : : 220000h 220FFFh 21F000h 21FFFFh : : 210000h 210FFFh 20F000h 20FFFFh : : 200000h 200FFFh REV. 1.1, SEP. 09, 2010 12 MX25L3255D Block 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Sector 511 : 496 495 : 480 479 : 464 463 : 448 447 : 432 431 : 416 415 : 400 399 : 384 383 : 368 367 : 352 351 : 336 335 : 320 319 : 304 303 : 288 287 : 272 271 : 256 255 : 240 Block Address Range 1FF000h 1FFFFFh : : 1F0000h 1F0FFFh 1EF000h 1EFFFFh : : 1E0000h 1E0FFFh 1DF000h 1DFFFFh : : 1D0000h 1D0FFFh 1CF000h 1CFFFFh : : 1C0000h 1C0FFFh 1BF000h 1BFFFFh : : 1B0000h 1B0FFFh 1AF000h 1AFFFFh : : 1A0000h 1A0FFFh 19F000h 19FFFFh : : 190000h 190FFFh 18F000h 18FFFFh : : 180000h 180FFFh 17F000h 17FFFFh : : 170000h 170FFFh 16F000h 16FFFFh : : 160000h 160FFFh 15F000h 15FFFFh : : 150000h 150FFFh 14F000h 14FFFFh : : 140000h 140FFFh 13F000h 13FFFFh : : 130000h 130FFFh 12F000h 12FFFFh : : 120000h 120FFFh 11F000h 11FFFFh : : 110000h 110FFFh 10F000h 10FFFFh : : 100000h 100FFFh 0FF000h 0FFFFFh : : 0F0000h 0F0FFFh 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P/N: PM1431 Sector 239 : 224 223 : 208 207 : 192 191 : 176 175 : 160 159 : 144 143 : 128 127 : 112 111 : 96 95 : 80 79 : 64 63 : 48 47 : 32 31 : 16 15 : 3 2 1 0 Address Range 0EF000h 0EFFFFh : : 0E0000h 0E0FFFh 0DF000h 0DFFFFh : : 0D0000h 0D0FFFh 0CF000h 0CFFFFh : : 0C0000h 0C0FFFh 0BF000h 0BFFFFh : : 0B0000h 0B0FFFh 0AF000h 0AFFFFh : : 0A0000h 0A0FFFh 09F000h 09FFFFh : : 090000h 090FFFh 08F000h 08FFFFh : : 080000h 080FFFh 07F000h 07FFFFh : : 070000h 070FFFh 06F000h 06FFFFh : : 060000h 060FFFh 05F000h 05FFFFh : : 050000h 050FFFh 04F000h 04FFFFh : : 040000h 040FFFh 03F000h 03FFFFh : : 030000h 030FFFh 02F000h 02FFFFh : : 020000h 020FFFh 01F000h 01FFFFh : : 010000h 010FFFh 00F000h 00FFFFh : : 003000h 003FFFh 002000h 002FFFh 001000h 001FFFh 000000h 000FFFh REV. 1.1, SEP. 09, 2010 13 MX25L3255D DEVICE OPERATION 1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation. 2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z. 3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next CS# rising edge. 4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as Figure 1. 5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, 2READ, DREAD, 4READ, QREAD, RDBLOCK, RDPLOCK, RES, REMS, REMS2 and REMS4 the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRLB, SE, BE, CE, PP, 4PP, CP, RDP, DP, BLOCKP, UNLOCK, ENSO, and EXSO, the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglected and not affect the current operation of Write Status Register, Program, Erase. Figure 1. Serial Modes Supported CPOL CPHA shift in (Serial mode 0) 0 0 SCLK (Serial mode 3) 1 1 SCLK SI shift out MSB SO MSB Note: CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is supported. P/N: PM1431 REV. 1.1, SEP. 09, 2010 14 MX25L3255D COMMAND DESCRIPTION Table 4. Command Set COMMAND WREN (write WRDI (write RDID (read (byte) enable) disable) identification) 1st byte 2nd byte 3rd byte 4th byte Action 06 (hex) 04 (hex) 9F (hex) 05 (hex) BLOCKP (Block Write Lock protection) E2 (hex) RDSR (read status register) RDBLOCK (read Block Write Lock status) FB (hex) FAST READ (fast read data) 2READ (2 x I/O read command) Note1 DREAD (1I 2O read command) 4READ (4 x I/O read command) QREAD (1I 4O read command) 1st byte 0B (hex) BB (hex) 3B (hex) EB (hex) 6B (hex) 2nd byte AD1 ADD(2) AD1 AD1 x 3rd byte AD2 ADD(2) & Dummy(2) ADD(4) & Dummy(4) AD2 Dummy(4) AD2 x Action COMMAND (byte) 1st byte 2nd byte 3rd byte 4th byte Action READ (read data) 03 (hex) AD1 AD1 AD1 (A23-A16) AD2 AD2 AD2 (A15-A8) AD3 AD3 AD3 (A7-A0) sets the resets the outputs JEDEC to read out assign a read reset Block n bytes read (WEL) write (WEL) write ID: 1-byte the values block (64KB) assigned Write Lock out until CS# enable latch enable latch Manufacturer of the status to lock Block Write protection bit goes high bit bit ID & 2-byte register protection Lock status whole chip Device ID COMMAND (byte) 4th byte 5th byte UNLOCK (chip unprotect) Release Read Enhanced FF (hex) F3 (hex) 4PP (quad page program) SE (sector erase) 38 (hex) 20 (hex) AD1 AD1 AD2 AD3 AD3 AD3 x Dummy Dummy Dummy n bytes read n bytes read n bytes read n bytes read n bytes read All these quad input out until CS# out by 2 x I/ out by Dual out by 4 x I/ out by Quad commands to program goes high O until CS# output until O until CS# output until FFh,00h,AAh the selected goes high CS# goes goes high CS# goes or 55h will page high high escape the performance enhance mode CP (Continuously DP (Deep program power down) mode) D8 (hex) 60 or C7 (hex) 02 (hex) AD (hex) B9 (hex) AD1 AD1 AD1 AD2 AD2 AD2 AD3 AD3 AD3 to erase the to erase to program continously enters deep selected whole chip the selected program power down block page whole chip, mode the address is automatically increase BE (block erase) CE (chip erase) PP (Page program) P/N: PM1431 RDP (Release RES (read from deep electronic ID) power down) AB (hex) AB (hex) x x x release from to read out deep power 1-byte Device down mode ID AD3 to erase the selected sector REMS (read electronic manufacturer & device ID) 90 (hex) x x ADD (Note 2) output the Manufacturer ID & Device ID REV. 1.1, SEP. 09, 2010 15 MX25L3255D COMMAND (byte) 1st byte 2nd byte 3rd byte 4th byte Action REMS4 (read ENSO (enter EXSO (exit RDSCUR REMS2 (read ID for 4x I/O secured secured (read security ID for 2x I/O mode) OTP) OTP) register) mode) EF (hex) DF (hex) B1 (hex) x x x x ADD (Note 2) ADD (Note 2) output the output the to enter Manufacturer Manufactthe 4K-bit ID & Device urer ID & Secured ID device ID OTP mode C1 (hex) 2B (hex) WRSCUR (write security register) 2F (hex) ESRY DSRY (enable SO (disable SO to output RY/ to output RY/ BY#) BY#) 70 (hex) 80 (hex) to exit to read value to set the to enable SO to disable SO the 4K-bit of security lock-down bit to output RY/ to output RY/ Secured register as "1" (once BY# during BY# during OTP mode lock-down, CP mode CP mode cannot be updated) Note 1: The count base is 4-bit for ADD(2) and Dummy(2) because of 2 x I/O. And the MSB is on SI/SIO1 which is different from 1 x I/O condition. Note 2: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first. Note 3: It is not allowed to adopt any other code which is not in the above command definition table. P/N: PM1431 REV. 1.1, SEP. 09, 2010 16 MX25L3255D (1) Write Enable (WREN) The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP, BLOCKP, PLOCK, UNLOCK, CP, SE, BE, and CE which are intended to change the device content, should be set every time after the WREN instruction setting the WEL bit. The sequence of issuing WREN instruction is: CS# goes low→ sending WREN instruction code→ CS# goes high. (see Figure 9) (2) Write Disable (WRDI) The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit. The sequence of issuing WRDI instruction is: CS# goes low→ sending WRDI instruction code→ CS# goes high. (see Figure 10) The WEL bit is reset by following situations: - Power-up - Write Disable (WRDI) instruction completion - Page Program (PP) instruction completion - Quad Page Program (4PP) instruction completion - Sector Erase (SE) instruction completion - Block Erase (BE) instruction completion - Chip Erase (CE) instruction completion - Continuously program mode (CP) instruction completion - Block Write Lock Protection (BLOCKP) instruction completion - Chip Unprotect (UNLOCK) instruction completion (3) Read Identification (RDID) The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC Manufacturer ID is C2(hex), the memory type ID is 9E (hex) as the first-byte device ID, and the individual device ID of second-byte ID are listed as table of "ID Definitions". (see table 5) The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code → 24-bits ID data out on SO→ to end RDID operation can use CS# to high at any time during data out. (see Figure 11.) While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage. (4) Read Status Register (RDSR) The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in progress. The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register data out on SO (see Figure 12) The definition of the status register bits is as below: P/N: PM1431 REV. 1.1, SEP. 09, 2010 17 MX25L3255D WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. The program/erase command will be ignored and not affect value of WEL bit if it is applied to a protected memory area. Status Register bit7 bit6 bit5 bit4 bit3 bit2 x x x x x x reserved reserved reserved reserved reserved reserved Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit bit1 bit0 WEL WIP (write enable (write in latch) progress bit) 1=write 1=write enable operation 0=not write 0=not in write enable operation volatile bit volatile bit (5) Block Write Lock Protection (BLOCKP) The BLOCKP instruction is for write protection a specified block of memory, using A23-A16 (A15-A0 don't care) address bits to assign a 64Kbyte block to be protected as read only. This feature allows user to stop protecting the entire block through the chip unprotect command (UNLOCK). The WREN (Write Enable) instruction is required before issuing BLOCKP instruction. The sequence of issuing BLOCKP instruction is: CS# goes low→send BLOCKP (E2h) instruction → send 3 address bytes assign one block to be protected on SI pin → CS# goes high. (see Figure 13) The CS# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not be executed. (6) Read Block Write Lock status (RDBLOCK) The RDPLOCK instruction is for reading the status of permanent lock of a specified block, using A23-A16 (A15-A0 =0) address bits to assign a 64Kbyte block and read permanent lock status bit which the first byte of Read-out cycle. The first byte data out DQ0 is"1" to indicate that this block has be locked permanently, that user can read only but cannot write, program or erase this block permanently. The first byte data out DQ0 is "0" to indicate that this block hasn't be protected, and user can read and write this block. The sequence of issuing RDBLOCK instruction is: CS# goes low→ send RDBLOCK (FBh) instruction→ send 3 address bytes to assign one block on SI pin→ read block's protection lock status bit on SO pin → CS# goes high. (see Figure 16) P/N: PM1431 REV. 1.1, SEP. 09, 2010 18 MX25L3255D (7) Chip Unprotect (UNLOCK) The UNLOCK instruction is for disabling the lock protection block of the whole chip. The WREN (Write Enable) instruction is required before issuing UNLOCK instruction. The sequence of issuing UNLOCK instruction is: CS# goes low → send UNLOCK (F3h) instruction → CS# goes high. (see Figure 14) The CS# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not be executed. (8) Read Data Bytes (READ) The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing READ instruction is: CS# goes low→ sending READ instruction code→ 3-byte address on SI→ data out on SO→to end READ operation can use CS# to high at any time during data out. (see Figure 15) (9) Read Data Bytes at Higher Speed (FAST_READ) The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ instruction code-> 3-byte address on SI→ 1-dummy byte (default) address on SI→data out on SO→ to end FAST_READ operation can use CS# to high at any time during data out. (see Figure 17) While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. (10) 2 x I/O Read Mode (2READ) The 2READ instruction enable double throughput of Serial Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits(interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit. The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 24-bit address interleave on SIO1 & SIO0→ 4-bit dummy cycle on SIO1 & SIO0→data out interleave on SIO1 & SIO0→ to end 2READ operation can use CS# to high at any time during data out (see Figure 18 for 2 x I/O Read Mode Timing Waveform). While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. P/N: PM1431 REV. 1.1, SEP. 09, 2010 19 MX25L3255D (11) Dual Read Mode (DREAD) The DREAD instruction enable double throughput of Serial Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits(interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruction, the following data out will perform as 2-bit instead of previous 1-bit. The sequence of issuing DREAD instruction is: CS# goes low→ sending DREAD instruction→3-byte address on SIO0→ 8-bit dummy cycle on SIO0→ data out interleave on SIO1 & SIO0→ to end 2READ operation can use CS# to high at any time during data out (see Figure 19 for Dual Read Mode Timing Waveform). While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. (12) 4 x I/O Read Mode (4READ) The 4READ instruction enable quad throughput of Serial Flash in read mode. The address is latched on rising edge of SCLK, and data of every four bits(interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit. The sequence of issuing 4READ instruction is: CS# goes low→ sending 4READ instruction→ 24-bit address interleave on SIO3, SIO2, SIO1 & SIO0→ 6 dummy cycles → data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end 4READ operation can use CS# to high at any time during data out (see Figure 20 for 4 x I/O Read Mode Timing Waveform). Another sequence of issuing 4 READ instruction especially useful in random access is : CS# goes low→ sending 4 READ instruction→ 3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 → performance enhance toggling bit P[7:0]→ 4 dummy cycles → data out still CS# goes high → CS# goes low (reduce 4 Read instruction) → 24-bit random access address (see Figure 21 for 4x I/O read enhance performance mode timing waveform). In the performance-enhancing mode, P[7:4] must be toggling with P[3:0] ; likewise P[7:0]=A5h,5Ah,F0h or 0Fh can make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0]; likewise P[7:0]=FFh,00h,AAh or 55h. And afterwards CS# is raised or issuing FF command(CS# goes high -> CS# goes low -> sending 0xFF -> CS# goes high) instead of no toggling,the system then will escape from performance enhance mode and return to normal opertaion.In these cases,tSHSL=15ns(min) will be specified. While Program/Erase cycle is in progress, 4READ instruction is rejected without any impact on the Program/Erase current cycle. (13) Quad Read Mode (QREAD) The QREAD instruction enable quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status Register must be set to "1" before seding the QREAD instruction.The address is latched on rising edge of SCLK, and data of every four bits(interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ. The first address byte can be at any location. The address is automatically increased to the next higher address P/N: PM1431 REV. 1.1, SEP. 09, 2010 20 MX25L3255D after each byte data is shifted out, so the whole memory can be read out at a single QREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing QREAD instruction, the following data out will perform as 4-bit instead of previous 1-bit. The sequence of issuing QREAD instruction is: CS# goes low→ sending QREAD instruction→ 24-bit address on SIO0→ 8 dummy cycles → data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end QREAD operation can use CS# to high at any time during data out (see Figure 22 for Quad Read Mode Timing Waveform). While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. (14) Sector Erase (SE) The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector (see table 3) is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. Address bits [Am-A12] (Am is the most significant address) select the sector address. The sequence of issuing SE instruction is: CS# goes low → sending SE instruction code→ 3-byte address on SI → CS# goes high. (see Figure 26) The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the sector is protected, the Sector Erase (SE) instruction will not be executed on the sector. (15) Block Erase (BE) The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 64K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (see table 3) is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing BE instruction is: CS# goes low →sending BE instruction code→ 3-byte address on SI →CS# goes high. (see Figure 27) The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the block is protected, the Block Erase (BE) instruction will not be executed on the block. (16) Chip Erase (CE) The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must go P/N: PM1431 REV. 1.1, SEP. 09, 2010 21 MX25L3255D high exactly at the byte boundary, otherwise the instruction will be rejected and not executed. The sequence of issuing CE instruction is: CS# goes low→ sending CE instruction code→ CS# goes high. (see Figure 28) The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. (17) Page Program (PP) The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device programs only the last 256 data bytes sent to the device. If the entire 256 data bytes are going to be programmed, A7A0 (The eight least significant address bits) should be set to 0. If the eight least significant address bits (A7-A0) are not all 0, all transmitted data going beyond the end of the current page are programmed from the start address of the same page (from the address A7-A0 are all 0). If more than 256 bytes are sent to the device, the data of the last 256-byte is programmed at the request page and previous data will be disregarded. If less than 256 bytes are sent to the device, the data is programmed at the requested address of the page without effect on other address of the same page. The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→3-byte address on SI→ at least 1-byte on data on SI→ CS# goes high. (see Figure 23) The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte boundary (the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed. The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected, the Page Program (PP) instruction will not be executed. (18) 4 x I/O Page Program (4PP) The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit. The Quad Page Programming takes four pins: SIO0, SIO1, SIO2, and SIO3 as address and data input, which can improve programer performance and the effectiveness of application of lower clock less than 20MHz. For system with faster clock, the Quad page program cannot provide more actual favors, because the required internal page program time is far more than the time data flows in. Therefore, we suggest that while executing this command (especially during sending data), user can slow the clock speed down to 20MHz below. The other function descriptions are as same as standard page program. The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on SIO[3:0]→ at least 1-byte on data on SIO[3:0]→ CS# goes high. (see Figure 24) (19) Continuously program mode (CP mode) The CP mode may enhance program performance by automatically increasing address to the next higher address after each byte data has been programmed. P/N: PM1431 REV. 1.1, SEP. 09, 2010 22 MX25L3255D The Continuously program (CP) instruction is for multiple byte program to Flash. A write Enable (WREN) instruction must execute to set the Write Enable Latch(WEL) bit before sending the Continuously program (CP) instruction. CS# requires to go high before CP instruction is executing. After CP instruction and address input, two bytes of data is input sequentially from MSB(bit7) to LSB(bit0). The first byte data will be programmed to the initial address range with A0=0 and second byte data with A0=1. If only one byte data is input, the CP mode will not process. If more than two bytes data are input, the additional data will be ignored and only two byte data are valid. The CP program instruction will be ignored and not affect the WEL bit if it is applied to a protected memory area. Any byte to be programmed should be in the erase state (FF) first. It will not roll over during the CP mode, once the last unprotected address has been reached, the chip will exit CP mode and reset write Enable Latch bit (WEL) as "0" and CP mode bit as "0". Please check the WIP bit status if it is not in write progress before entering next valid instruction. During CP mode, the valid commands are CP command (AD hex), WRDI command (04 hex), RDSR command (05 hex), and RDSCUR command (2B hex). And the WRDI command is valid after completion of a CP programming cycle, which means the WIP bit=0. The sequence of issuing CP instruction is : CS# high to low→ sending CP instruction code→ 3-byte address on SI-> Data Byte on SI→CS# goes high to low→sending CP instruction......→ last desired byte programmed or sending Write Disable (WRDI) instruction to end CP mode→ sending RDSR instruction to verify if CP mode is ended. (see Figure 25 of CP mode timing waveform) Three methods to detect the completion of a program cycle during CP mode: 1) Software method-I: by checking WIP bit of Status Register to detect the completion of CP mode. 2) Software method-II: by waiting for a tBP time out to determine if it may load next valid command or not. 3) Hardware method: by writing ESRY (enable SO to output RY/BY#) instruction to detect the completion of a program cycle during CP mode. The ESRY instruction must be executed before CP mode execution. Once it is enable in CP mode, the CS# goes low will drive out the RY/BY# status on SO, "0" indicates busy stage, "1" indicates ready stage, SO pin outputs tri-state if CS# goes high. DSRY (disable SO to output RY/BY#) instruction to disable the SO to output RY/BY# and return to status register data output during CP mode. Please note that the ESRY/DSRY command are not accepted unless the completion of CP mode. (20) Deep Power-down (DP) The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to entering the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep power-down mode. It's different from Standby mode. The sequence of issuing DP instruction is: CS# goes low→sending DP instruction code→ CS# goes high. (see Figure 29) Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP) and Read Electronic Signature (RES) instruction. (those instructions allow the ID being reading out). When Powerdown, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2. (21) Release from Deep Power-down (RDP), Read Electronic Signature (RES) The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the P/N: PM1431 REV. 1.1, SEP. 09, 2010 23 MX25L3255D Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2(max), as specified in Table 8. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new design, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/ write cycle in progress. The sequence is shown as Figure 30, 31. The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction. The RDP instruction is for releasing from Deep Power Down Mode. (22) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4) The REMS, REMS2 & REMS4 instruction is an alternative to the Release from Power-down/Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. The REMS, REMS2 & REMS4 instruction is very similar to the Release from Power-down/Device ID instruction. The instruction is initiated by driving the CS# pin low and shift the instruction code "90h" or "EFh" or "DFh"followed by two dummy bytes and one bytes address (A7~A0). After which, the Manufacturer ID for MXIC (C2h) and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 32. The Device ID values are listed in Table of ID Definitions. If the one-byte address is initially set to 01h, then the device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high. Table 5. ID Definitions RDID Command manufacturer ID C2 memory type 9E electronic ID 9E device ID 9E RES Command REMS/REMS2/REMS4/ Command manufacturer ID C2 P/N: PM1431 memory density 16 REV. 1.1, SEP. 09, 2010 24 MX25L3255D (23) Enter Secured OTP (ENSO) The ENSO instruction is for entering the additional 4K-bit secured OTP mode. The additional 4K-bit secured OTP is independent from main array, which may use to store unique serial number for system identifier. After entering the Secured OTP mode, and then follow standard read or program, procedure to read out the data or update data. The Secured OTP data cannot be updated again once it is lock-down. The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP mode→ CS# goes high. Please note that WRSCUR commands is not acceptable during the access of secure OTP region, once security OTP is lock down, only read related commands are valid. (24) Exit Secured OTP (EXSO) The EXSO instruction is for exiting the additional 4K-bit secured OTP mode. The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP mode→ CS# goes high. (25) Read Security Register (RDSCUR) The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read at any time (even in program/erase/write status register/write parameter register/write security register condition) and continuously. The sequence of issuing RDSCUR instruction is : CS# goes low→ send ing RDSCUR instruction → Security Register data out on SO→ CS# goes high. The definition of the Security Register bits is as below: Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory before ex- factory or not. When it is "0", it indicates non- factory lock; "1" indicates factory- lock. Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for customer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 4K-bit Secured OTP area cannot be update any more. While it is in 4K-bit secured OTP mode, array access is not allowed. Continuously Program Mode (CP mode) bit. The Continuously Program Mode bit indicates the status of CP mode, "0" indicates not in CP mode; "1" indicates in CP mode. P/N: PM1431 REV. 1.1, SEP. 09, 2010 25 MX25L3255D Table 6. Security Register Definition bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 x x x Continuously Program mode (CP mode) x x LDSO (indicate if lock-down Secured OTP indicator bit reserved reserved 0 = not lock0 = non-factory down lock 1 = lock-down 1 = factory (cannot lock program/erase OTP) volatile bit volatile bit non-volatile bit non-volatile bit reserved reserved reserved 0=normal Program mode 1=CP mode (default=0) volatile bit volatile bit volatile bit volatile bit (26) Write Security Register (WRSCUR) The WRSCUR instruction is for changing the values of Security Register Bits. The WREN instruction is not required before sending WRSCUR instruction. The WRSCUR instruction may change the values of bit1 (LDSO bit) for customer to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area cannot be updated any more. The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high. The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. P/N: PM1431 REV. 1.1, SEP. 09, 2010 26 MX25L3255D POWER-ON STATE The device is at below states when power-up: - Standby mode ( please note it is not deep power-down mode) - Write Enable Latch (WEL) bit is reset The device must not be selected during power-up and power-down stage unless the VCC achieves below correct level: - VCC minimum at power-up stage and then after a delay of tVSL - GND at power-down Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level. An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change during power up state. For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The read, write, erase, and program command should be sent after the time delay: - tVSL after VCC reached VCC minimum level The device can accept read command after VCC reached VCC minimum and a time delay of tVSL. Please refer to the figure of "power-up timing". Note: - To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended. (generally around 0.1uF) P/N: PM1431 REV. 1.1, SEP. 09, 2010 27 MX25L3255D ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS RATING VALUE Ambient Operating Temperature Industrial grade -40°C to 85°C Storage Temperature -65°C to 150°C Applied Input Voltage -0.5V to 4.6V Applied Output Voltage -0.5V to 4.6V VCC to Ground Potential -0.5V to 4.6V NOTICE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. 2. Specifications contained within the following tables are subject to change. 3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see Figure 2, 3. Figure 3. Maximum Positive Overshoot Waveform Figure 2.Maximum Negative Overshoot Waveform 20ns 20ns 20ns Vss Vcc + 2.0V Vss-2.0V Vcc 20ns 20ns 20ns CAPACITANCE TA = 25°C, f = 1.0 MHz SYMBOL PARAMETER CIN COUT MIN. TYP MAX. UNIT Input Capacitance 6 pF VIN = 0V Output Capacitance 8 pF VOUT = 0V P/N: PM1431 CONDITIONS REV. 1.1, SEP. 09, 2010 28 MX25L3255D Figure 4. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL Input timing referance level 0.8VCC 0.2VCC 0.7VCC 0.3VCC Output timing referance level AC Measurement Level 0.5VCC Note: Input pulse rise and fall time are