MX25L512EMI-10G

MX25L512E MX25L512E DATASHEET P/N: PM1669 1 REV. 1.1, FEB. 10, 2012 MX25L512E Contents FEATURES................................................................................................................................................................... 4 GENERAL........................................................................................................................................................... 4 PERFORMANCE................................................................................................................................................ 4 SOFTWARE FEATURES.................................................................................................................................... 4 HARDWARE FEATURES.................................................................................................................................... 5 GENERAL DESCRIPTION.......................................................................................................................................... 5 PIN CONFIGURATIONS............................................................................................................................................... 6 8-PIN SOP (150mil) ........................................................................................................................................... 6 8-PIN TSSOP (173mil) ....................................................................................................................................... 6 8-LAND USON (2x3mm) .................................................................................................................................... 6 PIN DESCRIPTION....................................................................................................................................................... 6 BLOCK DIAGRAM........................................................................................................................................................ 7 DATA PROTECTION..................................................................................................................................................... 8 Table 1. Protected Area Sizes............................................................................................................................. 9 HOLD FEATURE........................................................................................................................................................... 9 Figure 1. Hold Condition Operation . .................................................................................................................. 9 Table 2. Command Definition............................................................................................................................ 10 Table 3. Memory Organization ......................................................................................................................... 11 DEVICE OPERATION................................................................................................................................................. 11 Figure 2. Serial Modes Supported.................................................................................................................... 11 COMMAND DESCRIPTION........................................................................................................................................ 12 (1) Write Enable (WREN).................................................................................................................................. 12 (2) Write Disable (WRDI)................................................................................................................................... 12 (3) Read Identification (RDID)........................................................................................................................... 12 (4) Read Status Register (RDSR)..................................................................................................................... 13 Status Register.................................................................................................................................................. 13 (5) Write Status Register (WRSR)..................................................................................................................... 14 Table 4. Protection Modes................................................................................................................................. 14 (6) Read Data Bytes (READ)............................................................................................................................ 15 (7) Read Data Bytes at Higher Speed (FAST_READ)...................................................................................... 15 (9) Sector Erase (SE)........................................................................................................................................ 15 (10) Block Erase (BE)....................................................................................................................................... 16 (11) Chip Erase (CE)......................................................................................................................................... 16 (12) Page Program (PP)................................................................................................................................... 16 (13) Deep Power-down (DP)............................................................................................................................. 17 (14) Release from Deep Power-down (RDP), Read Electronic Signature (RES) ............................................ 17 (15) Read Electronic Manufacturer ID & Device ID (REMS)............................................................................. 18 Table of ID Definitions....................................................................................................................................... 18 (16) Read SFDP Mode (RDSFDP).................................................................................................................... 19 Read Serial Flash Discoverable Parameter (RDSFDP) Sequence................................................................... 19 Table a. Signature and Parameter Identification Data Values .......................................................................... 20 Table b. Parameter Table (0): JEDEC Flash Parameter Tables........................................................................ 21 Table c. Parameter Table (1): Macronix Flash Parameter Tables...................................................................... 23 P/N: PM1669 2 REV. 1.1, FEB. 10, 2012 MX25L512E POWER-ON STATE.................................................................................................................................................... 25 ELECTRICAL SPECIFICATIONS............................................................................................................................... 26 ABSOLUTE MAXIMUM RATINGS.................................................................................................................... 26 Figure 3.Maximum Negative Overshoot Waveform.......................................................................................... 26 CAPACITANCE TA = 25°C, f = 1.0 MHz............................................................................................................ 26 Figure 4. Maximum Positive Overshoot Waveform........................................................................................... 26 Figure 5. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL............................................................. 27 Figure 6. OUTPUT LOADING.......................................................................................................................... 27 Table 5. DC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V) .28 Table 6. AC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V) .29 Table 7. Power-Up Timing................................................................................................................................. 30 INITIAL DELIVERY STATE............................................................................................................................... 30 Figure 7. Serial Input Timing............................................................................................................................. 30 Figure 8. Output Timing..................................................................................................................................... 30 Figure 9. Hold Timing........................................................................................................................................ 31 Figure 10. WP# Disable Setup and Hold Timing during WRSR when SRWD=1.............................................. 31 Figure 11. Write Enable (WREN) Sequence (Command 06)............................................................................ 32 Figure 12. Write Disable (WRDI) Sequence (Command 04)............................................................................. 32 Figure 13. Read Identification (RDID) Sequence (Command 9F)..................................................................... 32 Figure 14. Read Status Register (RDSR) Sequence (Command 05)............................................................... 33 Figure 15. Write Status Register (WRSR) Sequence (Command 01).............................................................. 33 Figure 16. Read Data Bytes (READ) Sequence (Command 03)..................................................................... 33 Figure 17. Read at Higher Speed (FAST_READ) Sequence (Command 0B)................................................. 34 Figure 18. Dual Output Read Mode Sequence (Command 3B)........................................................................ 34 Figure 19. Page Program (PP) Sequence (Command 02).............................................................................. 35 Figure 20. Sector Erase (SE) Sequence (Command 20)................................................................................. 36 Figure 21. Block Erase (BE) Sequence (Command 52 or D8)......................................................................... 36 Figure 22. Chip Erase (CE) Sequence (Command 60 or C7).......................................................................... 37 Figure 23. Deep Power-down (DP) Sequence (Command B9)....................................................................... 37 Figure 24. Read Electronic Signature (RES) Sequence (Command AB).......................................................... 37 Figure 25. Release from Deep Power-down (RDP) Sequence (Command AB).............................................. 38 Figure 26. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90)............................ 38 Figure 27. Power-up Timing.............................................................................................................................. 39 RECOMMENDED OPERATING CONDITIONS.......................................................................................................... 40 Figure 28. AC Timing at Device Power-Up........................................................................................................ 40 Figure 29. Power-Down Sequence................................................................................................................... 41 ERASE AND PROGRAMMING PERFORMANCE..................................................................................................... 42 DATA RETENTION..................................................................................................................................................... 42 LATCH-UP CHARACTERISTICS............................................................................................................................... 42 ORDERING INFORMATION....................................................................................................................................... 43 PART NAME DESCRIPTION...................................................................................................................................... 44 PACKAGE INFORMATION......................................................................................................................................... 45 REVISION HISTORY ................................................................................................................................................. 48 P/N: PM1669 3 REV. 1.1, FEB. 10, 2012 MX25L512E 512K-BIT [x 1/x 2] CMOS SERIAL FLASH FEATURES GENERAL • Serial Peripheral Interface compatible -- Mode 0 and Mode 3 • 524,288 x 1 bit structure or 262,144 x 2 bits (Dual Output mode) Structure • 16 Equal Sectors with 4K byte each - Any Sector can be erased individually • Single Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations • Latch-up protected to 100mA from -1V to Vcc +1V PERFORMANCE • High Performance - Fast access time: 104MHz serial clock - Serial clock of Dual Output mode: 80MHz - Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page) - Byte program time: 9us - Fast erase time: 60ms(typ.)/sector (4K-byte per sector) ; 0.7s(typ.) and 2s(max.)/chip • Low Power Consumption - Low active read current: 12mA(max.) at 104MHz and 4mA(max.) at 33MHz - Low active programming current: 20mA (max.) - Low active sector erase current: 15mA (max.) - Low standby current: 25uA (max.) - Deep power-down mode 5uA (typical) • Minimum 100,000 erase/program cycles • 20 years data retention SOFTWARE FEATURES • Input Data Format - 1-byte Command code • Block Lock protection - The BP0~BP1 status bit defines the size of the area to be software protected against Program and Erase instructions. • Auto Erase and Auto Program Algorithm - Automatically erases and verifies data at selected sector - Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (Any page to be programed should have page in the erased state first) • Status Register Feature • Electronic Identification - JEDEC 2-byte Device ID - RES command, 1-byte Device ID • Support Serial Flash Discoverable Parameters (SFDP) mode P/N: PM1669 4 REV. 1.1, FEB. 10, 2012 MX25L512E HARDWARE FEATURES • SCLK Input - Serial clock input • SI/SIO0 - Serial Data Input or Serial Data Output for Dual output mode • SO/SIO1 - Serial Data Output or Serial Data Output for Dual output mode • WP# pin - Hardware write protection • HOLD# pin - pause the chip without diselecting the chip • PACKAGE - 8-pin SOP (150mil) - 8-USON (2x3mm) - 8-pin TSSOP (173mil) - All devices are RoHS Compliant GENERAL DESCRIPTION MX25L512E is a CMOS 524,288 bit serial Flash memory, which is configured as 65,536 x 8 internally. MX25L512E features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input. MX25L512E provides sequential read operation on whole chip. After program/erase command is issued, auto program/erase algorithms which program/erase and verify the specified page or sector/block locations will be executed. Program command is executed on page (256 bytes) basis, and erase command is executes on chip or sector (4K-bytes). To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. When the device is not in operation and CS# is high, it is put in standby mode and draws less than 25uA DC current. The MX25L512E utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles. P/N: PM1669 5 REV. 1.1, FEB. 10, 2012 MX25L512E PIN CONFIGURATIONS 8-PIN SOP (150mil) CS# SO/SIO1 WP# GND 1 2 3 4 8-LAND USON (2x3mm) 8 7 6 5 CS# SO/SIO1 WP# GND VCC HOLD# SCLK SI/SIO0 8-PIN TSSOP (173mil) CS# SO/SIO1 WP# GND P/N: PM1669 1 2 3 4 1 2 3 4 8 7 6 5 VCC HOLD# SCLK SI/SIO0 PIN DESCRIPTION 8 7 6 5 SYMBOL DESCRIPTION CS# Chip Select Serial Data Input (for 1 x I/O)/ Serial Data SI/SIO0 Input & Output (for Dual output mode) Serial Data Output (for 1 x I/O)/ Serial Data SO/SIO1 Input & Output (for Dual output mode) SCLK Clock Input Hold, to pause the device without HOLD# deselecting the device WP# Write Protection VCC + 3.3V Power Supply GND Ground VCC HOLD# SCLK SI/SIO0 6 REV. 1.1, FEB. 10, 2012 MX25L512E BLOCK DIAGRAM X-Decoder Address Generator Memory Array Page Buffer SI Data Register Y-Decoder SRAM Buffer CS# Mode Logic Sense Amplifier State Machine Output Buffer HV Generator SO SCLK P/N: PM1669 Clock Generator 7 REV. 1.1, FEB. 10, 2012 MX25L512E DATA PROTECTION MX25L512E is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the standby mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise. • Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary. • Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other command to change data. The WEL bit will return to reset stage under following situation: - Power-up - Write Disable (WRDI) command completion - Write Status Register (WRSR) command completion - Page Program (PP) command completion - Sector Erase (SE) command completion - Block Erase (BE) command completion - Chip Erase (CE) command completion • Software Protection Mode (SPM): by using BP0-BP1 bits to set the part of Flash protected from data change. • Hardware Protection Mode (HPM): by using WP# going low to protect the BP0-BP1 bits and SRWD bit from data change. • Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing all commands except Release from Deep Power-down mode command (RDP) and Read Electronic Signature command (RES). P/N: PM1669 8 REV. 1.1, FEB. 10, 2012 MX25L512E Table 1. Protected Area Sizes BP1 0 0 1 1 Status bit BP0 0 1 0 1 Protect level 512b 0 (none) 1 (All) 2 (All) 3 (All) None All All All HOLD FEATURE HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the operation of write status register, programming, or erasing in progress. The operation of HOLD requires Chip Select(CS#) keeping low and starts on falling edge of HOLD# pin signal while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Serial Clock(SCLK) signal is being low(if Serial Clock signal is not being low, HOLD operation will not end until Serial Clock being low), see Figure 1. Figure 1. Hold Condition Operation CS# SCLK HOLD# Hold Condition (standard) Hold Condition (non-standard) The Serial Data Output (SO) is high impedance, both Serial Data Input (SI) and Serial Clock (SCLK) are don't care during the HOLD operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and CS# must be at low. P/N: PM1669 9 REV. 1.1, FEB. 10, 2012 MX25L512E Table 2. Command Definition RDID (Read Identification) 9F (hex) RDSR (Read Status Register) 05 (hex) WRSR (Write Status Register) 01 (hex) sets the (WEL) resets the (WEL) outputs write enable write enable manufacturer latch bit latch bit ID and 2-byte device ID to read out the status register to write new n bytes read out values to the until CS# goes status register high COMMAND WREN WRDI (byte) (Write Enable) (Write Disable) 1st 2nd 3rd 4th 5th Action 06 (hex) 04 (hex) COMMAND (byte) Fast Read (Fast Read Data) RDSFDP (Read SFDP) DREAD (Dual Output mode) 1st 0B (hex) 5A (hex) 3B (hex) 20 (hex) 52 or D8 (hex) 2nd 3rd 4th 5th AD1 AD2 AD3 Dummy n bytes read out until CS# goes high AD1 AD2 AD3 Dummy Read SFDP mode AD1 AD2 AD3 AD1 AD2 AD3 AD1 AD2 AD3 COMMAND (byte) PP (Page Program) DP (Deep Powerdown) RDP (Release from Deep Powerdown) 1st 02 (hex) B9 (hex) AB (hex) 2nd 3rd 4th 5th AD1 AD2 AD3 Action Action to program the selected page enters deep power down mode BE SE (Block Erase) (Sector Erase) (2) n bytes read out to erase the until CS# goes selected sector high release from deep power down mode to erase the selected block READ (Read Data) 03 (hex) AD1 AD2 AD3 CE (Chip Erase) 60 or C7 (hex) to erase the whole chip REMS RES (Read (Read Electronic Electronic ID) Manufacturer & Device ID) AB (hex) 90 (hex) x x x x x ADD(1) to read out Output the 1-byte Device manufacturer ID ID and device ID (1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first. (2) BE command may erase whole 512Kb chip. (3) It is not recommended to adopt any other code which is not in the command definition table above. P/N: PM1669 10 REV. 1.1, FEB. 10, 2012 MX25L512E Table 3. Memory Organization Sector 15 : 3 2 1 0 Address Range 00F000h 00FFFFh : : 003000h 003FFFh 002000h 002FFFh 001000h 001FFFh 000000h 000FFFh DEVICE OPERATION 1. Before a command is issued, status register should be checked to ensure the device is ready for the intended operation. 2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z. The CS# falling time needs to follow tCHCL spec. (Please refer to Table 6. AC CHARACTERISTICS) 3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next CS# rising edge. The CS# rising time needs to follow tCLCH spec. (Please refer to Table 6. AC CHARACTERISTICS) 4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as Figure 2. 5. For the following instructions: RDID, RDSR, READ, FAST_READ, RDSFDP, DREAD, RES and REMS the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE, CE, PP, RDP and DP the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglected and not affect the current operation of Write Status Register, Program, and Erase. Figure 2. Serial Modes Supported CPOL CPHA shift in (Serial mode 0) 0 0 SCLK (Serial mode 3) 1 1 SCLK SI shift out MSB SO MSB Note: CPOL indicates clock polarity of Serial master: -CPOL=1 for SCLK high while idle, -CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is supported. P/N: PM1669 11 REV. 1.1, FEB. 10, 2012 MX25L512E COMMAND DESCRIPTION (1) Write Enable (WREN) The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, SE, BE, CE, and WRSR, which are intended to change the device content, should be set every time after the WREN instruction setting the WEL bit. The sequence of issuing WREN instruction is: CS# goes low→ sending WREN instruction code→ CS# goes high. (see Figure 11) (2) Write Disable (WRDI) The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit. The sequence of issuing WRDI instruction is: CS# goes low→ sending WRDI instruction code→ CS# goes high. (see Figure 12) The WEL bit is reset by following situations: - Power-up - Write Disable (WRDI) instruction completion - Write Status Register (WRSR) instruction completion - Page Program (PP) instruction completion - Sector Erase (SE) instruction completion - Block Erase (BE) instruction completion - Chip Erase (CE) instruction completion (3) Read Identification (RDID) RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC Manufacturer ID is C2(hex), the memory type ID is 20(hex) as the first-byte device ID, and the individual device ID of second-byte ID is as followings: 10(hex) for MX25L512E. The sequence of issuing RDID instruction is: CS# goes low→sending RDID instruction code→24-bits ID data out on SO→to end RDID operation can use CS# to high at any time during data out. (see Figure. 13) While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage. P/N: PM1669 12 REV. 1.1, FEB. 10, 2012 MX25L512E (4) Read Status Register (RDSR) The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in progress. The sequence of issuing RDSR instruction is: CS# goes low→sending RDSR instruction code→Status Register data out on SO (see Figure. 14) The definition of the status register bits is as below: WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. BP1, BP0 bits. The Block Protect (BP1, BP0) bits, non-volatile bits, indicate the protected area(as defined in table 1) of the device to against the program/erase instruction without hardware protection mode being set. To write the Block Protect (BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed) SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection (WP#) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP# pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP1, BP0) are read only. Status Register bit7 bit6 bit5 bit4 SRWD (status register write protect) 0 0 0 1=status register write disable bit3 BP1 (level of protected block) bit2 BP0 (level of protected block) (Note 1) (Note 1) bit1 bit0 WEL WIP (write enable (write in latch) progress bit) 1=write 1=write enable operation 0=not write 0=not in write enable operation Notes: 1. See the table "Protected Area Sizes". P/N: PM1669 13 REV. 1.1, FEB. 10, 2012 MX25L512E (5) Write Status Register (WRSR) The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP1, BP0) bits to define the protected area of memory (as shown in table 1). The WRSR also can set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#) pin signal. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered. The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register data on SI→ CS# goes high. (see Figure 15) The WRSR instruction has no effect on b6, b5, b4, b1, b0 of the status register. The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset. Table 4. Protection Modes Mode Software protection mode (SPM) Hardware protection mode (HPM) Status register condition WP# and SRWD bit status Memory Status register can be written in (WEL bit is set to "1") and the SRWD, BP0-BP1 bits can be changed. WP#=1 and SRWD bit=0, or WP#=0 and SRWD bit=0, or WP#=1 and SRWD=1 The protected area cannot be programmed or erased. The SRWD, BP0-BP1 of status register bits cannot be changed. WP#=0, SRWD bit=1 The protected area cannot be programmed or erased. Note: 1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 1. As the table above showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM). Software Protected Mode (SPM): - When SRWD bit=0, no matter WP# is low or high, the WREN instruction may set the WEL bit and can change the values of SRWD, BP1, BP0. The protected area, which is defined by BP1, BP0, is at software protected mode (SPM). - When SRWD bit=1 and WP# is high, the WREN instruction may set the WEL bit can change the values of SRWD, BP1, BP0. The protected area, which is defined by BP1, BP0, is at software protected mode (SPM) Note: If SRWD bit=1 but WP# is low, it is impossible to write the Status Register even if the WEL bit has previously been set. It is rejected to write the Status Register and not be executed. Hardware Protected Mode (HPM): - When SRWD bit=1, and then WP# is low (or WP# is low before SRWD bit=1), it enters the hardware protected mode (HPM). The data of the protected area is protected by software protected mode by BP1, BP0 and hardware protected mode by the WP# to against data modification. Note: to exit the hardware protected mode, it requires WP# driving high once the hardware protected mode is entered. If the WP# pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via BP1, BP0. P/N: PM1669 14 REV. 1.1, FEB. 10, 2012 MX25L512E (6) Read Data Bytes (READ) The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing READ instruction is: CS# goes low→ sending READ instruction code→ 3-byte address on SI→ data out on SO→ to end READ operation can use CS# to high at any time during data out. (see Figure. 16) (7) Read Data Bytes at Higher Speed (FAST_READ) The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ instruction code→ 3-byte address on SI→ 1-dummy byte address on SI→data out on SO→ to end FAST_READ operation can use CS# to high at any time during data out. (see Figure. 17) While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. (8) Dual Output Mode (DREAD) The DREAD instruction enable double throughput of Serial Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits(interleave on 1I/2O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruction, the following data out will perform as 2-bit instead of previous 1-bit. The sequence is shown as Figure 18. While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. The DREAD only performs read operation. Program/Erase /Read ID/Read status....operations do not support DREAD throughputs. (9) Sector Erase (SE) The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector (see table 3) is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. P/N: PM1669 15 REV. 1.1, FEB. 10, 2012 MX25L512E Address bits [Am-A12] (Am is the most significant address) select the sector address. The sequence of issuing SE instruction is: CS# goes low → sending SE instruction code→ 3-byte address on SI → CS# goes high. (see Figure 20) The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked out during the Sector Erase cycle is in progress. The WIP sets 1 during the tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the page. (10) Block Erase (BE) The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (see table 3) is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing BE instruction is: CS# goes low → sending BE instruction code→ 3-byte address on SI → CS# goes high. (see Figure 21) The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the page. (11) Chip Erase (CE) The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). Any address of the sector (see table 3) is a valid address for Chip Erase (CE) instruction. The CS# must go high exactly at the byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing CE instruction is: CS# goes low→ sending CE instruction code→ CS# goes high. (see Figure 22) The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is protected by BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when BP1, BP0 all set to "0". (12) Page Program (PP) The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). If the eight least significant address bits (A7-A0) are not all 0, all transmitted data which goes beyond the end of the current page are programmed from the start address if the same page (from the address whose 8 least significant address bits (A7A0) are all 0). The CS# must keep during the whole Page Program cycle. The CS# must go high exactly at the byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not P/N: PM1669 16 REV. 1.1, FEB. 10, 2012 MX25L512E executed. If more than 256 bytes are sent to the device, the data of the last 256-byte is programmed at the request page and previous data will be disregarded. If less than 256 bytes are sent to the device, the data is programmed at the request address of the page without effect on other address of the same page. The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→ at least 1-byte on data on SI→ CS# goes high. (see Figure 19) The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP1, BP0 bits, the Page Program (PP) instruction will not be executed. (13) Deep Power-down (DP) The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to entering the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep power-down mode. It's different from Standby mode. The sequence of issuing DP instruction is: CS# goes low→ sending DP instruction code→ CS# goes high. (see Figure 22) Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP) and Read Electronic Signature (RES) instruction. (RES instruction to allow the ID been read out). When Powerdown, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2. (14) Release from Deep Power-down (RDP), Read Electronic Signature (RES) The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2(max), as specified in Table 6. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new deisng, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/ write cycle in progress. The sequence is shown as Figure 24 and Figure 25. P/N: PM1669 17 REV. 1.1, FEB. 10, 2012 MX25L512E The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least tRES2(max). Once in the standby mode, the device waits to be selected, so it can be received, be decoded, and be executed instruction. The RDP instruction is for releasing from Deep Power Down Mode. (15) Read Electronic Manufacturer ID & Device ID (REMS) The REMS instruction is an alternative to the Release from Power-down/Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. The REMS instruction is very similar to the Release from Power-down/Device ID instruction. The instruction is initiated by driving the CS# pin low and shift the instruction code "90h" followed by two dummy bytes and one bytes address (A7~A0). After which, the Manufacturer ID for MXIC (C2h) and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 26. The Device ID values are listed in Table of ID Definitions. If the one-byte address is initially set to 01h, then the device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high. Table of ID Definitions RDID Command manufacturer ID C2 memory type 20 electronic ID 05 device ID 05 RES Command REMS Command P/N: PM1669 manufacturer ID C2 18 memory density 10 REV. 1.1, FEB. 10, 2012 MX25L512E (16) Read SFDP Mode (RDSFDP) The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on CFI. The sequence of issuing RDSFDP instruction is CS# goes low→send RDSFDP instruction (5Ah)→send 3 address bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP operation can use CS# to high at any time during data out. SFDP is a standard of JEDEC. JESD216. v1.0. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI SO 24 BIT ADDRESS 23 22 21 5Ah 3 2 1 0 High-Z CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Cycle SI 7 6 5 4 3 2 1 0 DATA OUT 2 DATA OUT 1 SO 7 6 5 3 2 1 0 7 MSB MSB P/N: PM1669 4 19 6 5 4 3 2 1 0 7 MSB REV. 1.1, FEB. 10, 2012 MX25L512E Table a. Signature and Parameter Identification Data Values Description SFDP Signature Comment Fixed: 50444653h Add (h) DW Add Data (h/b) (Byte) (Bit) (Note1) 00h 07:00 53h Data (h) 53h 01h 15:08 46h 46h 02h 23:16 44h 44h 03h 31:24 50h 50h SFDP Minor Revision Number Start from 00h 04h 07:00 00h 00h SFDP Major Revision Number Start from 01h 05h 15:08 01h 01h Number of Parameter Headers Start from 01h 06h 23:16 01h 01h 07h 31:24 FFh FFh 00h: it indicates a JEDEC specified header. 08h 07:00 00h 00h Start from 00h 09h 15:08 00h 00h Start from 01h 0Ah 23:16 01h 01h How many DWORDs in the Parameter table 0Bh 31:24 09h 09h 0Ch 07:00 30h 30h 0Dh 15:08 00h 00h 0Eh 23:16 00h 00h 0Fh 31:24 FFh FFh it indicates Macronix manufacturer ID 10h 07:00 C2h C2h Start from 00h 11h 15:08 00h 00h Start from 01h 12h 23:16 01h 01h How many DWORDs in the Parameter table 13h 31:24 04h 04h 14h 07:00 60h 60h 15h 15:08 00h 00h 16h 23:16 00h 00h 17h 31:24 FFh FFh Unused ID number (JEDEC) Parameter Table Minor Revision Number Parameter Table Major Revision Number Parameter Table Length (in double word) Parameter Table Pointer (PTP) First address of JEDEC Flash Parameter table Unused ID number (Macronix manufacturer ID) Parameter Table Minor Revision Number Parameter Table Major Revision Number Parameter Table Length (in double word) Parameter Table Pointer (PTP) First address of Macronix Flash Parameter table Unused P/N: PM1669 20 REV. 1.1, FEB. 10, 2012 MX25L512E Table b. Parameter Table (0): JEDEC Flash Parameter Tables Description Comment Block/Sector Erase sizes 00: Reserved, 01: 4KB erase, 10: Reserved, 11: not suport 4KB erase Write Granularity Write Enable Instruction Requested for Writing to Volatile Status Registers Add (h) DW Add Data (h/b) (Byte) (Bit) (Note1) 01:00 01b 0: 1Byte, 1: 64Byte or larger 02 1b 0: Nonvolatitle status bit 1: Volatitle status bit (BP status register bit) 03 0b 30h 0: use 50h opcode, 1: use 06h opcode Write Enable Opcode Select for Note: If target flash status register is Writing to Volatile Status Registers nonvolatile, then bits 3 and 4 must be set to 00b. Contains 111b and can never be Unused changed 4KB Erase Opcode 31h E5h 04 0b 07:05 111b 15:08 20h 16 1b 18:17 00b 19 0b 20 0b (1-1-2) Fast Read (Note2) 0=not support 1=support Address Bytes Number used in addressing flash array Double Transfer Rate (DTR) Clocking 00: 3Byte only, 01: 3 or 4Byte, 10: 4Byte only, 11: Reserved (1-2-2) Fast Read 0=not support 1=support (1-4-4) Fast Read 0=not support 1=support 21 0b (1-1-4) Fast Read 0=not support 1=support 22 0b 23 1b 33h 31:24 FFh 37h:34h 31:00 0=not support 1=support 32h Unused Unused Flash Memory Density (1-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states (Note3) Clocks) not support (1-4-4) Fast Read Number of 000b: Mode Bits not support Mode Bits (Note4) 38h (1-4-4) Fast Read Opcode 39h (1-1-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (1-1-4) Fast Read Number of 000b: Mode Bits not support Mode Bits 3Ah (1-1-4) Fast Read Opcode 3Bh P/N: PM1669 21 Data (h) 20h 81h FFh 0007FFFFh 04:00 0 0000b 07:05 000b 15:08 FFh 20:16 0 0000b 23:21 000b 31:24 FFh 00h FFh 00h FFh REV. 1.1, FEB. 10, 2012 MX25L512E Description Comment (1-1-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (1-1-2) Fast Read Number of 000b: Mode Bits not support Mode Bits (1-1-2) Fast Read Opcode Add (h) DW Add Data (h/b) (Byte) (Bit) (Note1) 3Ch 3Dh (1-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (1-2-2) Fast Read Number of 000b: Mode Bits not support Mode Bits 3Eh (1-2-2) Fast Read Opcode 3Fh (2-2-2) Fast Read 0=not support 1=support Unused (4-4-4) Fast Read 0=not support 1=support 40h Unused 04:00 0 1000b 07:05 000b 15:08 3Bh 20:16 0 0000b 23:21 000b 31:24 FFh 00 0b 03:01 111b 04 0b 07:05 111b Data (h) 08h 3Bh 00h FFh EEh Unused 43h:41h 31:08 0xFFh 0xFFh Unused 45h:44h 15:00 0xFFh 0xFFh 20:16 0 000b 23:21 000b (2-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (2-2-2) Fast Read Number of 000b: Mode Bits not support Mode Bits 46h (2-2-2) Fast Read Opcode 47h 31:24 FFh FFh 49h:48h 15:00 0xFFh 0xFFh 20:16 0 0000b 23:21 000b Unused 00h (4-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (4-4-4) Fast Read Number of 000b: Mode Bits not support Mode Bits 4Ah (4-4-4) Fast Read Opcode 4Bh 31:24 FFh FFh 4Ch 07:00 0Ch 0Ch 4Dh 15:08 20h 20h 4Eh 23:16 10h 10h 4Fh 31:24 D8h D8h 50h 07:00 00h 00h 51h 15:08 FFh FFh 52h 23:16 00h 00h 53h 31:24 FFh FFh Sector Type 1 Size Sector/block size = 2^N bytes (Note5) 0x00b: this sector type doesn't exist Sector Type 1 erase Opcode Sector Type 2 Size Sector/block size = 2^N bytes 0x00b: this sector type doesn't exist Sector Type 2 erase Opcode Sector Type 3 Size Sector/block size = 2^N bytes 0x00b: this sector type doesn't exist Sector Type 3 erase Opcode Sector Type 4 Size Sector/block size = 2^N bytes 0x00b: this sector type doesn't exist Sector Type 4 erase Opcode P/N: PM1669 22 00h REV. 1.1, FEB. 10, 2012 MX25L512E Table c. Parameter Table (1): Macronix Flash Parameter Tables Description Comment Add (h) DW Add Data (h/b) (Byte) (Bit) (Note1) Data (h) Vcc Supply Maximum Voltage 2000h=2.000V 2700h=2.700V 3600h=3.600V 61h:60h 07:00 15:08 00h 36h 00h 36h Vcc Supply Minimum Voltage 1650h=1.650V 2250h=2.250V 2350h=2.350V 2700h=2.700V 63h:62h 23:16 31:24 00h 27h 00h 27h HW Reset# pin 0=not support 1=support 00 0b HW Hold# pin 0=not support 1=support 01 1b Deep Power Down Mode 0=not support 1=support 02 1b SW Reset 0=not support 1=support 03 0b SW Reset Opcode Reset Enable (66h) should be issued 65h:64h before Reset command 11:04 1111 1111b (FFh) Program Suspend/Resume 0=not support 1=support 12 0b Erase Suspend/Resume 0=not support 1=support 13 0b 14 1b 15 0b 66h 23:16 FFh FFh 67h 31:24 FFh FFh Unused Wrap-Around Read mode 0=not support 1=support Wrap-Around Read mode Opcode Wrap-Around Read data length 08h:support 8B wrap-around read 16h:8B&16B 32h:8B&16B&32B 64h:8B&16B&32B&64B Individual block lock 0=not support 1=support 00 0b Individual block lock bit (Volatile/Nonvolatile) 0=Volatile 1=Nonvolatile 01 1b 09:02 1111 1111b 10 1b 11 1b Individual block lock Opcode 4FF6h Individual block lock Volatile protect bit default protect status 0=protect 1=unprotect Secured OTP 0=not support 1=support Read Lock 0=not support 1=support 12 0b Permanent Lock 0=not support 1=support 13 0b Unused 15:14 11b Unused 31:16 0xFFh 0xFFh 31:00 0xFFh 0xFFh Unused P/N: PM1669 6Bh:68h 6Fh:6Ch 23 CFFEh REV. 1.1, FEB. 10, 2012 MX25L512E Note 1: h/b is hexadecimal or binary. Note 2: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x), address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1), (2-2-2), and (4-4-4) Note 3: Wait States is required dummy clock cycles after the address bits or optional mode bits. Note 4: Mode Bits is optional control bits that follow the address bits. These bits are driven by the system controller if they are specified. (eg,read performance enhance toggling bits) Note 5: 4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h Note 6: 0xFFh means all data is blank ("1b"). P/N: PM1669 24 REV. 1.1, FEB. 10, 2012 MX25L512E POWER-ON STATE The device is at the states as below when power-up: - Standby mode (please note it is not deep power-down mode) - Write Enable Latch (WEL) bit is reset The device must not be selected during power-up and power-down stage unless the VCC achieves below correct level (Please refer to the figure of "power-up timing"): - VCC minimum at power-up stage and then after a delay of tVSL - GND at power-down Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level. An internal Power-On Reset (POR) circuit may protect the device from data corruption and inadvertent data change during power up state. For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The read, write, erase, and program command should be sent after the time delay: tVSL after VCC reached VCC minimum level. Please refer to the figure of "power-up timing". The device can accept read command after VCC reached VCC minimum and a time delay of tVSL. Note: - To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended.(generally around 0.1uF) P/N: PM1669 25 REV. 1.1, FEB. 10, 2012 MX25L512E ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS RATING VALUE Ambient Operating Temperature Industrial grade -40°C to 85°C Storage Temperature -65°C to 150°C Applied Input Voltage -0.5V to 4.6V Applied Output Voltage -0.5V to 4.6V VCC to Ground Potential -0.5V to 4.6V NOTICE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. 2. Specifications contained within the following tables are subject to change. 3. During voltage transitions, all pins may overshoot to 4.6V or -0.5V for period up to 20ns. 4. All input and output pins may overshoot to VCC+0.5V while VCC+0.5V is smaller than or equal to 4.6V. Figure 4. Maximum Positive Overshoot Waveform Figure 3.Maximum Negative Overshoot Waveform 20ns 4.6V 0V 3.6V -0.5V 20ns CAPACITANCE TA = 25°C, f = 1.0 MHz Symbol Parameter CIN COUT P/N: PM1669 Min. Typ. Max. Unit Input Capacitance 6 pF VIN = 0V Output Capacitance 8 pF VOUT = 0V 26 Conditions REV. 1.1, FEB. 10, 2012 MX25L512E Figure 5. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL Input timing reference level 0.8VCC 0.2VCC 0.7VCC 0.3VCC Output timing reference level AC Measurement Level 0.5VCC Note: Input pulse rise and fall time are