MX25L6436EM2I-10G

MX25L6436E MX25L6436E HIGH PERFORMANCE SERIAL FLASH SPECIFICATION P/N: PM1772 1 REV. 2.0, AUG. 02, 2012 MX25L6436E Contents FEATURES................................................................................................................................................................... 5 GENERAL DESCRIPTION.......................................................................................................................................... 7 Table 1. Additional Features ........................................................................................................................ 7 PIN CONFIGURATION................................................................................................................................................. 8 PIN DESCRIPTION....................................................................................................................................................... 8 BLOCK DIAGRAM........................................................................................................................................................ 9 DATA PROTECTION................................................................................................................................................... 10 Table 2. Protected Area Sizes.................................................................................................................... 11 Table 3. 4K-bit Secured OTP Definition..................................................................................................... 11 Memory Organization................................................................................................................................................ 12 Table 4. Memory Organization................................................................................................................... 12 DEVICE OPERATION................................................................................................................................................. 13 Figure 1. Serial Modes Supported (for Normal Serial mode).....................................................................13 COMMAND DESCRIPTION........................................................................................................................................ 14 Table 5. Command Sets............................................................................................................................. 14 (1) Write Enable (WREN).................................................................................................................................. 16 (2) Write Disable (WRDI)................................................................................................................................... 16 (3) Read Identification (RDID)........................................................................................................................... 16 (4) Read Status Register (RDSR)..................................................................................................................... 17 (5) Write Status Register (WRSR)..................................................................................................................... 18 Protection Modes.............................................................................................................................................. 18 (6) Read Data Bytes (READ)............................................................................................................................ 19 (7) Read Data Bytes at Higher Speed (FAST_READ)...................................................................................... 19 (8) Dual Read Mode (DREAD).......................................................................................................................... 19 (9) Quad Read Mode (QREAD)........................................................................................................................ 19 (10) Sector Erase (SE)...................................................................................................................................... 20 (11) Block Erase (BE)........................................................................................................................................ 20 (12) Block Erase (BE32K)................................................................................................................................. 20 (13) Chip Erase (CE)......................................................................................................................................... 21 (14) Page Program (PP)................................................................................................................................... 21 (15) 4 x I/O Page Program (4PP)...................................................................................................................... 22 Program/Erase Flow(1) with read array data.................................................................................................... 23 Program/Erase Flow(2) without read array data............................................................................................... 24 (16) Continuously program mode (CP mode)................................................................................................... 25 (17) Deep Power-down (DP)............................................................................................................................. 26 (18) Release from Deep Power-down (RDP), Read Electronic Signature (RES)............................................. 26 (19) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4)........................................... 26 Table 6. ID Definitions ............................................................................................................................... 27 (20) Enter Secured OTP (ENSO)...................................................................................................................... 27 (21) Exit Secured OTP (EXSO)......................................................................................................................... 27 (22) Read Security Register (RDSCUR)........................................................................................................... 27 Security Register Definition............................................................................................................................... 28 (23) Write Security Register (WRSCUR)........................................................................................................... 28 (24) Write Protection Selection (WPSEL).......................................................................................................... 29 P/N: PM1772 2 REV. 2.0, AUG. 02, 2012 MX25L6436E BP and SRWD if WPSEL=0.............................................................................................................................. 29 The individual block lock mode is effective after setting WPSEL=1.................................................................. 30 WPSEL Flow..................................................................................................................................................... 31 (25) Single Block Lock/Unlock Protection (SBLK/SBULK)................................................................................ 32 Block Lock Flow................................................................................................................................................ 32 Block Unlock Flow............................................................................................................................................. 33 (26) Read Block Lock Status (RDBLOCK)........................................................................................................ 34 (27) Gang Block Lock/Unlock (GBLK/GBULK)................................................................................................. 34 (28) Clear SR Fail Flags (CLSR)....................................................................................................................... 34 (29) Enable SO to Output RY/BY# (ESRY)....................................................................................................... 34 (30) Disable SO to Output RY/BY# (DSRY)...................................................................................................... 34 (31) Read SFDP Mode (RDSFDP).................................................................................................................... 35 Table 7. Signature and Parameter Identification Data Values ................................................................... 36 Table 8. Parameter Table (0): JEDEC Flash Parameter Tables................................................................. 37 Table 9. Parameter Table (1): Macronix Flash Parameter Tables.............................................................. 39 POWER-ON STATE.................................................................................................................................................... 41 ELECTRICAL SPECIFICATIONS............................................................................................................................... 42 ABSOLUTE MAXIMUM RATINGS.................................................................................................................... 42 Figure 3. Maximum Negative Overshoot Waveform..................................................................................42 CAPACITANCE TA = 25°C, f = 1.0 MHz............................................................................................................ 42 Figure 4. Maximum Positive Overshoot Waveform....................................................................................42 Figure 5. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL......................................................43 Figure 6. OUTPUT LOADING...................................................................................................................43 Table 10. DC CHARACTERISTICS .......................................................................................................... 44 Table 11. AC CHARACTERISTICS........................................................................................................... 45 Timing Analysis......................................................................................................................................................... 47 Figure 7. Serial Input Timing......................................................................................................................47 Figure 8. Output Timing..............................................................................................................................47 Figure 9. WP# Setup Timing and Hold Timing during WRSR when SRWD=1..........................................48 Figure 10. Write Enable (WREN) Sequence (Command 06).....................................................................48 Figure 11. Write Disable (WRDI) Sequence (Command 04)......................................................................48 Figure 12. Read Identification (RDID) Sequence (Command 9F)..............................................................49 Figure 13. Read Status Register (RDSR) Sequence (Command 05)........................................................49 Figure 14. Write Status Register (WRSR) Sequence (Command 01).......................................................49 Figure 15. Read Data Bytes (READ) Sequence (Command 03)...............................................................50 Figure 16. Read at Higher Speed (FAST_READ) Sequence (Command 0B)...........................................50 Figure 17. Dual Read Mode Sequence (Command 3B)............................................................................50 Figure 18. Quad Read Mode Sequence (Command 6B)...........................................................................51 Figure 19. Sector Erase (SE) Sequence (Command 20)...........................................................................52 Figure 20. Block Erase (BE/BE32K) Sequence (Command D8/52)...........................................................52 Figure 21. Chip Erase (CE) Sequence (Command 60 or C7)....................................................................52 Figure 22. Page Program (PP) Sequence (Command 02)........................................................................53 Figure 23. 4 x I/O Page Program (4PP) Sequence (Command 38)...........................................................53 Figure 24. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD)...........54 Figure 25. Deep Power-down (DP) Sequence (Command B9).................................................................54 Figure 26. Read Electronic Signature (RES) Sequence (Command AB)...................................................55 Figure 27. Release from Deep Power-down (RDP) Sequence (Command AB)........................................55 Figure 28. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF)...56 P/N: PM1772 3 REV. 2.0, AUG. 02, 2012 MX25L6436E Figure 29. Write Protection Selection (WPSEL) Sequence (Command 68)..............................................56 Figure 30. Single Block Lock/Unlock Protection (SBLK/SBULK) Sequence (Command 36/39)................57 Figure 31. Read Block Protection Lock Status (RDBLOCK) Sequence (Command 3C)...........................57 Figure 32. Gang Block Lock/Unlock (GBLK/GBULK) Sequence (Command 7E/98).................................57 Figure 33. Power-up Timing.......................................................................................................................58 Table 12. Power-Up Timing ....................................................................................................................... 58 INITIAL DELIVERY STATE............................................................................................................................... 58 OPERATING CONDITIONS........................................................................................................................................ 59 Figure 34. AC Timing at Device Power-Up.................................................................................................59 Figure 35. Power-Down Sequence............................................................................................................60 ERASE AND PROGRAMMING PERFORMANCE..................................................................................................... 61 DATA RETENTION..................................................................................................................................................... 61 LATCH-UP CHARACTERISTICS............................................................................................................................... 61 ORDERING INFORMATION....................................................................................................................................... 62 PART NAME DESCRIPTION...................................................................................................................................... 63 PACKAGE INFORMATION......................................................................................................................................... 64 REVISION HISTORY .................................................................................................................................................. 67 P/N: PM1772 4 REV. 2.0, AUG. 02, 2012 MX25L6436E 64M-BIT [x 1/x 2/x 4] CMOS MXSMIOTM (SERIAL MULTI I/O) FLASH MEMORY FEATURES GENERAL • Serial Peripheral Interface compatible -- Mode 0 and Mode 3 • 64Mb: 67,108,864 x 1 bit structure or 33,554,432 x 2 bits (two I/O mode) structure or 16,777,216 x 4 bits (four I/ O mode) structure • 2048 Equal Sectors with 4K bytes each - Any Sector can be erased individually • 256 Equal Blocks with 32K bytes each - Any Block can be erased individually • 128 Equal Blocks with 64K bytes each - Any Block can be erased individually • Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations • Latch-up protected to 100mA from -1V to Vcc +1V PERFORMANCE • High Performance VCC = 2.7~3.6V - Normal read - 50MHz - Fast read (Normal Serial Mode) - 1 I/O: 104MHz with 8 dummy cycles - 2 I/O: 70MHz with 8 dummy cycles - 4 I/O: 75MHz with 8 dummy cycles - Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page) - Byte program time: 9us (typical) - Continuously Program mode (automatically increase address under word program mode) - Fast erase time: 60ms (typ.)/sector (4K-byte per sector) ; 0.7s(typ.) /block (64K-byte per block); 50s(typ.) /chip • Low Power Consumption - Low active read current: 19mA(max.) at 104MHz, 15mA(max.) at 66MHz and 10mA(max.) at 33MHz - Low active programming current: 25mA (max.) - Low active erase current: 25mA (max.) - Low standby current: 50uA (max.) - Deep power down current: 20uA (max.) • Typical 100,000 erase/program cycles • 20 years data retention SOFTWARE FEATURES • Input Data Format - 1-byte Command code • Advanced Security Features - BP0-BP3 block group protect - Flexible individual block protect when OTP WPSEL=1 - Additional 4K bits secured OTP for unique identifier P/N: PM1772 5 REV. 2.0, AUG. 02, 2012 MX25L6436E • Auto Erase and Auto Program Algorithms - Automatically erases and verifies data at selected sector - Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse width (Any page to be programed should have page in the erased state first.) • Status Register Feature • Electronic Identification - JEDEC 1-byte Manufacturer ID and 2-byte Device ID - RES command for 1-byte Device ID - REMS, REMS2 and REMS4 commands for 1-byte Manufacturer ID and 1-byte Device ID • Support Serial Flash Discoverable Parameters (SFDP) mode HARDWARE FEATURES • SCLK Input - Serial clock input • SI/SIO0 - Serial Data Input or Serial Data Input/Output for 2 x I/O mode and 4 x I/O mode • SO/SIO1 - Serial Data Output or Serial Data Input/Output for 2 x I/O mode and 4 x I/O mode • WP#/SIO2 - Hardware write protection or serial data Input/Output for 4 x I/O mode • NC/SIO3 - NC pin or serial data Input/Output for 4 x I/O mode • PACKAGE - 16-pin SOP (300mil) - 8-WSON (8x6mm) - 8-pin SOP (200mil) - All devices are RoHS Compliant P/N: PM1772 6 REV. 2.0, AUG. 02, 2012 MX25L6436E GENERAL DESCRIPTION MX25L6436E is 67,108,864 bits serial Flash memory, which is configured as 8,388,608 x 8 internally. When it is in two or four I/O mode, the structure becomes 33,554,432 bits x 2 or 16,777,216 bits x 4. The MX25L6436E features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input. MX25L6436E provides high performance read mode, which may latch address and data on both rising and falling edge of clock. By using this high performance read mode, the data throughput may be doubling. Moreover, the performance may reach direct code execution, the RAM size of the system may be reduced and further saving system cost. MX25L6436E, MXSMIOTM (Serial Multi I/O) flash memory, provides sequential read operation on the whole chip and multi-I/O features. When it is in dual I/O mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and data output. When it is in quad I/O mode, the SI pin, SO pin, WP# pin and NC pin become SIO0 pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data Input/Output. After program/erase command is issued, auto program/erase algorithms which program/erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256 bytes) basis, or word basis. Continuously Program mode and erase command are executed on 4K-byte sector, 32Kbyte/64K-byte block, or whole chip basis. To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via the WIP bit. When the device is not in operation and CS# is high, it is put in standby mode and draws less than 100uA DC current. The MX25L6436E utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles. Table 1. Additional Features Additional Features Part Name MX25L6436E Protection and Security Read Performance Flexible or Individual block (or sector) protection 4K-bit secured OTP 1 I/O Read (104 MHz) 2 I/O Read (70 MHz) 4 I/O Read (75 MHz) V V V V V Additional Features Part Name MX25L6436E P/N: PM1772 Identifier RES (command: AB hex) REMS (command: 90 hex) REMS2 (command: EF hex) REMS4 (command: DF hex) RDID (command: 9F hex) 16 (hex) C2 16 (hex) C2 16 (hex) C2 16 (hex) C2 20 17 (hex) 7 REV. 2.0, AUG. 02, 2012 MX25L6436E PIN CONFIGURATION PIN DESCRIPTION 16-PIN SOP (300mil) * NC/SIO3 VCC NC NC NC NC CS# SO/SIO1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SYMBOL DESCRIPTION CS# Chip Select Serial Data Input (for 1xI/O)/ Serial Data SI/SIO0 Input & Output (for 2xI/O or 4xI/O mode) Serial Data Output (for 1xI/O)/Serial SO/SIO1 Data Input & Output (for 2xI/O or 4xI/O mode) SCLK Clock Input Write protection: connect to GND or WP#/SIO2 Serial Data Input & Output (for 4xI/O mode) NC pin (Not connect) or Serial Data NC/SIO3 Input & Output (for 4xI/O mode) VCC + 3.3V Power Supply GND Ground NC No Connection SCLK SI/SIO0 NC NC NC NC GND WP#/SIO2 8-PIN SOP (200mil) CS# SO/SIO1 WP#/SIO2 GND 1 2 3 4 8 7 6 5 VCC NC/SIO3 SCLK SI/SIO0 8-WSON (8x6mm) * CS# SO/SIO1 WP#/SIO2 GND 1 2 3 4 8 7 6 5 VCC NC/SIO3 SCLK SI/SIO0 * Advanced Information P/N: PM1772 8 REV. 2.0, AUG. 02, 2012 MX25L6436E BLOCK DIAGRAM X-Decoder Address Generator Memory Array Page Buffer SI/SIO0 Data Register Y-Decoder SRAM Buffer Sense Amplifier CS# WP#/SIO2 NC/SIO3 SCLK Mode Logic State Machine Clock Generator Output Buffer SO/SIO1 P/N: PM1772 HV Generator 9 REV. 2.0, AUG. 02, 2012 MX25L6436E DATA PROTECTION During power transition, there may be some false system level signals which result in inadvertent erasure or programming. The device is designed to protect itself from these accidental write cycles. The state machine will be reset as standby mode automatically during power up. In addition, the control register architecture of the device constrains that the memory contents can only be changed after specific command sequences have completed successfully. In the following, there are several features to protect the system from the accidental write cycles during VCC powerup and power-down or from system noise. • Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary. • Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before issuing other commands to change data. The WEL bit will return to reset stage under following situations: - Power-up - Write Disable (WRDI) command completion - Write Status Register (WRSR) command completion - Page Program (PP, 4PP) command completion - Continuously Program mode (CP) instruction completion - Sector Erase (SE) command completion - Block Erase (BE, BE32K) command completion - Chip Erase (CE) command completion - Single Block Lock/Unlock (SBLK/SBULK) instruction completion - Gang Block Lock/Unlock (GBLK/GBULK) instruction completion • Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing all commands except Release from Deep Power Down mode command (RDP) and Read Electronic Signature command (RES). I. Block lock protection - The Software Protected Mode (SPM) uses (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected as read only. The protected area definition is shown as table of "Protected Area Sizes", the protected areas are more flexible which may protect various area by setting value of BP0-BP3 bits. Please refer to table of "Protected Area Sizes". - The Hardware Protected Mode (HPM) uses WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and SRWD bit. If the system goes into four I/O mode, the feature of HPM will be disabled. - MX25L6436E provides individual block (or sector) write protect & unprotect. User may enter the mode with WPSEL command and conduct individual block (or sector) write protect with SBLK instruction, or SBULK for individual block (or sector) unprotect. Under the mode, user may conduct whole chip (all blocks) protect with GBLK instruction and unlock the whole chip with GBULK instruction. P/N: PM1772 10 REV. 2.0, AUG. 02, 2012 MX25L6436E Table 2. Protected Area Sizes Status bit Protection Area BP3 BP2 BP1 BP0 64Mb 0 0 0 0 0 (none) 0 0 0 1 1 (2 blocks, block 126th-127th) 0 0 1 0 2 (4 blocks, block 124th-127th) 0 0 1 1 3 (8 blocks, block 120th-127th) 0 1 0 0 4 (16 blocks, block 112nd-127th) 0 1 0 1 5 (32 blocks, block 96th-127th) 0 1 1 0 6 (64 blocks, block 64th-127th) 0 1 1 1 7 (128 blocks, all) 1 0 0 0 8 (128 blocks, all) 1 0 0 1 9 (128 blocks, all) 1 0 1 0 10 (128 blocks, all) 1 0 1 1 11 (128 blocks, all) 1 1 0 0 12 (128 blocks, all) 1 1 0 1 13 (128 blocks, all) 1 1 1 0 14 (128 blocks, all) 1 1 1 1 15 (128 blocks, all) Note: The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP3, BP2, BP1, BP0) are 0. II. Additional 4K-bit secured OTP for unique identifier: to provide 4K-bit One-Time Program area for setting device unique serial number - Which may be set by factory or system maker. Please refer to Table 3. 4K-bit Secured OTP Definition. - Security register bit 0 indicates whether the chip is locked by factory or not. - To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with ENSO command), and going through normal program procedure, and then exiting 4K-bit secured OTP mode by writing EXSO command. - Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register) command to set customer lock-down bit1 as "1". Please refer to table of "Security Register Definition" for security register bit definition and table of "4K-bit Secured OTP Definition" for address range definition. - Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit Secured OTP mode, array access is not allowed. Table 3. 4K-bit Secured OTP Definition Address range Size Standard Factory Lock xxx000~xxx00F 128-bit ESN (electrical serial number) xxx010~xxx1FF 3968-bit N/A P/N: PM1772 11 Customer Lock Determined by customer REV. 2.0, AUG. 02, 2012 MX25L6436E Memory Organization Table 4. Memory Organization Block(64K-byte) Block(32K-byte) Sector (4K-byte) 126 252 individual block lock/unlock unit:64K-byte 251 125 250 7F8FFFh 2039 7F7000h 7F7FFFh … individual 16 sectors lock/unlock unit:4K-byte 2032 7F0000h 7F0FFFh 2031 7EF000h 7EFFFFh … 253 7F8000h 2024 7E8000h 7E8FFFh 2023 7E7000h 7E7FFFh … 254 2040 2016 7E0000h 7E0FFFh 2015 7DF000h 7DFFFFh … 127 7FFFFFh 2008 7D8000h 7D8FFFh 2007 7D7000h 7D7FFFh 2000 7D0000h 7D0FFFh 47 02F000h 02FFFFh … 255 Address Range 7FF000h … 2047 1 2 1 0 0 027FFFh 32 020000h 020FFFh 31 01F000h 01FFFFh … 028FFFh 027000h … 3 028000h 39 24 018000h 018FFFh 23 017000h 017FFFh … 4 individual block lock/unlock unit:64K-byte 40 16 010000h 010FFFh 15 00F000h 00FFFFh 8 008000h 008FFFh 7 007000h 007FFFh 000000h 000FFFh … 2 0 P/N: PM1772 individual 16 sectors lock/unlock unit:4K-byte … 5 … individual block lock/unlock unit:64K-byte 12 REV. 2.0, AUG. 02, 2012 MX25L6436E DEVICE OPERATION 1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation. 2. When incorrect command is inputted to this device, it enters standby mode and remains in standby mode until next CS# falling edge. In standby mode, SO pin of the device is High-Z. 3. When correct command is inputted to this device, it enters active mode and remains in active mode until next CS# rising edge. 4. For standard single data rate serial mode, input data is latched on the rising edge of Serial Clock (SCLK) and data is shifted out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as Figure 1. 5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, RDSFDP, DREAD, QREAD, RDBLOCK, RES, REMS, REMS2, and REMS4 the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE, BE32K, CE, PP, CP, 4PP, RDP, DP, WPSEL, SBLK, SBULK, GBLK, GBULK, ENSO, EXSO, WRSCUR, ESRY, DSRY and CLSR the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. While a Write Status Register, Program or Erase operation is in progress, access to the memory array is neglected and will not affect the current operation of Write Status Register, Program, Erase. Figure 1. Serial Modes Supported (for Normal Serial mode) CPOL CPHA shift in (Serial mode 0) 0 0 SCLK (Serial mode 3) 1 1 SCLK SI shift out MSB SO MSB Note: CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is supported. P/N: PM1772 13 REV. 2.0, AUG. 02, 2012 MX25L6436E COMMAND DESCRIPTION Table 5. Command Sets COMMAND (byte) Command (hex) Input Cycles Dummy Cycles Action COMMAND (byte) Command (hex) Input Cycles Dummy Cycles WREN (write enable) WRDI (write disable) RDID (read identification) RDSR (read status register) WRSR (write status register) READ (read data) FAST READ (fast read data) 06 04 9F 05 01 03 0B Data(8) ADD(24) ADD(24) 8 sets the (WEL) resets the outputs JEDEC to read out the to write new write enable (WEL) write ID: 1-byte values of the values to the latch bit enable latch bit Manufacturer status register status register ID & 2-byte Device ID Command (hex) Input Cycles Dummy Cycles Action P/N: PM1772 n bytes read out until CS# goes high RDSFDP (Read SFDP) DREAD (1I 2O read) QREAD (1I 4O read) 4PP (quad page program) SE (sector erase) BE (block erase 64KB) BE 32K (block erase 32KB) 5A 3B 6B 38 20 D8 52 ADD(24) ADD(24) ADD(24) ADD(6)+ Data(512) ADD(24) ADD(24) ADD(24) 8 8 8 Read SFDP mode Action COMMAND (byte) n bytes read out until CS# goes high n bytes read n bytes read quad input to to erase the to erase the to erase the out by Dual out by Quad program the selected sector selected 64KB selected 32KB output until output until selected page block block CS# goes high CS# goes high CP DP (Deep (Continuously power down) program mode) CE (chip erase) PP (Page program) 60 or C7 02 AD ADD(24)+ Data(2048) ADD(24)+ Data(16) B9 RDP REMS RES (Release from (read electronic (read electronic deep power manufacturer & ID) down) device ID) AB AB 90 ADD(24) 24 to erase whole to program the chip selected page continously program whole chip, the address is automatically increase enters deep power down mode 14 release from deep power down mode to read out output the 1-byte Device Manufacturer ID ID & Device ID REV. 2.0, AUG. 02, 2012 MX25L6436E COMMAND (byte) Command (hex) Input Cycles Dummy Cycles Action ESRY DSRY REMS2 REMS4 (read ENSO (enter EXSO (exit RDSCUR WRSCUR (enable SO (disable SO (read ID for ID for 4x I/O secured secured (read security (write security to output RY/ to output RY/ 2x I/O mode) mode) OTP) OTP) register) register) BY#) BY#) EF DF ADD(24) ADD(24) output the Manufacturer ID & Device ID output the Manufacturer ID & device ID COMMAND CLSR (Clear (byte) SR Fail Flags) Command (hex) Input Cycles Dummy Cycles Action 30 B1 C1 2B 2F 70 80 to enter to exit the 4K- to read value to set the to enable SO to disable SO the 4K-bit bit Secured of security lock-down bit to output RY/ to output RY/ Secured OTP OTP mode register as "1" (once BY# during BY# during mode lock-down, CP mode CP mode cannot be updated) WPSEL (write protection selection) SBLK (single block lock) *Note 2 68 36 39 3C ADD(24) ADD(24) ADD(24) RDBLOCK SBULK (single (block protect block unlock) read) clear security to enter and individual block individual block read individual register bit 6 enable individal (64K-byte) or (64K-byte) or block or sector and bit 5 block protect sector (4K-byte) sector (4K-byte) write protect mode write protect unprotect status GBLK (gang block lock) GBULK (gang block unlock) 7E 98 whole chip write protect whole chip unprotect Notes: 1. It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden mode. 2: In individual block write protection mode, all blocks/sectors are locked as defualt. P/N: PM1772 15 REV. 2.0, AUG. 02, 2012 MX25L6436E (1) Write Enable (WREN) The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP, CP, SE, BE, BE32K, CE, WRSR, SBLK, SBULK, GBLK and GBULK, which are intended to change the device content, should be set every time after the WREN instruction setting the WEL bit. The sequence of issuing WREN instruction is: CS# goes low→ sending WREN instruction code→ CS# goes high. (Please refer to Figure 10) (2) Write Disable (WRDI) The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit. The sequence of issuing WRDI instruction is: CS# goes low→ sending WRDI instruction code→ CS# goes high. (Please refer to Figure 11) The WEL bit is reset by following situations: - Power-up - Write Disable (WRDI) instruction completion - Write Status Register (WRSR) instruction completion - Page Program (PP, 4PP) instruction completion - Sector Erase (SE) instruction completion - Block Erase (BE, BE32K) instruction completion - Chip Erase (CE) instruction completion - Continuously Program mode (CP) instruction completion - Single Block Lock/Unlock (SBLK/SBULK) instruction completion - Gang Block Lock/Unlock (GBLK/GBULK) instruction completion (3) Read Identification (RDID) The RDID instruction is for reading the Manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC Manufacturer ID is C2(hex), the memory type ID is 20(hex) as the first-byte Device ID, and the individual Device ID of second-byte ID are listed as table of "ID Definitions". (Please refer to Table 6) The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code → 24-bits ID data out on SO→ to end RDID operation can use CS# to high at any time during data out. (Please refer to Figure 12) While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage. P/N: PM1772 16 REV. 2.0, AUG. 02, 2012 MX25L6436E (4) Read Status Register (RDSR) The RDSR instruction is for reading Status Register. The Read Status Register can be read at any time (even in program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in progress. The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register data out on SO (Please refer to Figure 13). The definition of the status register bits is as below: WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch. When WEL bit sets to "1", which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. The program/erase command will be ignored and will reset WEL bit if it is applied to a protected memory area. BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area (as defined in Table 2) of the device to against the program/erase instruction without hardware protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip Erase (CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed). QE bit. The Quad Enable (QE) bit, non-volatile bit, while it is "0" (factory default), it performs non-Quad and WP# is enable. While QE is "1", it performs Quad I/O mode and WP# is disabled. In the other word, if the system goes into four I/O mode (QE=1), the feature of HPM will be disabled. SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, default value is "0". SRWD bit is operated together with Write Protection (WP#/SIO2) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are read only. Status Register bit7 bit6 SRWD (status register write protect) QE (Quad Enable) 1= Quad 1=status Enable register write 0=not Quad disable Enable Non-volatile Non-volatile bit bit bit5 BP3 (level of protected block) bit4 BP2 (level of protected block) bit3 BP1 (level of protected block) bit2 BP0 (level of protected block) (note 1) (note 1) (note 1) (note 1) Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit bit1 bit0 WEL WIP (write enable (write in latch) progress bit) 1=write 1=write enable operation 0=not write 0=not in write enable operation volatile bit volatile bit Note: see the "Table 2. Protected Area Sizes". P/N: PM1772 17 REV. 2.0, AUG. 02, 2012 MX25L6436E (5) Write Status Register (WRSR) The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1, BP0) bits to define the protected area of memory (as shown in Table 2). The WRSR also can set or reset the Quad enable (QE) bit and set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#/SIO2) pin signal, but has no effect on bit1(WEL) and bit0 (WIP) of the status register. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered. The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register data on SI→ CS# goes high. (Please refer to Figure 14) The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset. Protection Modes Mode Software protection mode(SPM) Hardware protection mode (HPM) Status register condition WP# and SRWD bit status Memory Status register can be written in (WEL bit is set to "1") and the SRWD, BP0-BP3 bits can be changed WP#=1 and SRWD bit=0, or WP#=0 and SRWD bit=0, or WP#=1 and SRWD=1 The protected area cannot be program or erase. The SRWD, BP0-BP3 of status register bits cannot be changed WP#=0, SRWD bit=1 The protected area cannot be program or erase. Note: As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in Table 2. As the table above showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM): Software Protected Mode (SPM): - When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM). - When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM) Hardware Protected Mode (HPM): - When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2, BP1, BP0 and hardware protected mode by the WP#/SIO2 to against data modification. Note: To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is entered. If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via BP3, BP2, BP1, BP0. If the system goes into four I/O mode, the feature of HPM will be disabled. P/N: PM1772 18 REV. 2.0, AUG. 02, 2012 MX25L6436E (6) Read Data Bytes (READ) The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing READ instruction is: CS# goes low→ sending READ instruction code→3-byte address on SI →data out on SO→ to end READ operation can use CS# to high at any time during data out. (Please refer to Figure 15) (7) Read Data Bytes at Higher Speed (FAST_READ) The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing FAST_READ instruction is: CS# goes low→sending FAST_READ instruction code→3-byte address on SI→ 1-dummy byte (default) address on SI→data out on SO→ to end FAST_READ operation can use CS# to high at any time during data out. (Please refer to Figure 16) While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. (8) Dual Read Mode (DREAD) The DREAD instruction enable double throughput of Serial Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruction, the following data out will perform as 2-bit instead of previous 1-bit. The sequence of issuing DREAD instruction is: CS# goes low → sending DREAD instruction → 3-byte address on SI → 8-bit dummy cycle → data out interleave on SO1 & SO0 → to end DREAD operation can use CS# to high at any time during data out (Please refer to Figure 17). While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. (9) Quad Read Mode (QREAD) The QREAD instruction enable quad throughput of Serial Flash in read mode. The address is latched on rising edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ. The first address byte can be at any location. The address is automatically increased to the next high- P/N: PM1772 19 REV. 2.0, AUG. 02, 2012 MX25L6436E er address after each byte data is shifted out, so the whole memory can be read out at a single QREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing QREAD instruction, the following data out will perform as 4-bit instead of previous 1-bit. The sequence of issuing QREAD instruction is: CS# goes low→ sending QREAD instruction → 3-byte address on SI → 8-bit dummy cycle → data out interleave on SO3, SO2, SO1 & SO0→ to end QREAD operation can use CS# to high at any time during data out (Please refer to Figure 18). While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. (10) Sector Erase (SE) The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector (see Table 4) is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of the address been latchedin); otherwise, the instruction will be rejected and not executed. The sequence of issuing SE instruction is: CS# goes low → sending SE instruction code→ 3-byte address on SI →CS# goes high. (Please refer to Figure 19) The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets during the tSE timing, and clears when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the sector is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no change) and the WEL bit still be reset. (11) Block Erase (BE) The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 64K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (see Table 4) is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing BE instruction is: CS# goes low → sending BE instruction code → 3-byte address on SI → CS# goes high. (Please refer to Figure 20) The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets during the tBE timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the block is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no change) and the WEL bit still be reset. (12) Block Erase (BE32K) The Block Erase (BE32) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 32K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable P/N: PM1772 20 REV. 2.0, AUG. 02, 2012 MX25L6436E Latch (WEL) bit before sending the Block Erase (BE32). Any address of the block (see Table 4) is a valid address for Block Erase (BE32) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing BE32 instruction is: CS# goes low → sending BE32 instruction code → 3-byte address on SI → CS# goes high. (Please refer to Figure 20) The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets during the tBE timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the block is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no change) and the WEL bit still be reset. (13) Chip Erase (CE) The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. The sequence of issuing CE instruction is: CS# goes low → sending CE instruction code → CS# goes high. (Please refer to Figure 21) The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Chip Erase cycle is in progress. The WIP sets during the tCE timing, and clears when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the chip is protected, the Chip Erase (CE) instruction will not be executed, but WEL will be reset. (14) Page Program (PP) The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device programs only the last 256 data bytes sent to the device. If the entire 256 data bytes are going to be programmed, A7-A0 (the eight least significant address bits) should be set to 0. If the eight least significant address bits (A7-A0) are not all 0, all transmitted data going beyond the end of the current page are programmed from the start address of the same page (from the address A7-A0 are all 0). If more than 256 bytes are sent to the device, the data of the last 256-byte is programmed at the requested page and previous data will be disregarded. If less than 256 bytes are sent to the device, the data is programmed at the requested address of the page without effect on other address of the same page. The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→ at least 1-byte on data on SI→ CS# goes high. (Please refer to Figure 22) The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte boundary( the latest eighth bit of data being latched in), otherwise, the instruction will be rejected and will not be executed. The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Page Program cycle is in progress. The WIP sets during the tPP timing, and clears when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the page is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no P/N: PM1772 21 REV. 2.0, AUG. 02, 2012 MX25L6436E change) and the WEL bit will still be reset. (15) 4 x I/O Page Program (4PP) The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1" before sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1, SIO2, and SIO3, which can raise programer performance and and the effectiveness of application of lower clock less than 20MHz. For system with faster clock, the Quad page program cannot provide more performance, because the required internal page program time is far more than the time data flows in. Therefore, we suggest that while executing this command (especially during sending data), user can slow the clock speed down to 20MHz below. The other function descriptions are as same as standard page program. The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on SIO[3:0]→ at least 1-byte on data on SIO[3:0]→ CS# goes high. (Please refer to Figure 23) If the page is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no change) and the WEL bit will still be reset. P/N: PM1772 22 REV. 2.0, AUG. 02, 2012 MX25L6436E The Program/Erase function instruction function flow is as follows: Program/Erase Flow(1) with read array data Start WREN command RDSR command* WREN=1? No Yes Program/erase command Write program data/address (Write erase address) RDSR command No WIP=0? Yes Read array data (same address of PGM/ERS) Verify OK? No Yes Program/erase fail Program/erase successfully CLSR(30h) command Program/erase another block? No Yes * * Issue RDSR to check BP[3:0]. * If WPSEL=1, issue RDBLOCK to check the block status. Program/erase completed P/N: PM1772 23 REV. 2.0, AUG. 02, 2012 MX25L6436E Program/Erase Flow(2) without read array data Start WREN command RDSR command* WREN=1? No Yes Program/erase command Write program data/address (Write erase address) RDSR command No WIP=0? Yes RDSCUR command P_FAIL/E_FAIL=1? Yes No Program/erase fail Program/erase successfully CLSR(30h) command Program/erase Yes another block? No * Issue RDSR to check BP[3:0]. * If WPSEL=1, issue RDBLOCK to check the block status. Program/erase completed P/N: PM1772 24 REV. 2.0, AUG. 02, 2012 MX25L6436E (16) Continuously program mode (CP mode) The CP mode may enhance program performance by automatically increasing address to the next higher address after each byte data has been programmed. The Continuously program (CP) instruction is for multiple byte program to Flash. A write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Continuously program (CP) instruction. CS# requires to go high before CP instruction is executing. After CP instruction and address input, two bytes of data is input sequentially from MSB(bit7) to LSB(bit0). The first byte data will be programmed to the initial address range with A0=0 and second byte data with A0=1. If only one byte data is input, the CP mode will not process. If more than two bytes data are input, the additional data will be ignored and only two byte data are valid. Any byte to be programmed should be in the erase state (FF) first. It will not roll over during the CP mode, once the last unprotected address has been reached, the chip will exit CP mode and reset write Enable Latch bit (WEL) as "0" and CP mode bit as "0". Please check the WIP bit status if it is not in write progress before entering next valid instruction. During CP mode, the valid commands are CP command (AD hex), WRDI command (04 hex), RDSR command (05 hex), and RDSCUR command (2B hex). And the WRDI command is valid after completion of a CP programming cycle, which means the WIP bit=0. The sequence of issuing CP instruction is : CS# goes low → sending CP instruction code → 3-byte address on SI pin → two data bytes on SI → CS# goes high to low → sending CP instruction and then continue two data bytes are programmed → CS# goes high to low → till last desired two data bytes are programmed → CS# goes high to low →sending WRDI (Write Disable) instruction to end CP mode → send RDSR instruction to verify if CP mode word program ends, or send RDSCUR to check bit4 to verify if CP mode ends. (Please refer to Figure 24) Two methods to detect the completion of a program cycle during CP mode: 1) Software method-I: by checking WIP bit of Status Register to detect the completion of CP mode. 2) Software method-II: by waiting for a tBP time out to determine if it may load next valid command or not. 3) Hardware method: by writing ESRY (enable SO to output RY/BY#) instruction to detect the completion of a program cycle during CP mode. The ESRY instruction must be executed before CP mode execution. Once it is enable in CP mode, the CS# goes low will drive out the RY/BY# status on SO, "0" indicates busy stage, "1" indicates ready stage, SO pin outputs tri-state if CS# goes high. DSRY (disable SO to output RY/BY#) instruction to disable the SO to output RY/BY# and return to status register data output during CP mode. Please note that the ESRY/DSRY command are not accepted unless the completion of CP mode. If the page is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no change) and the WEL bit will still be reset. P/N: PM1772 25 REV. 2.0, AUG. 02, 2012 MX25L6436E (17) Deep Power-down (DP) The Deep Power-down (DP) instruction is for setting the device to minimum power consumption (the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction are ignored. The sequence of issuing DP instruction is: CS# goes low→ sending DP instruction code→ CS# goes high. (Please refer to Figure 25) Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP) and Read Electronic Signature (RES) instruction. (those instructions allow the ID being reading out). When Powerdown, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2. (18) Release from Deep Power-down (RDP), Read Electronic Signature (RES) The Release from Deep Power-down (RDP) instruction is completed by driving Chip Select (CS#) High. When Chip Select (CS#) is driven High, the device is put in the Standby Power mode. If the device was not previously in the Deep Power-down mode, the transition to the standby Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the standby Power mode is delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2(max), as specified in Table 11. Once in the standby mode, the device waits to be selected, so that it can receive, decode and execute instructions. RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new design, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device is in progress of program/erase/write cycles; there's no effect on the current program/erase/write cycles in progress. The sequence is shown as Figure 26, Figure 27. The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction. The RDP instruction is for releasing from Deep Power-down Mode. (19) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4) The REMS, REMS2 and REMS4 instruction provides both the JEDEC assigned Manufacturer ID and the specific Device ID. The instruction is initiated by driving the CS# pin low and shift the instruction code "90h", "DFh" or "EFh" followed by two dummy bytes and one bytes address (A7~A0). After which, the Manufacturer ID for MXIC (C2h) and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 34. The Device ID values are listed in table of ID Definitions. If the one-byte address is initially set to 01h, then the Device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high. P/N: PM1772 26 REV. 2.0, AUG. 02, 2012 MX25L6436E Table 6. ID Definitions Command Type RDID MX25L6436E memory type 20 electronic ID 16 device ID 16 manufacturer ID C2 RES REMS/REMS2/REMS4 manufacturer ID C2 memory density 17 (20) Enter Secured OTP (ENSO) The ENSO instruction is for entering the additional 4K-bit Secured OTP mode. While device is in 4K-bit Secured OTP mode, main array access is not available. The additional 4K-bit Secured OTP is independent from main array, and may be used to store unique serial number for system identifier. After entering the Secured OTP mode, follow standard read or program procedure to read out the data or update data. The Secured OTP data cannot be updated again once it is lock-down. The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP mode→ CS# goes high. Please note that WRSR/WRSCUR/WPSEL/SBLK/GBLK/SBULK/GBULK/CE/BE/SE/BE32K commands are not acceptable during the access of secure OTP region, once Security OTP is lock down, only read related commands are valid. (21) Exit Secured OTP (EXSO) The EXSO instruction is for exiting the additional 4K-bit Secured OTP mode. The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP mode→ CS# goes high. (22) Read Security Register (RDSCUR) The RDSCUR instruction is for reading the value of Security Register. The Read Security Register can be read at any time (even in program/erase/write status register/write security register condition) and continuously. The sequence of issuing RDSCUR instruction is : CS# goes low→ sending RDSCUR instruction → Security Register data out on SO→ CS# goes high. The definition of the Security Register is as below: Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory before ex- factory or not. When it is "0", it indicates non-factory lock; "1" indicates factory- lock. Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for customer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 4K-bit Secured OTP area cannot be updated any more. P/N: PM1772 27 REV. 2.0, AUG. 02, 2012 MX25L6436E Continuously Program Mode (CP mode) bit. The Continuously Program Mode bit indicates the status of CP mode, "0" indicates not in CP mode; "1" indicates in CP mode. Program Fail Flag bit. If the program operation fails on a protected memory region or locked OTP region, this bit will also be set. This bit can be the failure indication of one or more program operations. This fail flag bit will be reset by command CLSR (30h). Erase Fail Flag bit. If the erase operation fails on a protected memory region or locked OTP region, this bit will also be set. This bit can be the failure indication of one or more erase operations. This fail flag bit will be reset by command CLSR (30h). Write Protection Select bit. The Write Protection Select bit indicates that WPSEL has been executed successfully. Once this bit has been set (WPSEL=1), all the blocks or sectors will be write-protected after the power-on every time. Once WPSEL has been set, it cannot be changed again, which means it's only for individual WP mode. Under the individual block protection mode (WPSEL=1), hardware protection is performed by driving WP#=0. Once WP#=0 all array blocks/sectors are protected regardless of the contents of SRAM lock bits. Security Register Definition bit7 bit6 bit5 bit4 Continuously Program mode (CP mode) bit3 x bit2 x bit1 bit0 LDSO (lock-down 4K-bit 4K-bit Se- Secured OTP cured OTP) WPSEL E_FAIL P_FAIL 0=normal WP mode 1=individual WP mode (default=0) 0=normal Erase succeed 1=indicate Erase failed (default=0) 0=normal Program succeed 1=indicate Program failed (default=0) 0=normal Program mode 1=CP mode (default=0) reserved reserved 0 = not lockdown 1 = lockdown (cannot program/ erase OTP) non-volatile bit volatile bit volatile bit volatile bit volatile bit volatile bit non-volatile bit non-volatile bit OTP Read Only Read Only Read Only Read Only Read Only OTP Read Only 0= nonfactory lock 1 = factory lock (23) Write Security Register (WRSCUR) The WRSCUR instruction is for changing the values of Security Register Bits. Unlike write status register, the WREN instruction is not required before sending WRSCUR instruction. The WRSCUR instruction may change the values of bit1 (LDSO bit) for customer to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area cannot be updated any more. The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high. The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. P/N: PM1772 28 REV. 2.0, AUG. 02, 2012 MX25L6436E (24) Write Protection Selection (WPSEL) There are two write protection methods, (1) BP protection mode (2) individual block protection mode. If WPSEL=0, flash is under BP protection mode . If WPSEL=1, flash is under individual block protection mode. The default value of WPSEL is “0”. WPSEL command can be used to set WPSEL=1. Please note that WPSEL is an OTP bit. Once WPSEL is set to 1, there is no chance to recovery WPSEL back to “0”. If the flash is put on BP mode, the individual block protection mode is disabled. Contrarily, if flash is on the individual block protection mode, the BP mode is disabled. Every time after the system is powered-on the Security Register bit 7 is checked. If WPSEL=1, all the blocks and sectors will be write protected by default. User may only unlock the blocks or sectors via SBULK and GBULK instructions. Program or erase functions can only be operated after the Unlock instruction is executed. BP protection mode, WPSEL=0: ARRAY is protected by BP3~BP0 and BP3~BP0 bits are protected by “SRWD=1 and WP#=0”, where SRWD is bit 7 of status register that can be set by WRSR command. Individual block protection mode, WPSEL=1: Blocks are individually protected by their own SRAM lock bits which are set to “1” after power up. SBULK and SBLK command can set SRAM lock bit to “0” and “1”. When the system accepts and executes WPSEL instruction, bit 7 in the security register will be set. It will activate SBLK, SBULK, RDBLOCK, GBLK, GBULK etc instructions to conduct block lock protection and replace the original Software Protect Mode (SPM) use (BP3~BP0) indicated block methods. Under the individual block protection mode (WPSEL=1), hardware protection is performed by driving WP#=0. Once WP#=0 all array blocks/sectors are protected regardless of the contents of SRAM lock bits. The sequence of issuing WPSEL instruction is: CS# goes low → sending WPSEL instruction to enter the individual block protect mode → CS# goes high. WPSEL instruction function flow is as follows: BP and SRWD if WPSEL=0 WP# pin BP3 BP2 BP1 BP0 SRWD 64KB 64KB 64KB (1) BP3~BP0 is used to define the protection group region. (The protected area size see Table 2) (2) “SRWD=1 and WP#=0” is used to protect BP3~BP0. In this case, SRWD and BP3~BP0 of status register bits can not be changed by WRSR . . . 64KB P/N: PM1772 29 REV. 2.0, AUG. 02, 2012 MX25L6436E The individual block lock mode is effective after setting WPSEL=1 SRAM SRAM … … TOP 4KBx16 Sectors 4KB 4KB 4KB SRAM SRAM … 64KB SRAM … …… Uniform 64KB blocks 64KB 4KB SRAM … … Bottom 4KBx16 Sectors 4KB SRAM • Power-Up: All SRAM bits=1 (all blocks are default protected). All array cannot be programmed/erased • SBLK/SBULK(36h/39h): - SBLK(36h): Set SRAM bit=1 (protect): array can not be programmed/erased - SBULK(39h): Set SRAM bit=0 (unprotect): array can be programmed/erased - All the top 4KBx16 sectors and bottom 4KBx16 sectors and other 64KB uniform blocks can be protected and unprotected with SRAM bits individually by SBLK/SBULK command set. • GBLK/ GBULK(7Eh/98h): - GBLK(7Eh): Set all SRAM bits=1, the whole chip is protected and cannot be programmed/erased. - GBULK(98h): Set all SRAM bits=0, the whole chip is unprotected and can be programmed/erased. - All sectors and blocks SRAM bits of the whole chip can be protected and unprotected at one time by GBLK/GBULK command set. • RDBLOCK(3Ch): - use RDBLOCK mode to check the SRAM bits status after SBULK/SBLK/GBULK/GBLK command set. SBULK / SBLK / GBULK / GBLK / RDBLOCK P/N: PM1772 30 REV. 2.0, AUG. 02, 2012 MX25L6436E WPSEL Flow start RDSCUR(2Bh) command Yes WPSEL=1? No WPSEL disable, block protected by BP[3:0] WPSEL(68h) command RDSR command WIP=0? No Yes RDSCUR(2Bh) command WPSEL=1? No Yes WPSEL set successfully WPSEL set fail WPSEL enable. Block protected by individual lock (SBLK, SBULK, … etc). P/N: PM1772 31 REV. 2.0, AUG. 02, 2012 MX25L6436E (25) Single Block Lock/Unlock Protection (SBLK/SBULK) These instructions are only effective after WPSEL was executed. The SBLK instruction is for write protection a specified block(or sector) of memory, using A23-A16 or (A23-A12) address bits to assign a 64Kbyte block (or 4K bytes sector) to be protected as read only. The SBULK instruction will cancel the block (or sector) write protection state. This feature allows user to stop protecting the entire block (or sector) through the chip unprotect command (GBULK). The WREN (Write Enable) instruction is required before issuing SBLK/SBULK instruction. The sequence of issuing SBLK/SBULK instruction is: CS# goes low → send SBLK/SBULK (36h/39h) instruction → send 3 address bytes assign one block (or sector) to be protected on SI pin → CS# goes high. (Please refer to Figure 30) The CS# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not be executed. SBLK/SBULK instruction function flow is as follows: Block Lock Flow Start RDSCUR(2Bh) command WPSEL=1? No WPSEL command Yes WREN command SBLK command ( 36h + 24bit address ) RDSR command WIP=0? No Yes RDBLOCK command ( 3Ch + 24bit address ) Data = FFh ? No Yes Block lock successfully Lock another block? Block lock fail Yes No Block lock completed P/N: PM1772 32 REV. 2.0, AUG. 02, 2012 MX25L6436E Block Unlock Flow start RDSCUR(2Bh) command WPSEL=1? No WPSEL command Yes WREN command SBULK command ( 39h + 24bit address ) RDSR command No WIP=0? Yes Unlock another block? Yes Unlock block completed? P/N: PM1772 33 REV. 2.0, AUG. 02, 2012 MX25L6436E (26) Read Block Lock Status (RDBLOCK) This instruction is only effective after WPSEL was executed. The RDBLOCK instruction is for reading the status of protection lock of a specified block (or sector), using A23-A16 (or A23-A12) address bits to assign a 64K bytes block (4K bytes sector) and read protection lock status bit which the first byte of Read-out cycle. The status bit is"1" to indicate that this block has be protected, that user can read only but cannot write/program /erase this block. The status bit is "0" to indicate that this block hasn't be protected, and user can read and write this block. The sequence of issuing RDBLOCK instruction is: CS# goes low → send RDBLOCK (3Ch) instruction → send 3 address bytes to assign one block on SI pin → read block's protection lock status bit on SO pin → CS# goes high. (Please refer to Figure 31) (27) Gang Block Lock/Unlock (GBLK/GBULK) These instructions are only effective after WPSEL was executed. The GBLK/GBULK instruction is for enable/disable the lock protection block of the whole chip. The WREN (Write Enable) instruction is required before issuing GBLK/GBULK instruction. The sequence of issuing GBLK/GBULK instruction is: CS# goes low → send GBLK/GBULK (7Eh/98h) instruction → CS# goes high. (Please refer to Figure 32) The CS# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed. (28) Clear SR Fail Flags (CLSR) The CLSR instruction is for resetting the Program/Erase Fail Flag bit of Security Register. It should be executed before program/erase another block during programming/erasing flow without read array data. The sequence of issuing CLSR instruction is: CS# goes low → send CLSR instruction code → CS# goes high. The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. (29) Enable SO to Output RY/BY# (ESRY) The ESRY instruction is for outputting the ready/busy status to SO during CP mode. The sequence of issuing ESRY instruction is: CS# goes low → sending ESRY instruction code → CS# goes high. The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. (30) Disable SO to Output RY/BY# (DSRY) The DSRY instruction is for resetting ESRY during CP mode. The ready/busy status will not output to SO after DSRY issued. The sequence of issuing DSRY instruction is: CS# goes low → send DSRY instruction code → CS# goes high. The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. P/N: PM1772 34 REV. 2.0, AUG. 02, 2012 MX25L6436E (31) Read SFDP Mode (RDSFDP) The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on CFI. The sequence of issuing RDSFDP instruction is CS# goes low→send RDSFDP instruction (5Ah)→send 3 address bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP operation can use CS# to high at any time during data out. SFDP is a JEDEC Standard, JESD216. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI SO 24 BIT ADDRESS 23 22 21 5Ah 3 2 1 0 High-Z CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Cycle SI 7 6 5 4 3 2 1 0 DATA OUT 2 DATA OUT 1 SO 7 6 5 3 2 1 0 7 MSB MSB P/N: PM1772 4 35 6 5 4 3 2 1 0 7 MSB REV. 2.0, AUG. 02, 2012 MX25L6436E Table 7. Signature and Parameter Identification Data Values Description SFDP Signature Comment Fixed: 50444653h Add (h) DW Add Data (h/b) (Byte) (Bit) (Note1) 00h 07:00 53h Data (h) 53h 01h 15:08 46h 46h 02h 23:16 44h 44h 03h 31:24 50h 50h SFDP Minor Revision Number Start from 00h 04h 07:00 00h 00h SFDP Major Revision Number Start from 01h This number is 0-based. Therefore, 0 indicates 1 parameter header. 05h 15:08 01h 01h 06h 23:16 01h 01h 07h 31:24 FFh FFh 00h: it indicates a JEDEC specified header. 08h 07:00 00h 00h Start from 00h 09h 15:08 00h 00h Start from 01h 0Ah 23:16 01h 01h How many DWORDs in the Parameter table 0Bh 31:24 09h 09h 0Ch 07:00 30h 30h 0Dh 15:08 00h 00h 0Eh 23:16 00h 00h 0Fh 31:24 FFh FFh it indicates Macronix manufacturer ID 10h 07:00 C2h C2h Start from 00h 11h 15:08 00h 00h Start from 01h 12h 23:16 01h 01h How many DWORDs in the Parameter table 13h 31:24 04h 04h 14h 07:00 60h 60h 15h 15:08 00h 00h 16h 23:16 00h 00h 17h 31:24 FFh FFh Number of Parameter Headers Unused ID number (JEDEC) Parameter Table Minor Revision Number Parameter Table Major Revision Number Parameter Table Length (in double word) Parameter Table Pointer (PTP) First address of JEDEC Flash Parameter table Unused ID number (Macronix manufacturer ID) Parameter Table Minor Revision Number Parameter Table Major Revision Number Parameter Table Length (in double word) Parameter Table Pointer (PTP) First address of Macronix Flash Parameter table Unused P/N: PM1772 36 REV. 2.0, AUG. 02, 2012 MX25L6436E Table 8. Parameter Table (0): JEDEC Flash Parameter Tables Description Comment Block/Sector Erase sizes 00: Reserved, 01: 4KB erase, 10: Reserved, 11: not suport 4KB erase Write Granularity 0: 1Byte, 1: 64Byte or larger Write Enable Instruction Required 0: not required for Writing to Volatile Status 1: required 00h to be written to the Registers status register Add (h) DW Add Data (h/b) (Byte) (Bit) (Note1) 01b 02 1b 03 0b 30h 0: use 50h opcode, 1: use 06h opcode Write Enable Opcode Select for Note: If target flash status register is Writing to Volatile Status Registers nonvolatile, then bits 3 and 4 must be set to 00b. Contains 111b and can never be Unused changed 4KB Erase Opcode 01:00 31h Data (h) E5h 04 0b 07:05 111b 15:08 20h 16 1b 18:17 00b 19 0b 20 0b 20h (1-1-2) Fast Read (Note2) 0=not support 1=support Address Bytes Number used in addressing flash array Double Transfer Rate (DTR) Clocking 00: 3Byte only, 01: 3 or 4Byte, 10: 4Byte only, 11: Reserved (1-2-2) Fast Read 0=not support 1=support (1-4-4) Fast Read 0=not support 1=support 21 0b (1-1-4) Fast Read 0=not support 1=support 22 1b 23 1b 33h 31:24 FFh 37h:34h 31:00 03FF FFFFh 0=not support 1=support 32h Unused Unused Flash Memory Density (1-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states (Note3) Clocks) not support (1-4-4) Fast Read Number of 000b: Mode Bits not support Mode Bits (Note4) 38h (1-4-4) Fast Read Opcode 39h (1-1-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (1-1-4) Fast Read Number of 000b: Mode Bits not support Mode Bits 3Ah (1-1-4) Fast Read Opcode 3Bh P/N: PM1772 37 04:00 0 0000b 07:05 000b 15:08 FFh 20:16 0 1000b 23:21 000b 31:24 6Bh C1h FFh 00h FFh 08h 6Bh REV. 2.0, AUG. 02, 2012 MX25L6436E Description Comment (1-1-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (1-1-2) Fast Read Number of 000b: Mode Bits not support Mode Bits Add (h) DW Add Data (h/b) (Byte) (Bit) (Note1) 3Ch (1-1-2) Fast Read Opcode 3Dh (1-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (1-2-2) Fast Read Number of 000b: Mode Bits not support Mode Bits 3Eh (1-2-2) Fast Read Opcode 3Fh (2-2-2) Fast Read 0=not support 1=support Unused (4-4-4) Fast Read 0=not support 1=support 40h Unused 04:00 0 1000b 07:05 000b 15:08 3Bh 20:16 0 0000b 23:21 000b 31:24 FFh 00 0b 03:01 111b 04 0b 07:05 111b Data (h) 08h 3Bh 00h FFh EEh Unused 43h:41h 31:08 FFh FFh Unused 45h:44h 15:00 FFh FFh 20:16 0 000b 23:21 000b (2-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (2-2-2) Fast Read Number of 000b: Mode Bits not support Mode Bits 46h (2-2-2) Fast Read Opcode 47h 31:24 FFh FFh 49h:48h 15:00 FFh FFh 20:16 0 0000b 23:21 000b Unused 00h (4-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (4-4-4) Fast Read Number of 000b: Mode Bits not support Mode Bits 4Ah (4-4-4) Fast Read Opcode 4Bh 31:24 FFh FFh 4Ch 07:00 0Ch 0Ch 4Dh 15:08 20h 20h 4Eh 23:16 0Fh 0Fh 4Fh 31:24 52h 52h 50h 07:00 10h 10h 51h 15:08 D8h D8h 52h 23:16 00h 00h 53h 31:24 FFh FFh Sector Type 1 Size Sector/block size = 2^N bytes (Note5) 0x00b: this sector type doesn't exist Sector Type 1 erase Opcode Sector Type 2 Size Sector/block size = 2^N bytes 0x00b: this sector type doesn't exist Sector Type 2 erase Opcode Sector Type 3 Size Sector/block size = 2^N bytes 0x00b: this sector type doesn't exist Sector Type 3 erase Opcode Sector Type 4 Size Sector/block size = 2^N bytes 0x00b: this sector type doesn't exist Sector Type 4 erase Opcode P/N: PM1772 38 00h REV. 2.0, AUG. 02, 2012 MX25L6436E Table 9. Parameter Table (1): Macronix Flash Parameter Tables Description Comment Add (h) DW Add Data (h/b) (Byte) (Bit) (Note1) Data (h) Vcc Supply Maximum Voltage 2000h=2.000V 2700h=2.700V 3600h=3.600V 61h:60h 07:00 15:08 00h 36h 00h 36h Vcc Supply Minimum Voltage 1650h=1.650V 2250h=2.250V 2350h=2.350V 2700h=2.700V 63h:62h 23:16 31:24 00h 27h 00h 27h H/W Reset# pin 0=not support 1=support 00 0b H/W Hold# pin 0=not support 1=support 01 0b Deep Power Down Mode 0=not support 1=support 02 1b S/W Reset 0=not support 1=support 03 0b S/W Reset Opcode Reset Enable (66h) should be issued 65h:64h before Reset Opcode 11:04 1111 1111b (FFh) Program Suspend/Resume 0=not support 1=support 12 0b Erase Suspend/Resume 0=not support 1=support 13 0b 14 1b 15 0b 66h 23:16 FFh FFh 67h 31:24 FFh FFh Unused Wrap-Around Read mode 0=not support 1=support Wrap-Around Read mode Opcode Wrap-Around Read data length 08h:support 8B wrap-around read 16h:8B&16B 32h:8B&16B&32B 64h:8B&16B&32B&64B Individual block lock 0=not support 1=support 00 1b Individual block lock bit (Volatile/Nonvolatile) 0=Volatile 1=Nonvolatile 01 0b 09:02 0011 0110b (36h) 10 0b 11 1b Individual block lock Opcode 4FF4h Individual block lock Volatile protect bit default protect status 0=protect 1=unprotect Secured OTP 0=not support 1=support Read Lock 0=not support 1=support 12 0b Permanent Lock 0=not support 1=support 13 0b Unused 15:14 11b Unused 31:16 FFh FFh 31:00 FFh FFh Unused P/N: PM1772 6Bh:68h 6Fh:6Ch 39 C8D9h REV. 2.0, AUG. 02, 2012 MX25L6436E Note 1: h/b is hexadecimal or binary. Note 2: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x), address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1), (2-2-2), and (4-4-4) Note 3: Wait States is required dummy clock cycles after the address bits or optional mode bits. Note 4: Mode Bits is optional control bits that follow the address bits. These bits are driven by the system controller if they are specified. (eg,read performance enhance toggling bits) Note 5: 4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h Note 6: All unused and undefined area data is blank FFh. P/N: PM1772 40 REV. 2.0, AUG. 02, 2012 MX25L6436E POWER-ON STATE The device is at the following states after power-up: - Standby mode ( please note it is not Deep Power-down mode) - Write Enable Latch (WEL) bit is reset The device must not be selected during power-up and power-down stage until the VCC reaches the following levels: - VCC minimum at power-up stage and then after a delay of tVSL - GND at power-down Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level. An internal Power-on Reset (POR) circuit may protect the device from data corruption and inadvertent data change during power up state. For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The read, write, erase, and program command should be sent after the time delay: - tVSL after VCC reached VCC minimum level The device can accept read command after VCC reached VCC minimum and a time delay of tVSL. Please refer to the figure of "Power-up Timing". Note: - To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended. (generally around 0.1uF) P/N: PM1772 41 REV. 2.0, AUG. 02, 2012 MX25L6436E ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS RATING VALUE Ambient Operating Temperature Industrial grade -40°C to 85°C Storage Temperature -65°C to 150°C Applied Input Voltage -0.5V to 4.6V Applied Output Voltage -0.5V to 4.6V VCC to Ground Potential -0.5V to 4.6V NOTICE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. 2. Specifications contained within the following tables are subject to change. 3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see Figure 2, 3. Figure 4. Maximum Positive Overshoot Waveform Figure 3. Maximum Negative Overshoot Waveform 20ns 20ns 20ns Vss Vcc + 2.0V Vss-2.0V Vcc 20ns 20ns 20ns CAPACITANCE TA = 25°C, f = 1.0 MHz Symbol Parameter CIN COUT P/N: PM1772 Min. Typ. Max. Unit Input Capacitance 10 pF VIN = 0V Output Capacitance 8 pF VOUT = 0V 42 Conditions REV. 2.0, AUG. 02, 2012 MX25L6436E Figure 5. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL Input timing reference level 0.8VCC 0.2VCC 0.7VCC 0.3VCC Output timing reference level AC Measurement Level 0.5VCC Note: Input pulse rise and fall time are