MX25L8006E
MX25L8006E
3V, 8M-BIT [x 1/x 2]
CMOS SERIAL FLASH MEMORY
Key Features
• Hold Feature
• Low Power Consumption
• Auto Erase and Auto Program Algorithms
• Additional 512 bit secured OTP for unique identifier
P/N: PM1613
1
Rev. 1.6, August 28, 2017
MX25L8006E
Contents
FEATURES................................................................................................................................................................... 5
GENERAL DESCRIPTION.......................................................................................................................................... 6
PIN CONFIGURATIONS .............................................................................................................................................. 7
PIN DESCRIPTION....................................................................................................................................................... 7
BLOCK DIAGRAM........................................................................................................................................................ 8
MEMORY ORGANIZATION.......................................................................................................................................... 9
Table 1. Memory Organization.............................................................................................................................. 9
DEVICE OPERATION................................................................................................................................................. 10
Figure 1. Serial Modes Supported....................................................................................................................... 10
DATA PROTECTION................................................................................................................................................... 11
Table 2. Protected Area Sizes............................................................................................................................. 12
Table 3. 512 bit Secured OTP Definition............................................................................................................. 13
HOLD FEATURE......................................................................................................................................................... 14
Figure 2. Hold Condition Operation .................................................................................................................... 14
COMMAND DESCRIPTION........................................................................................................................................ 15
Table 4. COMMAND DEFINITION...................................................................................................................... 15
(1) Write Enable (WREN).................................................................................................................................... 16
(2) Write Disable (WRDI)..................................................................................................................................... 16
(3) Read Status Register (RDSR)....................................................................................................................... 16
Table 5. Status Register ..................................................................................................................................... 17
(4) Write Status Register (WRSR)....................................................................................................................... 17
Table 6. Protection Modes................................................................................................................................... 18
(5) Read Data Bytes (READ).............................................................................................................................. 19
(6) Read Data Bytes at Higher Speed (FAST_READ)........................................................................................ 19
(7) Dual Output Mode (DREAD).......................................................................................................................... 19
(8) Sector Erase (SE).......................................................................................................................................... 19
(9) Block Erase (BE)............................................................................................................................................ 20
(10) Chip Erase (CE)........................................................................................................................................... 20
(11) Page Program (PP)...................................................................................................................................... 20
(12) Deep Power-down (DP)............................................................................................................................... 21
(13) Release from Deep Power-down (RDP), Read Electronic Signature (RES) .............................................. 21
(14) Read Identification (RDID)........................................................................................................................... 22
(15) Read Electronic Manufacturer ID & Device ID (REMS)............................................................................... 22
Table 7. ID DEFINITIONS .................................................................................................................................. 22
(16) Enter Secured OTP (ENSO)........................................................................................................................ 22
(17) Exit Secured OTP (EXSO)........................................................................................................................... 22
(18) Read Security Register (RDSCUR)............................................................................................................. 23
Table 8. SECURITY REGISTER DEFINITION.................................................................................................... 23
(19) Write Security Register (WRSCUR)............................................................................................................. 23
P/N: PM1613
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Rev. 1.6, August 28, 2017
MX25L8006E
(20) Read SFDP Mode (RDSFDP)...................................................................................................................... 24
Figure 3. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence...................................................... 24
Table 9. Signature and Parameter Identification Data Values ............................................................................ 25
Table 10. Parameter Table (0): JEDEC Flash Parameter Tables........................................................................ 26
Table 11. Parameter Table (1): Macronix Flash Parameter Tables...................................................................... 28
POWER-ON STATE.................................................................................................................................................... 30
ELECTRICAL SPECIFICATIONS............................................................................................................................... 31
ABSOLUTE MAXIMUM RATINGS...................................................................................................................... 31
Figure 4. Maximum Negative Overshoot Waveform.......................................................................................... 31
CAPACITANCE TA = 25°C, f = 1.0 MHz.............................................................................................................. 31
Figure 5. Maximum Positive Overshoot Waveform............................................................................................. 31
Figure 6. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL.............................................................. 32
Figure 7. OUTPUT LOADING............................................................................................................................ 32
Figure 8. SCLK TIMING DEFINITION................................................................................................................. 32
Table 12. DC CHARACTERISTICS..................................................................................................................... 33
Table 13. AC CHARACTERISTICS..................................................................................................................... 34
Timing Analysis......................................................................................................................................................... 35
Figure 9. Serial Input Timing............................................................................................................................... 35
Figure 10. Output Timing..................................................................................................................................... 35
Figure 11. Hold Timing........................................................................................................................................ 36
Figure 12. WP# Disable Setup and Hold Timing during WRSR when SRWD=1................................................ 36
Figure 13. Write Enable (WREN) Sequence (Command 06).............................................................................. 37
Figure 14. Write Disable (WRDI) Sequence (Command 04)............................................................................... 37
Figure 15. Read Status Register (RDSR) Sequence (Command 05)................................................................. 38
Figure 16. Write Status Register (WRSR) Sequence (Command 01)................................................................ 38
Figure 17. Read Data Bytes (READ) Sequence (Command 03)....................................................................... 38
Figure 18. Read at Higher Speed (FAST_READ) Sequence (Command 0B).................................................... 39
Figure 19. Dual Output Read Mode Sequence (Command 3B).......................................................................... 40
Figure 20. Sector Erase (SE) Sequence (Command 20)................................................................................... 40
Figure 21. Block Erase (BE) Sequence (Command 52 or D8)........................................................................... 40
Figure 22. Chip Erase (CE) Sequence (Command 60 or C7)............................................................................ 41
Figure 23. Page Program (PP) Sequence (Command 02)................................................................................. 41
Figure 24. Deep Power-down (DP) Sequence (Command B9) ......................................................................... 42
Figure 25. Release from Deep Power-down (RDP) Sequence (Command AB) ............................................... 42
Figure 26. Read Electronic Signature (RES) Sequence (Command AB) .......................................................... 42
Figure 27. Read Identification (RDID) Sequence (Command 9F)....................................................................... 43
Figure 28. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90)............................... 43
Figure 29. Read Security Register (RDSCUR) Sequence (Command 2B)......................................................... 44
Figure 30. Write Security Register (WRSCUR) Sequence (Command 2F)........................................................ 44
Figure 31. Power-up Timing................................................................................................................................ 45
Table 14. Power-Up Timing ................................................................................................................................ 45
P/N: PM1613
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Rev. 1.6, August 28, 2017
MX25L8006E
OPERATING CONDITIONS........................................................................................................................................ 46
Figure 32. AC Timing at Device Power-Up.......................................................................................................... 46
Figure 33. Power-Down Sequence..................................................................................................................... 47
ERASE AND PROGRAMMING PERFORMANCE..................................................................................................... 48
DATA RETENTION..................................................................................................................................................... 48
LATCH-UP CHARACTERISTICS............................................................................................................................... 48
ORDERING INFORMATION....................................................................................................................................... 49
PART NAME DESCRIPTION...................................................................................................................................... 50
PACKAGE INFORMATION......................................................................................................................................... 51
REVISION HISTORY .................................................................................................................................................. 56
P/N: PM1613
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Rev. 1.6, August 28, 2017
MX25L8006E
8M-BIT [x 1 / x 2] CMOS SERIAL FLASH
FEATURES
GENERAL
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Supports Serial Peripheral Interface -- Mode 0 and Mode 3
• 8,388,608 x 1 bit structure or 4,194,304 x 2 bits (Dual Output mode) structure
• 256 Equal Sectors with 4K byte each
- Any Sector can be erased individually
• 16 Equal Blocks with 64K byte each
- Any Block can be erased individually
• Program Capability
- Byte base
- Page base (256 bytes)
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
- Fast access time: 86MHz serial clock
- Serial clock of Dual Output mode : 80MHz
- Fast program time: 0.6ms(typ.) and 3ms(max.)/page
- Byte program time: 9us (typical)
- Fast erase time: 40ms(typ.) /sector ; 0.4s(typ.) /block
• Low Power Consumption
- Low active read current: 12mA(max.) at 86MHz
- Low active programming current: 15mA (typ.)
- Low active Sector/Block erase current: 9mA (typ.)
- Low standby current: 15uA (typ.)
- Deep power-down mode 2uA (typ.)
• Typical 100,000 erase/program cycles
• 20 years of data retention
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block lock protection
The BP2-BP0 status bit defines the size of the area to be software protection against program and erase instructions
- Additional 512 bit secured OTP for unique identifier
• Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected sector
- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse widths (Any page to be programed should have page in the erased state first)
• Status Register Feature
• Electronic Identification
- JEDEC 1-byte manufacturer ID and 2-byte device ID
- RES command for 1-byte Device ID
- REMS command for 1-byte manufacturer ID and 1-byte device ID
• Support Serial Flash Discoverable Parameters (SFDP) mode
P/N: PM1613
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Rev. 1.6, August 28, 2017
MX25L8006E
HARDWARE FEATURES
• PACKAGE
- 8-pin SOP (150mil)
- 8-pin SOP (200mil)
- 8-pin PDIP (300mil)
- 8-land WSON (6x5mm)
- 8-land USON (4x4mm)
- All devices are RoHS Compliant and Halogen-free
GENERAL DESCRIPTION
The device features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus.
The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access
to the device is enabled by CS# input.
When it is in Dual Output read mode, the SI and SO pins become SIO0 and SIO1 pins for data output.
The device provides sequential read operation on the whole chip.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page basis, or
word basis. Erase command is executed on sector, or block, or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
Advanced security features enhance the protection and security functions, please see security features section for
more details.
When the device is not in operation and CS# is high, it is put in standby mode.
The device utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after typical
100,000 program and erase cycles.
P/N: PM1613
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Rev. 1.6, August 28, 2017
MX25L8006E
PIN CONFIGURATIONS
8-PIN PDIP (300mil)
8-PIN SOP (200mil, 150mil)
CS#
SO/SIO1
WP#
GND
1
2
3
4
8
7
6
5
CS#
SO/SIO1
WP#
GND
VCC
HOLD#
SCLK
SI/SIO0
P/N: PM1613
1
2
3
4
8
7
6
5
8
7
6
5
VCC
HOLD#
SCLK
SI/SIO0
PIN DESCRIPTION
8-LAND WSON (6x5mm), USON (4x4mm)
CS#
SO/SIO1
WP#
GND
1
2
3
4
SYMBOL DESCRIPTION
VCC
HOLD#
SCLK
SI/SIO0
CS#
Chip Select
Serial Data Input (for 1 x I/O)/ Serial Data
SI/SIO0
Input & Output (for Dual Output mode)
Serial Data Output (for 1 x I/O)/ Serial Data
SO/SIO1
Output (for Dual Output mode)
SCLK Clock Input
WP# Write protection
Hold, to pause the device without
HOLD#
deselecting the device
VCC
+ 3.3V Power Supply
GND Ground
7
Rev. 1.6, August 28, 2017
MX25L8006E
BLOCK DIAGRAM
X-Decoder
Address
Generator
SI/SIO0
SO/SIO1
SIO2
SIO3
WP#
HOLD#
RESET#
CS#
SCLK
Memory Array
Y-Decoder
*
*
*
*
*
Data
Register
Sense
Amplifier
SRAM
Buffer
Mode
Logic
State
Machine
HV
Generator
Clock Generator
Output
Buffer
* Depends on part number options.
P/N: PM1613
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Rev. 1.6, August 28, 2017
MX25L8006E
MEMORY ORGANIZATION
Table 1. Memory Organization
Block
15
14
Sector
255
:
240
239
:
224
Address Range
0FF000h
0FFFFFh
:
:
0F0000h
0F0FFFh
0EF000h
0EFFFFh
:
:
0E0000h
0E0FFFh
:
:
:
:
:
:
:
:
0
15
:
3
2
1
0
00F000h
:
003000h
002000h
001000h
000000h
00FFFFh
:
003FFFh
002FFFh
001FFFh
000FFFh
P/N: PM1613
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Rev. 1.6, August 28, 2017
MX25L8006E
DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation.
2. When incorrect command is inputted to this device, it enters standby mode and remains in standby mode until
next CS# falling edge. In standby mode, SO pin of the device is High-Z. The CS# falling time needs to follow
tCHCL spec.
3. When correct command is inputted to this device, it enters active mode and remains in active mode until next
CS# rising edge. The CS# rising time needs to follow tCLCH spec.
4. Input data is latched on the rising edge of Serial Clock(SCLK) and data is shifted out on the falling edge of
SCLK. The difference of Serial mode 0 and mode 3 is shown in Figure 1.
5. For the following instructions:RDID, RDSR, RDSCUR, READ, FAST_READ, RDSFDP, DREAD, RES, and
REMS the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted
out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE, CE, PP, RDP, DP,
ENSO, EXSO,and WRSCUR, the CS# must go high exactly at the byte boundary; otherwise, the instruction will
be rejected and not executed.
6. While a Write Status Register, Program or Erase operation is in progress, access to the memory array is neglected and will not affect the current operation of Write Status Register, Program, Erase.
Figure 1. Serial Modes Supported
CPOL
CPHA
shift in
(Serial mode 0)
0
0
SCLK
(Serial mode 3)
1
1
SCLK
SI
shift out
MSB
SO
MSB
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is
supported.
P/N: PM1613
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Rev. 1.6, August 28, 2017
MX25L8006E
DATA PROTECTION
During power transition, there may be some false system level signals which result in inadvertent erasure or
programming. The device is designed to protect itself from these accidental write cycles.
The state machine will be reset as standby mode automatically during power up. In addition, the control register
architecture of the device constrains that the memory contents can only be changed after specific command
sequences have completed successfully.
In the following, there are several features to protect the system from the accidental write cycles during VCC powerup and power-down or from system noise.
• Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
other command to change data. The WEL bit will return to reset stage under following situation:
- Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP) command completion
- Sector Erase (SE) command completion
- Block Erase (BE) command completion
- Chip Erase (CE) command completion
• Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from
writing all commands except Release from deep power down mode command (RDP) and Read Electronic Signature command (RES).
• Advanced Security Features: there are some protection and security features which protect content from inadvertent write and hostile access.
I. Block lock protection
- The Software Protected Mode (SPM):
MX25L8006E: use (BP2, BP1, BP0) bits to allow part of memory to be protected as read only. The proected area
definition is shown as "Table 2. Protected Area Sizes", the protected areas are more flexible which may protect
various area by setting value of BP0-BP2 bits.
Please refer to "Table 2. Protected Area Sizes".
- The Hardware Proteced Mode (HPM) uses WP# to protect the MX25L8006E:BP2-BP0 bits and SRWD bit.
P/N: PM1613
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Rev. 1.6, August 28, 2017
MX25L8006E
Table 2. Protected Area Sizes
BP2
0
0
0
0
1
1
1
1
P/N: PM1613
Status bit
BP1
0
0
1
1
0
0
1
1
BP0
0
1
0
1
0
1
0
1
Protect Level
MX25L8006E
0 (none)
1 (1block, block 15th)
2 (2blocks, block 14th-15th)
3 (4blocks, block 12th-15th)
4 (8blocks, block 8th-15th)
5 (All)
6 (All)
7 (All)
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Rev. 1.6, August 28, 2017
MX25L8006E
II. Additional 512 bit secured OTP for unique identifier: to provide 512 bit one-time program area for setting
device unique serial number - Which may be set by factory or system customer. Please refer to "Table 3. 512 bit
Secured OTP Definition".
- Security register bit 0 indicates whether the chip is locked by factory or not.
- To program the 512 bit secured OTP by entering 512 bit secured OTP mode (with ENSO command), and going
through normal program procedure, and then exiting 512 bit secured OTP mode by writing EXSO command.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register)
command to set customer lock-down bit1 as "1". Please refer to "Table 8. SECURITY REGISTER DEFINITION" for security register bit definition and "Table 3. 512 bit Secured OTP Definition" for address range definition.
- Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 512 bit secured OTP mode, array access is not allowed.
Table 3. 512 bit Secured OTP Definition
Address range
Size
Standard Factory Lock
Customer Lock
xxxx00-xxxx0F
128-bit
ESN (electrical serial number)
Determined by customer
xxxx10-xxxx3F
384-bit
N/A
P/N: PM1613
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Rev. 1.6, August 28, 2017
MX25L8006E
HOLD FEATURE
HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the
operation of write status register, programming, or erasing in progress.
The operation of HOLD requires Chip Select (CS#) keeping low and starts on falling edge of HOLD# pin signal while Serial
Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start until Serial Clock
signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Serial Clock(SCLK) signal is
being low (if Serial Clock signal is not being low, HOLD operation will not end until Serial Clock being low).
≈
SI/SIO0
≈ ≈
SO/SIO1
(internal)
SO/SIO1
(External)
Don’t care
Valid Data
Valid Data
High_Z
Bit 6
Bit 5
Bit 6
≈
≈ ≈
SO/SIO1
(internal)
SO/SIO1
(External)
High_Z
Bit 7
Bit 5
≈
≈
SI/SIO0
≈
HOLD#
≈ ≈
SCLK
Valid Data
Bit 6
Bit 7
CS#
Don’t care
Bit 7
≈
HOLD#
≈ ≈
SCLK
≈
CS#
≈
Figure 2. Hold Condition Operation
Don’t care
Valid Data
Bit 7
Bit 7
Valid Data
Bit 6
High_Z
Don’t care
Bit 5
Bit 6
Bit 5
Valid Data
Bit 4
High_Z
Bit 3
Bit 4
Bit 3
During the HOLD operation, the Serial Data Output (SO) is high impedance when Hold# pin goes low and will
keep high impedance until Hold# pin goes high and SCLK goes low. The Serial Data Input (SI) is don't care if
both Serial Clock (SCLK) and Hold# pin goes low and will keep the state until SCLK goes low and Hold# pin
goes high. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of the device. To
re-start communication with chip, the HOLD# must be at high and CS# must be at low.
Note: The HOLD feature is disabled during Quad I/O mode.
P/N: PM1613
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Rev. 1.6, August 28, 2017
MX25L8006E
COMMAND DESCRIPTION
Table 4. COMMAND DEFINITION
FAST READ
(fast read
data)
06 (hex)
04 (hex)
03 (hex)
0B (hex)
AD1
AD1
AD2
AD2
AD3
AD3
Dummy
to write new
outputs
to read out n bytes read n bytes read
sets the (WEL) resets the
write enable (WEL) write values to the
JEDEC
the values out until CS# out until CS#
goes high
latch bit
enable latch status register ID: 1-byte
of the status
goes high
bit
Manufact-urer
register
ID & 2-byte
Device ID
Command WREN (write WRDI (write
(byte)
enable)
disable)
1st byte
2nd byte
3rd byte
4th byte
5th byte
Action
WRSR
RDID
RDSR
(write status (read identific- (read status
register)
ation)
register)
01 (hex)
9F (hex)
05 (hex)
REMS (read
Command
RDSFDP
RES (read
electronic
(byte)
(Read SFDP) electronic ID) manufacturer
& device ID)
1st byte
5A (hex)
AB (hex)
90 (hex)
2nd byte
AD1
x
x
3rd byte
AD2
x
x
4th byte
AD3
x
ADD (Note 1)
5th byte
Dummy
Read SFDP to read out
output the
mode
1-byte Device Manufacturer
Action
ID
ID & Device
ID
Command
(byte)
PP (page
program)
1st byte
2nd byte
3rd byte
4th byte
5th byte
02 (hex)
AD1
AD2
AD3
Action
READ (read
data)
DREAD
(Double
SE (sector
BE (block
CE (chip
Output Mode
erase)
erase)
erase)
command)
3B (hex)
20 (hex)
52 or D8 (hex) 60 or C7 (hex)
AD1
AD1
AD1
AD2
AD2
AD2
AD3
AD3
AD3
Dummy
to erase
n bytes read to erase the to erase the
whole chip
selected
selected
out by Dual
Output until
sector
block
CS# goes
high
RDSCUR
WRSCUR
RDP (Release
ENSO (enter EXSO (exit
DP (Deep
(read security (write security
from deep
secured OTP) secured OTP) power down)
register)
register)
power down)
2B (hex)
2F (hex)
B1 (hex)
C1 (hex)
B9 (hex)
AB (hex)
to enter
to exit the 512 enters deep
to program to read value
to set the
bit secured power down
the selected
of security lock-down bit the 512 bit
mode
page
register
as "1" (once secured OTP OTP mode
lock-down,
mode
cannot be
updated)
release from
deep power
down mode
Note 1: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first.
Note 2: It is not recommended to adopt any other code not in the command definition table, which will potentially
enter the hidden mode.
P/N: PM1613
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Rev. 1.6, August 28, 2017
MX25L8006E
(1) Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, SE,
BE, CE, and WRSR, which are intended to change the device content, should be set every time after the WREN instruction setting the WEL bit.
The sequence is shown as Figure 13.
(2) Write Disable (WRDI)
The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.
The sequence is shown as Figure 14.
The WEL bit is reset by following situations:
- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase (BE) instruction completion
- Chip Erase (CE) instruction completion
(3) Read Status Register (RDSR)
The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in
program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP)
bit before sending a new instruction when a program, erase, or write status register operation is in progress.
The sequence is shown as Figure 15.
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write
status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status
register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status
register cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable
latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/
erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. The program/erase command will be ignored and
not affect value of WEL bit if it is applied to a protected memory area.
BP2, BP1, BP0 bits. The Block Protect (BP2-BP0) bits, non-volatile bits, indicate the protected area (as defined in
"Table 2. Protected Area Sizes") of the device to against the program/erase instruction without hardware protection
mode being set. To write the Block Protect (BP2-BP0) bits requires the Write Status Register (WRSR) instruction to
be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE),
Block Erase (BE) and Chip Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be
executed).
P/N: PM1613
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Rev. 1.6, August 28, 2017
MX25L8006E
SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, and its default value is "0". SRWD bit is
operated together with Write Protection (WP#) pin for providing hardware protection mode. The hardware protection
mode requires SRWD sets to 1 and WP# pin signal is low stage. In the hardware protection mode, the Write Status
Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP2-BP0)
are read only. The SRWD bit defaults to be "0".
Table 5. Status Register
bit7
bit6
bit5
SRWD (status
register write
protect)
0
0
1=status
register write
disabled
0=status
register write
enabled
0
0
bit4
BP2
(level of
protected
block)
bit3
BP1
(level of
protected
block)
(note 1)
(note 1)
Non-volatile
Non-volatile Non-volatile
0
0
bit
bit
bit
note 1: Please refer to the "Table 2. Protected Area Sizes".
bit2
BP0
(level of
protected
block)
(note 1)
Non-volatile
bit
bit1
bit0
WEL
WIP
(write enable
(write in
latch)
progress bit)
1=write
1=write
enable
operation
0=not write 0=not in write
enable
operation
volatile bit
volatile bit
(4) Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the
Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP2-BP0) bits to define the protected area of
memory (as shown in "Table 2. Protected Area Sizes"). The WRSR also can set or reset the Status Register Write
Disable (SRWD) bit in accordance with Write Protection (WP#) pin signal. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered.
The sequence is shown as Figure 16.
The WRSR instruction has no effect on b6, b1, b0 of the status register.
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1
during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL)
bit is reset.
P/N: PM1613
17
Rev. 1.6, August 28, 2017
MX25L8006E
Table 6. Protection Modes
Mode
Software protection
mode (SPM)
Hardware protection
mode (HPM)
Status register condition
WP# and SRWD bit status
Memory
Status register can be written
in (WEL bit is set to "1") and
the SRWD, BP2-BP0
bits can be changed
WP#=1 and SRWD bit=0, or
WP#=0 and SRWD bit=0, or
WP#=1 and SRWD=1
The protected area
cannot
be program or erase.
The SRWD, BP2-BP0 of
status register bits cannot be
changed
WP#=0, SRWD bit=1
The protected area
cannot
be program or erase.
Note:
1. As defined by the values in the Block Protect (BP2-BP0) bits of the Status Register, as shown in "Table 2. Protected Area Sizes".
As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM).
Software Protected Mode (SPM):
- When SRWD bit=0, no matter WP# is low or high, the WREN instruction may set the WEL bit and can change
the values of SRWD, BP2-BP0. The protected area, which is defined by BP2-BP0 is at software protected mode
(SPM).
- When SRWD bit=1 and WP# is high, the WREN instruction may set the WEL bit can change the values of
SRWD, BP2-BP0. The protected area, which is defined by BP2-BP0, is at software protected mode (SPM).
Note: If SRWD bit=1 but WP# is low, it is impossible to write the Status Register even if the WEL bit has previously
been set. It is rejected to write the Status Register and not be executed.
Hardware Protected Mode (HPM):
- When SRWD bit=1, and then WP# is low (or WP# is low before SRWD bit=1), it enters the hardware protected
mode (HPM). The data of the protected area is protected by software protected mode by BP2-BP0 and hardware
protected mode by the WP# to against data modification.
Note: to exit the hardware protected mode requires WP# driving high once the hardware protected mode is entered.
If the WP# pin is permanently connected to high, the hardware protected mode can never be entered; only can use
software protected mode via BP2-BP0.
P/N: PM1613
18
Rev. 1.6, August 28, 2017
MX25L8006E
(5) Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on
the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address
is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can
be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been
reached.
The sequence is shown as Figure 17.
(6) Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and
data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at
any location. The address is automatically increased to the next higher address after each byte data is shifted out,
so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when
the highest address has been reached.
The sequence is shown as Figure 18.
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle.
(7) Dual Output Mode (DREAD)
The DREAD instruction enable double throughput of Serial Flash in read mode. The address is latched on rising
edge of SCLK, and data of every two bits(interleave on 1I/2O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruction, the data out will perform as 2-bit instead of previous 1-bit.
The sequence is shown as Figure 19.
While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
The DREAD only perform read operation. Program/Erase /Read ID/Read status....operation do not support DREAD
throughputs.
(8) Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for
any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before
sending the Sector Erase (SE). Any address of the sector (see "Table 1. Memory Organization") is a valid address
for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of the
address been latched-in); otherwise, the instruction will be rejected and not executed.
Address bits [Am-A12] (Am is the most significant address) select the sector address.
The sequence is shown as Figure 20.
P/N: PM1613
19
Rev. 1.6, August 28, 2017
MX25L8006E
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked out during the Sector Erase cycle is in progress. The WIP sets during the tSE
timing, and clears when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the
page is protected by BP2-BP0 bits, the Sector Erase (SE) instruction will not be executed on the page.
(9) Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for
64K-byte sector erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable
Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (see "Table 1. Memory Organization") is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the
least significant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence is shown as Figure 21.
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets during the tBE timing, and clears when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the page
is protected by BP2-BP0 bits, the Block Erase (BE) instruction will not be executed on the page.
(10) Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). Any address of
the sector (see "Table 1. Memory Organization") is a valid address for Chip Erase (CE) instruction. The CS# must
go high exactly at the byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction
will be rejected and not executed.
The sequence is shown as Figure 22.
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Chip Erase cycle is in progress. The WIP sets during the tCE timing, and clears when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the chip is
protected by BP2-BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when BP2BP0 all set to "0".
(11) Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction
must be executed to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The last address byte (the eight least significant address bits, A7-A0) should be set to 0 for 256 bytes page program. If A7A0 are not all zero, transmitted data that exceed page length are programmed from the starting address (24-bit
address that last 8 bit are all 0) of currently selected page. The CS# must keep during the whole Page Program
cycle. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. If the data bytes sent to the device exceeds 256, the last
256 data byte is programmed at the requested page and previous data will be disregarded. If the data bytes sent to
the device has not exceeded 256, the data will be programmed at the request address of the page. There will be no
effort on the other data bytes of the same page.
The sequence is shown as Figure 23.
P/N: PM1613
20
Rev. 1.6, August 28, 2017
MX25L8006E
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Page Program cycle is in progress. The WIP sets during the tPP
timing, and clears when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the
page is protected by BP2-BP0 bits, the Page Program (PP) instruction will not be executed.
(12) Deep Power-down (DP)
The Deep Power-down (DP) instruction places the device into a minimum power consumption state, Deep Powerdown mode, in which the quiescent current is reduced from ISB1 to ISB2.
The sequence of issuing DP instruction: CS# goes low→ send DP instruction code→ CS# goes high. The CS# must
go high at the byte boundary (after exactly eighth bits of the instruction code have been latched-in); otherwise the
instruction will not be executed. The sequence is shown as Figure 24.
After CS# goes high there is a delay of tDP before the device transitions from Stand-by mode to Deep Power-down
mode and before the current reduces from ISB1 to ISB2. Once in Deep Power-down mode, all instructions will be
ignored except Release from Deep Power-down (RDP).
The device exits Deep Power-down mode and returns to Stand-by mode if it receives a Release from Deep Powerdown (RDP) instruction, power-cycle, or reset.
(13) Release from Deep Power-down (RDP), Read Electronic Signature (RES)
The Release from Deep Power-down (RDP) instruction is completed by driving Chip Select (CS#) High. When Chip
Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the
Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in
the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES1, and Chip Select (CS#) must remain High for at least tRES1(max), as specified in Table 13. Once in the Stand-by Power mode,
the device waits to be selected, so that it can receive, decode and execute instructions.
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as "Table 7. ID
DEFINITIONS". This is not the same as RDID instruction. It is not recommended to use for new design. For new design, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/
erase/write cycle in progress.
The sequence is shown in Figure 25 and Figure 26.
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously
in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in
Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least
tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute
instruction.
The RDP instruction is for releasing from Deep Power Down Mode.
P/N: PM1613
21
Rev. 1.6, August 28, 2017
MX25L8006E
(14) Read Identification (RDID)
The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC
Manufacturer ID and Device ID are listed as "Table 7. ID DEFINITIONS".
The sequence is shown as Figure 27.
While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.
(15) Read Electronic Manufacturer ID & Device ID (REMS)
The REMS instruction returns both the JEDEC assigned manufacturer ID and the device ID. The Device ID values
are listed in "Table 7. ID DEFINITIONS".
The REMS instruction is initiated by driving the CS# pin low and sending the instruction code "90h" followed by two
dummy bytes and one address byte (A7-A0). After which the manufacturer ID for Macronix (C2h) and the device
ID are shifted out on the falling edge of SCLK with the most significant bit (MSB) first as shown in "Figure 28. Read
Electronic Manufacturer & Device ID (REMS) Sequence (Command 90)". If the address byte is 00h, the manufacturer ID will be output first, followed by the device ID. If the address byte is 01h, then the device ID will be output
first, followed by the manufacturer ID. While CS# is low, the manufacturer and device IDs can be read continuously,
alternating from one to the other. The instruction is completed by driving CS# high.
Table 7. ID DEFINITIONS
Command Type
RDID Command
Manufacturer ID
C2
RES Command
REMS
Manufacturer ID
C2
MX25L8006E
Memory Type
20
Electronic ID
13
Device ID
13
Memory Density
14
(16) Enter Secured OTP (ENSO)
The ENSO instruction is for entering the additional 512 bit secured OTP mode. While the device is in 512 bit secured OTP mode, array access is not available. The additional 512 bit secured OTP is independent from main array,
and may be used to store unique serial number for system identifier. After entering the Secured OTP mode, follow
standard read or program, procedure to read out the data or update data. The Secured OTP data cannot be updated again once it is lock-down.
Please note that WRSR/WRSCUR commands are not acceptable during the access of secure OTP region, once security OTP is lock down, only read related commands are valid.
(17) Exit Secured OTP (EXSO)
The EXSO instruction is for exiting the additional 512 bit secured OTP mode.
P/N: PM1613
22
Rev. 1.6, August 28, 2017
MX25L8006E
(18) Read Security Register (RDSCUR)
The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read
at any time (even in program/erase/write status register/write security register condition) and continuously.
The sequence is shown as Figure 29.
The definition of the Security Register bits is as below:
Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory or not. When it is
"0", it indicates non- factory lock; "1" indicates factory- lock.
Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for customer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 512 bit Secured OTP
area cannot be updated any more.
Table 8. SECURITY REGISTER DEFINITION
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
x
x
x
x
x
x
LDSO
(indicate if
lock-down
Secured OTP
indicator bit
0 = nonfactory
lock
1 = factory
lock
non-volatile bit
reserved
reserved
reserved
reserved
reserved
reserved
0 = not lockdown
1 = lock-down
(cannot
program/erase
OTP)
volatile bit
volatile bit
volatile bit
volatile bit
volatile bit
volatile bit
non-volatile bit
(19) Write Security Register (WRSCUR)
The WRSCUR instruction is for changing the values of Security Register Bits. Unlike write status register, the WREN
instruction is not required before sending WRSCUR instruction. The WRSCUR instruction may change the values
of bit1 (LDSO bit) for customer to lock-down the 512 bit Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area cannot be updated any more.
The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
The sequence is shown as Figure 30.
P/N: PM1613
23
Rev. 1.6, August 28, 2017
MX25L8006E
(20) Read SFDP Mode (RDSFDP)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional
and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables
can be interrogated by host system software to enable adjustments needed to accommodate divergent features
from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on
CFI.
The sequence of issuing RDSFDP instruction is CS# goes low→send RDSFDP instruction (5Ah)→send 3 address
bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP operation can use CS#
to high at any time during data out.
SFDP is a standard of JEDEC. JESD216. v1.0.
Figure 3. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
SO
24 BIT ADDRESS
23 22 21
5Ah
3
2
1
0
High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Cycle
SI
7
6
5
4
3
2
1
0
DATA OUT 2
DATA OUT 1
SO
7
6
5
3
2
1
0
7
MSB
MSB
P/N: PM1613
4
24
6
5
4
3
2
1
0
7
MSB
Rev. 1.6, August 28, 2017
MX25L8006E
Table 9. Signature and Parameter Identification Data Values
SFDP Table below is for MX25L8006EM1I-12G, MX25L8006EM2I-12G, MX25L8006EPI-12G, MX25L8006EZNI12G and MX25L8006EZUI-12G
Description
SFDP Signature
Comment
Fixed: 50444653h
Add (h) DW Add Data (h/b) Data
(Byte)
(Bit)
(Note1)
(h)
00h
07:00
53h
53h
01h
15:08
46h
46h
02h
23:16
44h
44h
03h
31:24
50h
50h
SFDP Minor Revision Number
Start from 00h
04h
07:00
00h
00h
SFDP Major Revision Number
Start from 01h
This number is 0-based. Therefore,
0 indicates 1 parameter header.
05h
15:08
01h
01h
06h
23:16
01h
01h
07h
31:24
FFh
FFh
00h: it indicates a JEDEC specified
header.
08h
07:00
00h
00h
Start from 00h
09h
15:08
00h
00h
Start from 01h
0Ah
23:16
01h
01h
How many DWORDs in the
Parameter table
0Bh
31:24
09h
09h
0Ch
07:00
30h
30h
0Dh
15:08
00h
00h
0Eh
23:16
00h
00h
0Fh
31:24
FFh
FFh
it indicates Macronix manufacturer
ID
10h
07:00
C2h
C2h
Start from 00h
11h
15:08
00h
00h
Start from 01h
12h
23:16
01h
01h
How many DWORDs in the
Parameter table
13h
31:24
04h
04h
14h
07:00
60h
60h
15h
15:08
00h
00h
16h
23:16
00h
00h
17h
31:24
FFh
FFh
Number of Parameter Headers
Unused
ID number (JEDEC)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length
(in double word)
Parameter Table Pointer (PTP)
First address of JEDEC Flash
Parameter table
Unused
ID number
(Macronix manufacturer ID)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length
(in double word)
Parameter Table Pointer (PTP)
First address of Macronix Flash
Parameter table
Unused
P/N: PM1613
25
Rev. 1.6, August 28, 2017
MX25L8006E
Table 10. Parameter Table (0): JEDEC Flash Parameter Tables
SFDP Table below is for MX25L8006EM1I-12G, MX25L8006EM2I-12G, MX25L8006EPI-12G, MX25L8006EZNI12G and MX25L8006EZUI-12G
Description
Comment
Block/Sector Erase sizes
00: Reserved, 01: 4KB erase,
10: Reserved,
11: not support 4KB erase
Write Granularity
0: 1Byte, 1: 64Byte or larger
Write Enable Instruction Required 0: not required
1: required 00h to be written to the
for Writing to Volatile Status
status register
Registers
Add (h) DW Add Data (h/b)
(Byte)
(Bit)
(Note1)
01b
02
1b
03
0b
30h
0: use 50h opcode,
1: use 06h opcode
Write Enable Opcode Select for
Note: If target flash status register is
Writing to Volatile Status Registers
nonvolatile, then bits 3 and 4 must
be set to 00b.
Contains 111b and can never be
Unused
changed
4KB Erase Opcode
01:00
31h
Data
(h)
E5h
04
0b
07:05
111b
15:08
20h
16
1b
18:17
00b
19
0b
20
0b
20h
(1-1-2) Fast Read (Note2)
0=not support 1=support
Address Bytes Number used in
addressing flash array
Double Transfer Rate (DTR)
Clocking
00: 3Byte only, 01: 3 or 4Byte,
10: 4Byte only, 11: Reserved
(1-2-2) Fast Read
0=not support 1=support
(1-4-4) Fast Read
0=not support 1=support
21
0b
(1-1-4) Fast Read
0=not support 1=support
22
0b
23
1b
33h
31:24
FFh
37h:34h
31:00
007F FFFFh
0=not support 1=support
32h
Unused
Unused
Flash Memory Density
(1-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
states (Note3)
Clocks) not support
(1-4-4) Fast Read Number of
000b: Mode Bits not support
Mode Bits (Note4)
38h
(1-4-4) Fast Read Opcode
39h
(1-1-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
states
Clocks) not support
(1-1-4) Fast Read Number of
000b: Mode Bits not support
Mode Bits
3Ah
(1-1-4) Fast Read Opcode
3Bh
P/N: PM1613
26
04:00
0 0000b
07:05
000b
15:08
FFh
20:16
0 0000b
23:21
000b
31:24
FFh
81h
FFh
00h
FFh
00h
FFh
Rev. 1.6, August 28, 2017
MX25L8006E
SFDP Table below is for MX25L8006EM1I-12G, MX25L8006EM2I-12G, MX25L8006EPI-12G, MX25L8006EZNI12G and MX25L8006EZUI-12G
Description
Comment
(1-1-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy
states
Clocks) not support
(1-1-2) Fast Read Number of
000b: Mode Bits not support
Mode Bits
(1-1-2) Fast Read Opcode
Add (h) DW Add Data (h/b)
(Byte)
(Bit)
(Note1)
3Ch
3Dh
(1-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy
states
Clocks) not support
(1-2-2) Fast Read Number of
000b: Mode Bits not support
Mode Bits
3Eh
(1-2-2) Fast Read Opcode
3Fh
(2-2-2) Fast Read
0=not support 1=support
Unused
(4-4-4) Fast Read
0=not support 1=support
40h
Unused
04:00
0 1000b
07:05
000b
15:08
3Bh
20:16
0 0000b
23:21
000b
31:24
FFh
00
0b
03:01
111b
04
0b
07:05
111b
Data
(h)
08h
3Bh
00h
FFh
EEh
Unused
43h:41h
31:08
FFh
FFh
Unused
45h:44h
15:00
FFh
FFh
20:16
0 0000b
23:21
000b
(2-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy
states
Clocks) not support
(2-2-2) Fast Read Number of
000b: Mode Bits not support
Mode Bits
46h
(2-2-2) Fast Read Opcode
47h
31:24
FFh
FFh
49h:48h
15:00
FFh
FFh
20:16
0 0000b
23:21
000b
Unused
00h
(4-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
states
Clocks) not support
(4-4-4) Fast Read Number of
000b: Mode Bits not support
Mode Bits
4Ah
(4-4-4) Fast Read Opcode
4Bh
31:24
FFh
FFh
4Ch
07:00
0Ch
0Ch
4Dh
15:08
20h
20h
4Eh
23:16
10h
10h
4Fh
31:24
D8h
D8h
50h
07:00
00h
00h
51h
15:08
FFh
FFh
52h
23:16
00h
00h
53h
31:24
FFh
FFh
Sector Type 1 Size
Sector/block size = 2^N bytes (Note5)
0x00b: this sector type doesn't exist
Sector Type 1 erase Opcode
Sector Type 2 Size
Sector/block size = 2^N bytes
0x00b: this sector type doesn't exist
Sector Type 2 erase Opcode
Sector Type 3 Size
Sector/block size = 2^N bytes
0x00b: this sector type doesn't exist
Sector Type 3 erase Opcode
Sector Type 4 Size
Sector/block size = 2^N bytes
0x00b: this sector type doesn't exist
Sector Type 4 erase Opcode
P/N: PM1613
27
00h
Rev. 1.6, August 28, 2017
MX25L8006E
Table 11. Parameter Table (1): Macronix Flash Parameter Tables
SFDP Table below is for MX25L8006EM1I-12G, MX25L8006EM2I-12G, MX25L8006EPI-12G, MX25L8006EZNI12G and MX25L8006EZUI-12G
Description
Vcc Supply Maximum Voltage
Vcc Supply Minimum Voltage
Comment
2000h=2.000V
2700h=2.700V
3600h=3.600V
1650h=1.650V, 1750h=1.750V
2250h=2.250V, 2350h=2.350V
2650h=2.650V, 2700h=2.700V
Add (h) DW Add Data (h/b)
(Byte)
(Bit)
(Note1)
Data
(h)
61h:60h
07:00
15:08
00h
36h
00h
36h
63h:62h
23:16
31:24
00h
27h
00h
27h
H/W Reset# pin
0=not support 1=support
00
0b
H/W Hold# pin
0=not support 1=support
01
1b
Deep Power Down Mode
0=not support 1=support
02
1b
S/W Reset
0=not support 1=support
03
0b
S/W Reset Opcode
Reset Enable (66h) should be
issued before Reset Opcode
Program Suspend/Resume
0=not support 1=support
12
0b
Erase Suspend/Resume
0=not support 1=support
13
0b
14
1b
15
0b
66h
23:16
FFh
FFh
67h
31:24
FFh
FFh
65h:64h
Unused
Wrap-Around Read mode
0=not support 1=support
Wrap-Around Read mode Opcode
11:04
1111 1111b
4FF6h
(FFh)
Wrap-Around Read data length
08h:support 8B wrap-around read
16h:8B&16B
32h:8B&16B&32B
64h:8B&16B&32B&64B
Individual block lock
0=not support 1=support
00
0b
Individual block lock bit
(Volatile/Nonvolatile)
0=Volatile 1=Nonvolatile
01
1b
09:02
1111 1111b
(FFh)
10
1b
11
1b
Individual block lock Opcode
Individual block lock Volatile
protect bit default protect status
0=protect 1=unprotect
Secured OTP
0=not support 1=support
Read Lock
0=not support 1=support
12
0b
Permanent Lock
0=not support 1=support
13
0b
Unused
15:14
11b
Unused
31:16
FFh
FFh
31:00
FFh
FFh
Unused
6Bh:68h
6Fh:6Ch
CFFEh
MX25L8006EM1I-12G-SFDP_2014-10-14
P/N: PM1613
28
Rev. 1.6, August 28, 2017
MX25L8006E
Note 1: h/b is hexadecimal or binary.
Note 2: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x),
address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1),
(2-2-2), and (4-4-4)
Note 3: Wait States is required dummy clock cycles after the address bits or optional mode bits.
Note 4: Mode Bits is optional control bits that follow the address bits. These bits are driven by the system
controller if they are specified. (eg,read performance enhance toggling bits)
Note 5: 4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h
Note 6: All unused and undefined area data is blank FFh for SFDP Tables that are defined in Parameter
Identification Header. All other areas beyond defined SFDP Table are reserved by Macronix.
P/N: PM1613
29
Rev. 1.6, August 28, 2017
MX25L8006E
POWER-ON STATE
The device is at the following states after power-up:
- Standby mode ( please note it is not deep power-down mode)
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage until the VCC reaches the following levels:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change
during power up state.
For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not
guaranteed. The read, write, erase, and program command should be sent after the below time delay:
- tVSL after VCC reached VCC minimum level
The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.
Please refer to "Figure 31. Power-up Timing".
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended.(generally around 0.1uF)
INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status
Register contains 00h (all Status Register bits are 0).
P/N: PM1613
30
Rev. 1.6, August 28, 2017
MX25L8006E
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
RATING
VALUE
Ambient Operating Temperature
Industrial grade
-40°C to 85°C
Storage Temperature
-65°C to 150°C
Applied Input Voltage
-0.5V to VCC+0.5V
Applied Output Voltage
-0.5V to VCC+0.5V
VCC to Ground Potential
-0.5V to 4.0V
NOTICE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is stress rating only and functional operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended period may affect reliability.
2. Specifications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see "Figure 4.
Maximum Negative Overshoot Waveform" and "Figure 5. Maximum Positive Overshoot Waveform".
Figure 4. Maximum Negative Overshoot Waveform
20ns
Figure 5. Maximum Positive Overshoot Waveform
20ns
20ns
Vss
Vcc + 2.0V
Vss-2.0V
Vcc
20ns
20ns
20ns
CAPACITANCE TA = 25°C, f = 1.0 MHz
Symbol
CIN
COUT
P/N: PM1613
Parameter
Input Capacitance
Output Capacitance
Min.
Typ.
31
Max.
6
8
Unit
pF
pF
Conditions
VIN = 0V
VOUT = 0V
Rev. 1.6, August 28, 2017
MX25L8006E
Figure 6. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL
Input timing reference level
0.8VCC
0.2VCC
Output timing reference level
0.7VCC
AC
Measurement
Level
0.3VCC
0.5VCC
Note: Input pulse rise and fall time are
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