MX25U12832F
MX25U12832F
1.8V, 128M-BIT [x 1/x 2/x 4]
CMOS MXSMIO® (SERIAL MULTI I/O)
FLASH MEMORY
Key Features
• Protocol Support - Single I/O, Dual I/O and Quad I/O
• Quad Peripheral Interface (QPI) available
• Support clock frequency up to 133MHz
• Program/Erase Suspend and Resume
• Additional 8K-bit secured OTP
P/N: PM2642
Macronix Proprietary
1
Rev. 1.2, November 21, 2019
MX25U12832F
Contents
1. FEATURES............................................................................................................................................................... 4
2. GENERAL DESCRIPTION...................................................................................................................................... 5
Table 1. Read performance Comparison.....................................................................................................5
3. PIN CONFIGURATIONS .......................................................................................................................................... 6
4. PIN DESCRIPTION................................................................................................................................................... 6
5. BLOCK DIAGRAM.................................................................................................................................................... 7
6. DATA PROTECTION................................................................................................................................................. 8
Table 2. Protected Area Sizes......................................................................................................................9
Table 3. 8K-bit Secured OTP Definition.....................................................................................................10
7. Memory Organization............................................................................................................................................ 11
Table 4. Memory Organization................................................................................................................... 11
8. DEVICE OPERATION............................................................................................................................................. 12
8-1. Quad Peripheral Interface (QPI) Read Mode........................................................................................... 14
9. COMMAND DESCRIPTION.................................................................................................................................... 15
9-1.
9-2.
9-3.
9-4.
9-5.
9-6.
9-7.
9-8.
9-9.
9-10.
9-11.
9-12.
9-13.
9-14.
9-15.
9-16.
9-17.
9-18.
9-19.
9-20.
9-21.
9-22.
9-23.
P/N: PM2642
Table 5. Command Set...............................................................................................................................15
Write Enable (WREN)............................................................................................................................... 18
Write Disable (WRDI)................................................................................................................................ 19
Factory Mode Enable (FMEN).................................................................................................................. 20
Read Identification (RDID)........................................................................................................................ 21
Read Electronic Signature (RES)............................................................................................................. 22
Read Electronic Manufacturer ID & Device ID (REMS)............................................................................ 23
QPI ID Read (QPIID)................................................................................................................................ 24
Table 6. ID Definitions ...............................................................................................................................24
Read Status Register (RDSR).................................................................................................................. 25
Read Configuration Register (RDCR)....................................................................................................... 26
Table 7. Status Register.............................................................................................................................29
Table 8. Configuration Register Table........................................................................................................30
Table 9. Output Driver Strength Table........................................................................................................31
Table 10. Dummy Cycle and Frequency Table (MHz)................................................................................31
Write Status Register (WRSR).................................................................................................................. 32
Table 11. Protection Modes........................................................................................................................33
Read Data Bytes (READ)......................................................................................................................... 36
Read Data Bytes at Higher Speed (FAST_READ)................................................................................... 37
Dual Output Read Mode (DREAD)........................................................................................................... 38
2 x I/O Read Mode (2READ).................................................................................................................... 39
Quad Read Mode (QREAD)..................................................................................................................... 40
4 x I/O Read Mode (4READ).................................................................................................................... 41
Burst Read................................................................................................................................................ 43
Performance Enhance Mode.................................................................................................................... 44
Sector Erase (SE)..................................................................................................................................... 47
Block Erase (BE32K)................................................................................................................................ 48
Block Erase (BE)...................................................................................................................................... 49
Chip Erase (CE)........................................................................................................................................ 50
Page Program (PP).................................................................................................................................. 51
Macronix Proprietary
2
Rev. 1.2, November 21, 2019
MX25U12832F
9-24.
9-25.
9-26.
9-27.
9-28.
9-29.
9-30.
9-31.
4 x I/O Page Program (4PP)..................................................................................................................... 53
Factory Mode Erase/Program Operations................................................................................................ 54
Read Factory Mode Status....................................................................................................................... 56
Deep Power-down (DP)............................................................................................................................ 57
Enter Secured OTP (ENSO)..................................................................................................................... 58
Exit Secured OTP (EXSO)........................................................................................................................ 58
Read Security Register (RDSCUR).......................................................................................................... 59
Write Security Register (WRSCUR).......................................................................................................... 60
Table 12. Security Register Definition........................................................................................................61
9-32. Write Protection Selection (WPSEL)......................................................................................................... 62
9-33. Advanced Sector Protection..................................................................................................................... 64
Table 13. Lock Register..............................................................................................................................65
Table 14. SPB Register..............................................................................................................................66
Table 15. DPB Register..............................................................................................................................68
9-34. Program Suspend and Erase Suspend.................................................................................................... 70
Table 16. Readable Area of Memory While a Program or Erase Operation is Suspended........................70
Table 17. Acceptable Commands During Program/Erase Suspend after tPSL/tESL.................................71
Table 18. Acceptable Commands During Suspend (tPSL/tESL not required)............................................71
9-35. Program Resume and Erase Resume...................................................................................................... 72
9-36. No Operation (NOP)................................................................................................................................. 73
9-37. Software Reset (Reset-Enable (RSTEN) and Reset (RST)).................................................................... 73
9-38. Read SFDP Mode (RDSFDP)................................................................................................................... 75
10. RESET.................................................................................................................................................................. 76
Table 19. Reset Timing-(Power On)...........................................................................................................76
Table 20. Reset Timing-(Other Operation).................................................................................................76
11. POWER-ON STATE.............................................................................................................................................. 77
12. ELECTRICAL SPECIFICATIONS......................................................................................................................... 78
Table 21. ABSOLUTE MAXIMUM RATINGS.............................................................................................78
Table 22. CAPACITANCE TA = 25°C, f = 1.0 MHz.....................................................................................78
Table 23. DC CHARACTERISTICS ..........................................................................................................80
Table 24. AC CHARACTERISTICS ..........................................................................................................81
13. OPERATING CONDITIONS.................................................................................................................................. 83
Table 25. Power-Up/Down Voltage and Timing..........................................................................................85
13-1. INITIAL DELIVERY STATE....................................................................................................................... 85
14. ERASE AND PROGRAMMING PERFORMANCE............................................................................................... 86
15. ERASE AND PROGRAMMING PERFORMANCE (Factory Mode) ................................................................... 86
16. DATA RETENTION............................................................................................................................................... 87
17. LATCH-UP CHARACTERISTICS......................................................................................................................... 87
18. ORDERING INFORMATION................................................................................................................................. 88
19. PART NAME DESCRIPTION................................................................................................................................ 89
20. PACKAGE INFORMATION................................................................................................................................... 90
20-1. 8-pin SOP (200mil)................................................................................................................................... 90
20-2. 8-land WSON (6x5mm)............................................................................................................................ 91
20-3. 16-pin SOP (300mil)................................................................................................................................. 92
20-4. 8-land WSON (8x6mm 3.4 x 4.3EP)......................................................................................................... 93
21. REVISION HISTORY ............................................................................................................................................ 94
P/N: PM2642
Macronix Proprietary
3
Rev. 1.2, November 21, 2019
MX25U12832F
1.8V 128M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O)
FLASH MEMORY
1. FEATURES
GENERAL
• Supports Serial Peripheral Interface -- Mode 0 and
Mode 3
• Single Power Supply Operation
- 1.65 to 2.0 volt for read, erase, and program
operations
• 134,217,728 x 1 bit structure
or 67,108,864 x 2 bits (two I/O mode) structure
or 33,554,432 x 4 bits (four I/O mode) structure
• Protocol Support
- Single I/O, Dual I/O and Quad I/O
• Latch-up protected to 100mA from -1V to Vcc +1V
• Fast read for SPI mode
- Support clock frequency up to 133MHz for all
protocols
- Support Fast Read, 2READ, DREAD, 4READ,
QREAD instructions.
- Configurable dummy cycle number for fast read
operation
• Quad Peripheral Interface (QPI) available
• Equal Sectors with 4K byte each, or Equal Blocks
with 32K byte each or Equal Blocks with 64K byte
each
- Any Block can be erased individually
• Programming :
- 256byte page buffer
- Quad Input/Output page program(4PP) to enhance
program performance
• Typical 100,000 erase/program cycles
• 20 years data retention
• Command Reset
• Program/Erase Suspend and Resume operation
• Electronic Identification
- JEDEC 1-byte manufacturer ID and 2-byte device
ID
- RES command for 1-byte Device ID
- REMS command for 1-byte manufacturer ID and
1-byte device ID
• Support Serial Flash Discoverable Parameters
(SFDP) mode
HARDWARE FEATURES
• SCLK Input
- Serial clock input
• SI/SIO0
- Serial Data Input or Serial Data Input/Output for 2
x I/O read mode and 4 x I/O read mode
• SO/SIO1
- Serial Data Output or Serial Data Input/Output for
2 x I/O read mode and 4 x I/O read mode
• WP#/SIO2
- Hardware write protection or Serial Data Input/
Output for 4 x I/O read mode
• RESET#
- Hardware Reset pin
• DNU/SIO3
- Do not use or Serial Data Input/Output for 4xI/O
read mode
• RESET#/SIO3
- Hardware Reset pin or Serial Data Input/Output for
4 x I/O read mode
• PACKAGE
- 8-pin SOP (200mil)
- 8-land WSON (6x5mm)
- 8-land WSON (8x6mm 3.4 x 4.3EP)
-16-pin SOP (300mil)
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block lock protection
The BP0-BP3 and T/B status bit defines the size of
the area to be protection against program and erase
instructions
- Advanced sector protection function (Solid Protect)
• Additional 8K bit security OTP
- Features unique identifier
- Factory locked identifiable, and customer lockable
P/N: PM2642
- All devices are RoHS Compliant and Halogenfree
Macronix Proprietary
4
Rev. 1.2, November 21, 2019
MX25U12832F
2. GENERAL DESCRIPTION
MX25U12832F is 128Mb bits Serial NOR Flash memory, which is configured as 16,777,216 x 8 internally. When it is
in two or four I/O mode, the structure becomes 67,108,864 bits x 2 or 33,554,432 bits x 4. MX25U12832F features
a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single I/O
mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial
access to the device is enabled by CS# input.
When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# and RESET# pin (of the 8-pin packages) become SIO0 pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output.
The MX25U12832F MXSMIO (Serial Multi I/O) provides sequential read operation on the whole chip.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis, or word basis. Erase command is executed on 4K-byte sector, 32K-byte block, or 64K-byte block, or
whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
Advanced security features enhance the protection and security functions, please refer to the security features section for more details.
When the device is not in operation and CS# is high, it will remain in standby mode.
The MX25U12832F utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after
100,000 program and erase cycles.
Table 1. Read performance Comparison
Numbers
of Dummy
Cycles
Fast Read
(MHz)
Dual Output
Fast Read
(MHz)
Quad Output
Fast Read
(MHz)
Dual IO
Fast Read
(MHz)
Quad IO
Fast Read
(MHz)
Quad IO Fast
Read (QPI)
(MHz)
4
-
-
-
84*
66
66
6
104
104
84
104
84*
84*
8
104*
104*
104*
104
104
104
10
133
133
133
133
133
133
Note: * mean default status.
P/N: PM2642
Macronix Proprietary
5
Rev. 1.2, November 21, 2019
MX25U12832F
3. PIN CONFIGURATIONS
4. PIN DESCRIPTION
8-PIN SOP (200mil)
CS#
SO/SIO1
WP#/SIO2
GND
1
2
3
4
8
7
6
5
SYMBOL
CS#
DESCRIPTION
Chip Select
Serial Data Input (for 1 x I/O)/ Serial
SI/SIO0
Data Input & Output (for 2xI/O or 4xI/O
read mode)
Serial Data Output (for 1 x I/O)/ Serial
SO/SIO1
Data Input & Output (for 2xI/O or 4xI/O
read mode)
SCLK
Clock Input
Write protection Active low or Serial
WP#/SIO2 Data Input & Output (for 4xI/O read
mode)
RESET#
Hardware Reset Pin Active low
Hardware Reset Pin Active low or
RESET#/SIO3 Serial Data Input & Output (for 4xI/O
read mode)
Do not use or Serial Data Input &
DNU/SIO3
Output (for 4xI/O read mode)
VCC
+ 1.8V Power Supply
GND
Ground
Notes:
The pin of RESET#/SIO3 or WP#/SIO2 will remain
internal pull up function while this pin is not physically
connected in system configuration.
However, the internal pull up function will be disabled if
the system has physical connection to RESET#/SIO3
or WP#/SIO2 pin.
VCC
RESET#/SIO3
SCLK
SI/SIO0
8-WSON (6x5mm, 8x6mm 3.4 x 4.3EP)
1
2
3
4
CS#
SO/SIO1
WP#/SIO2
GND
8
7
6
5
VCC
RESET#/SIO3
SCLK
SI/SIO0
16-PIN SOP (300mil)
DNU/SIO3
VCC
RESET#
NC
NC
NC
CS#
SO/SIO1
P/N: PM2642
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SCLK
SI/SIO0
NC
NC
NC
NC
GND
WP#/SIO2
Macronix Proprietary
6
Rev. 1.2, November 21, 2019
MX25U12832F
5. BLOCK DIAGRAM
X-Decoder
Address
Generator
SI/SIO0
SO/SIO1
SIO2 *
SIO3 *
Y-Decoder
Data
Register
WP# *
HOLD# *
RESET# *
CS#
SCLK
Memory Array
Sense
Amplifier
SRAM
Buffer
Mode
Logic
State
Machine
HV
Generator
Clock Generator
Output
Buffer
* Depends on part number options.
P/N: PM2642
Macronix Proprietary
7
Rev. 1.2, November 21, 2019
MX25U12832F
6. DATA PROTECTION
During power transition, there may be some false system level signals which result in inadvertent erasure or
programming. The device is designed to protect itself from these accidental write cycles.
The state machine will be reset as standby mode automatically during power up. In addition, the control register
architecture of the device constrains that the memory contents can only be changed after specific command
sequences have completed successfully.
In the following, there are several features to protect the system from the accidental write cycles during VCC powerup and power-down or from system noise.
• Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
other command to change data.
• Deep Power Down Mode: By entering deep power down mode, the flash device is under protected from writing
all commands except toggling the CS#. For more details, please refer to "9-27. Deep Power-down (DP)".
• Advanced Security Features: there are some protection and security features which protect content from inadvertent write and hostile access.
P/N: PM2642
Macronix Proprietary
8
Rev. 1.2, November 21, 2019
MX25U12832F
I. Block lock protection
- The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0 and T/B) bits to allow part of memory to be
protected as read only. The protected area definition is shown as "Table 2. Protected Area Sizes", the protected
areas are more flexible which may protect various area by setting value of BP0-BP3 bits.
- The Hardware Protected Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and Status Register Write Protect bit.
- In four I/O and QPI mode, the feature of HPM will be disabled.
Table 2. Protected Area Sizes
Protected Area Sizes (T/B bit = 0)
Status bit
BP3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
BP2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
BP1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
BP0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Protect Level
128Mb
0 (none)
1 (1 block, protected block 255th)
2 (2 blocks, block 254th-255th)
3 (4 blocks, block 252nd-255th)
4 (8 blocks, block 248th-255th)
5 (16 blocks, block 240th-255th)
6 (32 blocks, block 224th-255th)
7 (64 blocks, block 192nd-255th)
8 (128 blocks, block 128th-255th)
9 (256 blocks, protected all)
10 (256 blocks, protected all)
11 (256 blocks, protected all)
12 (256 blocks, protected all)
13 (256 blocks, protected all)
14 (256 blocks, protected all)
15 (256 blocks, protected all)
Protected Area Sizes (T/B bit = 1)
Status bit
BP3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
P/N: PM2642
BP2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
BP1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
BP0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Protect Level
128Mb
0 (none)
1 (1 block, protected block 0th)
2 (2 blocks, protected block 0th-1st)
3 (4 blocks, protected block 0th-3rd)
4 (8 blocks, protected block 0th-7th)
5 (16 blocks, protected block 0th-15th)
6 (32 blocks, protected block 0th-31st)
7 (64 blocks, protected block 0th-63rd)
8 (128 blocks, protected block 0th-127th)
9 (256 blocks, protected all)
10 (256 blocks, protected all)
11 (256 blocks, protected all)
12 (256 blocks, protected all)
13 (256 blocks, protected all)
14 (256 blocks, protected all)
15 (256 blocks, protected all)
Macronix Proprietary
9
Rev. 1.2, November 21, 2019
MX25U12832F
II. Additional 8K-bit secured OTP for unique identifier: to provide 8K-bit One-Time Program area for setting device
unique serial number - Which may be set by factory or system maker.
The 8K-bit secured OTP area is composed of two rows of 4K-bit. Customer could lock the first 4K-bit OTP area
and factory could lock the other.
- Security register bit 0 indicates whether the second 4K-bit is locked by factory or not.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register) command to set customer lock-down bit1 as "1". Please refer to "Table 12. Security Register Definition" for security
register bit definition and "Table 3. 8K-bit Secured OTP Definition" for address range definition.
- To program 8K-bit secured OTP by entering secured OTP mode (with ENSO command), and going through normal program procedure, and then exiting secured OTP mode by writing EXSO command.
Note: Once lock-down whatever by factory or customer, the corresponding secured area cannot be changed any
more. While in 8K-bit Secured OTP mode, array access is not allowed.
Table 3. 8K-bit Secured OTP Definition
Address range
Size
Customer Lock
Standard Factory Lock
xxx000-xxx1FF
4096-bit
Determined by customer
N/A
xxx200-xxx3FF
4096-bit
N/A
Determined by factory
P/N: PM2642
Macronix Proprietary
10
Rev. 1.2, November 21, 2019
MX25U12832F
7. Memory Organization
Table 4. Memory Organization
Block(64K-byte) Block(32K-byte)
Sector
254
508
individual block
lock/unlock unit:64K-byte
507
253
506
FF8FFFh
4087
FF7000h
FF7FFFh
…
individual 16 sectors
lock/unlock unit:4K-byte
4080
FF0000h
FF0FFFh
4079
FEF000h
FEFFFFh
…
509
FF8000h
4072
FE8000h
FE8FFFh
4071
FE7000h
FE7FFFh
…
510
4088
4064
FE0000h
FE0FFFh
4063
FDF000h
FDFFFFh
…
255
FFFFFFh
4056
FD8000h
FD8FFFh
4055
FD7000h
FD7FFFh
4048
FD0000h
FD0FFFh
47
02F000h
02FFFFh
…
511
Address Range
FFF000h
…
4095
1
2
1
0
0
027FFFh
…
028FFFh
027000h
32
020000h
020FFFh
31
01F000h
01FFFFh
…
3
028000h
39
24
018000h
018FFFh
23
017000h
017FFFh
…
4
individual block
lock/unlock unit:64K-byte
40
16
010000h
010FFFh
15
00F000h
00FFFFh
8
008000h
008FFFh
7
007000h
007FFFh
000000h
000FFFh
…
2
0
P/N: PM2642
individual 16 sectors
lock/unlock unit:4K-byte
…
5
…
individual block
lock/unlock unit:64K-byte
Macronix Proprietary
11
Rev. 1.2, November 21, 2019
MX25U12832F
8. DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation.
2. When incorrect command is inputted to this device, this device becomes standby mode and keeps the standby
mode until next CS# falling edge. In standby mode, SO pin of this device should be High-Z.
3. When correct command is inputted to this device, this device becomes active mode and keeps the active mode
until next CS# rising edge.
4. Input data is latched on the rising edge of Serial Clock (SCLK) and data shifts out on the falling edge of SCLK.
The difference of Serial mode 0 and mode 3 is shown as "Figure 1. Serial Modes Supported".
5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, 2READ, DREAD, 4READ, QREAD,
W4READ, RDSFDP, RES, REMS, QPIID, RDDPB, RDSPB, RDLR, RDCR the shifted-in instruction sequence
is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE32K, BE, CE, PP, 4PP, DP, ENSO, EXSO, WRSCUR, WPSEL,
GBLK, GBULK, SUSPEND, RESUME, NOP, RSTEN, RST, EQIO, RSTQIO the CS# must go high exactly at the
byte boundary; otherwise, the instruction will be rejected and not executed.
6. While a Write Status Register, Program, or Erase operation is in progress, access to the memory array is neglected and will not affect the current operation of Write Status Register, Program, Erase.
Figure 1. Serial Modes Supported
CPOL
CPHA
shift in
(Serial mode 0)
0
0
SCLK
(Serial mode 3)
1
1
SCLK
SI
shift out
MSB
SO
MSB
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is
supported.
P/N: PM2642
Macronix Proprietary
12
Rev. 1.2, November 21, 2019
MX25U12832F
Figure 2. Serial Input Timing
tSHSL
CS#
tCHSL
tSLCH
tCHSH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
tCLCH
LSB
MSB
SI
High-Z
SO
Figure 3. Output Timing
CS#
tCH
SCLK
tCLQV
tCLQX
tCL
tCLQV
tCLQX
LSB
SO
SI
P/N: PM2642
tSHQZ
ADDR.LSB IN
Macronix Proprietary
13
Rev. 1.2, November 21, 2019
MX25U12832F
8-1. Quad Peripheral Interface (QPI) Read Mode
QPI protocol enables user to take full advantage of Quad I/O Serial NOR Flash by providing the Quad I/O interface
in command cycles, address cycles and as well as data output cycles.
Enable QPI mode
By issuing EQIO command (35h), the QPI mode is enabled. After QPI mode has been enabled, the device enter
quad mode (4-4-4) without QE bit status changed.
Figure 4. Enable QPI Sequence
CS#
MODE 3
SCLK
0
1
2
3
4
5
6
7
MODE 0
SIO0
35h
SIO[3:1]
Reset QPI (RSTQIO)
To reset the QPI mode, the RSTQIO (F5h) command is required. After the RSTQIO command is issued, the device
returns from QPI mode (4 I/O interface in command cycles) to SPI mode (1 I/O interface in command cycles).
Note:
For EQIO and RSTQIO commands, CS# high width has to follow "From Write/Erase/Program to Read Status
Register spec" tSHSL (as defined in "Table 24. AC CHARACTERISTICS") for next instruction.
Figure 5. Reset QPI Mode
CS#
SCLK
SIO[3:0]
P/N: PM2642
F5h
Macronix Proprietary
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Rev. 1.2, November 21, 2019
MX25U12832F
9. COMMAND DESCRIPTION
Table 5. Command Set
Address Byte
Command
Code
SPI
Dummy
Cycle
Data
Byte
03 (hex)
ADD3
0
1- ∞
ADD2
ADD3
8*
1- ∞
ADD1
ADD2
ADD3
4*
1- ∞
3
ADD1
ADD2
ADD3
8*
1- ∞
3
ADD1
ADD2
ADD3
6 *
1- ∞
V
3
ADD1
ADD2
ADD3
8*
1- ∞
E7 (hex)
V
3
ADD1
ADD2
ADD3
4
1- ∞
02 (hex)
V
3
ADD1
ADD2
ADD3
0
1-256
38 (hex)
V
3
ADD1
ADD2
ADD3
0
1-256
20 (hex)
V
V
3
ADD1
ADD2
ADD3
0
0
52 (hex)
V
V
3
ADD1
ADD2
ADD3
0
0
D8 (hex)
V
V
3
ADD1
ADD2
ADD3
0
0
60 or C7
(hex)
V
V
0
0
0
06 (hex)
V
V
0
0
0
04 (hex)
V
V
0
0
0
68 (hex)
V
V
0
0
0
35 (hex)
V
0
0
0
V
0
0
0
V
V
0
0
0
V
V
0
0
0
V
V
0
0
0
Total
ADD
Byte
Byte 1
Byte 2
Byte 3
V
3
ADD1
ADD2
0B (hex)
V
3
ADD1
BB (hex)
V
3
3B (hex)
V
EB (hex)
V
6B (hex)
QPI
Byte 4
Array access
READ
(normal read)
FAST READ
(fast read data)
2READ
(2 x I/O read command)
DREAD
(1I 2O read)
4READ
(4 I/O read)
QREAD
(1I 4O read)
W4READ
(4 I/O read with 4 dummy cycles)
PP
(page program)
4PP
(quad page program)
SE
(sector erase)
BE 32K
(block erase 32KB)
BE
(block erase 64KB)
CE
(chip erase)
V
V
Device operation
WREN
(write enable)
WRDI
(write disable)
WPSEL
(Write Protect Selection)
EQIO
(Enable QPI)
RSTQIO
(Reset QPI)
PGM/ERS Suspend
(Suspends Program/ Erase)
PGM/ERS Resume
(Resumes Program/ Erase)
DP
(Deep power down)
F5 (hex)
75 or B0
(hex)
7A or 30
(hex)
B9 (hex)
* Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in configuration register.
P/N: PM2642
Macronix Proprietary
15
Rev. 1.2, November 21, 2019
MX25U12832F
NOP
(No Operation)
RSTEN
(Reset Enable)
RST
(Reset Memory)
GBLK
(gang block lock)
GBULK
(gang block unlock)
FMEN
(factory mode enable)
Address Byte
Command
Code
SPI
QPI
Total
ADD
Byte
Dummy
Cycle
Data
Byte
00 (hex)
V
V
0
0
0
66 (hex)
V
V
0
0
0
99 (hex)
V
V
0
0
0
7E (hex)
V
V
0
0
0
98 (hex)
V
V
0
0
0
41 (hex)
V
V
0
0
0
9F (hex)
V
0
0
3
AB (hex)
V
0
24
1
90 (hex)
V
16
1
0
3
8
1- ∞
(Note2)
(Note2)
Byte 1
Byte 2
Byte 3
Byte 4
Register Access
RDID
(read identification)
RES
(read electronic ID)
REMS
(read electronic manufacturer &
device ID)
QPIID
(QPI ID Read)
RDSFDP
(Read SFDP Table)
RDSR
(read status register)
RDCR
(read configuration register)
RDFMSR
(Read Factory Mode Status
Register)
WRSR
(write status/configuration register)
RDSCUR
(read security register)
WRSCUR
(write security register)
SBL
(Set Burst Length)
ENSO
(enter secured OTP)
EXSO
(exit secured OTP)
WRLR
(write Lock register)
RDLR
(read Lock register)
WRSPB
(SPB bit program)
ESSPB
(all SPB bit erase)
RDSPB
(read SPB status)
P/N: PM2642
AF (hex)
V
1
V
ADD1
0
5A (hex)
V
3
ADD1
05 (hex)
V
V
0
0
1
15 (hex)
V
V
0
0
1
44 (hex)
V
V
0
0
1
01 (hex)
V
V
0
0
1-2
2B (hex)
V
V
0
0
1
2F (hex)
V
V
0
0
1
C0 (hex)
V
V
0
0
1
B1 (hex)
V
V
0
0
0
C1 (hex)
V
V
0
0
0
2C (hex)
V
0
0
2
2D (hex)
V
0
0
2
E3 (hex)
V
4
0
1
E4 (hex)
V
0
0
0
E2 (hex)
V
4
0
1
ADD1
ADD1
Macronix Proprietary
16
ADD2
ADD2
ADD2
ADD3
ADD3
ADD3
ADD4
ADD4
Rev. 1.2, November 21, 2019
MX25U12832F
WRDPB
(write DPB register)
RDDPB
(read DPB register)
Address Byte
Command
Code
Total
ADD
Byte
SPI
Byte 1
Byte 2
Byte 3
Byte 4
Dummy
Cycle
Data
Byte
E1 (hex)
V
4
ADD1
ADD2
ADD3
ADD4
0
1
E0 (hex)
V
4
ADD1
ADD2
ADD3
ADD4
0
1
QPI
Note 1: It is not recommended to adopt any other code/address not in the command definition table, which will potentially enter
the hidden mode.
Note 2: The RSTEN command must be executed before executing the RST command. If any other command is issued
in-between RSTEN and RST, the RST command will be ignored.
P/N: PM2642
Macronix Proprietary
17
Rev. 1.2, November 21, 2019
MX25U12832F
9-1. Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP,
SE, BE32K, BE, CE, and WRSR, which are intended to change the device content WEL bit should be set every time
after the WREN instruction setting the WEL bit.
The sequence of issuing WREN instruction is: CS# goes low→sending WREN instruction code→ CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care in
SPI mode.
Figure 6. Write Enable (WREN) Sequence (SPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
SCLK
Mode 0
Command
SI
06h
High-Z
SO
Figure 7. Write Enable (WREN) Sequence (QPI Mode)
CS#
0
Mode 3
1
SCLK
Mode 0
Command
06h
SIO[3:0]
P/N: PM2642
Macronix Proprietary
18
Rev. 1.2, November 21, 2019
MX25U12832F
9-2. Write Disable (WRDI)
The Write Disable (WRDI) instruction is to reset Write Enable Latch (WEL) bit.
The sequence of issuing WRDI instruction is: CS# goes low→sending WRDI instruction code→CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care in
SPI mode.
The WEL bit is reset by following situations:
- Power-up
- Reset# pin driven low
- WRDI command completion
- WRSR command completion
- PP command completion
- 4PP command completion
- SE command completion
- BE32K command completion
- BE command completion
- CE command completion
- PGM/ERS Suspend command completion
- Softreset command completion
- WRSCUR command completion
- WPSEL command completion
- GBLK command completion
- GBULK command completion
- WRLR command completion
- WRSPB command completion
- ESSPB command completion
- WRDPB command completion
Figure 8. Write Disable (WRDI) Sequence (SPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
SCLK
Mode 0
Command
SI
SO
P/N: PM2642
04h
High-Z
Macronix Proprietary
19
Rev. 1.2, November 21, 2019
MX25U12832F
Figure 9. Write Disable (WRDI) Sequence (QPI Mode)
CS#
0
Mode 3
1
SCLK
Mode 0
Command
04h
SIO[3:0]
9-3. Factory Mode Enable (FMEN)
The Factory Mode Enable (FMEN) instruction is for enhance Program and Erase performance for increase factory
production throughput. The FMEN instruction need to combine with the instructions which are intended to change
the device content, like PP, 4PP, SE, BE32K, BE, and CE.
The sequence of issuing FMEN instruction is: CS# goes low→sending FMEN instruction code→ CS# goes high. A
valid factory mode operation need to included three sequences: WREN instruction → FMEN instruction→ Program
or Erase instruction.
Suspend command is not acceptable under factory mode.
The FMEN is reset by following situations
- Power-up
- Reset# pin driven low
- PP command completion
- 4PP command completion
- SE command completion
- BE32K command completion
- BE command completion
- CE command completion
- Softreset command completion
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care in
SPI mode.
Figure 10. Factory Mode Enable (FMEN) Sequence (SPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
SCLK
Mode 0
Command
SI
SO
P/N: PM2642
41h
High-Z
Macronix Proprietary
20
Rev. 1.2, November 21, 2019
MX25U12832F
Figure 12. Factory Mode Enable (FMEN) Sequence (QPI Mode)
CS#
0
Mode 3
1
SCLK
Mode 0
Command
41h
SIO[3:0]
9-4. Read Identification (RDID)
The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Macronix Manufacturer ID and Device ID are listed as "Table 6. ID Definitions".
The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code→24-bits ID data out
on SO→ to end RDID operation can drive CS# to high at any time during data out.
While Program/Erase operation is in progress, it will not decode the RDID instruction, therefore there's no effect on
the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby
stage.
Figure 11. Read Identification (RDID) Sequence (SPI mode only)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10
13 14 15 16 17 18
28 29 30 31
SCLK
Mode 0
Command
SI
9Fh
Manufacturer Identification
SO
High-Z
7
6
5
2
1
MSB
P/N: PM2642
Device Identification
0 15 14 13
3
2
1
0
MSB
Macronix Proprietary
21
Rev. 1.2, November 21, 2019
MX25U12832F
9-5. Read Electronic Signature (RES)
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as "Table 6. ID
Definitions". This is not the same as RDID instruction. It is not recommended to use for new design. For new design,
please use RDID instruction.
The SIO[3:1] are "don't care".
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly
if continuously send the additional clock cycles on SCLK while CS# is at low.
Figure 13. Read Electronic Signature (RES) Sequence (SPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38
SCLK
Mode 0
Command
SI
3 Dummy Bytes
23 22 21
ABh
3
2
1
0
MSB
SO
Electronic Signature Out
High-Z
7
6
5
4
3
2
1
0
MSB
Figure 14. Read Electronic Signature (RES) Sequence (QPI Mode)
CS#
MODE 3
0
1
2
3
4
5
6
7
SCLK
MODE 0
3 Dummy Bytes
Command
SIO[3:0]
ABh
X
X
X
X
X
X
H0
L0
MSB LSB
Electronic Signature Out
Data In
P/N: PM2642
Macronix Proprietary
22
Rev. 1.2, November 21, 2019
MX25U12832F
9-6. Read Electronic Manufacturer ID & Device ID (REMS)
The REMS instruction returns both the JEDEC assigned manufacturer ID and the device ID. The Device ID values
are listed in "Table 6. ID Definitions".
The REMS instruction is initiated by driving the CS# pin low and sending the instruction code "90h" followed by two
dummy bytes and one address byte (A7~A0). After which the manufacturer ID for Macronix (C2h) and the device
ID are shifted out on the falling edge of SCLK with the most significant bit (MSB) first. If the address byte is 00h, the
manufacturer ID will be output first, followed by the device ID. If the address byte is 01h, then the device ID will be
output first, followed by the manufacturer ID. While CS# is low, the manufacturer and device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high.
Figure 15. Read Electronic Manufacturer & Device ID (REMS) Sequence (SPI Mode only)
CS#
SCLK
Mode 3
0
1
2
Mode 0
3
4
5
6
7
8
Command
SI
9 10
2 Dummy Bytes
15 14 13
90h
3
2
1
0
High-Z
SO
CS#
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
ADD (1)
SI
7
6
5
4
3
2
1
0
Manufacturer ID
SO
7
6
5
4
3
2
1
Device ID
0
7
MSB
MSB
6
5
4
3
2
1
7
0
MSB
Note: (1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first.
P/N: PM2642
Macronix Proprietary
23
Rev. 1.2, November 21, 2019
MX25U12832F
9-7. QPI ID Read (QPIID)
User can execute this QPIID Read instruction to identify the Device ID and Manufacturer ID. The sequence of issue
QPIID instruction is CS# goes low→sending QPI ID instruction→Data out on SO→CS# goes high. Most significant
bit (MSB) first.
After the command cycle, the device will immediately output data on the falling edge of SCLK. The manufacturer ID,
memory type, and device ID data byte will be output continuously, until the CS# goes high.
Table 6. ID Definitions
Command Type
RDID
9Fh
RES
ABh
REMS
90h
QPIID
AFh
MX25U12832F
Manufacturer ID
C2
Memory Type
25
Electronic ID
38
Device ID
38
Memory Type
25
Manufacturer ID
C2
Manufacturer ID
C2
Memory Density
38
Memory Density
38
Figure 16. QPI ID Read (QPIID) Sequence (QPI Mode only)
CS#
Mode 3 0
1
2
3
4
5
6
7
N
SCLK
Mode 0
SIO[3:0]
AFh H0 L0 H0 L0 H0 L0
H0 L0
MSB LSB
ID Byte
P/N: PM2642
ID Byte
ID Byte
Macronix Proprietary
24
ID Byte
Rev. 1.2, November 21, 2019
MX25U12832F
9-8. Read Status Register (RDSR)
The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even
in program/erase/write status register condition). It is recommended to check the Write in Progress (WIP) bit before
sending a new instruction when a program, erase, or write status register operation is in progress.
The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register data
out on SO.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
Figure 17. Read Status Register (RDSR) Sequence (SPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
Mode 0
command
05h
SI
SO
Status Register Out
High-Z
7
6
5
4
3
2
1
Status Register Out
0
7
6
5
4
3
2
1
0
7
MSB
MSB
Figure 18. Read Status Register (RDSR) Sequence (QPI Mode)
CS#
Mode 3 0
1
2
3
4
5
6
7
N
SCLK
Mode 0
SIO[3:0]
05h H0 L0 H0 L0 H0 L0
H0 L0
MSB LSB
Status Byte Status Byte Status Byte
P/N: PM2642
Macronix Proprietary
25
Status Byte
Rev. 1.2, November 21, 2019
MX25U12832F
9-9. Read Configuration Register (RDCR)
The RDCR instruction is for reading Configuration Register Bits. The Read Configuration Register can be read at
any time (even in program/erase/write configuration register condition). It is recommended to check the Write in
Progress (WIP) bit before sending a new instruction when a program, erase, or write configuration register operation
is in progress.
The sequence of issuing RDCR instruction is: CS# goes low→ sending RDCR instruction code→ Configuration Register data out on SO.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
Figure 19. Read Configuration Register (RDCR) Sequence (SPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
Mode 0
command
15h
SI
SO
Configuration register Out
High-Z
7
6
5
4
3
2
1
0
Configuration register Out
7
6
5
4
3
2
1
0
7
MSB
MSB
Figure 20. Read Configuration Register (RDCR) Sequence (QPI Mode)
CS#
Mode 3 0
1
2
3
4
5
6
7
N
SCLK
Mode 0
SIO[3:0]
15h H0 L0 H0 L0 H0 L0
H0 L0
MSB LSB
Config. Byte Config. Byte Config. Byte
P/N: PM2642
Macronix Proprietary
26
Config. Byte
Rev. 1.2, November 21, 2019
MX25U12832F
For user to check if Program/Erase operation is finished or not, RDSR instruction flow are shown as follows:
Figure 21. Program/Erase flow with read array data
start
WREN command
RDSR command*
WEL=1?
No
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
WIP=0?
No
Yes
RDSR command
Read WEL=0, BP[3:0], QE,
and SRWD data
Read array data
(same address of PGM/ERS)
Verify OK?
No
Yes
Program/erase successfully
Program/erase
another block?
No
Program/erase fail
Yes
* Issue RDSR to check BP[3:0].
* If WPSEL = 1, issue RDSPB and RDDPB to check the block status.
Program/erase completed
P/N: PM2642
Macronix Proprietary
27
Rev. 1.2, November 21, 2019
MX25U12832F
Figure 22. Program/Erase flow without read array data (read P_FAIL/E_FAIL flag)
start
WREN command
RDSR command*
WEL=1?
No
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
WIP=0?
No
Yes
RDSR command
Read WEL=0, BP[3:0], QE,
and SRWD data
RDSCUR command
Yes
P_FAIL/E_FAIL =1 ?
No
Program/erase fail
Program/erase successfully
Program/erase
another block?
No
Yes
* Issue RDSR to check BP[3:0].
* If WPSEL = 1, issue RDSPB and RDDPB to check the block status.
Program/erase completed
P/N: PM2642
Macronix Proprietary
28
Rev. 1.2, November 21, 2019
MX25U12832F
Status Register
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register
progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register
cycle.
WEL bit. The Write Enable Latch (WEL) bit is a volatile bit that is set to “1” by the WREN instruction. WEL needs to be
set to “1” before the device can accept program and erase instructions, otherwise the program and erase instructions
are ignored. WEL automatically clears to “0” when a program or erase operation completes. To ensure that both WIP
and WEL are “0” and the device is ready for the next program or erase operation, it is recommended that WIP be
confirmed to be “0” before checking that WEL is also “0”. If a program or erase instruction is applied to a protected
memory area, the instruction will be ignored and WEL will clear to “0”.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area
(as defined in "Table 2. Protected Area Sizes") of the device to against the program/erase instruction without hardware
protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR)
instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector
Erase (SE), Block Erase 32KB (BE32K), Block Erase (BE) and Chip Erase (CE) instructions (only if Block Protect bits
(BP3:BP0) set to 0, the CE instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as default. Which is unprotected.
QE bit. The Quad Enable (QE) bit is a non-volatile bit with a factory default of “0”. When QE is “0”, Quad mode commands are ignored; pins WP#/SIO2 and RESET#/SIO3 function as WP# and RESET#, respectively. When QE is
“1”, Quad mode is enabled and Quad mode commands are supported along with Single and Dual mode commands.
Pins WP#/SIO2 and RESET#/SIO3 function as SIO2 and SIO3, respectively, and their alternate pin functions are
disabled. Enabling Quad mode also disables the HPM feature and the hardware RESET feature.
SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection
(WP#/SIO2) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and
WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is
no longer accepted for execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are read only. The
SRWD bit defaults to be "0".
Table 7. Status Register
bit7
bit6
SRWD (status
register write
protect)
QE
(Quad
Enable)
1=status
register write
1=Quad
Enabled
disabled
0=not Quad
0=status
Enabled
register write
enabled
bit5
BP3
(level of
protected
block)
(note 1)
bit4
BP2
(level of
protected
block)
bit3
BP1
(level of
protected
block)
(note 1)
(note 1)
Non-volatile Non-volatile Non-volatile Non-volatile Non-volatile
bit
bit
bit
bit
bit
Note 1: Please refer to the "Table 2. Protected Area Sizes".
P/N: PM2642
Macronix Proprietary
29
bit2
BP0
(level of
protected
block)
(note 1)
Non-volatile
bit
bit1
bit0
WEL
WIP
(write enable
(write in
latch)
progress bit)
1=write
1=write
enabled
operation
0=not write 0=not in write
enabled
operation
volatile bit
volatile bit
Rev. 1.2, November 21, 2019
MX25U12832F
Configuration Register
The Configuration Register is able to change the default status of Flash memory. Flash memory will be configured
after the CR bit is set.
ODS bit
The output driver strength (ODS2, ODS1, ODS0) bits are volatile bits, which indicate the output driver level (as
defined in "Table 9. Output Driver Strength Table") of the device. The Output Driver Strength is defaulted as 30
Ohms when delivered from factory. To write the ODS bits requires the Write Status Register (WRSR) instruction to
be executed.
TB bit
The Top/Bottom (TB) bit is a non-volatile OTP bit. The Top/Bottom (TB) bit is used to configure the Block Protect
area by BP bit (BP3, BP2, BP1, BP0), starting from TOP or Bottom of the memory array. The TB bit is defaulted as
“0”, which means Top area protect. When it is set as “1”, the protect area will change to Bottom area of the memory
device. To write the TB bits requires the Write Status Register (WRSR) instruction to be executed.
Table 8. Configuration Register Table
bit7
DC1
(Dummy
cycle 1)
bit6
DC0
(Dummy
cycle 0)
bit5
bit4
Reserved
Reserved
(note 2)
(note 2)
x
x
volatile bit
volatile bit
x
x
bit3
bit2
bit1
bit0
TB
ODS 2
ODS 1
ODS 0
(top/bottom (output driver (output driver (output driver
selected)
strength)
strength)
strength)
0=Top area
protect
1=Bottom
(note 1)
(note 1)
(note 1)
area protect
(Default=0)
OTP
volatile bit
volatile bit
volatile bit
Note 1: Please refer to "Table 9. Output Driver Strength Table".
Note 2: Please refer to "Table 10. Dummy Cycle and Frequency Table (MHz)".
P/N: PM2642
Macronix Proprietary
30
Rev. 1.2, November 21, 2019
MX25U12832F
Table 9. Output Driver Strength Table
ODS2
ODS1
ODS0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Resistance (Ohm)
Reserved
90 Ohms
45 Ohms
45 Ohms
Reserved
15 Ohms
15 Ohms
30 Ohms (Default)
Table 10. Dummy Cycle and Frequency Table (MHz)
DC[1:0]
00 (default)
01
10
11
DC[1:0]
00 (default)
01
10
11
DC[1:0]
00 (default)
01
10
11
P/N: PM2642
Numbers of Dummy
clock cycles
8
6
8
10
Numbers of Dummy
clock cycles
4
6
8
10
Fast Read
104
104
104
133
Dual Output Fast
Read
104
104
104
133
Quad Output Fast
Read
104
84
104
133
Dual IO Fast Read
84
104
104
133
Numbers of Dummy
Quad IO Fast Read
clock cycles
6
84
4
66
8
104
10
133
Macronix Proprietary
31
Quad IO Fast Read
(QPI)
84
66
104
133
Rev. 1.2, November 21, 2019
MX25U12832F
9-10. Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits and Configuration Register Bits. Before
sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write
Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1,
BP0) bits to define the protected area of memory (as shown in "Table 2. Protected Area Sizes"). The WRSR also
can set or reset the Quad enable (QE) bit and set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#/SIO2) pin signal, but has no effect on bit1(WEL) and bit0 (WIP) of the status register. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered.
The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register
data on SI→ Configuration Register data on SI→ CS# goes high.
The CS# must go high exactly at the 8 bits or 16 bits data boundary; otherwise, the instruction will be rejected and
not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes
high. The Write in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress.
The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset.
Figure 23. Write Status Register (WRSR) Sequence (SPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Mode 0
SI
SO
command
01h
Status
Register In
7
6
4
5
Configuration
Register In
2
3
0 15 14 13 12 11 10 9
1
8
MSB
High-Z
Note : The CS# must go high exactly at 8 bits or 16 bits data boundary to completed the write register command.
Figure 24. Write Status Register (WRSR) Sequence (QPI Mode)
CS#
Mode 3
0
1
2
3
4
5
Mode 3
SCLK
Mode 0
Mode 0
SR in
Command
SIO[3:0]
P/N: PM2642
01h
H0
L0
CR in
H1
Macronix Proprietary
32
L1
Rev. 1.2, November 21, 2019
MX25U12832F
Software Protected Mode (SPM):
- When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can
change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1,
BP0 and T/B bit, is at software protected mode (SPM).
- When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values
of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0 and T/B bit, is at
software protected mode (SPM)
Note:
If SRWD bit=1 but WP#/SIO2 is low, it is impossible to write the Status Register even if the WEL bit has previously
been set. It is rejected to write the Status Register and not be executed.
Hardware Protected Mode (HPM):
- When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware
protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2,
BP1, BP0 and T/B bit and hardware protected mode by the WP#/SIO2 to against data modification.
Note:
To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is entered.
If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be entered; only
can use software protected mode via BP3, BP2, BP1, BP0 and T/B bit.
If the system enter QPI or set QE=1, the feature of HPM will be disabled.
Table 11. Protection Modes
Mode
Software protection
mode (SPM)
Hardware protection
mode (HPM)
Status register condition
WP# and SRWD bit status
Memory
Status register can be written
in (WEL bit is set to "1") and
the SRWD, BP0-BP3
bits can be changed
WP#=1 and SRWD bit=0, or
WP#=0 and SRWD bit=0, or
WP#=1 and SRWD=1
The protected area
cannot
be program or erase.
The SRWD, BP0-BP3 of
status register bits cannot be
changed
WP#=0, SRWD bit=1
The protected area
cannot
be program or erase.
Note:
1. As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in "Table 2.
Protected Area Sizes".
P/N: PM2642
Macronix Proprietary
33
Rev. 1.2, November 21, 2019
MX25U12832F
Figure 25. WRSR flow
start
WREN command
RDSR command
No
WEL=1?
Yes
WRSR command
Write status register data
RDSR command
No
WIP=0?
Yes
RDSR command
Read WEL=0, BP[3:0], QE,
and SRWD data
No
Verify OK?
Yes
WRSR successfully
P/N: PM2642
WRSR fail
Macronix Proprietary
34
Rev. 1.2, November 21, 2019
MX25U12832F
Figure 26. WP# Setup Timing and Hold Timing during WRSR when SRWD=1
WP#
tSHWL
tWHSL
CS#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCLK
01h
SI
SO
High-Z
Note: WP# must be kept high until the embedded operation finish.
P/N: PM2642
Macronix Proprietary
35
Rev. 1.2, November 21, 2019
MX25U12832F
9-11. Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on
the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address
is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can
be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been
reached.
The sequence of issuing READ instruction is: CS# goes low→sending READ instruction code→ 3-byte address on
SI→ data out on SO→to end READ operation can use CS# to high at any time during data out.
Figure 27. Read Data Bytes (READ) Sequence (SPI Mode only)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Mode 0
SI
command
03h
24-Bit Address
23 22 21
3
2
1
0
MSB
SO
Data Out 1
High-Z
7
6
5
4
3
2
Data Out 2
1
0
7
MSB
P/N: PM2642
Macronix Proprietary
36
Rev. 1.2, November 21, 2019
MX25U12832F
9-12. Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and
data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at
any location. The address is automatically increased to the next higher address after each byte data is shifted out,
so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when
the highest address has been reached.
The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ instruction code→
3-byte address on SI→ 8 dummy cycles (default)→ data out on SO→ to end FAST_READ operation can use CS#
to high at any time during data out.
In the performance-enhancing mode, P[7:4] must be toggling with P[3:0] ; likewise P[7:0]=A5h,5Ah,F0h or 0Fh can
make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0]; likewise P[7:0]=FFh, 00h, AAh or 55h and afterwards CS# is raised and then lowered, the system then will escape from
performance enhance mode and return to normal operation.
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle.
Figure 28. Read at Higher Speed (FAST_READ) Sequence
CS#
SCLK
Mode 3
0
1
2
Mode 0
3
5
6
7
8
9 10
Command
SI
SO
4
28 29 30 31
24-Bit Address
23 22 21
0Bh
3
2
1
0
High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Configurable
Dummy Cycle
SI
7
6
5
4
3
2
1
0
DATA OUT 2
DATA OUT 1
SO
7
6
5
4
3
2
1
7
MSB
MSB
P/N: PM2642
0
Macronix Proprietary
37
6
5
4
3
2
1
0
7
MSB
Rev. 1.2, November 21, 2019
MX25U12832F
9-13. Dual Output Read Mode (DREAD)
The DREAD instruction enable double throughput of Serial NOR Flash in read mode. The address is latched on
rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a
maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the
next higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD
instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD
instruction, the following data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing DREAD instruction is: CS# goes low→ sending DREAD instruction→3-byte address on
SIO0→ 8 dummy cycles (default) on SIO0→ data out interleave on SIO1 & SIO0→ to end DREAD operation can
use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
Figure 29. Dual Read Mode Sequence
CS#
0
1
2
3
4
5
6
7
8
SCLK
…
Command
SI/SIO0
SO/SIO1
P/N: PM2642
30 31 32
9
3B
…
24 ADD Cycle
A23 A22
…
39 40 41 42 43 44 45
Configurable
Dummy Cycle
A1 A0
High Impedance
Data Out
1
Data Out
2
D6 D4 D2 D0 D6 D4
D7 D5 D3 D1 D7 D5
Macronix Proprietary
38
Rev. 1.2, November 21, 2019
MX25U12832F
9-14. 2 x I/O Read Mode (2READ)
The 2READ instruction enable double throughput of Serial NOR Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a
maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the
next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ
instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ
instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 3-byte address interleave on SIO1 & SIO0→ 4 dummy cycles (default) on SIO1 & SIO0→ data out interleave on SIO1 & SIO0→ to end
2READ operation can use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
Figure 30. 2 x I/O Read Mode Sequence (SPI Mode only)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10
17 18 19 20 21 22 23 24 25 26 27 28 29 30
Mode 3
SCLK
Mode 0
Command
SI/SIO0
SO/SIO1
P/N: PM2642
BBh
12 ADD Cycles
Configurable
Dummy Cycle
Data
Out 1
Mode 0
Data
Out 2
A22 A20 A18
A4 A2 A0
D6 D4 D2 D0 D6 D4 D2 D0
A23 A21 A19
A5 A3 A1
D7 D5 D3 D1 D7 D5 D3 D1
Macronix Proprietary
39
Rev. 1.2, November 21, 2019
MX25U12832F
9-15. Quad Read Mode (QREAD)
The QREAD instruction enable quad throughput of Serial NOR Flash in read mode. A Quad Enable (QE) bit of
status Register must be set to "1" before sending the QREAD instruction. The address is latched on rising edge of
SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ. The first address byte can be at any location. The address is automatically increased to the next higher
address after each byte data is shifted out, so the whole memory can be read out at a single QREAD instruction.
The address counter rolls over to 0 when the highest address has been reached. Once writing QREAD instruction,
the following data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing QREAD instruction is: CS# goes low→ sending QREAD instruction → 3-byte address on
SI → 8 dummy cycle (Default) → data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end QREAD operation can
use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
Figure 31. Quad Read Mode Sequence
CS#
0
1
2
3
4
5
6
7
8
SCLK
…
Command
SIO0
SIO1
SIO2
SIO3
P/N: PM2642
29 30 31 32 33
9
6B
…
24 ADD Cycles
A23 A22
…
38 39 40 41 42
A2 A1 A0
High Impedance
Configurable
dummy cycles
Data Data Data
Out 1 Out 2 Out 3
D4 D0 D4 D0 D4
D5 D1 D5 D1 D5
High Impedance
D6 D2 D6 D2 D6
High Impedance
D7 D3 D7 D3 D7
Macronix Proprietary
40
Rev. 1.2, November 21, 2019
MX25U12832F
9-16. 4 x I/O Read Mode (4READ)
The 4READ instruction enable quad throughput of Serial NOR Flash in read mode. A Quad Enable (QE) bit of status
Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCLK,
and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency
fQ. The first address byte can be at any location. The address is automatically increased to the next higher address
after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address
counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following
address/dummy/data out will perform as 4-bit instead of previous 1-bit.
4 x I/O Read on SPI Mode (4READ) The sequence of issuing 4READ instruction is: CS# goes low→ sending
4READ instruction→ 3-byte address interleave on SIO3, SIO2, SIO1 & SIO0→ 6 dummy cycles (Default) →data out
interleave on SIO3, SIO2, SIO1 & SIO0→ to end 4READ operation can use CS# to high at any time during data out.
4 x I/O Read on QPI Mode (4READ) The 4READ instruction also support on QPI command mode. The sequence
of issuing 4READ instruction QPI mode is: CS# goes low→ sending 4READ instruction→ 3-byte address interleave
on SIO3, SIO2, SIO1 & SIO0→ 6 dummy cycles (Default) →data out interleave on SIO3, SIO2, SIO1 & SIO0→ to
end 4READ operation can use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
W4READ instruction (E7h) is also available for 4 I/O read. Please refer to "Figure 32. W4READ (Quad Read with 4
dummy cycles) Sequence".
Figure 32. W4READ (Quad Read with 4 dummy cycles) Sequence
CS#
Mode 3
SCLK
０
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Mode ０
4 Dummy
Cycles
Data
Out 2
Data
Out 3
A20 A16 A12 A8 A4 A0
D4 D0 D4 D0
D4 D0
D4
SIO1
A21 A17 A13 A9 A5 A1
D5 D1 D5 D1
D5 D1
D5
SIO2
A22 A18 A14 A10 A6 A2
D6 D2 D6 D2
D6 D2
D6
SIO3
A23 A19 A15 A11 A7 A3
D7 D3 D7 D3
D7 D3
D7
Command
SIO0
E7h
6 ADD Cycles
Data
Out 1
Notes:
1. Hi-impedance is inhibited for the two clock cycles.
2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited.
P/N: PM2642
Macronix Proprietary
41
Rev. 1.2, November 21, 2019
MX25U12832F
Figure 33. 4 x I/O Read Mode Sequence (SPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
Mode 3
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SCLK
Mode 0
Command
6 ADD Cycles
Data
Out 1
Performance
enhance
indicator (Note 1)
Data
Out 2
Mode 0
Data
Out 3
Configurable
Dummy Cycle (Note 3)
EBh
A20 A16 A12 A8 A4 A0 P4 P0
D4 D0 D4 D0 D4 D0
SIO1
A21 A17 A13 A9 A5 A1 P5 P1
D5 D1 D5 D1 D5 D1
SIO2
A22 A18 A14 A10 A6 A2 P6 P2
D6 D2 D6 D2 D6 D2
SIO3
A23 A19 A15 A11 A7 A3 P7 P3
D7 D3 D7 D3 D7 D3
SIO0
Notes:
1. Hi-impedance is inhibited for the two clock cycles.
2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited.
3. Configuration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in
configuration register.
Figure 34. 4 x I/O Read Mode Sequence (QPI Mode)
CS#
MODE 3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
MODE 3
SCLK
MODE 0
SIO[3:0]
MODE 0
EBh
Data In
X
A5 A4 A3 A2 A1 A0
P(7:4)
P(3:0)
Performance
24-bit Address
X
X
enhance
indicator (Note 1)
X
H0 L0 H1 L1 H2 L2 H3 L3
MSB
Data Out
Configurable Dummy Cycles
(Note 3)
Notes:
1. Hi-impedance is inhibited for the two clock cycles.
2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited.
3. Configuration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in
configuration register.
P/N: PM2642
Macronix Proprietary
42
Rev. 1.2, November 21, 2019
MX25U12832F
9-17. Burst Read
The Burst Read feature allows applications to fill a cache line with a fixed length of data without using multiple read
commands. Burst Read is disabled by default at power-up or reset. Burst Read is enabled by setting the Burst
Length. When the Burst Length is set, reads will wrap on the selected boundary (8/16/32/64-bytes) containing the
initial target address. For example if an 8-byte Wrap Depth is selected, reads will wrap on the 8-byte-page-aligned
boundary containing the initial read address.
To set the Burst Length, drive CS# low → send SET BURST LENGTH instruction code → send WRAP CODE →
drive CS# high. Refer to the table below for valid 8-bit Wrap Codes and their corresponding Wrap Depth.
Data
00h
01h
02h
03h
1xh
Wrap Around
Yes
Yes
Yes
Yes
No
Wrap Depth
8-byte
16-byte
32-byte
64-byte
X
Once Burst Read is enabled, it will remain enabled until the device is power-cycled or reset. The SPI and QPI mode
4READ read commands support the wrap around feature after Burst Read is enabled. To change the wrap depth,
resend the Burst Read instruction with the appropriate Wrap Code. To disable Burst Read, send the Burst Read
instruction with Wrap Code 1xh. QPI “EBh” and SPI “EBh” “E7h” support wrap around feature after wrap around is
enabled. Both SPI (8 clocks) and QPI (2 clocks) command cycle can be accepted by this instruction. The SIO[3:1]
are don't care during SPI mode.
Figure 35. Burst Read (SPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9
D7
D6
10
11
12
13
14
15
SCLK
Mode 0
SIO
C0h
D5
D4
D3
D2
D1
D0
Figure 36. Burst Read (QPI Mode)
CS#
Mode 3
0
1
2
3
SCLK
Mode 0
SIO[3:0]
C0h
H0
MSB
L0
LSB
Note: MSB=Most Significant Bit
LSB=Least Significant Bit
P/N: PM2642
Macronix Proprietary
43
Rev. 1.2, November 21, 2019
MX25U12832F
9-18. Performance Enhance Mode
The device could waive the command cycle bits if the two cycle bits after address cycle toggles.
Performance enhance mode is supported in both SPI and QPI mode.
In QPI mode, “EBh” and SPI “EBh” commands support enhance mode. The performance enhance mode is not supported in dual I/O mode.
To enter performance-enhancing mode, P[7:4] must be toggling with P[3:0]; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh
can make this mode continue and skip the next 4READ instruction. To leave enhance mode, P[7:4] is no longer toggling with P[3:0]; likewise P[7:0]=FFh, 00h, AAh or 55h along with CS# is afterwards raised and then lowered. Issuing ”FFh” data cycle can also exit enhance mode. The system then will leave performance enhance mode and return
to normal operation.
After entering enhance mode, following CS# go high, the device will stay in the read mode and treat CS# go low of
the first clock as address instead of command cycle.
This sequence of issuing 4READ instruction is especially useful in random access: CS# goes low→send 4READ
instruction→3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 →performance enhance toggling bit P[7:0]→
4 dummy cycles (Default) →data out until CS# goes high → CS# goes low (The following 4READ instruction is not
allowed, hence 8 cycles of 4READ can be saved comparing to normal 4READ mode) → 3-bytes random access address.
To conduct the Performance Enhance Mode Reset operation in SPI mode, FFh data cycle, 8 clocks, should be issued in 1I/O sequence. In QPI Mode, FFFFFFFFh data cycle, 8 clocks, in 4I/O should be issued.
If the system controller is being Reset during operation, the flash device will return to the standard SPI operation.
P/N: PM2642
Macronix Proprietary
44
Rev. 1.2, November 21, 2019
MX25U12832F
Figure 37. 4 x I/O Read performance enhance Mode Sequence (SPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22
n
SCLK
Mode 0
Data
Out 2
Data
Out n
A20 A16 A12 A8 A4 A0 P4 P0
D4 D0 D4 D0
D4 D0
SIO1
A21 A17 A13 A9 A5 A1 P5 P1
D5 D1 D5 D1
D5 D1
SIO2
A22 A18 A14 A10 A6 A2 P6 P2
D6 D2 D6 D2
D6 D2
SIO3
A23 A19 A15 A11 A7 A3 P7 P3
D7 D3 D7 D3
D7 D3
Command
6 ADD Cycles
Data
Out 1
Performance
enhance
indicator (Note 1)
Configurable
Dummy Cycle (Note 2)
EBh
SIO0
CS#
n+1
...........
n+7 ...... n+9
........... n+13
...........
Mode 3
SCLK
6 ADD Cycles
Data
Out 1
Performance
enhance
indicator (Note 1)
Data
Out 2
Data
Out n
Mode 0
Configurable
Dummy Cycle (Note 2)
SIO0
A20 A16 A12 A8 A4 A0 P4 P0
D4 D0 D4 D0
D4 D0
SIO1
A21 A17 A13 A9 A5 A1 P5 P1
D5 D1 D5 D1
D5 D1
SIO2
A22 A18 A14 A10 A6 A2 P6 P2
D6 D2 D6 D2
D6 D2
SIO3
A23 A19 A15 A11 A7 A3 P7 P3
D7 D3 D7 D3
D7 D3
Notes:
1. If not using performance enhance recommend to keep 1 or 0 in performance enhance indicator.
Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF.
2. Configuration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in
configuration register.
P/N: PM2642
Macronix Proprietary
45
Rev. 1.2, November 21, 2019
MX25U12832F
Figure 38. 4 x I/O Read Performance Enhance Mode Sequence (QPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
A1
A0
8
9
10
11
12
13
14
15
16
17
H0
L0
H1
L1
SCLK
Mode 0
SIO[3:0]
EBh
A5
A4
A3
A2
X
X
X
X
MSB LSB MSB LSB
P(7:4) P(3:0)
Data In
Data Out
performance
enhance
indicator
Configurable
Dummy Cycle (Note 1)
CS#
n+1
.............
SCLK
Mode 0
SIO[3:0]
A5
A4
A3
A2
A1
X
A0
X
X
H0
L0
H1
L1
MSB LSB MSB LSB
P(7:4) P(3:0)
6 Address cycles
X
Data Out
performance
enhance
indicator
Configurable
Dummy Cycle (Note 1)
Notes:
1. Configuration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in
configuration register.
2. Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF.
P/N: PM2642
Macronix Proprietary
46
Rev. 1.2, November 21, 2019
MX25U12832F
9-19. Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used
for any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit
before sending the Sector Erase (SE). Any address of the sector (please refer to "Table 4. Memory Organization")
is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the least
significant bit of the address byte been latched-in); otherwise, the instruction will be rejected and not executed.
Address bits [Am-A12] (Am is the most significant address) select the sector address.
The sequence of issuing SE instruction is: CS# goes low→ sending SE instruction code→ 3-byte address on SI→
CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets 1 during the tSE
timing, and clears when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the
Block is protected by BP bits (WPSEL=0; Block Lock (BP) protection mode) or SPB/DPB (WPSEL=1; Advanced
Sector Protection mode), the Sector Erase (SE) instruction will not be executed on the block.
Figure 39. Sector Erase (SE) Sequence (SPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Mode 0
24-Bit Address
Command
SI
20h
A23 A22
A2 A1 A0
MSB
Figure 40. Sector Erase (SE) Sequence (QPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
SCLK
Mode 0
24-Bit Address
Command
SIO[3:0]
20h A5 A4 A3 A2 A1 A0
MSB
P/N: PM2642
Macronix Proprietary
47
Rev. 1.2, November 21, 2019
MX25U12832F
9-20. Block Erase (BE32K)
The Block Erase (BE32K) instruction is for erasing the data of the chosen block to be "1". The instruction is used for
32K-byte block erase operation. A Write Enable (WREN) instruction be executed to set the Write Enable Latch (WEL)
bit before sending the Block Erase (BE32K). Any address of the block (Please refer to "Table 4. Memory Organization") is a valid address for Block Erase (BE32K) instruction. The CS# must go high exactly at the byte boundary (the
least significant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE32K instruction is: CS# goes low→ sending BE32K instruction code→ 3-byte address
on SI→CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
The self-timed Block Erase Cycle time (tBE32K) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while during the Block Erase cycle is in progress. The WIP sets during the
tBE32K timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If
the Block is protected by BP bits (WPSEL=0; Block Lock (BP) protection mode) or SPB/DPB (WPSEL=1; Advanced
Sector Protection mode), the Block Erase (BE32K) instruction will not be executed on the block.
Figure 41. Block Erase 32KB (BE32K) Sequence (SPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Mode 0
Command
SI
24-Bit Address
52h
A23 A22
A2 A1 A0
MSB
Figure 42. Block Erase 32KB (BE32K) Sequence (QPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
SCLK
Mode 0
24-Bit Address
Command
SIO[3:0]
52h
A5 A4 A3 A2 A1 A0
MSB
P/N: PM2642
Macronix Proprietary
48
Rev. 1.2, November 21, 2019
MX25U12832F
9-21. Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for
64K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable Latch
(WEL) bit before sending the Block Erase (BE). Any address of the block (Please refer to "Table 4. Memory Organization") is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the
least significant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE instruction is: CS# goes low→ sending BE instruction code→ 3-byte address on SI→
CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets during the tBE
timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the Block
is protected by BP bits (WPSEL=0; Block Lock (BP) protection mode) or SPB/DPB (WPSEL=1; Advanced Sector
Protection mode), the Block Erase (BE) instruction will not be executed on the block.
Figure 43. Block Erase (BE) Sequence (SPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Mode 0
Command
SI
24-Bit Address
D8h
A23 A22
A2 A1 A0
MSB
Figure 44. Block Erase (BE) Sequence (QPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
SCLK
Mode 0
24-Bit Address
Command
SIO[3:0]
D8h
A5 A4 A3 A2 A1 A0
MSB
P/N: PM2642
Macronix Proprietary
49
Rev. 1.2, November 21, 2019
MX25U12832F
9-22. Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must
go high exactly at the byte boundary, otherwise the instruction will be rejected and not executed.
The sequence of issuing CE instruction is: CS# goes low→sending CE instruction code→CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Chip Erase cycle is in progress. The WIP sets during the tCE timing, and clears when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared.
When the chip is under "Block Lock (BP) protection mode" (WPSEL=0): The Chip Erase(CE) instruction will not be
executed, if one (or more) sector is protected by BP3-BP0 bits. It will be only executed when BP3-BP0 all set to "0".
When the chip is under "Advanced Sector Protection mode" (WPSEL=1): The Chip Erase (CE) instruction will be
executed on unprotected block. The protected Block will be skipped. If one (or more) 4K byte sector was protected
in top or bottom 64K byte block, the protected block will also skip the chip erase command.
Figure 45. Chip Erase (CE) Sequence (SPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
SCLK
Mode 0
Command
SI
60h or C7h
Figure 46. Chip Erase (CE) Sequence (QPI Mode)
CS#
Mode 3
0
1
SCLK
Mode 0
Command
SIO[3:0]
P/N: PM2642
60h or C7h
Macronix Proprietary
50
Rev. 1.2, November 21, 2019
MX25U12832F
9-23. Page Program (PP)
The Page Program (PP) instruction is for programming memory bits to "0". One to 256 bytes can be sent to the device to be programmed. A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL)
bit before sending the Page Program (PP). If more than 256 data bytes are sent to the device, only the last 256
data bytes will be accepted and the previous data bytes will be disregarded. The Page Program instruction requires
that all the data bytes fall within the same 256-byte page. The low order address byte A[7:0] specifies the starting
address within the selected page. Bytes that will cross a page boundary will wrap to the beginning of the selected
page. The device can accept (256 minus A[7:0]) data bytes without wrapping. If 256 data bytes are going to be programmed, A[7:0] should be set to 0.
The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→ at
least 1-byte on data on SI→ CS# goes high.
The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte boundary (
the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed.
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Page Program cycle is in progress. The WIP sets during the tPP
timing, and clears when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the
Block is protected by BP bits (WPSEL=0; Block Lock (BP) protection mode) or SPB/DPB (WPSEL=1; Advanced
Sector Protection mode) the Page Program (PP) instruction will not be executed.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
P/N: PM2642
Macronix Proprietary
51
Rev. 1.2, November 21, 2019
MX25U12832F
Figure 47. Page Program (PP) Sequence (SPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
1
0
7
6
5
3
2
1
0
2079
2
2078
3
2077
23 22 21
02h
SI
Data Byte 1
24-Bit Address
2076
Command
2075
Mode 0
4
1
0
MSB
MSB
2074
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
2073
2072
CS#
SCLK
Data Byte 2
7
SI
6
5
4
3
2
Data Byte 3
1
MSB
0
7
6
5
4
3
2
Data Byte 256
1
7
0
MSB
6
5
4
3
2
MSB
Figure 48. Page Program (PP) Sequence (QPI Mode)
CS#
Mode 3
0
1
2
SCLK
Mode 0
Command
SIO[3:0]
02h
Data In
P/N: PM2642
24-Bit Address
A5
A4
A3
A2
A1
A0
H0
L0
H1
L1
H2
L2
H3
L3
Data Byte Data Byte Data Byte Data Byte
1
2
3
4
Macronix Proprietary
52
H255 L255
......
Data Byte
256
Rev. 1.2, November 21, 2019
MX25U12832F
9-24. 4 x I/O Page Program (4PP)
The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1" before sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1, SIO2, and
SIO3 as address and data input, which can improve programmer performance and the effectiveness of application.
The other function descriptions are as same as standard page program.
The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on
SIO[3:0]→ at least 1-byte on data on SIO[3:0]→CS# goes high.
If the page is protected by BP bits (WPSEL=0; Block Lock (BP) protection mode) or SPB/DPB (WPSEL=1; Advanced Sector Protection mode), the Quad Page Program (4PP) instruction will not be executed.
Figure 49. 4 x I/O Page Program (4PP) Sequence (SPI Mode only)
CS#
Mode 3
0
1
2
3
4
5
6
7
9 10 11 12 13 14 15 16 17 18 19 20 21
8
SCLK
Mode 0
Data Data Data Data
Byte 1 Byte 2 Byte 3 Byte 4
6 Address cycle
A0
4
0
4
0
4
0
4
0
SIO1
A21 A17 A13 A9 A5 A1
5
1
5
1
5
1
5
1
SIO2
A22 A18 A14 A10 A6 A2
6
2
6
2
6
2
6
2
SIO3
A23 A19 A15 A11 A7 A3
7
3
7
3
7
3
7
3
SIO0
P/N: PM2642
Command
38h
A20 A16 A12 A8 A4
Macronix Proprietary
53
Rev. 1.2, November 21, 2019
MX25U12832F
9-25. Factory Mode Erase/Program Operations
9-25-1. Factory Mode Sector Erase / 32KB Block Erase / 64KB Block Erase/ Chip Erase
To apply Factory Mode Sector Erase / 32KB Block Erase / 64KB Block Erase / Chip Erase, customers need to follow
the operation below:
Factory Mode Enable (FMEN): The Factory Mode Enable (FMEN) instruction is for enhancing Sector Erase / 32KB
Block Erase / 64KB Block Erase / Chip Erase performance, which increase factory production throughput. The
FMEN instruction will need to be combined with the SE / BE32K / BE / CE instruction when user intends to change
the device content.
A valid factory mode operation need to include three sequences: WREN instruction → FMEN instruction→ SE /
BE32K / BE / CE instruction. The sequence of issuing FMEN instruction is: CS# goes low→send FMEN instruction
code→ CS# goes high. Please note that Suspend command is not acceptable during factory mode.
The FMEN will be reset in following situations: Power-up, Reset# pin driven low, SE / BE32K / BE / CE command
completion, and Softreset command completion.
Figure 50. Factory Mode Erase Flow
Start
WREN Command
RDSR Command
WEL=1?
No
Yes
FMEN Command
Read Factory
Status Command
Factory Status Bit
[7:0]=FFh?
No
Yes
Sector Erase /
32KB Block Erase /
64KB Block Erase /
Chip Erase Command*
Factory Mode
Sector Erase /
32KB Block Erase /
64KB Block Erase /
Chip Erase
Completed
Note: * Please refer to "Figure 21. Program/Erase flow with read array data" and "Figure 22. Program/Erase flow
without read array data (read P_FAIL/E_FAIL flag)".
P/N: PM2642
Macronix Proprietary
54
Rev. 1.2, November 21, 2019
MX25U12832F
9-25-2. Factory Mode Page Program
To apply Factory Mode Page Program, customers need to follow the operation below:
Factory Mode Enable (FMEN): The Factory Mode Enable (FMEN) instruction is for enhancing Page Program
performance, which increase factory production throughput. The FMEN instruction will need to be combined with the
PP instruction when user intends to change the device content.
A valid factory mode operation need to include three sequences: WREN instruction → FMEN instruction→ PP
instruction. The sequence of issuing FMEN instruction is: CS# goes low→send FMEN instruction code→ CS# goes
high. Please note that Suspend command is not acceptable during factory mode.
The FMEN will be reset in following situations: Power-up, Reset# pin driven low, PP command completion, and
Softreset command completion.
Figure 51. Factory Mode Page Program Flow
Start
WREN Command
RDSR Command
WEL=1?
No
Yes
FMEN Command
Read Factory
Status Command
Factory Status Bit
[7:0]=FFh?
No
Yes
Page Program Command*
Factory Mode
PP Completed
Note: * Please reference Program/Erase flow chart in datasheet.
Note: Please refer to "Figure 21. Program/Erase flow with read array data" and "Figure 22. Program/Erase flow
without read array data (read P_FAIL/E_FAIL flag)".
P/N: PM2642
Macronix Proprietary
55
Rev. 1.2, November 21, 2019
MX25U12832F
9-26. Read Factory Mode Status
• Read Factory Mode Status Register command is used to read chip status and check it is at factory mode or not.
• Like RDSR (Read Status Register, 05h), Factory Mode status will be outputted to the SO pin following this Read
Factory Mode Status Register command (RDFMSR command, 44h). Please note that Read Factory Mode Status
Register command is only available in read mode and it is not workable in program/erase process.
• Factory Mode status bit [7:0] shows Factory mode indicators. FMEN command can set them to 1, and the bits will
automatically be reset after the end of erase or program operation.
Bit
Description
7 to 0
FACTORY_MODE
Bit Status
00h = Not in Factory Mode
FFh = In Factory Mode
Default
00h
Figure 52. Read Factory Mode Status Register (SPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
Mode 0
command
44h
SI
SO
Factory Mode Status Register Out Factory Mode Status Register Out
High-Z
7
6
5
4
3
2
MSB
1
0
7
6
5
4
3
2
1
0
7
MSB
Figure 53. Read Status Register (RDSR) Sequence (QPI Mode)
CS#
Mode 3 0
1
2
3
4
5
6
7
N
SCLK
Mode 0
SIO[3:0]
44h H0 L0 H0 L0 H0 L0
H0 L0
MSB LSB
Factory Mode Factory Mode Factory Mode
Status Byte Status Byte Status Byte
P/N: PM2642
Macronix Proprietary
56
Factory Mode
Status Byte
Rev. 1.2, November 21, 2019
MX25U12832F
9-27. Deep Power-down (DP)
The Deep Power-down (DP) instruction places the device into a minimum power consumption state, Deep Power
down mode, in which the quiescent current is reduced from ISB1 to ISB2.
The sequence of issuing DP instruction: CS# goes low→ send DP instruction code→ CS# goes high. The CS# must
go high at the byte boundary; otherwise the instruction will not be executed. SIO[3:1] are "don't care".
After CS# goes high there is a delay of tDP before the device transitions from Stand-by mode to Deep Power-down
mode and the current reduces from ISB1 to ISB2. Once in Deep Power-down mode, all instructions will be ignored.
CS# must not be pulsed low until the device has been in Deep Power-down mode for a minimum of tDPDD. The
device exits Deep Power-down mode and returns to Stand-by mode if CS# pulses low for tCRDP or if the device is
power-cycled or hardware reset. After CS# goes high, there is a delay of tRDP before the device transitions from
Deep Power-down mode back to Stand-by mode.
Figure 54. Deep Power-down (DP) Sequence and Release from Deep Power-down Sequence (SPI Mode)
tCRDP
CS#
tDP
Mode 3
0
1
2
3
4
5
6
tDPDD
tRDP
7
SCLK
Mode 0
Command
B9h
SI
Stand-by Mode
Deep Power-down Mode
Stand-by Mode
Figure 55. Deep Power-down (DP) Sequence and Release from Deep Power-down Sequence (QPI Mode)
CS#
tDP
Mode 3
0
tDPDD
tCRDP
1
tRDP
SCLK
Mode 0
Command
SIO[3:0]
B9h
Stand-by Mode
P/N: PM2642
Deep Power-down Mode
Macronix Proprietary
57
Stand-by Mode
Rev. 1.2, November 21, 2019
MX25U12832F
9-28. Enter Secured OTP (ENSO)
The ENSO instruction is for entering the additional 8K-bit secured OTP mode. The additional 8K-bit secured OTP is
independent from main array, which may use to store unique serial number for system identifier. After entering the
Secured OTP mode, and then follow standard read or program procedure to read out the data or update data. The
Secured OTP data cannot be updated again once it is lock-down.
The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP
mode→ CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
Please note that after issuing ENSO command user can only access secure OTP region with standard read or program procedure. Furthermore, once security OTP is lock down, only read related commands are valid.
9-29. Exit Secured OTP (EXSO)
The EXSO instruction is for exiting the additional 8K-bit secured OTP mode.
The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP
mode→ CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
P/N: PM2642
Macronix Proprietary
58
Rev. 1.2, November 21, 2019
MX25U12832F
9-30. Read Security Register (RDSCUR)
The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read
at any time (even in program/erase/write status register/write security register condition) and continuously.
The sequence of issuing RDSCUR instruction is : CS# goes low→sending RDSCUR instruction→Security Register
data out on SO→ CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
Figure 56. Read Security Register (RDSCUR) Sequence (SPI Mode)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
command
2Bh
SI
SO
Security register Out
High-Z
7
6
5
4
3
2
1
Security register Out
0
7
6
5
4
3
2
1
0
7
MSB
MSB
Figure 57. Read Security Register (RDSCUR) Sequence (QPI Mode)
CS#
Mode 3 0
1
2
3
4
5
6
7
N
SCLK
Mode 0
SIO[3:0]
2Bh H0 L0 H0 L0 H0 L0
H0 L0
MSB LSB
Security Byte Security Byte Security Byte
P/N: PM2642
Macronix Proprietary
59
Security Byte
Rev. 1.2, November 21, 2019
MX25U12832F
9-31. Write Security Register (WRSCUR)
The WRSCUR instruction is for changing the values of Security Register Bits. The WREN (Write Enable) instruction
is required before issuing WRSCUR instruction. The WRSCUR instruction may change the values of bit1 (LDSO bit)
for customer to lock-down the 1st 4K-bit Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area
cannot be updated any more.
The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
Figure 58. Write Security Register (WRSCUR) Sequence (SPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
SCLK
Mode 0
Command
SI
2Fh
High-Z
SO
Figure 59. Write Security Register (WRSCUR) Sequence (QPI Mode)
CS#
Mode 3
0
1
SCLK
Mode 0
Command
SIO[3:0]
P/N: PM2642
2Fh
Macronix Proprietary
60
Rev. 1.2, November 21, 2019
MX25U12832F
Security Register
The definition of the Security Register bits is as below:
Write Protection Selection bit. Please reference to "9-32. Write Protection Selection (WPSEL)".
Erase Fail bit. The Erase Fail bit shows the status of last Erase operation. The bit will be set to "1" if the erase
operation failed or the erase region was protected. It will be automatically cleared to "0" if the next erase operation
succeeds. Please note that it will not interrupt or stop any operation in the flash memory.
Program Fail bit. The Program Fail bit shows the status of the last Program operation. The bit will be set to "1" if
the program operation failed or the program region was protected. It will be automatically cleared to "0" if the next
program operation succeeds. Please note that it will not interrupt or stop any operation in the flash memory.
Erase Suspend bit. Erase Suspend Bit (ESB) indicates the status of Erase Suspend operation. Users may use
ESB to identify the state of flash memory. After the flash memory is suspended by Erase Suspend command, ESB
is set to "1". ESB is cleared to "0" after erase operation resumes.
Program Suspend bit. Program Suspend Bit (PSB) indicates the status of Program Suspend operation. Users may
use PSB to identify the state of flash memory. After the flash memory is suspended by Program Suspend command,
PSB is set to "1". PSB is cleared to "0" after program operation resumes.
Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for cus
tomer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 1st 4K-bit Secured
OTP area cannot be updated any more. While it is in 8K-bit secured OTP mode, main array access is not allowed.
Secured OTP Indicator bit. The Secured OTP indicator bit shows the 2nd 4K-bit Secured OTP area is locked by
factory or not. When it is "0", it indicates non-factory lock; "1" indicates factory-lock.
Table 12. Security Register Definition
bit7
WPSEL
bit6
E_FAIL
0= Block Lock
0= normal
(BP) protection
Erase
mode
succeed
1= Advanced
1= indicate
Sector Protection
Erase failed
mode
(default=0)
(default=0)
Non-volatile bit
(OTP)
P/N: PM2642
Volatile bit
bit5
P_FAIL
bit4
bit3
bit2
ESB
PSB
Reserved
(Erase
(Program
Suspend bit) Suspend bit)
0= normal
Program
succeed
1= indicate
Program
failed
(default=0)
-
0= Erase
is not
suspended
1= Erase
suspended
(default=0)
Volatile bit
Volatile bit
Volatile bit
Macronix Proprietary
61
bit1
bit0
LDSO
Secured OTP
(lock-down Indicator bit
1st 4K-bit
(2nd 4K-bit
Secured
Secured
OTP)
OTP)
0= not
0= Program
lockdown 0= nonfactory
is not
lock
suspended 1= lock-down
(cannot
1= factory
1= Program
suspended
program/
lock
(default=0) erase OTP)
Volatile bit
Non-volatile
bit (OTP)
Non-volatile
bit (OTP)
Rev. 1.2, November 21, 2019
MX25U12832F
9-32. Write Protection Selection (WPSEL)
There are two write protection methods provided on this device, (1) Block Protection (BP) mode or (2) Advanced
Sector Protection mode. The protection modes are mutually exclusive. The WPSEL bit selects which protection
mode is enabled. If WPSEL=0 (factory default), BP mode is enabled and Advanced Sector Protection mode is disabled. If WPSEL=1, Advanced Sector Protection mode is enabled and BP mode is disabled. The WPSEL command
is used to set WPSEL=1. A WREN command must be executed to set the WEL bit before sending the WPSEL command. Please note that the WPSEL bit is an OTP bit. Once WPSEL is set to “1”, it cannot be programmed back to “0”.
When WPSEL = 0: Block Lock (BP) protection mode,
The memory array is write protected by the BP3-BP0 bits.
When WPSEL =1: Advanced Sector Protection mode,
Blocks are individually protected by their own SPB or DPB. On power-up, all blocks are write protected by the Dynamic Protection Bits (DPB) by default. The Advanced Sector Protection instructions WRLR, RDLR, WRSPB, ESSPB, WRDPB, RDDPB, GBLK, and GBULK are activated. The BP3-BP0 bits of the Status Register are disabled
and have no effect. Hardware protection is performed by driving WP#=0. Once WP#=0 all blocks and sectors are
write protected regardless of the state of each SPB or DPB.
The sequence of issuing WPSEL instruction is: CS# goes low → send WPSEL instruction to enable the Advanced
Sector Protection mode → CS# goes high.
Figure 60. Write Protection Selection
Start
(Default in BP Mode)
WPSEL=1
Set
WPSEL Bit
Advanced
Sector Protection
P/N: PM2642
WPSEL=0
Block Protection
(BP)
Macronix Proprietary
62
Rev. 1.2, November 21, 2019
MX25U12832F
Figure 61. WPSEL Flow
start
WREN command
RDSCUR command
Yes
WPSEL=1?
No
WPSEL disable,
block protected by BP[3:0]
WPSEL command
RDSR command
WIP=0?
No
Yes
RDSCUR command
WPSEL=1?
No
Yes
WPSEL set successfully
WPSEL set fail
WPSEL enable.
Block protected by Advance Sector Protection
P/N: PM2642
Macronix Proprietary
63
Rev. 1.2, November 21, 2019
MX25U12832F
9-33. Advanced Sector Protection
Advanced Sector Protection can protect individual 4KB sectors in the bottom and top 64KB of memory and protect
individual 64KB blocks in the rest of memory.
There is one non-volatile Solid Protection Bit (SPB) and one volatile Dynamic Protection Bit (DPB) assigned to each
4KB sector at the bottom and top 64KB of memory and to each 64KB block in the rest of memory. A sector or block
is write-protected from programming or erasing when its associated SPB or DPB is set to “1”.
The figure below helps describing an overview of these methods. The device is default to the Solid mode when
shipped from factory. The detail algorithm of advanced sector protection is shown as follows:
Solid Protection mode permits the SPB bits to be modified after power-on or a reset. The figure below is an
overview of Advanced Sector Protection.
Figure 62. Advanced Sector Protection Overview
Start
Set
SPB Lock Bit ?
SPBLKDN# = 0
SPB Lock bit locked
All SPB can not be changeable
SPBLKDN# = 1
SPB Lock bit Unlocked
SPB is changeable
SPB Access Register
(SPB)
Dynamic Protect Bit Register
(DPB)
DPB=1 sector protect
Sector Array
SPB=1 Write Protect
SPB=0 Write Unprotect
DPB=0 sector unprotect
P/N: PM2642
DPB 0
SA 0
SPB 0
DPB 1
SA 1
SPB 1
DPB 2
SA 2
SPB 2
:
:
:
:
:
:
DPB N-1
SA N-1
SPB N-1
DPB N
SA N
SPB N
Macronix Proprietary
64
Rev. 1.2, November 21, 2019
MX25U12832F
9-33-1. Lock Register
The Lock Register is a 16-bit one-time programmable register. Lock Register bit [6] is SPB Lock Down Bit (SPBLKDN)
which is an unique bit assigned to control all SPB bit status.
When SPBLKDN is 1, SPB can be changed. When it is locked as 0, all SPB can not be changed anymore, and
SPBLKDN bit itself can not be altered anymore, either.
The Lock Register is programmed using the WRLR (Write Lock Register) command. A WREN command must be
executed to set the WEL bit before sending the WRLR command.
Table 13. Lock Register
Bits
Field Name
Function
Type
Default
State
15 to 7
RFU
Reserved
OTP
1
6
SPBLKDN
SPB Lock Down
OTP
1
5 to 0
RFU
Reserved
OTP
1
Description
Reserved for Future Use
1 = SPB changeable
0 = freeze SPB
Reserved for Future Use
Figure 63. Read Lock Register (RDLR) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
Mode 0
command
2Dh
SI
Register Out
High-Z
SO
7
6
5
4
3
2
Register Out
1
0 15 14 13 12 11 10 9
7
8
MSB
MSB
Figure 64. Write Lock Register (WRLR) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Mode 0
SI
SO
P/N: PM2642
Command
2Ch
High-Z
Lock Register In
7
6
5
4
3
2
1
0 15 14 13 12 11 10 9
8
MSB
Macronix Proprietary
65
Rev. 1.2, November 21, 2019
MX25U12832F
9-33-2. Solid Protection Bits
The Solid Protection Bits (SPBs) are nonvolatile bits for enabling or disabling write-protection to sectors and blocks.
The SPB bits have the same endurance as the Flash memory. An SPB is assigned to each 4KB sector in the bottom
and top 64KB of memory and to each 64KB block in the remaining memory. The factory default state of the SPB bits
is “0”, which has the sector/block write-protection disabled.
When an SPB is set to “1”, the associated sector or block is write-protected. Program and erase operations on the
sector or block will be inhibited. SPBs can be individually set to “1” by the WRSPB command. However, the SPBs
cannot be individually cleared to “0”. Issuing the ESSPB command clears all SPBs to “0”. A WREN command must
be executed to set the WEL bit before sending the WRSPB or ESSPB command.
The RDSPB command reads the status of the SPB of a sector or block. The RDSPB command returns 00h if the
SPB is “0”, indicating write-protection is disabled. The RDSPB command returns FFh if the SPB is “1”, indicating
write-protection is enabled.
Note: If SPBLKDN=0, commands to set or clear the SPB bits will be ignored.
Table 14. SPB Register
Bit
Description
7 to 0 SPB (Solid Protection Bit)
P/N: PM2642
Bit Status
00h = Unprotect Sector / Block
FFh = Protect Sector / Block
Macronix Proprietary
66
Default
Type
00h
Non-volatile
Rev. 1.2, November 21, 2019
MX25U12832F
Figure 65. Read SPB Status (RDSPB) Sequence
CS#
0
Mode 3
1
2
3
4
5
6
7
8
37 38 39 40 41 42 43 44 45 46 47
9
SCLK
Mode 0
Command
SI
32-Bit Address
(Note)
E2h
A31 A30
A2 A1 A0
MSB
Data Out
High-Z
SO
7
6
5
4
3
2
1
0
MSB
Note: A31-A24 are don't care.
Figure 66. SPB Erase (ESSPB) Sequence
CS#
1
0
Mode 3
2
3
4
5
6
7
SCLK
Mode 0
Command
SI
E4h
High-Z
SO
Figure 67. SPB Program (WRSPB) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
37 38 39
9
SCLK
Mode 0
SI
Command
32-Bit Address
(Note)
E3h
A31 A30
A2 A1 A0
MSB
Note: A31-A24 are don't care
P/N: PM2642
Macronix Proprietary
67
Rev. 1.2, November 21, 2019
MX25U12832F
9-33-3. Dynamic Protection Bits
The Dynamic Protection Bits (DPBs) are volatile bits for quickly and easily enabling or disabling write-protection
to sectors and blocks. A DPB is assigned to each 4KB sector in the bottom and top 64KB of memory and to each
64KB block in the rest of the memory. The DBPs can enable write-protection on a sector or block regardless of the
state of the corresponding SPB. However, the DPB bits can only unprotect sectors or blocks whose SPB bits are “0”
(unprotected).
When a DPB is “1”, the associated sector or block will be write-protected, preventing any program or erase
operation on the sector or block. All DPBs default to “1” after power-on or reset. When a DPB is cleared to “0”, the
associated sector or block will be unprotected if the corresponding SPB is also “0”.
DPB bits can be individually set to “1” or “0” by the WRDPB command. The DBP bits can also be globally cleared to
“0” with the GBULK command or globally set to “1” with the GBLK command. A WREN command must be executed
to set the WEL bit before sending the WRDPB, GBULK, or GBLK command.
The RDDPB command reads the status of the DPB of a sector or block. The RDDPB command returns 00h if the
DPB is “0”, indicating write-protection is disabled. The RDDPB command returns FFh if the DPB is “1”, indicating
write-protection is enabled.
Table 15. DPB Register
Bit
Description
Bit Status
00h = Unprotect Sector / Block
FFh = Protect Sector / Block
7 to 0 DPB (Dynamic Protection Bit)
Default
Type
FFh
Volatile
Figure 68. Read DPB Register (RDDPB) Sequence
CS#
0
Mode 3
1
2
3
4
5
6
7
8
37 38 39 40 41 42 43 44 45 46 47
9
SCLK
Mode 0
Command
SI
32-Bit Address
(Note)
E0h
A31 A30
A2
A1
A0
MSB
Data Out
High-Z
SO
7
6
5
4
3
2
1
0
MSB
Note: A31-A24 are don't care.
Figure 69. Write DPB Register (WRDPB) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
37 38 39 40 41 42 43 44 45 46 47
9
SCLK
Mode 0
SI
Command
E1h
Data Byte 1
32-Bit Address
(Note)
A31 A30
A2 A1 A0
MSB
7
6
5
4
3
2
1
0
MSB
Note: A31-A24 are don't care.
P/N: PM2642
Macronix Proprietary
68
Rev. 1.2, November 21, 2019
MX25U12832F
9-33-4. Gang Block Lock/Unlock (GBLK/GBULK)
These instructions are only effective if WPSEL=1. The GBLK and GBULK instructions provide a quick method to set
or clear all DPB bits at once.
The WREN (Write Enable) instruction is required before issuing the GBLK/GBULK instruction.
The sequence of issuing GBLK/GBULK instruction is: CS# goes low → send GBLK/GBULK (7Eh/98h) instruction
→CS# goes high.
The GBLK and GBULK commands are accepted in both SPI and QPI mode.
The CS# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed.
9-33-5. Sector Protection States Summary Table
Protection Status
DPB
SPB
Sector/Block
Protection State
0
0
Unprotected
0
1
Protected
1
0
Protected
1
1
Protected
P/N: PM2642
Macronix Proprietary
69
Rev. 1.2, November 21, 2019
MX25U12832F
9-34. Program Suspend and Erase Suspend
The Suspend instruction interrupts a Page Program, Sector Erase, or Block Erase operation to allow access to the
memory array. After the program or erase operation has entered the suspended state, the memory array can be
read except for the page being programmed or the sector or block being erased ("Table 16. Readable Area of Memory While a Program or Erase Operation is Suspended").
Table 16. Readable Area of Memory While a Program or Erase Operation is Suspended
Suspended Operation
Readable Region of Memory Array
Page Program
All but the Page being programmed
Sector Erase (4KB)
All but the 4KB Sector being erased
Block Erase (32KB)
All but the 32KB Block being erased
Block Erase (64KB)
All but the 64KB Block being erased
When the Serial NOR Flash receives the Suspend instruction, there is a latency of tPSL or tESL ("Figure 70. Suspend to Read Latency") before the Write Enable Latch (WEL) bit clears to “0” and the PSB or ESB sets to “1”, after
which the device is ready to accept one of the commands listed in "Table 17. Acceptable Commands During Program/Erase Suspend after tPSL/tESL" (e.g. FAST READ). Refer to "Table 24. AC CHARACTERISTICS" for tPSL
and tESL timings. "Table 18. Acceptable Commands During Suspend (tPSL/tESL not required)" lists the commands
for which the tPSL and tESL latencies do not apply. For example, RDSR, RDSCUR, RSTEN, and RST can be issued at any time after the Suspend instruction.
Security Register bit 2 (PSB) and bit 3 (ESB) can be read to check the suspend status. The PSB (Program Suspend
Bit) sets to “1” when a program operation is suspended. The ESB (Erase Suspend Bit) sets to “1” when an erase
operation is suspended. The PSB or ESB clears to “0” when the program or erase operation is resumed.
Figure 70. Suspend to Read Latency
tPSL / tESL
CS#
Suspend Command
Read Command
tPSL: Program Latency
tESL: Erase Latency
P/N: PM2642
Macronix Proprietary
70
Rev. 1.2, November 21, 2019
MX25U12832F
Table 17. Acceptable Commands During Program/Erase Suspend after tPSL/tESL
Command Name
Command Code
READ
03h
FAST READ
0Bh
DREAD
3Bh
QREAD
6Bh
2READ
BBh
4READ
EBh
W4READ
E7h
RDSFDP
5Ah
RDID
9Fh
QPIID
AFh
REMS
90h
EQIO
35h
RSTQIO
F5h
ENSO
B1h
EXSO
C1h
SBL
C0h
RDLR
2Dh
RDSPB
E2h
RDDPB
E0h
WREN
06h
RESUME
7Ah or 30h
PP
02h
4PP
38h
Suspend Type
Program Suspend
Erase Suspend
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Table 18. Acceptable Commands During Suspend (tPSL/tESL not required)
Command Name
Command Code
WRDI
04h
RDSR
05h
RDCR
15h
RDSCUR
2Bh
RES
ABh
RSTEN
66h
RST
99h
NOP
00h
P/N: PM2642
Suspend Type
Program Suspend
Erase Suspend
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Macronix Proprietary
71
Rev. 1.2, November 21, 2019
MX25U12832F
9-34-1. Erase Suspend to Program
The “Erase Suspend to Program” feature allows Page Programming while an erase operation is suspended. Page
Programming is permitted in any unprotected memory except within the sector of a suspended Sector Erase
operation or within the block of a suspended Block Erase operation. The Write Enable (WREN) instruction must be
issued before any Page Program instruction.
A Page Program operation initiated within a suspended erase cannot itself be suspended and must be allowed to
finish before the suspended erase can be resumed. The Status Register can be polled to determine the status of
the Page Program operation. The WEL and WIP bits of the Status Register will remain “1” while the Page Program
operation is in progress and will both clear to “0” when the Page Program operation completes.
Figure 71. Suspend to Program Latency
CS#
Suspend Command
tPSL / tESL
Program Command
tPSL: Program Latency
tESL: Erase Latency
9-35. Program Resume and Erase Resume
The Resume instruction resumes a suspended Page Program, Sector Erase, or Block Erase operation. Before
issuing the Resume instruction to restart a suspended erase operation, make sure that there is no Page Program
operation in progress.
Immediately after the Serial NOR Flash receives the Resume instruction, the WEL and WIP bits are set to “1” and
the PSB or ESB is cleared to “0”. The program or erase operation will continue until finished ("Figure 72. Resume
to Read Latency") or until another Suspend instruction is received. A resume-to-suspend latency of tPRS or tERS
must be observed before issuing another Suspend instruction ("Figure 73. Resume to Suspend Latency").
Please note that the Resume instruction will be ignored if the Serial NOR Flash is in “Performance Enhance Mode”.
Make sure the Serial NOR Flash is not in “Performance Enhance Mode” before issuing the Resume instruction.
Figure 72. Resume to Read Latency
tSE / tBE / tPP
CS#
Resume Command
Read Command
Figure 73. Resume to Suspend Latency
tPRS / tERS
CS#
Resume Command
Suspend Command
tPRS: Program Resume to another Suspend
tERS: Erase Resume to another Suspend
P/N: PM2642
Macronix Proprietary
72
Rev. 1.2, November 21, 2019
MX25U12832F
9-36. No Operation (NOP)
The “No Operation” command is only able to terminate the Reset Enable (RSTEN) command and will not affect any
other command.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
during SPI mode.
9-37. Software Reset (Reset-Enable (RSTEN) and Reset (RST))
The Software Reset operation combines two instructions: Reset-Enable (RSTEN) command following a Reset (RST)
command. It returns the device to a standby mode. All the volatile bits and settings will be cleared then, which
makes the device return to the default status as power on.
To execute Reset command (RST), the Reset-Enable (RSTEN) command must be executed first to perform the
Reset operation. If there is any other command to interrupt after the Reset-Enable command, the Reset-Enable will
be invalid.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
If the Reset command is executed during program or erase operation, the operation will be disabled, the data under
processing could be damaged or lost.
The reset time is different depending on the last operation. For details, please refer to "Table 20. Reset Timing(Other Operation)" for tREADY2.
P/N: PM2642
Macronix Proprietary
73
Rev. 1.2, November 21, 2019
MX25U12832F
Figure 74. Software Reset Recovery
Stand-by Mode
66
CS#
99
tREADY2
Mode
Note: Refer to "Table 20. Reset Timing-(Other Operation)" for tREADY2.
Figure 75. Reset Sequence (SPI mode)
tSHSL
CS#
SCLK
Mode 3
Mode 3
Mode 0
Mode 0
Command
Command
99h
66h
SIO0
Figure 76. Reset Sequence (QPI mode)
tSHSL
CS#
MODE 3
MODE 3
MODE 3
SCLK
MODE 0
SIO[3:0]
P/N: PM2642
Command
MODE 0
66h
Command
MODE 0
99h
Macronix Proprietary
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Rev. 1.2, November 21, 2019
MX25U12832F
9-38. Read SFDP Mode (RDSFDP)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional
and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables
can be interrogated by host system software to enable adjustments needed to accommodate divergent features
from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on
CFI.
The sequence of issuing RDSFDP instruction is CS# goes low→send RDSFDP instruction (5Ah)→send 3 address
bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP operation can use CS#
to high at any time during data out.
SFDP is a JEDEC Standard, JESD216B.
For SFDP register values detail, please contact local Macronix sales channel for Application Note.
Figure 77. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
SO
24 BIT ADDRESS
23 22 21
5Ah
3
2
1
0
High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Cycle
SI
7
6
5
4
3
2
1
0
DATA OUT 2
DATA OUT 1
SO
7
6
5
4
3
2
0
7
MSB
MSB
P/N: PM2642
1
Macronix Proprietary
75
6
5
4
3
2
1
0
7
MSB
Rev. 1.2, November 21, 2019
MX25U12832F
10. RESET
Driving the RESET# pin low for a period of tRLRH or longer will reset the device. After reset cycle, the device is at
the following states:
- Standby mode
- All the volatile bits such as WEL/WIP/SRAM lock bit will return to the default status as power on.
- 3-byte address mode
If the device is under programming or erasing, driving the RESET# pin low will also terminate the operation and data
could be lost. During the resetting cycle, the SO data becomes high impedance and the current will be reduced to
minimum.
Figure 78. RESET Timing
CS#
tRHSL
SCLK
tRH tRS
RESET#
tRLRH
tREADY1 / tREADY2
Table 19. Reset Timing-(Power On)
Symbol Parameter
tRHSL Reset# high before CS# low
tRS
Reset# setup time
tRH
Reset# hold time
tRLRH Reset# low pulse width
tREADY1 Reset Recovery time
Min.
10
15
15
10
35
Typ.
Max.
Unit
us
ns
ns
us
us
Min.
10
15
15
10
40
35
310
12
25
100
40
Typ.
Max.
Unit
us
ns
ns
us
us
us
us
ms
ms
ms
ms
Table 20. Reset Timing-(Other Operation)
Symbol
tRHSL
tRS
tRH
tRLRH
Parameter
Reset# high before CS# low
Reset# setup time
Reset# hold time
Reset# low pulse width
Reset Recovery time (During instruction decoding)
Reset Recovery time (for read operation)
Reset Recovery time (for program operation)
tREADY2 Reset Recovery time(for SE4KB operation)
Reset Recovery time (for BE64K/BE32KB operation)
Reset Recovery time (for Chip Erase operation)
Reset Recovery time (for WRSR operation)
P/N: PM2642
Macronix Proprietary
76
Rev. 1.2, November 21, 2019
MX25U12832F
11. POWER-ON STATE
The device is at below states when power-up:
- Standby mode (please note it is not deep power-down mode)
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage unless the VCC achieves below correct
level:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change
during power up state. When VCC is lower than VWI (POR threshold voltage value), the internal logic is reset and
the flash device has no response to any command.
For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not
guaranteed. The read, write, erase, and program command should be sent after the below time delay:
- tVSL after VCC reached VCC minimum level
Please refer to the "Figure 86. Power-up Timing".
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended. (generally around 0.1uF)
- At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response
to any command. The data corruption might occur during the stage while a write, program, erase cycle is in
progress.
P/N: PM2642
Macronix Proprietary
77
Rev. 1.2, November 21, 2019
MX25U12832F
12. ELECTRICAL SPECIFICATIONS
Table 21. ABSOLUTE MAXIMUM RATINGS
RATING
VALUE
Ambient Operating Temperature
Industrial grade
-40°C to 85°C
Storage Temperature
-65°C to 150°C
Applied Input Voltage
-0.5V to VCC+0.5V
Applied Output Voltage
-0.5V to VCC+0.5V
VCC to Ground Potential
-0.5V to 2.5V
NOTICE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage
to the device. This is stress rating only and functional operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended period may affect reliability.
2. Specifications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see
Figure 79 and Figure 80.
Figure 80. Maximum Positive Overshoot Waveform
Figure 79. Maximum Negative Overshoot Waveform
20ns
20ns
20ns
Vss
Vcc + 2.0V
Vss-2.0V
Vcc
20ns
20ns
20ns
Table 22. CAPACITANCE TA = 25°C, f = 1.0 MHz
Symbol Parameter
CIN
COUT
P/N: PM2642
Min.
Typ.
Max.
Unit
Input Capacitance
6
pF
VIN = 0V
Output Capacitance
8
pF
VOUT = 0V
Macronix Proprietary
78
Conditions
Rev. 1.2, November 21, 2019
MX25U12832F
Figure 81. DATA INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL
Input timing reference level
0.8VCC
Output timing referance level
0.7VCC
AC
Measurement
Level
0.2VCC
0.1VCC
0.5VCC
Note: Input pulse rise and fall time are 50MHz
Others
45% x (1/fTSCLK)
(fSCLK/fTSCLK)
Clock High Time
≤ 50MHz
7
Normal Read (fRSCLK)
7
45% x (1/fSCLK)
> 50MHz
Others
45% x (1/fTSCLK)
(fSCLK/fTSCLK)
Clock Low Time
≤ 50MHz
7
Normal Read (fRSCLK)
7
Clock Rise Time (peak to peak)
0.1
Clock Fall Time (peak to peak)
0.1
CS# Active Setup Time (relative to SCLK)
5
CS# Not Active Hold Time (relative to SCLK)
5
Data In Setup Time
2
Data In Hold Time
3
CS# Active Hold Time (relative to SCLK)
5
CS# Not Active Setup Time (relative to SCLK)
5
From Read to next Read
7
CS# Deselect Time
From Write/Erase/Program
30
to Read Status Register
Output Disable Time
Clock Low to Output Valid Loading: 30pF
Loading: 30pF/15pF
Loading: 15pF
Loading: 30pF
1
Output Hold Time
Loading: 15pF
1
Write Protect Setup Time
20
Write Protect Hold Time
100
CS# High to Deep Power-down Mode
Delay Time for Release from Deep Power-Down Mode once
entering Deep Power-Down Mode
CS# Toggling Time before Release from Deep Power-Down
Mode
Recovery Time for Release from deep power down mode
Write Status/Configuration Register Cycle Time
Byte-Program
Page Program Cycle Time
Sector Erase Cycle Time
Block Erase (32KB) Cycle Time
Block Erase (64KB) Cycle Time
Chip Erase Cycle Time
Erase Suspend Latency
Program Suspend Latency
Latency between Program Resume and next Suspend
Latency between Erase Resume and next Suspend
Macronix Proprietary
81
Max.
133
50
133(5)
133(5)
Unit
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
8
8
6
10
ns
ns
ns
ns
ns
ns
ns
us
30
us
20
ns
18
0.4
30
150
300
36
0.3
0.3
100
100
30
40
40
3
200
1000
2000
100
25
25
us
ms
us
ms
ms
ms
ms
s
us
us
us
us
Rev. 1.2, November 21, 2019
MX25U12832F
Notes:
1. tCH + tCL must be greater than or equal to 1/ Frequency.
2. Typical values given for TA=25°C. Not 100% tested.
3. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
4. Test condition is shown as "Figure 81. DATA INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL" and
"Figure 82. OUTPUT LOADING".
5. By default dummy cycle value. Please refer to the "Table 1. Read performance Comparison".
6. Latency time is required to complete Erase/Program Suspend operation until WIP bit is "0".
7. For tPRS, minimum timing must be observed before issuing the next program suspend command. However, a
period equal to or longer than the typical timing is required in order for the program operation to make progress.
8. For tERS, minimum timing must be observed before issuing the next erase suspend command. However, a period equal to or longer than the typical timing is required in order for the erase operation to make progress.
9. The value guaranteed by characterization, not 100% tested in production.
P/N: PM2642
Macronix Proprietary
82
Rev. 1.2, November 21, 2019
MX25U12832F
13. OPERATING CONDITIONS
At Device Power-Up and Power-Down
AC timing illustrated in "Figure 84. AC Timing at Device Power-Up" and "Figure 85. Power-Down Sequence" are
for the supply voltages and the control signals at device power-up and power-down. If the timing in the figures is ignored, the device will not operate correctly.
During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be
selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL.
Figure 84. AC Timing at Device Power-Up
VCC
VCC(min)
GND
tVR
tSHSL
CS#
tSLCH
tCHSL
tCHSH
tSHCH
SCLK
RESET#
tCHCL
tDVCH
tCLCH
tCHDX
High Impedance
SO
Symbol
tVR
LSB IN
MSB IN
SI
Parameter
VCC Rise Time
Notes
1
Min.
Max.
500000
Unit
us/V
Notes :
1. Sampled, not 100% tested.
2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to
"Table 24. AC CHARACTERISTICS".
P/N: PM2642
Macronix Proprietary
83
Rev. 1.2, November 21, 2019
MX25U12832F
Figure 85. Power-Down Sequence
During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.
VCC
CS#
SCLK
Figure 86. Power-up Timing
VCC
VCC(max)
Chip Selection is Not Allowed
VCC(min)
tVSL
Device is fully accessible
VWI
time
P/N: PM2642
Macronix Proprietary
84
Rev. 1.2, November 21, 2019
MX25U12832F
Figure 87. Power Up/Down and Voltage Drop
When powering down the device, VCC must drop below VPWD for at least tPWD to ensure the device will initialize
correctly during power up. Please refer to "Figure 87. Power Up/Down and Voltage Drop" and "Table 25. Power-Up/
Down Voltage and Timing" below for more details.
VCC
VCC (max.)
Chip Select is not allowed
VCC (min.)
tVSL
Full Device
Access
Allowed
VPWD (max.)
tPWD
Time
Table 25. Power-Up/Down Voltage and Timing
Symbol
tVSL
VWI
VPWD
tPWD
VCC
Parameter
VCC(min.) to device operation
Write Inhibit Voltage
VCC voltage needed to below VPWD for ensuring initialization will occur
The minimum duration for ensuring initialization will occur
VCC Power Supply
Min.
800
1.0
300
1.65
Max.
1.4
0.9
2.0
Unit
us
V
V
us
V
Note: These parameters are characterized only.
13-1. INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status
Register contains 00h (all Status Register bits are 0).
P/N: PM2642
Macronix Proprietary
85
Rev. 1.2, November 21, 2019
MX25U12832F
14. ERASE AND PROGRAMMING PERFORMANCE
Parameter
Min.
Typ. (1)
Write Status Register Cycle Time
Max. (2)
Unit
40
ms
Sector Erase Cycle Time (4KB)
30
200
ms
Block Erase Cycle Time (32KB)
0.15
1
s
Block Erase Cycle Time (64KB)
0.3
2
s
Chip Erase Cycle Time
36
100
s
Byte Program Time (via page program command)
18
40
us
Page Program Time
0.4
3
ms
Erase/Program Cycle
100,000
cycles
Note:
1. Typical program and erase time assumes the following conditions: 25°C, 1.8V, and checkerboard pattern.
2. Under worst conditions of 85°C and 1.65V.
3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming command.
15. ERASE AND PROGRAMMING PERFORMANCE (Factory Mode)
Parameter
Min.
Typ.
Max.
Unit
Sector Erase Cycle Time (4KB)
15
ms
Block Erase Cycle Time (32KB)
0.1
s
Block Erase Cycle Time (64KB)
0.2
s
Chip Erase Cycle Time
25
s
0.33
ms
Page Program Time
Erase/Program Cycle
50
cycles
Notice:
1. Factory Mode must be operated in 20°C to 45°C and VCC 1.8V-2.0V.
2. In Factory mode, the Erase/Program operation should not exceed 50 cycles, and "ERASE AND PROGRAMMING
PERFORMANCE" 100k cycles will not be affected.
3. During factory mode, Suspend command (75h or B0h) cannot be executed.
P/N: PM2642
Macronix Proprietary
86
Rev. 1.2, November 21, 2019
MX25U12832F
16. DATA RETENTION
Parameter
Condition
Min.
Data retention
55˚C
20
Max.
Unit
years
17. LATCH-UP CHARACTERISTICS
Min.
Input Voltage with respect to GND on all power pins
Max.
1.5 VCCmax
Input Current on all non-power pins
-100mA
+100mA
Test conditions: VCC = VCCmax, one pin at a time (compliant to JEDEC JESD78 standard).
P/N: PM2642
Macronix Proprietary
87
Rev. 1.2, November 21, 2019
MX25U12832F
18. ORDERING INFORMATION
Please contact Macronix regional sales for the latest product selection and available form factors.
PART NO.
Package
Temp.
-40°C to
85°C
-40°C to
MX25U12832FZNI02 8-WSON (6x5mm)
85°C
8-WSON
-40°C to
MX25U12832FZ4I02
(8x6mm, 3.4 x 4.3 EP)
85°C
-40°C to
MX25U12832FMI02
16-SOP (300mil)
85°C
MX25U12832FM2I02
P/N: PM2642
8-SOP (200mil)
I/O Configuration
H/W Configuration Remark
Dummy
CS# Default I/O
H/W Pin
Cycle
1 Pin Standard Standard
Reset#
1 Pin Standard Standard
Reset#
1 Pin Standard Standard
Reset#
1 Pin Standard Standard
Reset#
Macronix Proprietary
88
Rev. 1.2, November 21, 2019
MX25U12832F
19. PART NAME DESCRIPTION
MX 25U 12832F M2
I
02
MODEL CODE:
02: Default STR, RESET#, Manufacturing Location
TEMPERATURE RANGE:
I: Industrial (-40°C to 85°C)
PACKAGE:
M2: 8-SOP(200mil)
ZN: 8-WSON (6mmx5mm)
Z4: 8-WSON (8x6mm, 3.4 x 4.3 EP)
M: 16-SOP (300mil)
DENSITY & MODE:
12832F: 128Mb
DEVICE:
25U: Serial NOR Flash (1.65V-2.0V)
P/N: PM2642
Macronix Proprietary
89
Rev. 1.2, November 21, 2019
MX25U12832F
20. PACKAGE INFORMATION
20-1. 8-pin SOP (200mil)
P/N: PM2642
Macronix Proprietary
90
Rev. 1.2, November 21, 2019
MX25U12832F
20-2. 8-land WSON (6x5mm)
P/N: PM2642
Macronix Proprietary
91
Rev. 1.2, November 21, 2019
MX25U12832F
20-3. 16-pin SOP (300mil)
P/N: PM2642
Macronix Proprietary
92
Rev. 1.2, November 21, 2019
MX25U12832F
20-4. 8-land WSON (8x6mm 3.4 x 4.3EP)
P/N: PM2642
Macronix Proprietary
93
Rev. 1.2, November 21, 2019
MX25U12832F
21. REVISION HISTORY
Revision
Descriptions
Page
1. Initial Release.
All
August 31, 2018
0.00
February 27, 2019
0.01
1.
2.
3.
4.
5.
6.
7.
8.
9.
July 01, 2019
1.0
Added 8-land WSON (6x5mm) package part number.
Added Quad IO Fast Read (QPI) (MHz) values.
Added factory mode (command 41h).
Modified the Deep Power-down (DP) Sequence and Release from Deep
Power-down Sequence.
Revised the descriptions of Performance Enhance Mode and wrap around
feature.
Modified Suspend/Resume descriptions; added “Erase Suspend to
Program” feature.
Updated "Figure 81. DATA INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL".
Updated ISB2 and fTSCLK / tSLCH / tCHSL / tCHDX / tCHSH / tSHCH
values; Corrected tCH / tCL descriptions.
Modified LATCH-UP descriptions.
1. Removed the document status "ADVANCED INFORMATION" to align with
the product status.
2. Added Part Number: MX25U12832FMI02.
3. Content correction.
4. Added descriptions for Factory Mode.
5. Updated ISB2 / ICC1 / ICC2 / ICC4 / tSE / tCE.
6. Added RESET# in "Figure 84. AC Timing at Device Power-Up".
7. Added WRSCUR and RDSCUR command figures.
8. Revised LATCH-UP testing descriptions.
November 14, 2019
1.1
1. Update tRDP as maximum 30us.
2. Added typical ICC1 values and optimized typical ICC2/ICC4/ICC5/tPP/
tBE32/tBE/tCE.
3. Description modification.
94
P65-67
P74
P75-76
P82
All
P4-6, 88-89, 92
P8, 15, 42, 92
P16, 54-56
P80-81, 86
P83
P59-60
P87
P44, 47-51, 53,
61-62, 81-82,
87
P4, 6, 88-89, 93
November 21, 2019
1.2
1. Changed package 8-WSON (8x6mm) as 8-WSON (8x6mm, 3.4 x 4.3 EP).
2. Content modification.
Macronix Proprietary
P42-44
P81
P80-81, 86
4. Added Part Number: MX25U12832FZ2I02.
P/N: PM2642
P4, 6, 83-84, 86
P5, 31
P16, 20-21, 81
P22, 53-54, 76
P4, 6, 88-89, 93
P32
Rev. 1.2, November 21, 2019
MX25U12832F
Except for customized products which has been expressly identified in the applicable agreement, Macronix's
products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or
household applications only, and not for use in any applications which may, directly or indirectly, cause death,
personal injury, or severe property damages. In the event Macronix products are used in contradicted to their
target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its
actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or
distributors shall be released from any and all liability arisen therefrom.
Copyright© Macronix International Co., Ltd. 2018-2019. All rights reserved, including the trademarks and
tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, Nbit,
Macronix NBit, HybridNVM, HybridFlash, HybridXFlash, XtraROM, KH Logo, BE-SONOS, KSMC, Kingtech,
MXSMIO, Macronix vEE, RichBook, Rich TV, OctaBus, FitCAM, ArmorFlash. The names and brands of third
party referred thereto (if any) are for identification purposes only.
For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
95
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