MX25U8035ZNI-25G

MX25U8035E MX25U8035E DATASHEET P/N: PM1654 1 REV. 1.7, APR. 02, 2015 MX25U8035E Contents 1.FEATURES................................................................................................................................................................ 4 2.GENERAL DESCRIPTION....................................................................................................................................... 6 Table 1. Additional Feature Comparison....................................................................................................... 6 3.PIN CONFIGURATIONS ........................................................................................................................................... 7 4.PIN DESCRIPTION.................................................................................................................................................... 7 5.BLOCK DIAGRAM..................................................................................................................................................... 8 6.DATA PROTECTION.................................................................................................................................................. 9 Table 2. Protected Area Sizes..................................................................................................................... 10 Table 3. 4K-bit Secured OTP Definition ..................................................................................................... 10 7.Memory Organization............................................................................................................................................. 11 Table 4. Memory Organization (8Mb).......................................................................................................... 11 8.DEVICE OPERATION.............................................................................................................................................. 12 8-1. Quad Peripheral Interface (QPI) Read Mode.............................................................................................. 13 9.COMMAND DESCRIPTION..................................................................................................................................... 15 Table 5. Command Set............................................................................................................................... 15 9-1. Write Enable (WREN)................................................................................................................................. 17 9-2. Write Disable (WRDI).................................................................................................................................. 17 9-3. Read Identification (RDID).......................................................................................................................... 17 9-4. Read Status Register (RDSR).................................................................................................................... 17 Table 6. Status Register.............................................................................................................................. 21 9-5. Write Status Register (WRSR).................................................................................................................... 22 Table 7. Protection Modes.......................................................................................................................... 22 9-6. Read Data Bytes (READ)........................................................................................................................... 23 9-7. Read Data Bytes at Higher Speed (FAST_READ)..................................................................................... 23 9-8. 2 x I/O Read Mode (2READ)...................................................................................................................... 23 9-9. 4 x I/O Read Mode (4READ)...................................................................................................................... 24 9-10. Burst Read.................................................................................................................................................. 25 9-11. Performance Enhance Mode...................................................................................................................... 26 9-12. Performance Enhance Mode Reset (FFh).................................................................................................. 26 9-13. Sector Erase (SE)....................................................................................................................................... 26 9-14. Block Erase (BE32K).................................................................................................................................. 27 9-15. Block Erase (BE)......................................................................................................................................... 27 9-16. Chip Erase (CE).......................................................................................................................................... 27 9-17. Page Program (PP)..................................................................................................................................... 28 9-18. 4 x I/O Page Program (4PP)....................................................................................................................... 28 9-19. Deep Power-down (DP).............................................................................................................................. 29 9-20. Release from Deep Power-down (RDP), Read Electronic Signature (RES).............................................. 29 P/N: PM1654 2 REV. 1.7, APR. 02, 2015 MX25U8035E 9-21. Read Electronic Manufacturer ID & Device ID (REMS).............................................................................. 30 9-22. QPI ID Read (QPIID).................................................................................................................................. 30 Table 8. ID Definitions ................................................................................................................................ 30 9-23. Enter Secured OTP (ENSO)....................................................................................................................... 31 9-24. Exit Secured OTP (EXSO).......................................................................................................................... 31 9-25. Read Security Register (RDSCUR)............................................................................................................ 31 Table 9. Security Register Definition........................................................................................................... 32 9-26. Write Security Register (WRSCUR)............................................................................................................ 32 9-27. Write Protection Selection (WPSEL)........................................................................................................... 32 9-28. Single Block Lock/Unlock Protection (SBLK/SBULK)................................................................................. 34 9-29. Read Block Lock Status (RDBLOCK)......................................................................................................... 36 9-30. Gang Block Lock/Unlock (GBLK/GBULK)................................................................................................... 36 9-31. Program/ Erase Suspend/ Resume............................................................................................................ 36 9-32. Erase Suspend........................................................................................................................................... 36 9-33. Program Suspend....................................................................................................................................... 37 9-34. Write-Resume............................................................................................................................................. 37 9-35. No Operation (NOP)................................................................................................................................... 38 9-36. Software Reset (Reset-Enable (RSTEN) and Reset (RST))....................................................................... 38 9-37. Reset Quad I/O (RSTQIO).......................................................................................................................... 38 9-38. Read SFDP Mode (RDSFDP)..................................................................................................................... 39 Table 10. Signature and Parameter Identification Data Values .................................................................. 40 Table 11. Parameter Table (0): JEDEC Flash Parameter Tables................................................................ 41 Table 12. Parameter Table (1): Macronix Flash Parameter Tables............................................................. 43 10.POWER-ON STATE............................................................................................................................................... 45 11.ELECTRICAL SPECIFICATIONS.......................................................................................................................... 46 11-1. Absolute Maximum Ratings........................................................................................................................ 46 11-2. Capacitance................................................................................................................................................ 46 Table 13. DC Characteristics..................................................................................................................... 48 Table 14. AC Characteristics...................................................................................................................... 49 12.Timing Analysis.................................................................................................................................................... 50 Table 15. Power-Up Timing........................................................................................................................ 70 12-1. Initial Delivery State.................................................................................................................................... 70 13.OPERATING CONDITIONS................................................................................................................................... 71 13-1. At Device Power-Up and Power-Down....................................................................................................... 71 14.ERASE AND PROGRAMMING PERFORMANCE................................................................................................ 73 15.LATCH-UP CHARACTERISTICS.......................................................................................................................... 73 16.ORDERING INFORMATION.................................................................................................................................. 74 17.PART NAME DESCRIPTION................................................................................................................................. 75 18.PACKAGE INFORMATION.................................................................................................................................... 76 19.REVISION HISTORY ............................................................................................................................................. 80 P/N: PM1654 3 REV. 1.7, APR. 02, 2015 MX25U8035E 8M-BIT [x 1/x 2/x 4] 1.8V CMOS MXSMIO® (SERIAL MULTI I/O) FLASH MEMORY 1.FEATURES GENERAL • Supports Serial Peripheral Interface -- Mode 0 and Mode 3 • 8M : 8,388,608 x 1 bit structure or 4,194,304 x 2 bits (two I/O read mode) structure or 2,097,152 x 4 bits (four I/ O read mode) structure • Equal Sectors with 4K byte each, or Equal Blocks with 32K byte each or Equal Blocks with 64K byte each - Any Block can be erased individually • Single Power Supply Operation - 1.65 to 2.0 volt for read, erase, and program operations • Latch-up protected to 100mA from -1V to Vcc +1V • Low Vcc write inhibit is from 1.0V to 1.4V PERFORMANCE • High Performance - Fast read for SPI mode - 1 I/O: 104MHz with 8 dummy cycles - 2 I/O: 84MHz with 4 dummy cycles, equivalent to 168MHz - 4 I/O: 104MHz with 6 dummy cycles, equivalent to 416MHz - Fast read for QPI mode - 4 I/O: 84MHz with 4 dummy cycles, equivalent to 336MHz - 4 I/O: 104MHz with 6 dummy cycles, equivalent to 416MHz - Fast program time: 1.2ms(typ.) and 3ms(max.)/page (256-byte per page) - Byte program time: 10us (typical) - 8/16/32/64 byte Wrap-Around Burst Read Mode - Fast erase time: 45ms (typ.)/sector (4K-byte per sector); 250ms(typ.) /block (32K-byte per block); 500ms(typ.) / block (64K-byte per block); 5s(typ.) /chip • Low Power Consumption - Low active read current: 20mA(max.) at 104MHz, 15mA(max.) at 84MHz - Low active erase/programming current: 20mA (typ.) - Standby current: 25uA (typ.) • Deep Power Down: 2uA(typ.) • Typical 100,000 erase/program cycles • 20 years data retention SOFTWARE FEATURES • Input Data Format - 1-byte Command code • Advanced Security Features - Block lock protection The BP0-BP3 status bit defines the size of the area to be software protection against program and erase instructions - Additional 4k-bit secured OTP for unique identifier • Auto Erase and Auto Program Algorithm - Automatically erases and verifies data at selected sector or block - Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (Any page to be programed should have page in the erased state first) P/N: PM1654 4 REV. 1.7, APR. 02, 2015 MX25U8035E • • • • Status Register Feature Command Reset Program/Erase Suspend Electronic Identification - JEDEC 1-byte manufacturer ID and 2-byte device ID - RES command for 1-byte Device ID - REMS command for 1-byte manufacturer ID and 1-byte device ID • Support Serial Flash Discoverable Parameters (SFDP) mode HARDWARE FEATURES • SCLK Input - Serial clock input • SI/SIO0 - Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode • SO/SIO1 - Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode • WP#/SIO2 - Hardware write protection or serial data Input/Output for 4 x I/O read mode • NC/SIO3 - NC pin or Serial input & Output for 4 x I/O read mode • PACKAGE - 8-pin SOP (150mil) - 8-pin SOP (200mil) - 8-land WSON (6x5mm) - 8-land USON (4x4mm) - All devices are RoHS Compliant and Halogen-free P/N: PM1654 5 REV. 1.7, APR. 02, 2015 MX25U8035E 2.GENERAL DESCRIPTION The MX25U8035E are 8,388,608 bit serial Flash memory, which is configured as 1,048,576 x 8 internally. When it is in two or four I/O read mode, the structure becomes 4,194,304 bits x 2 or 2,097,152 bits x 4. MX25U8035E feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single I/O mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input. When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and data output. When it is in four I/O read mode, the SI pin, SO pin and WP# pin become SIO0 pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output. The MX25U8035E MXSMIO® (Serial Multi I/O) provides sequential read operation on whole chip. After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256 bytes) basis, or word basis for erase command is executed on sector (4K-byte), block (32K-byte), or block (64K-byte), or whole chip basis. To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. Advanced security features enhance the protection and security functions, please see security features section for more details. When the device is not in operation and CS# is high, it is put in standby mode. The MX25U8035E utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles. Table 1. Additional Feature Comparison Additional Features Read Performance Protection and Security SPI QPI Flexible Block 4K-bit security 1 I/O 2 I/O 4 I/O 4 I/O 4 I/O 4 I/O Protection OTP (104 MHz) (84 MHz) (84 MHz) (104 MHz) (84 MHz) (104 MHz) (BP0-BP3) Part Name MX25U8035E Additional Features Part Name MX25U8035E P/N: PM1654 V V V V V V V V Identifier RES REMS RDID (command: (command: (command: AB hex) 90 hex) 9F hex) C2 34 (hex) 34 (hex) C2 25 34 (if ADD=0) 6 QPIID (Command: AF hex) C2 25 34 REV. 1.7, APR. 02, 2015 MX25U8035E 3.PIN CONFIGURATIONS 8-PIN SOP (150mil) / 8-PIN SOP (200mil) 8-LAND USON (4x4mm) CS# SO/SIO1 WP#/SIO2 GND 1 2 3 4 8 7 6 5 VCC NC/SIO3 SCLK SI/SIO0 CS# SO/SIO1 WP#/SIO2 GND 1 2 3 4 8 7 6 5 SYMBOL CS# VCC NC/SIO3 SCLK SI/SIO0 SI/SIO0 SO/SIO1 SCLK WP#/SIO2 NC/SIO3 VCC GND P/N: PM1654 8 7 6 5 VCC NC/SIO3 SCLK SI/SIO0 4.PIN DESCRIPTION 8-LAND WSON (6x5mm) CS# SO/SIO1 WP#/SIO2 GND 1 2 3 4 7 DESCRIPTION Chip Select Serial Data Input (for 1 x I/O)/ Serial Data Input & Output (for 2xI/O or 4xI/ O read mode) Serial Data Output (for 1 x I/O)/ Serial Data Input & Output (for 2xI/O or 4xI/ O read mode) Clock Input Write Protection Active Low or Serial Data Input & Output (for 4xI/O read mode) NC pin (Not connected) or Serial Data Input & Output (for 4xI/O read mode) + 1.8V Power Supply Ground REV. 1.7, APR. 02, 2015 MX25U8035E 5.BLOCK DIAGRAM X-Decoder Address Generator SI/SIO0 SO/SIO1 SIO2 * SIO3 * WP# * HOLD# * RESET# * CS# SCLK Memory Array Y-Decoder Data Register Sense Amplifier SRAM Buffer Mode Logic State Machine HV Generator Clock Generator Output Buffer * Depends on part number options. P/N: PM1654 8 REV. 1.7, APR. 02, 2015 MX25U8035E 6.DATA PROTECTION During power transition, there may be some false system level signals which result in inadvertent erasure or programming. The device is designed to protect itself from these accidental write cycles. The state machine will be reset as standby mode automatically during power up. In addition, the control register architecture of the device constrains that the memory contents can only be changed after specific command sequences have completed successfully. In the following, there are several features to protect the system from the accidental write cycles during VCC powerup and power-down or from system noise. • Power-on reset and tPUW: to avoid sudden power switch by system power supply transition, the power-on reset and tPUW (internal timer) may protect the Flash. • Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary. • Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other command to change data. The WEL bit will return to reset stage under following situation: - Power-up - Write Disable (WRDI) command completion - Write Status Register (WRSR) command completion - Page Program (PP) command completion - Sector Erase (SE) command completion - Block Erase 32KB (BE32K) command completion - Block Erase (BE) command completion - Chip Erase (CE) command completion - Program/Erase Suspend - Softreset command completion - Write Security Register (WRSCUR) command completion - Write Protection Selection (WPSEL) command completion • Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing all commands except Release from deep power down mode command (RDP) and Read Electronic Signature command (RES) and softreset command. • Advanced Security Features: there are some protection and security features which protect content from inadvertent write and hostile access. I. Block lock protection - The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected as read only. The protected area definition is shown as "Table 2. Protected Area Sizes", the protected areas are more flexible which may protect various area by setting value of BP0-BP3 bits. Please refer to "Table 2. Protected Area Sizes". - The Hardware Proteced Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and Status Register Write Protect bit. - In four I/O and QPI mode, the feature of HPM will be disabled. P/N: PM1654 9 REV. 1.7, APR. 02, 2015 MX25U8035E Table 2. Protected Area Sizes BP3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Status bit BP2 BP1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 BP0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Protect Level 8Mb 0 (none) 1 (1block, protected block 15th) 2(2blocks, protected block 14th~15th) 3 (4blocks, protected block 12th~15th) 4 (8blocks, protected block 8th~15th) 5 (16blocks, protected all) 6 (16blocks, protected all) 7 (16blocks, protected all) 8 (16blocks, protected all) 9 (16blocks, protected all) 10 (16blocks, protected all) 11 (8blocks, protected block 0th~7th) 12 (12blocks, protected block 0th~11th) 13 (14blocks, protected block 0th~13th) 14 (15blocks, protected block 0th~14th) 15 (16blocks, protected all) II. Additional 4K-bit secured OTP for unique identifier: to provide 4K-bit one-time program area for setting device unique serial number - Which may be set by factory or system customer. Please refer to "Table 3. 4K-bit Secured OTP Definition". - Security register bit 0 indicates whether the chip is locked by factory or not. - To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with Enter Security OTP (ENSO) command), and going through normal program procedure, and then exiting 4K-bit secured OTP mode by writing Exit Security OTP (EXSO) command. - Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register) command to set customer lock-down bit1 as "1". Please refer to "Table 9. Security Register Definition" for security register bit definition and "Table 3. 4K-bit Secured OTP Definition" for address range definition. - Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit secured OTP mode, array access is not allowed. Table 3. 4K-bit Secured OTP Definition Address range Size Standard Factory Lock xxx000~xxx00F 128-bit ESN (electrical serial number) xxx010~xxx1FF 3968-bit N/A P/N: PM1654 10 Customer Lock Determined by customer REV. 1.7, APR. 02, 2015 MX25U8035E 7.Memory Organization Table 4. Memory Organization (8Mb) Block (64KB) 15 Block (32KB) 31 | 30 14 29 | 28 13 27 | 26 12 25 | 24 11 23 | 22 10 21 | 20 9 19 | 18 8 17 | 16 7 15 | 14 6 13 | 12 5 11 | 10 4 9 | 8 3 7 | 6 2 5 | 4 1 3 | 2 0 1 | 0 P/N: PM1654 Sector (4KB) 255 : 240 239 : 224 223 : 208 207 : 192 191 : 176 175 : 160 159 : 144 143 : 128 127 : 112 111 : 96 95 : 80 79 : 64 63 : 48 47 : 32 31 : 16 15 : 2 1 0 Address Range 0FF000h : 0F0000h 0EF000h : 0E0000h 0DF000h : 0D0000h 0CF000h : 0C0000h 0BF000h : 0B0000h 0AF000h : 0A0000h 09F000h : 090000h 08F000h : 080000h 07F000h : 070000h 06F000h : 060000h 05F000h : 050000h 04F000h : 040000h 03F000h : 030000h 02F000h : 020000h 01F000h : 010000h 00F000h : 002000h 001000h 000000h 0FFFFFh : 0F0FFFh 0EFFFFh : 0E0FFFh 0DFFFFh : 0D0FFFh 0CFFFFh : 0C0FFFh 0BFFFFh : 0B0FFFh 0AFFFFh : 0A0FFFh 09FFFFh : 090FFFh 08FFFFh : 080FFFh 07FFFFh : 070FFFh 06FFFFh : 060FFFh 05FFFFh : 050FFFh 04FFFFh : 040FFFh 03FFFFh : 030FFFh 02FFFFh : 020FFFh 01FFFFh : 010FFFh 00FFFFh : 002FFFh 001FFFh 000FFFh 11 REV. 1.7, APR. 02, 2015 MX25U8035E 8.DEVICE OPERATION 1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation. 2. When incorrect command is inputted to this device, it enters standby mode and remains in standby mode until next CS# falling edge. In standby mode, SO pin of the device is High-Z. 3. When correct command is inputted to this device, it enters active mode and remains in active mode until next CS# rising edge. 4. Input data is latched on the rising edge of Serial Clock (SCLK) and data is shifted out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as "Figure 1. Serial Modes Supported". 5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, RDSFDP, 2READ, 4READ, RES, REMS, SQIID, RDBLOCK, the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE32K, BE, CE, PP, 4PP, DP, ENSO, EXSO, WRSCUR, WPSEL, SBLK, SBULK, GBULK, SUSPEND, RESUME, NOP, RSTEN, RST, EQIO, RSTQIO the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. While a Write Status Register, Program, or Erase operation is in progress, access to the memory array is neglected and will not affect the current operation of Write Status Register, Program, Erase. Figure 1. Serial Modes Supported CPOL CPHA shift in (Serial mode 0) 0 0 SCLK (Serial mode 3) 1 1 SCLK SI shift out MSB SO MSB Note: CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is supported. P/N: PM1654 12 REV. 1.7, APR. 02, 2015 MX25U8035E 8-1. Quad Peripheral Interface (QPI) Read Mode QPI protocol enables user to take full advantage of Quad I/O Serial Flash by providing the Quad I/O interface in command cycles, address cycles and as well as data output cycles. Enable QPI mode By issuing 35H command, the QPI mode is enable. Figure 2. Enable QPI Sequence (Command 35H) CS# MODE 3 SCLK 0 1 2 3 4 5 6 7 MODE 0 SIO0 35 SIO[3:1] Reset QPI mode By issuing F5H command, the device is reset to 1-I/O SPI mode. Figure 3. Reset QPI Mode (Command F5H) CE# SCLK SIO[3:0] P/N: PM1654 F5 13 REV. 1.7, APR. 02, 2015 MX25U8035E Fast QPI Read mode (FASTRDQ) To increase the code transmission speed, the device provides a "Fast QPI Read Mode" (FASTRDQ). By issuing command code EBH, the FASTRDQ mode is enable. The number of dummy cycle increase from 4 to 6 cycles. The read cycle frequency will increase from 84MHz to 104MHz. Figure 4. Figure 5. Fast QPI Read Mode (FASTRDQ) (Command EBH) CS# MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 MODE 3 SCLK MODE 0 SIO[3:0] MODE 0 EB A5 A4 A3 A2 A1 A0 X X X X X H0 L0 H1 L1 H2 L2 H3 L3 MSB Data Out Data In P/N: PM1654 X 14 REV. 1.7, APR. 02, 2015 MX25U8035E 9.COMMAND DESCRIPTION Table 5. Command Set Read Commands I/O Read Mode Command (byte) Clock rate (MHz) 1st byte 2nd byte 3rd byte 4th byte 5th byte Action 1 SPI 2 SPI 2READ (2 FAST READ READ RDSFDP x I/O read * (fast read (normal read) (Read SFDP) command) data) Note1 33 1 SPI 104 1 SPI 104 4 SPI W4READ 84 03 (hex) AD1(8) AD2(8) AD3(8) 0B (hex) 5A (hex) BB (hex) AD1(8) AD1(8) AD1(4) AD2(8) AD2(8) AD2(4) AD3(8) AD3(8) AD3(4) Dummy(8) Dummy(8) Dummy(4) n bytes read n bytes read Read SFDP n bytes read out until CS# out until CS# mode out by 2 x I/ goes high goes high O until CS# goes high 4 4 4 SPI QPI QPI 4READ * 4READ * FAST READ (4 x I/O read (4 x I/O read * (fast read command) command) data) Note1 Note1 84 104 84 104 E7 (hex) AD1(2) AD2(2) AD3(2) Dummy(4) Quad I/O read with 4 dummy cycles in 84MHz EB (hex) AD1(2) AD2(2) AD3(2) Dummy(6) Quad I/O read with 6 dummy cycles in 104MHz 0B (hex) AD1(2) AD2(2) AD3(2) Dummy(4) n bytes read out until CS# goes high EB (hex) AD1(2) AD2(2) AD3(2) Dummy(6) Quad I/O read with 6 dummy cycles in 104MHz Program/Erase Commands Command (byte) 1st byte 2nd byte 3rd byte 4th byte Action Command (byte) 1st byte 2nd byte 3rd byte 4th byte Action P/N: PM1654 WREN* WRDI * RDSR * (read WRSR * (write 4PP (quad SE * BE 32K * (block (write enable) (write disable) status register) status register) page program) (sector erase) erase 32KB) 06 (hex) 38 (hex) 20 (hex) 52 (hex) AD1 AD1 AD1 AD2 AD2 AD2 AD3 AD3 AD3 quad input to to erase the to erase the resets the to read out the to write new sets the (WEL) program the selected sector selected 32K write enable (WEL) write values of the values of the block latch bit enable latch bit status register status register selected page BE * (block erase 64KB) 04 (hex) CE * (chip erase) 05 (hex) PP * (page program) 01 (hex) Values RDP * (Release DP * (Deep from deep power down) power down) D8 (hex) 60 or C7 (hex) 02 (hex) AD1 AD1 AD2 AD2 AD3 AD3 to erase the to erase whole to program the selected block chip selected page 15 B9 (hex) AB (hex) enters deep power down mode release from deep power down mode PGM/ERS Suspend * (Suspends Program/ Erase) B0 (hex) PGM/ERS Resume * (Resumes Program/ Erase) 30 (hex) REV. 1.7, APR. 02, 2015 MX25U8035E Security/ID/Mode Setting/Reset Commands RDID RES * (read Command (byte) (read identificelectronic ID) ation) 1st byte 2nd byte 3rd byte 4th byte 5th byte Action COMMAND (byte) 1st byte 2nd byte 3rd byte 4th byte Action COMMAND (byte) 1st byte 2nd byte 3rd byte 4th byte Action 9F (hex) AB (hex) x x x REMS (read RDSCUR * WRSCUR * electronic ENSO * (enter EXSO * (exit (read security (write security manufacturer secured OTP) secured OTP) register) register) & device ID) 90 (hex) B1 (hex) C1 (hex) 2B (hex) 2F (hex) x x ADD (Note 2) outputs JEDEC to read out output the to enter the to exit the 4K1-byte Device Manufacturer 4K-bit secured bit secured ID: 1-byte OTP mode Manufact-urer ID ID & Device ID OTP mode ID & 2-byte Device ID SBULK * SBLK * (single (single block block lock unlock) 36 (hex) 39 (hex) AD1 AD1 AD2 AD2 AD3 AD3 individual block individual (64K-byte) or block (64Kbyte) or sector sector (4K(4K-byte) write byte) unprotect protect RST * (Reset Memory) 99 (hex) RDBLOCK * GBLK * (gang GBULK * (gang (block protect block lock) block unlock) read) 3C (hex) 7E (hex) 98 (hex) AD1 AD2 AD3 read individual whole chip whole chip unprotect block or sector write protect write protect status EQIO RSTQIO QPIID (Enable Quad (Reset Quad I/ (QPI ID Read) I/O) O) 35 (hex) F5 (hex) AF (hex) Entering the Exiting the QPI QPI mode mode ID in QPI interface to read value to set the lockof security down bit as register "1" (once lockdown, cannot be update) NOP * (No Operation) RSTEN * (Reset Enable) 00 (hex) 66 (hex) SBL * (Set Burst Length) C0 (hex) Value WPSEL * (Write Protect Selection) 68 (hex) to set Burst length to enter and enable individal block protect mode Note 1: Command set highlighted with (*) are supported both in SPI and QPI mode. Note 2: The count base is 4-bit for ADD(2) and Dummy(2) because of 2 x I/O. And the MSB is on SI/SIO1 which is different from 1 x I/O condition. Note 3: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first. Note 4: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden mode. Note 5: Before executing RST command, RSTEN command must be executed. If there is any other command to interfere, the reset operation will be disabled. P/N: PM1654 16 REV. 1.7, APR. 02, 2015 MX25U8035E 9-1. Write Enable (WREN) The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP, SE, BE32K, BE, CE, and WRSR, which are intended to change the device content WEL bit should be set every time after the WREN instruction setting the WEL bit. The sequence of issuing WREN instruction is: CS# goes low→sending WREN instruction code→ CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care in SPI mode. (Please refer to "Figure 19. Write Enable (WREN) Sequence (Command 06) (SPI Mode)" and "Figure 20. Write Enable (WREN) Sequence (Command 06) (QPI Mode)") 9-2. Write Disable (WRDI) The Write Disable (WRDI) instruction is to reset Write Enable Latch (WEL) bit. The sequence of issuing WRDI instruction is: CS# goes low→sending WRDI instruction code→CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care in SPI mode. (Please refer to "Figure 21. Write Disable (WRDI) Sequence (Command 04) (SPI Mode)" and "Figure 23. Write Disable (WRDI) Sequence (Command 04) (QPI Mode)") The WEL bit is reset by following situations: - Power-up - Completion of Write Disable (WRDI) instruction - Completion of Write Status Register (WRSR) instruction - Completion of Page Program (PP) instruction - Completion of Quad Page Program (4PP) instruction - Completion of Sector Erase (SE) instruction - Completion of Block Erase 32KB (BE32K) instruction - Completion of Block Erase (BE) instruction - Completion of Chip Erase (CE) instruction - Pgm/Ers Suspend 9-3. Read Identification (RDID) The RDID instruction is to read the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC Manufacturer ID is C2(hex), the memory type ID is 25(hex) as the first-byte device ID, and the individual device ID of second-byte ID are listed as "Table 8. ID Definitions" The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code→24-bits ID data out on SO→ to end RDID operation can drive CS# to high at any time during data out. While Program/Erase operation is in progress, it will not decode the RDID instruction, therefore there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage. 9-4. Read Status Register (RDSR) The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in program/erase/write status register condition). It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in progress. P/N: PM1654 17 REV. 1.7, APR. 02, 2015 MX25U8035E The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register data out on SO. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. (Please refer to "Figure 24. Read Status Register (RDSR) Sequence (Command 05) (SPI Mode)" and "Figure 25. Read Status Register (RDSR) Sequence (Command 05) (QPI Mode)") For user to check if Program/Erase operation is finished or not, RDSR instruction flow are shown as follows: Figure 5. Program/Erase flow with read array data start WREN command RDSR command* WEL=1? No Yes Program/erase command Write program data/address (Write erase address) RDSR command WIP=0? No Yes RDSR command Read WEL=0, BP[3:0], QE, and SRWD data Read array data (same address of PGM/ERS) Verify OK? No Yes Program/erase successfully Program/erase another block? No Program/erase fail Yes * Issue RDSR to check BP[3:0]. * If WPSEL = 1, issue RDSLOCK to check the block status. Program/erase completed P/N: PM1654 18 REV. 1.7, APR. 02, 2015 MX25U8035E Figure 6. Program/ Erase flow without read array data (read P_FAIL/E_FAIL flag) start WREN command RDSR command* WEL=1? No Yes Program/erase command Write program data/address (Write erase address) RDSR command WIP=0? No Yes RDSR command Read WEL=0, BP[3:0], QE, and SRWD data RDSCUR command Yes REGPFAIL/REGEFAIL =1 ? No Program/erase fail Program/erase successfully Program/erase another block? No Yes * Issue RDSR to check BP[3:0]. * If WPSEL = 1, issue RDSLOCK to check the block status. Program/erase completed P/N: PM1654 19 REV. 1.7, APR. 02, 2015 MX25U8035E Figure 7. WRSR flow start WREN command RDSR command WEL=1? No Yes WRSR command Write status register data RDSR command WIP=0? No Yes RDSR command Read WEL=0, BP[3:0], QE, and SRWD data Verify OK? No Yes WRSR successfully P/N: PM1654 WRSR fail 20 REV. 1.7, APR. 02, 2015 MX25U8035E The definition of the status register bits is as below: WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. The program/erase command will be ignored if it is applied to a protected memory area. To ensure both WIP bit & WEL bit are both set to 0 and available for next program/erase/operations, WIP bit needs to be confirm to be 0 before polling WEL bit. After WIP bit confirmed, WEL bit needs to be confirm to be 0. BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area (as defined in "Table 2. Protected Area Sizes") of the device to against the program/erase instruction without hardware protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase 32KB (BE32K), Block Erase (BE) and Chip Erase (CE) instructions (only if Block Protect bits (BP3:BP0) set to 0, the CE instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as default. Which is unprotected. QE bit. The Quad Enable (QE) bit, non-volatile bit, performs SPI Quad modes when it is reset to "0" (factory default) to enable WP# or is set to "1" to enable Quad SIO2 and SIO3. QE bit is only valid for SPI mode. When operate in SPI mode, and quad IO read is desired (for command EBh/E7h, or quad IO program, 38h). WRSR command has to be set the through Status Register bit 6, the QE bit. Then the SPI Quad I/O commands (EBh/E7h/38h) will be accepted by flash. If QE bit is not set, SPI Quad I/O commands (EBh/E7h/38h) will be invalid commands, the device will not respond to them. Once QE bit is set, all SPI commands are valid. 1I/O commands and 2IO commands can be issued no matter QE bit is "0" or "1". When in QPI mode, QE bit will not affect the operation of QPI mode at all. Therefore either "0" or "1" value of QE bit does not affect the QPI mode operation. SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection (WP#/SIO2) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are read only. The SRWD bit defaults to be "0". Table 6. Status Register bit7 bit6 SRWD (status register write protect) QE (Quad Enable) bit5 BP3 (level of protected block) bit4 BP2 (level of protected block) 1=Quad 1=status Enable register write (note 1) (note 1) 0=not Quad disable Enable Non-volatile Non-volatile Non-volatile Non-volatile bit bit bit bit Note 1: see the "Table 2. Protected Area Sizes" P/N: PM1654 bit3 BP1 (level of protected block) bit2 BP0 (level of protected block) (note 1) (note 1) Non-volatile bit Non-volatile bit 21 bit1 bit0 WEL WIP (write enable (write in latch) progress bit) 1=write 1=write enable operation 0=not write 0=not in write enable operation volatile bit volatile bit REV. 1.7, APR. 02, 2015 MX25U8035E 9-5. Write Status Register (WRSR) The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1, BP0) bits to define the protected area of memory (as shown in "Table 2. Protected Area Sizes"). The WRSR also can set or reset the Quad enable (QE) bit and set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#/ SIO2) pin signal, but has no effect on bit1(WEL) and bit0 (WIP) of the status register. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered. The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register data on SI→CS# goes high. (Please refer to "Figure 26. Write Status Register (WRSR) Sequence (Command 01) (SPI Mode)" and "Figure 28. Write Status Register (WRSR) Sequence (Command 01) (QPI Mode)") The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset. Table 7. Protection Modes Mode Software protection mode (SPM) Hardware protection mode (HPM) Status register condition WP# and SRWD bit status Memory Status register can be written in (WEL bit is set to "1") and the SRWD, BP0-BP3 bits can be changed WP#=1 and SRWD bit=0, or WP#=0 and SRWD bit=0, or WP#=1 and SRWD=1 The protected area cannot be program or erase. The SRWD, BP0-BP3 of status register bits cannot be changed WP#=0, SRWD bit=1 The protected area cannot be program or erase. Note: 1. As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in "Table 2. Protected Area Sizes". As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM). Software Protected Mode (SPM): - When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM). - When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM) Note: If SRWD bit=1 but WP#/SIO2 is low, it is impossible to write the Status Register even if the WEL bit has previously been set. It is rejected to write the Status Register and not be executed. P/N: PM1654 22 REV. 1.7, APR. 02, 2015 MX25U8035E Hardware Protected Mode (HPM): - When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2, BP1, BP0 and hardware protected mode by the WP#/SIO2 to against data modification. Note: To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is entered. If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via BP3, BP2, BP1, BP0. If the system enter QPI or set QE=1, the feature of HPM will be disabled. 9-6. Read Data Bytes (READ) The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing READ instruction is: CS# goes low→sending READ instruction code→ 3-byte address on SI→ data out on SO→to end READ operation can use CS# to high at any time during data out. (Please refer to "Figure 27. Read Data Bytes (READ) Sequence (Command 03) (SPI Mode only) (33MHz)") 9-7. Read Data Bytes at Higher Speed (FAST_READ) The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has been reached. Read on SPI Mode The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ instruction code→ 3-byte address on SI→1-dummy byte (default) address on SI→ data out on SO→ to end FAST_ READ operation can use CS# to high at any time during data out. (Please refer to "Figure 29. Read at Higher Speed (FAST_READ) Sequence (Command 0B) (SPI Mode) (104MHz)") Read on QPI Mode The sequence of issuing FAST_READ instruction in QPI mode is: CS# goes low→ sending FAST_READ instruction, 2 cycles→ 24-bit address interleave on SIO3, SIO2, SIO1 & SIO0→4 dummy cycles→data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end QPI FAST_READ operation can use CS# to high at any time during data out. (Please refer to "Figure 30. Read at Higher Speed (FAST_READ) Sequence (Command 0B) (QPI Mode) (84MHz)") In the performance-enhancing mode, P[7:4] must be toggling with P[3:0] ; likewise P[7:0]=A5h,5Ah,F0h or 0Fh can make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0]; likewise P[7:0]=FFh,00h,AAh or 55h and afterwards CS# is raised and then lowered, the system then will escape from performance enhance mode and return to normal operation. While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. 9-8. 2 x I/O Read Mode (2READ) P/N: PM1654 23 REV. 1.7, APR. 02, 2015 MX25U8035E The 2READ instruction enable double throughput of Serial Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit. The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 24-bit address interleave on SIO1 & SIO0→ 4 dummy cycles on SIO1 & SIO0→ data out interleave on SIO1 & SIO0→ to end 2READ operation can use CS# to high at any time during data out (Please refer to "Figure 31. 2 x I/O Read Mode Sequence (Command BB) (SPI Mode only) (84MHz)"). While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. 9-9. 4 x I/O Read Mode (4READ) The 4READ instruction enable quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit. 4 x I/O Read on SPI Mode (4READ) The sequence of issuing 4READ instruction is: CS# goes low→ sending 4READ instruction→ 24-bit address interleave on SIO3, SIO2, SIO1 & SIO0→2+4 dummy cycles→data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end 4READ operation can use CS# to high at any time during data out. (Please refer to "Figure 32. 4 x I/O Read Mode Sequence (Command EB) (SPI Mode) (104MHz)"). W4READ instruction (E7) is also available is SPI mode for 4 I/O read. The sequence is similar to 4READ, but with only 4 dummy cycles. The clock rate runs at 84MHz. 4 x I/O Read on QPI Mode (4READ) The 4READ instruction also support on QPI command mode. The sequence of issuing 4READ instruction QPI mode is: CS# goes low→ sending 4READ instruction→ 24-bit address interleave on SIO3, SIO2, SIO1 & SIO0→2+4 dummy cycles→data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end 4READ operation can use CS# to high at any time during data out. Another sequence of issuing 4 READ instruction especially useful in random access is : CS# goes low→sending 4 READ instruction→3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 →performance enhance toggling bit P[7:0]→ 4 dummy cycles →data out still CS# goes high → CS# goes low (reduce 4 Read instruction) →24-bit random access address (Please refer to "Figure 33. 4 x I/O Read enhance performance Mode Sequence (Command EB) (SPI Mode) (104MHz)" and "Figure 35. 4 x I/O Read enhance performance Mode Sequence (Command EB) (QPI Mode) (104MHz)" ). In the performance-enhancing mode, P[7:4] must be toggling with P[3:0] ; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh can make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0]; likewise P[7:0]=FFh,00h,AAh or 55h and afterwards CS# is raised and then lowered, the system then will escape from performance enhance mode and return to normal operation. While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. P/N: PM1654 24 REV. 1.7, APR. 02, 2015 MX25U8035E 9-10. Burst Read This device supports Burst Read in both SPI and QPI mode. To set the Burst length, following command operation is required Issuing command: “C0h” in the first Byte (8-clocks), following 4 clocks defining wrap around enable with “0h” and disable with“1h”. Next 4 clocks is to define wrap around depth. Definition as following table: Data 1xh 1xh 1xh 1xh Wrap Around No No No No Wrap Depth X X X X Data 00h 01h 02h 03h Wrap Around Yes Yes Yes Yes Wrap Depth 8-byte 16-byte 32-byte 64-byte The wrap around unit is defined within the 256Byte page, with random initial address. It’s defined as “wrap-around mode disable” for the default state of the device. To exit wrap around, it is required to issue another “C0” command in which data=‘1xh”. Otherwise, wrap around status will be retained until power down or reset command. To change wrap around depth, it is requried to issue another “C0” command in which data=“0xh”. QPI “0Bh” “EBh” and SPI “EBh” “E7h” support wrap around feature after wrap around enable. Burst read is supported in both SPI and QPI mode. The device id default without Burst read. SPI Mode CS# 0 1 2 3 1 1 0 4 5 6 7 8 9 0 0 0 0 H H 10 11 12 13 H L L 14 15 SCLK SIO 0 H L L QPI Mode CS# 0 1 2 3 C1 C0 H0 L0 SCLK SIO[3:0] MSB LSB Note: MSB=Most Significant Bit LSB=Least Significant Bit P/N: PM1654 25 REV. 1.7, APR. 02, 2015 MX25U8035E 9-11. Performance Enhance Mode The device could waive the command cycle bits if the two cycle bits after address cycle toggles. (Please note "Figure 33. 4 x I/O Read enhance performance Mode Sequence (Command EB) (SPI Mode) (104MHz)" and "Figure 35. 4 x I/O Read enhance performance Mode Sequence (Command EB) (QPI Mode) (104MHz)". 4xI/O Read enhance performance mode sequence) Performance enhance mode is supported in both SPI and QPI mode. In QPI mode, “EBh” “0Bh” and SPI “EBh” “E7h” commands support enhance mode. The performance enhance mode is not supported in dual I/O mode. After entering enhance mode, following CSB go high, the device will stay in the read mode and treat CSB go low of the first clock as address instead of command cycle. To exit enhance mode, a new fast read command whose first two dummy cycles is not toggle then exit. Or issue ”FFh” command to exit enhance mode. 9-12. Performance Enhance Mode Reset (FFh) To conduct the Performance Enhance Mode Reset operation in SPI mode, FFh command code, 8 clocks, should be issued in 1I/O sequence. In QPI Mode, FFFFFFFFh command code, 8 clocks, in 4I/O should be issued. (Please refer to "Figure 58. Performance Enhance Mode Reset for Fast Read Quad I/O (SPI and QPI Mode)") If the system controller is being Reset during operation, the flash device will return to the standard SPI operation. Upon Reset of main chip, SPI instruction would be issued from the system. Instructions like Read ID (9Fh) or Fast Read (0Bh) would be issued. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. (Please refer to "Figure 58. Performance Enhance Mode Reset for Fast Read Quad I/O (SPI and QPI Mode)") 9-13. Sector Erase (SE) The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector (see "Table 4. Memory Organization (8Mb)") is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. Address bits [Am-A12] (Am is the most significant address) select the sector address. The sequence of issuing SE instruction is: CS# goes low→ sending SE instruction code→ 3-byte address on SI→ CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. (Please refer to "Figure 38. Sector Erase (SE) Sequence (Command 20) (SPI Mode)" and "Figure 40. Sector Erase (SE) Sequence (Command 20) (QPI Mode)") The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the P/N: PM1654 26 REV. 1.7, APR. 02, 2015 MX25U8035E tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the sector is protected by BP3, BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the sector. 9-14. Block Erase (BE32K) The Block Erase (BE32K) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 32K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE32K). Any address of the block (see "Table 4. Memory Organization (8Mb)") is a valid address for Block Erase (BE32K) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing BE32K instruction is: CS# goes low→ sending BE32K instruction code→ 3-byte address on SI→CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. (Please refer to "Figure 39. Block Erase 32KB (BE32K) Sequence (Command 52) (SPI Mode)" and "Figure 41. Block Erase 32KB (BE32K) Sequence (Command 52) (QPI Mode)") The self-timed Block Erase Cycle time (tBE32K) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Block Erase cycle is in progress. The WIP sets 1 during the tBE32K timing, and sets 0 when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the block is protected by BP3, BP2, BP1, BP0 bits, the Block Erase (tBE32K) instruction will not be executed on the block. 9-15. Block Erase (BE) The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 64K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (Please refer to "Table 4. Memory Organization (8Mb)") is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing BE instruction is: CS# goes low→ sending BE instruction code→ 3-byte address on SI→ CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. (Please refer to "Figure 42. Block Erase (BE) Sequence (Command D8) (SPI Mode)" and "Figure 43. Block Erase (BE) Sequence (Command D8) (QPI Mode)") The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Block Erase cycle is in progress. The WIP sets 1 during the tBE timing, and sets 0 when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the block is protected by BP3, BP2, BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the block. 9-16. Chip Erase (CE) The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not executed. P/N: PM1654 27 REV. 1.7, APR. 02, 2015 MX25U8035E The sequence of issuing CE instruction is: CS# goes low→sending CE instruction code→CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. (Please refer to "Figure 44. Chip Erase (CE) Sequence (Command 60 or C7) (SPI Mode)" and "Figure 45. Chip Erase (CE) Sequence (Command 60 or C7) (QPI Mode)") The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is protected by BP3, BP2, BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when BP3, BP2, BP1, BP0 all set to "0". 9-17. Page Program (PP) The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device programs only the last 256 data bytes sent to the device. The last address byte (the 8 least significant address bits, A7-A0) should be set to 0 for 256 bytes page program. If A7-A0 are not all zero, transmitted data that exceed page length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently selected page. If the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the request page and previous data will be disregarded. If the data bytes sent to the device has not exceeded 256, the data will be programmed at the request address of the page. There will be no effort on the other data bytes of the same page. The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→ at least 1-byte on data on SI→ CS# goes high. (Please refer to "Figure 34. Page Program (PP) Sequence (Command 02) (SPI Mode)" and "Figure 37. Page Program (PP) Sequence (Command 02) (QPI Mode)") The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte boundary( the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed. The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP3, BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. 9-18. 4 x I/O Page Program (4PP) The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1" before sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1, SIO2, and SIO3 as address and data input, which can improve programmer performance and the effectiveness of application of lower clock less than 33MHz. For system with faster clock, the Quad page program cannot provide more actual favors, because the required internal page program time is far more than the time data flows in. Therefore, we suggest that while executing this command (especially during sending data), user can slow the clock speed down to 33MHz below. The other function descriptions are as same as standard page program. The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on SIO[3:0]→ at least 1-byte on data on SIO[3:0]→CS# goes high. P/N: PM1654 28 REV. 1.7, APR. 02, 2015 MX25U8035E 9-19. Deep Power-down (DP) The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to entering the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction are ignored. When CS# goes high, it's only in deep power-down mode not standby mode. It's different from Standby mode. The sequence of issuing DP instruction is: CS# goes low→sending DP instruction code→CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. (Please refer to "Figure 46. Deep Power-down (DP) Sequence (Command B9) (SPI Mode)" and "Figure 47. Deep Power-down (DP) Sequence (Command B9) (QPI Mode)" ) Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP) and Read Electronic Signature (RES) instruction and softreset command. (those instructions allow the ID being reading out). When Power-down, or software reset command the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. For DP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode. 9-20. Release from Deep Power-down (RDP), Read Electronic Signature (RES) The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2(max), as specified in "Table 14. AC Characteristics". Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. The RDP instruction is only for releasing from Deep Power Down Mode. RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID Definitions on next page. This is not the same as RDID instruction. It is not recommended to use for new design. For new design, please use RDID instruction. The sequence is shown as "Figure 48. Read Electronic Signature (RES) Sequence (Command AB) (SPI Mode)", "Figure 50. Read Electronic Signature (RES) Sequence (Command AB) (QPI Mode)", "Figure 49. Release from Deep Power-down (RDP) Sequence (Command AB) (SPI Mode)" and "Figure 51. Release from Deep Powerdown (RDP) Sequence (Command AB) (QPI Mode)". Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in Deep Powerdown mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction. P/N: PM1654 29 REV. 1.7, APR. 02, 2015 MX25U8035E 9-21. Read Electronic Manufacturer ID & Device ID (REMS) The REMS instruction is an alternative to the Release from Power-down/Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. The REMS instruction is very similar to the Release from Power-down/Device ID instruction. The instruction is initiated by driving the CS# pin low and shift the instruction code "90h" followed by two dummy bytes and one bytes address (A7~A0). After which, the Manufacturer ID for MXIC (C2h) and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in "Figure 52. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90) (SPI Mode only)". The Device ID values are listed in "Table 8. ID Definitions". If the one-byte address is initially set to 01h, then the device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high. 9-22. QPI ID Read (QPIID) User can execute this ID Read instruction to identify the Device ID and Manufacturer ID. The sequence of issue QPIID instruction is CS# goes low→sending QPI ID instruction→→Data out on SO→CS# goes high. Most significant bit (MSB) first. After the command cycle, the device will immediately output data on the falling edge of SCLK. The manufacturer ID, memory type, and device ID data byte will be output continuously, until the CS# goes high. Table 8. ID Definitions Command Type RDID (JEDEC ID) manufacturer ID C2 RES REMS P/N: PM1654 manufacturer ID C2 MX25U8035E memory type 25 electronic ID 34 device ID 34 30 memory density 34 REV. 1.7, APR. 02, 2015 MX25U8035E 9-23. Enter Secured OTP (ENSO) The ENSO instruction is for entering the additional 4K-bit secured OTP mode. The additional 4K-bit secured OTP is independent from main array, which may use to store unique serial number for system identifier. After entering the Secured OTP mode, and then follow standard read or program, procedure to read out the data or update data. The Secured OTP data cannot be updated again once it is lock-down. The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP mode→ CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. Please note that WRSR/WRSCUR commands are not acceptable during the access of secure OTP region, once security OTP is lock down, only read related commands are valid. 9-24. Exit Secured OTP (EXSO) The EXSO instruction is for exiting the additional 4K-bit secured OTP mode. The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP mode→ CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. 9-25. Read Security Register (RDSCUR) The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read at any time (even in program/erase/write status register/write security register condition) and continuously. The sequence of issuing RDSCUR instruction is : CS# goes low→sending RDSCUR instruction→Security Register data out on SO→ CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. Please see "Figure 53. Read Security Register (RDSCUR) Sequence (Command 2B) (SPI Mode)" & "Figure 54. Read Security Register (RDSCUR) Sequence (Command 2B) (QPI Mode)". The definition of the Security Register bits is as below: Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory before ex- factory or not. When it is "0", it indicates non-factory lock; "1" indicates factory-lock. Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for customer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 4K-bit Secured OTP area cannot be update any more. While it is in 4K-bit secured OTP mode, main array access is not allowed. P/N: PM1654 31 REV. 1.7, APR. 02, 2015 MX25U8035E Table 9. Security Register Definition bit7 bit6 bit5 bit4 bit3 bit2 WPSEL E_FAIL P_FAIL Reserved Erase Suspend bit Program Suspend bit 0=normal WP mode 1=individual mode (default=0) 0=normal Erase succeed 1=individual Erase failed (default=0) 0=normal Program succeed 1=indicate Program failed (default=0) - 0=Erase is not suspended 1= Erase suspended (default=0) Non-volatile bit (OTP) Volatile bit Volatile bit Volatile bit Volatile bit bit1 bit0 LDSO Secured OTP (indicate if indicator bit lock-down) 0 = not lock0=Program down 0 = nonis not 1 = lock-down factory suspended (cannot lock 1= Program program/ 1 = factory suspended lock erase (default=0) OTP) Non-volatile Non-volatile Volatile bit bit bit (OTP) (OTP) 9-26. Write Security Register (WRSCUR) The WRSCUR instruction is for setting the values of Security Register Bits. The WREN (Write Enable) instruction is required before issuing WRSCUR instruction. The WRSCUR instruction may change the values of bit1 (LDSO bit) for customer to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area cannot be updated any more. The LDSO bit is an OTP bit. Once the LDSO bit is set, the value of LDSO bit can not be altered any more. The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. Please see "Figure 55. Write Security Register (WRSCUR) Sequence (Command 2F) (SPI Mode)" & "Figure 56. Write Security Register (WRSCUR) Sequence (Command 2F) (QPI Mode)". The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. 9-27. Write Protection Selection (WPSEL) When the system accepts and executes WPSEL instruction, the bit 7 in security register will be set. The WREN (Write Enable) instruction is required before issuing WPSEL instruction. It will activate SBLK, SBULK, RDBLOCK, GBLK, GBULK etc instructions to conduct block lock protection and replace the original Software Protect Mode (SPM) use (BP3~BP0) indicated block methods. The sequence of issuing WPSEL instruction is: CS# goes low → sending WPSEL instruction to enter the individual block protect mode→ CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. Every time after the system is powered-on, and the Security Register bit 7 is checked to be WPSEL=1, all the blocks or sectors will be write protected by default. User may only unlock the blocks or sectors via SBULK and GBULK instruction. Program or erase functions can only be operated after the Unlock instruction is conducted. Once WPSEL is setted, it cannot be changed. P/N: PM1654 32 REV. 1.7, APR. 02, 2015 MX25U8035E WPSEL instruction function flow is as follows: Figure 8. WPSEL Flow start WREN command RDSCUR(2Bh) command Yes WPSEL=1? No WPSEL disable, block protected by BP[3:0] WPSEL(68h) command RDSR command WIP=0? No Yes RDSCUR(2Bh) command WPSEL=1? No Yes WPSEL set successfully WPSEL set fail WPSEL enable. Block protected by individual lock (SBLK, SBULK, … etc). P/N: PM1654 33 REV. 1.7, APR. 02, 2015 MX25U8035E 9-28. Single Block Lock/Unlock Protection (SBLK/SBULK) These instructions are only effective after WPSEL was executed. The SBLK instruction is for write protection a specified block (or sector) of memory, using AMAX-A16 or (AMAX-A12) address bits to assign a 64Kbyte block (or 4K bytes sector) to be protected as read only. The SBULK instruction will cancel the block (or sector) write protection state. This feature allows user to stop protecting the entire block (or sector) through the chip unprotect command (GBULK). The WREN (Write Enable) instruction is required before issuing SBLK/SBULK instruction. The sequence of issuing SBLK/SBULK instruction is: CS# goes low → send SBLK/SBULK (36h/39h) instruction→send 3 address bytes assign one block (or sector) to be protected on SI pin → CS# goes high. The CS# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not be executed. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. SBLK/SBULK instruction function flow is as follows: Figure 9. Block Lock Flow Start RDSCUR(2Bh) command WPSEL=1? No WPSEL command Yes WREN command SBLK command ( 36h + 24bit address ) RDSR command WIP=0? No Yes RDBLOCK command ( 3Ch + 24bit address ) Data = FFh ? No Yes Block lock successfully Lock another block? Block lock fail Yes No Block lock P/N: PM1654 completed 34 REV. 1.7, APR. 02, 2015 MX25U8035E Figure 10. Block Unlock Flow start RDSCUR(2Bh) command WPSEL=1? No WPSEL command Yes WREN command SBULK command ( 39h + 24bit address ) RDSR command No WIP=0? Yes RDBLOCK command to verify ( 3Ch + 24bit address ) Data = FF ? Yes No Block unlock successfully Unlock another block? Block unlock fail Yes Unlock block completed? P/N: PM1654 35 REV. 1.7, APR. 02, 2015 MX25U8035E 9-29. Read Block Lock Status (RDBLOCK) This instruction is only effective after WPSEL was executed. The RDBLOCK instruction is for reading the status of protection lock of a specified block (or sector), using AMAX-A16 (or AMAX-A12) address bits to assign a 64K bytes block (4K bytes sector) and read protection lock status bit which the first byte of Read-out cycle. The status bit is"1" to indicate that this block has be protected, that user can read only but cannot write/program /erase this block. The status bit is "0" to indicate that this block hasn't be protected, and user can read and write this block. The sequence of issuing RDBLOCK instruction is: CS# goes low → send RDBLOCK (3Ch) instruction → send 3 address bytes to assign one block on SI pin → read block's protection lock status bit on SO pin → CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. 9-30. Gang Block Lock/Unlock (GBLK/GBULK) These instructions are only effective after WPSEL was executed. The GBLK/GBULK instruction is for enable/disable the lock protection block of the whole chip. The WREN (Write Enable) instruction is required before issuing GBLK/GBULK instruction. The sequence of issuing GBLK/GBULK instruction is: CS# goes low → send GBLK/GBULK (7Eh/98h) instruction →CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. The CS# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed. 9-31. Program/ Erase Suspend/ Resume The device allow the interruption of Sector-Erase, Block-Erase or Page-Program operations and conduct other operations. Details as follows. To enter the suspend/ resume mode: issuing B0h for suspend; 30h for resume (SPI/QPI all acceptable) Read security register bit2 (PSB) and bit3 (ESB) (please refer to "Table 9. Security Register Definition") to check suspend ready information. For "Suspend to Read", "Resume to Read", "Resume to Suspend" timing specification please note "Figure 62. Suspend to Read Latency", "Figure 63. Resume to Read Latency" and "Figure 64. Resume to Suspend Latency". ESB bit (Erase Suspend Bit) indicates the status of Erase suspend operation. When issue a suspend command during erase operation ESB=1, when erase operation resumes, ESB will be reset to "0". Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. 9-32. Erase Suspend Erase suspend allow the interruption of all erase operations. After erase suspend, WEL bit will be clear, following commands can be accepted. (including: 03h, 0Bh, BBh, EBh, E7h, 9Fh, AFh, 90h, 05h, 2Bh, B1h, C1h, 5Ah, 02h, 38h, 3Ch, 30h, 66h, 99h, C0h, 35h, F5h, 00h, ABh )Note P/N: PM1654 36 REV. 1.7, APR. 02, 2015 MX25U8035E Note: The device is divided into 2 banks, each bank's density is 4Mb. While conducting erase suspend in one bank, the programming operation that follows can only be conducted in the other bank and cannot be conducted in the bank executing the suspend operation. The boundaries of the banks are illustrated as below table. MX25U8035E BANK (4M bit) Address Range 1 080000h-0FFFFFh 0 000000h-07FFFFh After issue erase suspend command, latency time 20us is needed before issue another command. For "Suspend to Read", "Resume to Read", "Resume to Suspend" timing specification please note "Figure 62. Suspend to Read Latency", "Figure 63. Resume to Read Latency" and "Figure 64. Resume to Suspend Latency". ESB bit (Erase Suspend Bit) indicates the status of Erase suspend operation. When issue a suspend command during program operation ESB=1, when erase operation resumes, ESB will be reset to "0". Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. When ESB bit is issued, the Write Enable Latch (WEL) bit will be reset. See "Figure 62. Suspend to Read Latency" for Suspend to Read latency. 9-33. Program Suspend Program suspend allows the interruption of all program operations. After program suspend, WEL bit will be cleared, only read related, resume and reset command can be accepted. (including: 03h, 0Bh, BBh, EBh, E7h, 9Fh, AFh, 90h, 05h, 2Bh, B1h, C1h, 5Ah, 3Ch, 30h, 66h, 99h, C0h, 35h, F5h, 00h, ABh ) After issue program suspend command, latency time 20us is needed before issue another command. For "Suspend to Read", "Resume to Read", "Resume to Suspend" timing specification please note "Figure 62. Suspend to Read Latency", "Figure 63. Resume to Read Latency" and "Figure 64. Resume to Suspend Latency". PSB bit (Program Suspend Bit) indicates the status of Program suspend operation. When issue a suspend command during program operation PSB=1, when program operation resumes, PSB will be reset to "0". Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. 9-34. Write-Resume The Write operation is being resumed when Write-Resume instruction issued. ESB or PSB (suspend status bit) in Status register will be changed back to “0” The operation of Write-Resume is as follows: CS# drives low → send write resume command cycle (30H) → drive CS# high. By polling Busy Bit in status register, the internal write operation status could be checked to be completed or not. The user may also wait the time lag of TSE, TBE, TPP for Sector-erase, Block-erase or Page-programming. WREN (command "06" is not required to issue before resume. Resume to another suspend operation requires tPRS latency time. P/N: PM1654 37 REV. 1.7, APR. 02, 2015 MX25U8035E When Erase Suspend is being resumed, the WEL bit need to be set again if user desire to conduct the program or erase operation. Please note that, if "performance enhance mode" is executed during suspend operation, the device can not be resume. To restart the write command, disable the "performance enhance mode" is required. After the "performance enhance mode" is disable, the write-resume command is effective. 9-35. No Operation (NOP) The "No Operation" command is only able to terminate the Reset Enable (RSTEN) command and will not affect any other command. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. 9-36. Software Reset (Reset-Enable (RSTEN) and Reset (RST)) The Software Reset operation combines two instructions: Reset-Enable (RSTEN) command and Reset (RST) command. It returns the device to a standby mode. All the volatile bits and settings will be cleared then, which makes the device return to the default status as power on. To execute Reset command (RST), the Reset-Enable (RSTEN) command must be executed first to perform the Reset operation. If there is any other command to interrupt after the Reset-Enable command, the Reset-Enable will be invalid. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. If the Reset command is executed during program or erase operation, the operation will be disabled, the data under processing could be damaged or lost. The reset time is different depending on the last operation. Longer latency time is required to recover from a program operation than from other operations. 9-37. Reset Quad I/O (RSTQIO) To reset the QPI mode, the RSTQIO (F5H) command is required. After the RSTQIO command is issued, the device returns from QPI mode (4 I/O interface in command cycles) to SPI mode (1 I/O interface in command cycles). Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. Note: For EQIO and RSTQIO commands, CS# high width has to follow "write spec" tSHSL for next instruction. P/N: PM1654 38 REV. 1.7, APR. 02, 2015 MX25U8035E 9-38. Read SFDP Mode (RDSFDP) The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on CFI. The sequence of issuing RDSFDP instruction is CS# goes low→send RDSFDP instruction (5Ah)→send 3 address bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP operation can use CS# to high at any time during data out. SFDP is a standard of JEDEC. JESD216. v1.0. Figure 11. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI SO 24 BIT ADDRESS 23 22 21 5Ah 3 2 1 0 High-Z CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Cycle SI 7 6 5 4 3 2 1 0 DATA OUT 2 DATA OUT 1 SO 7 6 5 3 2 1 0 7 MSB MSB P/N: PM1654 4 39 6 5 4 3 2 1 0 7 MSB REV. 1.7, APR. 02, 2015 MX25U8035E Table 10. Signature and Parameter Identification Data Values SFDP Table below is for MX25U8035EM1I-10G, MX25U8035EM2I-10G, MX25U8035EZNI-10G and MX25U8035EZUI-10G Description SFDP Signature Comment Fixed: 50444653h Add (h) DW Add Data (h/b) Data (Byte) (Bit) (Note1) (h) 00h 07:00 53h 53h 01h 15:08 46h 46h 02h 23:16 44h 44h 03h 31:24 50h 50h SFDP Minor Revision Number Start from 00h 04h 07:00 00h 00h SFDP Major Revision Number Start from 01h This number is 0-based. Therefore, 0 indicates 1 parameter header. 05h 15:08 01h 01h 06h 23:16 01h 01h 07h 31:24 FFh FFh 00h: it indicates a JEDEC specified header. 08h 07:00 00h 00h Start from 00h 09h 15:08 00h 00h Start from 01h 0Ah 23:16 01h 01h How many DWORDs in the Parameter table 0Bh 31:24 09h 09h 0Ch 07:00 30h 30h 0Dh 15:08 00h 00h 0Eh 23:16 00h 00h 0Fh 31:24 FFh FFh it indicates Macronix manufacturer ID 10h 07:00 C2h C2h Start from 00h 11h 15:08 00h 00h Start from 01h 12h 23:16 01h 01h How many DWORDs in the Parameter table 13h 31:24 04h 04h 14h 07:00 60h 60h 15h 15:08 00h 00h 16h 23:16 00h 00h 17h 31:24 FFh FFh Number of Parameter Headers Unused ID number (JEDEC) Parameter Table Minor Revision Number Parameter Table Major Revision Number Parameter Table Length (in double word) Parameter Table Pointer (PTP) First address of JEDEC Flash Parameter table Unused ID number (Macronix manufacturer ID) Parameter Table Minor Revision Number Parameter Table Major Revision Number Parameter Table Length (in double word) Parameter Table Pointer (PTP) First address of Macronix Flash Parameter table Unused P/N: PM1654 40 REV. 1.7, APR. 02, 2015 MX25U8035E Table 11. Parameter Table (0): JEDEC Flash Parameter Tables SFDP Table below is for MX25U8035EM1I-10G, MX25U8035EM2I-10G, MX25U8035EZNI-10G and MX25U8035EZUI-10G Description Comment Block/Sector Erase sizes 00: Reserved, 01: 4KB erase, 10: Reserved, 11: not support 4KB erase Write Granularity 0: 1Byte, 1: 64Byte or larger Write Enable Instruction Required 0: not required 1: required 00h to be written to the for Writing to Volatile Status status register Registers Add (h) DW Add Data (h/b) (Byte) (Bit) (Note1) 01b 02 1b 03 0b 30h 0: use 50h opcode, 1: use 06h opcode Write Enable Opcode Select for Note: If target flash status register is Writing to Volatile Status Registers nonvolatile, then bits 3 and 4 must be set to 00b. Contains 111b and can never be Unused changed 4KB Erase Opcode 01:00 31h Data (h) E5h 04 0b 07:05 111b 15:08 20h 16 0b 18:17 00b 19 0b 20 1b 20h (1-1-2) Fast Read (Note2) 0=not support 1=support Address Bytes Number used in addressing flash array Double Transfer Rate (DTR) Clocking 00: 3Byte only, 01: 3 or 4Byte, 10: 4Byte only, 11: Reserved (1-2-2) Fast Read 0=not support 1=support (1-4-4) Fast Read 0=not support 1=support 21 1b (1-1-4) Fast Read 0=not support 1=support 22 0b 23 1b 33h 31:24 FFh 37h:34h 31:00 007F FFFFh 0=not support 1=support 32h Unused Unused Flash Memory Density (1-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states (Note3) Clocks) not support (1-4-4) Fast Read Number of 000b: Mode Bits not support Mode Bits (Note4) 38h (1-4-4) Fast Read Opcode 39h (1-1-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (1-1-4) Fast Read Number of 000b: Mode Bits not support Mode Bits 3Ah (1-1-4) Fast Read Opcode 3Bh P/N: PM1654 41 04:00 0 0100b 07:05 010b 15:08 EBh 20:16 0 0000b 23:21 000b 31:24 FFh B0h FFh 44h EBh 00h FFh REV. 1.7, APR. 02, 2015 MX25U8035E SFDP Table below is for MX25U8035EM1I-10G, MX25U8035EM2I-10G, MX25U8035EZNI-10G and MX25U8035EZUI-10G Description Comment (1-1-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (1-1-2) Fast Read Number of 000b: Mode Bits not support Mode Bits (1-1-2) Fast Read Opcode Add (h) DW Add Data (h/b) (Byte) (Bit) (Note1) 3Ch 3Dh (1-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (1-2-2) Fast Read Number of 000b: Mode Bits not support Mode Bits 3Eh (1-2-2) Fast Read Opcode 3Fh (2-2-2) Fast Read 0=not support 1=support Unused (4-4-4) Fast Read 0=not support 1=support 40h Unused 04:00 0 0000b 07:05 000b 15:08 FFh 20:16 0 0100b 23:21 000b 31:24 BBh 00 0b 03:01 111b 04 1b 07:05 111b Data (h) 00h FFh 04h BBh FEh Unused 43h:41h 31:08 FFh FFh Unused 45h:44h 15:00 FFh FFh 20:16 0 0000b 23:21 000b (2-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (2-2-2) Fast Read Number of 000b: Mode Bits not support Mode Bits 46h (2-2-2) Fast Read Opcode 47h 31:24 FFh FFh 49h:48h 15:00 FFh FFh 20:16 0 0100b 23:21 010b Unused 00h (4-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (4-4-4) Fast Read Number of 000b: Mode Bits not support Mode Bits 4Ah (4-4-4) Fast Read Opcode 4Bh 31:24 EBh EBh 4Ch 07:00 0Ch 0Ch 4Dh 15:08 20h 20h 4Eh 23:16 0Fh 0Fh 4Fh 31:24 52h 52h 50h 07:00 10h 10h 51h 15:08 D8h D8h 52h 23:16 00h 00h 53h 31:24 FFh FFh Sector Type 1 Size Sector/block size = 2^N bytes (Note5) 0x00b: this sector type doesn't exist Sector Type 1 erase Opcode Sector Type 2 Size Sector/block size = 2^N bytes 0x00b: this sector type doesn't exist Sector Type 2 erase Opcode Sector Type 3 Size Sector/block size = 2^N bytes 0x00b: this sector type doesn't exist Sector Type 3 erase Opcode Sector Type 4 Size Sector/block size = 2^N bytes 0x00b: this sector type doesn't exist Sector Type 4 erase Opcode P/N: PM1654 42 44h REV. 1.7, APR. 02, 2015 MX25U8035E Table 12. Parameter Table (1): Macronix Flash Parameter Tables SFDP Table below is for MX25U8035EM1I-10G, MX25U8035EM2I-10G, MX25U8035EZNI-10G and MX25U8035EZUI-10G Description Comment Add (h) DW Add Data (h/b) (Byte) (Bit) (Note1) Data (h) Vcc Supply Maximum Voltage 2000h=2.000V 2700h=2.700V 3600h=3.600V 61h:60h 07:00 15:08 00h 20h 00h 20h Vcc Supply Minimum Voltage 1650h=1.650V 2250h=2.250V 2350h=2.350V 2700h=2.700V 63h:62h 23:16 31:24 50h 16h 50h 16h H/W Reset# pin 0=not support 1=support 00 0b H/W Hold# pin 0=not support 1=support 01 0b Deep Power Down Mode 0=not support 1=support 02 1b S/W Reset 0=not support 1=support 03 1b S/W Reset Opcode Reset Enable (66h) should be issued before Reset Opcode Program Suspend/Resume 0=not support 1=support 12 1b Erase Suspend/Resume 0=not support 1=support 13 1b 14 1b 15 1b 66h 23:16 C0h C0h 67h 31:24 64h 64h 65h:64h Unused Wrap-Around Read mode 0=not support 1=support Wrap-Around Read mode Opcode 11:04 1001 1001b F99Ch (99h) Wrap-Around Read data length 08h:support 8B wrap-around read 16h:8B&16B 32h:8B&16B&32B 64h:8B&16B&32B&64B Individual block lock 0=not support 1=support 00 1b Individual block lock bit (Volatile/Nonvolatile) 0=Volatile 1=Nonvolatile 01 0b 09:02 0011 0110b (36h) 10 0b 11 1b Individual block lock Opcode Individual block lock Volatile protect bit default protect status 0=protect 1=unprotect Secured OTP 0=not support 1=support Read Lock 0=not support 1=support 12 0b Permanent Lock 0=not support 1=support 13 0b Unused 15:14 11b Unused 31:16 FFh FFh 31:00 FFh FFh Unused 6Bh:68h 6Fh:6Ch C8D9h MX25U8035EBAI-10G-SFDP_2014-04-09 P/N: PM1654 43 REV. 1.7, APR. 02, 2015 MX25U8035E Note 1: h/b is hexadecimal or binary. Note 2: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x), address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1), (2-2-2), and (4-4-4) Note 3: Wait States is required dummy clock cycles after the address bits or optional mode bits. Note 4: Mode Bits is optional control bits that follow the address bits. These bits are driven by the system controller if they are specified. (eg,read performance enhance toggling bits) Note 5: 4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h Note 6: All unused and undefined area data is blank FFh for SFDP Tables that are defined in Parameter Identification Header. All other areas beyond defined SFDP Table are reserved by Macronix. P/N: PM1654 44 REV. 1.7, APR. 02, 2015 MX25U8035E 10.POWER-ON STATE The device is at below states when power-up: - Standby Mode ( please note it is not Deep Power Down Mode) - Write Enable Latch (WEL) bit is reset The device must not be selected during power-up and power-down stage unless the VCC achieves below correct level: - VCC minimum at power-up stage and then after a delay of tVSL - GND at power-down Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level. An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change during power up state. For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The read, write, erase, and program command should be sent after the below time delay: - tVSL after VCC reached VCC minimum level Please refer to the figure of "Figure 66. Power-up Timing". Note: - To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended. (generally around 0.1uF) P/N: PM1654 45 REV. 1.7, APR. 02, 2015 MX25U8035E 11.ELECTRICAL SPECIFICATIONS 11-1. Absolute Maximum Ratings RATING VALUE Ambient Operating Temperature Industrial grade -40°C to 85°C Storage Temperature -65°C to 150°C Applied Input Voltage -0.5V to VCC+0.5V Applied Output Voltage -0.5V to VCC+0.5V VCC to Ground Potential -0.5V to 2.5V NOTICE: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. 2. Specifications contained within the following tables are subject to change. 3. During voltage transitions, all pins may overshoot to VCC+1.0V or -1.0V for period up to 20ns. Figure 13. Maximum Positive Overshoot Waveform Figure 12. Maximum Negative Overshoot Waveform 20ns 0V VCC+1.0V -1.0V 2.0V 20ns 11-2. Capacitance TA = 25°C, f = 1.0 MHz Symbol Parameter CIN COUT P/N: PM1654 Min. Typ. Max. Unit Input Capacitance 6 pF VIN = 0V Output Capacitance 8 pF VOUT = 0V 46 Conditions REV. 1.7, APR. 02, 2015 MX25U8035E Figure 14. Input Test Waveforms and Measurement Level Input timing reference level 0.8VCC Output timing reference level 0.7VCC AC Measurement Level 0.3VCC 0.2VCC 0.5VCC Note: Input pulse rise and fall time are