MX25V1035FZUI

MX25V1035F MX25V1035F 2.3V-3.6V, 1M-BIT [x 1/x 2/x 4] CMOS MXSMIO® (SERIAL MULTI I/O) FLASH MEMORY Key Features • 2.3V-3.6V for Read, Erase and Program Operations • Unique ID and Secure OTP Support • Multi I/O Support - Single I/O, Dual I/O and Quad I/O • Program Suspend/Resume & Erase Suspend/Resume P/N: PM2329 1 Rev. 1.2, July 17, 2017 MX25V1035F Contents 1. FEATURES............................................................................................................................................................... 4 2. GENERAL DESCRIPTION...................................................................................................................................... 5 Table 1. Additional Feature...........................................................................................................................6 3. PIN CONFIGURATIONS .......................................................................................................................................... 7 4. PIN DESCRIPTION................................................................................................................................................... 7 5. BLOCK DIAGRAM.................................................................................................................................................... 8 6. DATA PROTECTION................................................................................................................................................. 9 Table 2. Protected Area Sizes....................................................................................................................10 Table 3. 8K-bit Secured OTP Definition..................................................................................................... 11 7. MEMORY ORGANIZATION.................................................................................................................................... 12 Table 4. Memory Organization...................................................................................................................12 8. DEVICE OPERATION............................................................................................................................................. 13 9. HOLD FEATURE..................................................................................................................................................... 15 10. COMMAND DESCRIPTION.................................................................................................................................. 16 Table 5. Command Set...............................................................................................................................16 10-1. Write Enable (WREN)............................................................................................................................... 19 10-2. Write Disable (WRDI)................................................................................................................................ 20 10-3. Read Identification (RDID)........................................................................................................................ 21 10-4. Read Electronic Signature (RES)............................................................................................................. 22 10-5. Read Electronic Manufacturer ID & Device ID (REMS)............................................................................ 23 10-6. ID Read..................................................................................................................................................... 24 Table 6. ID Definitions ...............................................................................................................................24 10-7. Read Status Register (RDSR).................................................................................................................. 25 Table 7. Status Register.............................................................................................................................28 Table 8. Configuration Register..................................................................................................................29 Table 9. Dummy Cycle Table......................................................................................................................29 10-8. Read Configuration Register (RDCR)....................................................................................................... 30 10-9. Write Status Register (WRSR).................................................................................................................. 31 Table 10. Protection Modes........................................................................................................................32 10-10. Read Data Bytes (READ)......................................................................................................................... 35 10-11. Read Data Bytes at Higher Speed (FAST_READ)................................................................................... 36 10-12. Dual Read Mode (DREAD)....................................................................................................................... 37 10-13. 2 x I/O Read Mode (2READ).................................................................................................................... 38 10-14. Quad Read Mode (QREAD)..................................................................................................................... 39 10-15. 4 x I/O Read Mode (4READ).................................................................................................................... 40 10-16. Burst Read................................................................................................................................................ 42 10-17. Performance Enhance Mode.................................................................................................................... 43 10-18. Sector Erase (SE)..................................................................................................................................... 45 10-19. Block Erase (BE32K)................................................................................................................................ 46 10-20. Block Erase (BE)...................................................................................................................................... 47 10-21. Chip Erase (CE)........................................................................................................................................ 48 10-22. Page Program (PP).................................................................................................................................. 49 P/N: PM2329 2 Rev. 1.2, July 17, 2017 MX25V1035F 10-23. 4 x I/O Page Program (4PP)..................................................................................................................... 50 10-24. Deep Power-down (DP)............................................................................................................................ 51 10-25. Enter Secured OTP (ENSO)..................................................................................................................... 52 10-26. Exit Secured OTP (EXSO)........................................................................................................................ 52 10-27. Read Security Register (RDSCUR).......................................................................................................... 52 Table 11. Security Register Definition........................................................................................................53 10-28. Write Security Register (WRSCUR).......................................................................................................... 53 10-29. Program/Erase Suspend/Resume............................................................................................................ 54 Table 12. Readable Area of Memory While a Program or Erase Operation is Suspended........................54 Table 13. Acceptable Commands During Program/Erase Suspend after tPSL/tESL.................................54 Table 14. Acceptable Commands During Suspend (tPSL/tESL not required)............................................55 10-30. Program Resume and Erase Resume...................................................................................................... 56 10-31. No Operation (NOP)................................................................................................................................. 57 10-32. Software Reset (Reset-Enable (RSTEN) and Reset (RST)).................................................................... 57 10-33. High Voltage Operation............................................................................................................................. 59 10-34. Read SFDP Mode (RDSFDP)................................................................................................................... 60 11. POWER-ON STATE.............................................................................................................................................. 61 12. ELECTRICAL SPECIFICATIONS......................................................................................................................... 62 Table 15. Absolute Maximum Ratings........................................................................................................62 Table 16. Capacitance................................................................................................................................62 Table 17. DC Characteristics......................................................................................................................64 Table 18. AC Characteristics .....................................................................................................................65 13. OPERATING CONDITIONS.................................................................................................................................. 67 Table 19. Power-Up/Down Voltage and Timing..........................................................................................69 13-1. Initial Delivery State.................................................................................................................................. 69 14. ERASE AND PROGRAMMING PERFORMANCE............................................................................................... 70 15. LATCH-UP CHARACTERISTICS......................................................................................................................... 70 16. ORDERING INFORMATION................................................................................................................................. 71 17. PART NAME DESCRIPTION................................................................................................................................ 72 18. PACKAGE INFORMATION................................................................................................................................... 73 18-1. 8-pin SOP (150mil)................................................................................................................................... 73 18-2. 8-land USON (2x3mm)............................................................................................................................. 74 19. REVISION HISTORY ............................................................................................................................................ 75 P/N: PM2329 3 Rev. 1.2, July 17, 2017 MX25V1035F 2.3V-3.6V 1M-BIT [x 1/x 2/x 4] CMOS MXSMIO® (SERIAL MULTI I/O) FLASH MEMORY 1. FEATURES • Auto Erase and Auto Program Algorithm - Automatically erases and verifies data at selected sector or block - Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (Any page to be programed should have page in the erased state first) • Status Register Feature • Command Reset • Program/Erase Suspend and Program/Erase Resume • Electronic Identification - JEDEC 1-byte manufacturer ID and 2-byte device ID - RES command for 1-byte Device ID - REMS command for 1-byte manufacturer ID and 1-byte device ID • Support Serial Flash Discoverable Parameters (SFDP) mode • Support Unique ID (Please contact local Macronix sales for detail information) GENERAL • Supports Serial Peripheral Interface -- Mode 0 and Mode 3 • 1,048,576 x 1 bit structure or 524,288 x 2 bits (two I/O mode) structure or 262,144 x 4 bits (four I/O mode) structure • Equal Sectors with 4K byte each, or Equal Blocks with 32K/64K byte each - Any Block can be erased individually • Single Power Supply Operation - Operation Voltage: 2.3V-3.6V for Read, Erase and Program Operations • Latch-up protected to 100mA from -1V to Vcc +1V PERFORMANCE • High Performance - Fast read - 1 I/O: 108MHz with 8 dummy cycles - 2 I/O: 104MHz with 4 dummy cycles, equivalent to 208MHz - 4 I/O: 104MHz with 2+4 dummy cycles, equivalent to 416MHz - Fast program and erase time - 8/16/32/64 byte Wrap-Around Burst Read Mode • Low Power Consumption • Minimum 100,000 erase/program cycles • 20 years data retention HARDWARE FEATURES • SCLK Input - Serial clock input • SI/SIO0 - Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode • SO/SIO1 - Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode • WP#/SIO2 - Hardware write protection or Serial Data Input/ Output for 4 x I/O read mode • HOLD#/SIO3 - HOLD feature, to pause the device without deselecting the device or Serial input & Output for 4 x I/O read mode • PACKAGE - 8-pin SOP (150mil) - 8-land USON (2x3mm) - All devices are RoHS Compliant and Halogen-free SOFTWARE FEATURES • Input Data Format - 1-byte Command code • Advanced Security Features - Block lock protection The BP0-BP3 status bit defines the size of the area to be software protection against program and erase instructions • Additional 8K bits secured OTP - Features unique identifier. - Factory locked identifiable and customer lockable P/N: PM2329 4 Rev. 1.2, July 17, 2017 MX25V1035F 2. GENERAL DESCRIPTION MX25V1035F is 1Mb bits Serial NOR Flash memory, which is configured as 131,072 x 8 internally. When it is in four I/O mode, the structure becomes 262,144 bits x 4 or 524,288 bits x 2. MX25V1035F features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single I/O mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input. When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# pin and HOLD# pin become SIO0 pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output. The MX25V1035F MXSMIO® (Serial Multi I/O) provides sequential read operation on the whole chip. After program/erase command is issued, auto program/erase algorithms which program/erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256 bytes) basis, or word basis. Erase command is executed on 4K-byte sector, 32K-byte block, or 64K-byte block, or whole chip basis. To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. Advanced security features enhance the protection and security functions, please refer to the security features section for more details. The MX25V1035F utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles. P/N: PM2329 5 Rev. 1.2, July 17, 2017 MX25V1035F Table 1. Additional Feature Protection and Security MX25V1035F Flexible Block Protection (BP0-BP3) V 8K-bit security OTP V Fast Read Performance I/O Dummy Cycle Frequency P/N: PM2329 1 I/O 1I/2O 2 I/O 1I/4O 4 I/O 8 8 4 8 6 108MHz 104MHz 104MHz 104MHz 104MHz 6 Rev. 1.2, July 17, 2017 MX25V1035F 3. PIN CONFIGURATIONS 4. PIN DESCRIPTION 8-PIN SOP (150mil) CS# SO/SIO1 WP#/SIO2 GND SYMBOL CS# 1 2 3 4 8 7 6 5 DESCRIPTION Chip Select Serial Data Input (for 1 x I/O)/ Serial SI/SIO0 Data Input & Output (for 4xI/O read mode) Serial Data Output (for 1 x I/O)/ Serial SO/SIO1 Data Input & Output (for 4xI/O read mode) SCLK Clock Input Write Protection Active Low or Serial WP#/SIO2 Data Input & Output (for 4xI/O read mode) To pause the device without HOLD#/SIO3 deselecting the device or Serial Data Input & Output (for 4xI/O read mode) VCC Power Supply GND Ground VCC HOLD#/SIO3 SCLK SI/SIO0 8-LAND USON (2x3mm) CS# SO/SIO1 WP#/SIO2 GND 1 2 3 4 8 7 6 5 VCC HOLD#/SIO3 SCLK SI/SIO0 Note: The pin of HOLD#/SIO3 or WP#/SIO2 will remain internal pull up function while this pin is not physically connected in system configuration. However, the internal pull up function will be disabled if the system has physical connection to HOLD#/SIO3 or WP#/SIO2 pin. P/N: PM2329 7 Rev. 1.2, July 17, 2017 MX25V1035F 5. BLOCK DIAGRAM X-Decoder Address Generator SI/SIO0 SO/SIO1 SIO2 * SIO3 * WP# * RESET# * HOLD# * CS# SCLK Memory Array Y-Decoder Data Register Sense Amplifier SRAM Buffer Mode Logic State Machine HV Generator Clock Generator Output Buffer * Depends on part number options. P/N: PM2329 8 Rev. 1.2, July 17, 2017 MX25V1035F 6. DATA PROTECTION During power transition, there may be some false system level signals which result in inadvertent erasure or programming. The device is designed to protect itself from these accidental write cycles. The state machine will be reset as standby mode automatically during power up. In addition, the control register architecture of the device constrains that the memory contents can only be changed after specific command sequences have completed successfully. In the following, there are several features to protect the system from the accidental write cycles during VCC powerup and power-down or from system noise. • Power-on reset: to avoid sudden power switch by system power supply transition, the power-on reset may protect the Flash. • Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary. • Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before issuing other commands to change data. • Deep Power Down Mode: By entering deep power down mode, the flash device is under protected from writing all commands except toggling the CS#. For more detail please see "10-24. Deep Power-down (DP)". • Advanced Security Features: there are some protection and security features which protect content from inadvertent write and hostile access. I. Block lock protection - The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected as read only. The protected area definition is shown as "Table 2. Protected Area Sizes", the protected areas are more flexible which may protect various area by setting value of BP0-BP3 bits. - The Hardware Protected Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and Status Register Write Protect (SRWD) bit. If the system goes into four I/O mode, the feature of HPM will be disabled. P/N: PM2329 9 Rev. 1.2, July 17, 2017 MX25V1035F Table 2. Protected Area Sizes Protected Area Sizes (TB bit = 0) Status bit BP3 BP2 BP1 BP0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Protected Area Sizes (TB bit = 1) Status bit BP3 BP2 BP1 BP0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Protect Level 0 (none) 1 (1block, block 1st) 2 (2blocks, block 0th-1st) 3 (2blocks, protect all) 4 (2blocks, protect all) 5 (2blocks, protect all) 6 (2blocks, protect all) 7 (2blocks, protect all) 8 (2blocks, protect all) 9 (2blocks, protect all) 10 (2blocks, protect all) 11 (2blocks, protect all) 12 (2blocks, protect all) 13 (2blocks, protect all) 14 (2blocks, protect all) 15 (2blocks, protect all) Protect Level 0 (none) 1 (1block, block 0th) 2 (2blocks, block 0th-1st) 3 (2blocks, protect all) 4 (2blocks, protect all) 5 (2blocks, protect all) 6 (2blocks, protect all) 7 (2blocks, protect all) 8 (2blocks, protect all) 9 (2blocks, protect all) 10 (2blocks, protect all) 11 (2blocks, protect all) 12 (2blocks, protect all) 13 (2blocks, protect all) 14 (2blocks, protect all) 15 (2blocks, protect all) Note: The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP3, BP2, BP1, BP0) are 0. P/N: PM2329 10 Rev. 1.2, July 17, 2017 MX25V1035F II. Additional 8K-bit secured OTP for unique identifier: to provide 8K-bit One-Time Program area for setting device unique serial number - Which may be set by factory or system maker. The 8K-bit secured OTP area is composed of two rows of 4K-bit. Customer could lock the first 4K-bit OTP area and factory could lock the other. - Security register bit 0 indicates whether the 2nd 4K-bit is locked by factory or not. - Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register) command to set customer lock-down bit1 as "1". Please refer to table of "Table 11. Security Register Definition" for security register bit definition and table of "Table 3. 8K-bit Secured OTP Definition" for address range definition. - To program 8K-bit secured OTP by entering secured OTP mode (with ENSO command), and going through normal program procedure, and then exiting secured OTP mode by writing EXSO command. Note: Once lock-down whatever by factory or customer, the corresponding secured area cannot be changed any more. While in 8K-bit Secured OTP mode, array access is not allowed. Table 3. 8K-bit Secured OTP Definition Address range Size Lock-down xxx000-xxx1FF 4096-bit Determined by Customer xxx200-xxx3FF 4096-bit Determined by Factory P/N: PM2329 11 Rev. 1.2, July 17, 2017 MX25V1035F 7. MEMORY ORGANIZATION Table 4. Memory Organization Block (64KB) Block (32KB) Sector (4KB) 1 3 | 2 0 1 | 0 31 : 16 15 : 2 1 0 P/N: PM2329 Address Range 01F000h : 010000h 00F000h : 002000h 001000h 000000h 01FFFFh : 010FFFh 00FFFFh : 002FFFh 001FFFh 000FFFh 12 Rev. 1.2, July 17, 2017 MX25V1035F 8. DEVICE OPERATION 1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation. 2. When incorrect command is inputted to this device, it enters standby mode and remains in standby mode until next CS# falling edge. In standby mode, SO pin of the device is High-Z. 3. When correct command is inputted to this device, it enters active mode and remains in active mode until next CS# rising edge. 4. Input data is latched on the rising edge of Serial Clock (SCLK) and data shifts out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as "Figure 1. Serial Modes Supported". 5. For the following instructions: RDID, RDSR, RDCR, RDSCUR, READ, FAST_READ, DREAD, 2READ, 4READ, QREAD, RDSFDP, RES, REMS, the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE32K, BE, CE, PP, 4PP, DP, ENSO, EXSO, WRSCUR, SUSPEND, RESUME, NOP, RSTEN, RST, the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. While a Write Status Register, Program or Erase operation is in progress, access to the memory array is neglected and will not affect the current operation of Write Status Register, Program, Erase. Figure 1. Serial Modes Supported CPOL CPHA shift in (Serial mode 0) 0 0 SCLK (Serial mode 3) 1 1 SCLK SI shift out MSB SO MSB Note: CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is supported. P/N: PM2329 13 Rev. 1.2, July 17, 2017 MX25V1035F Figure 2. Serial Input Timing tSHSL CS# tCHSL tSLCH tCHSH tSHCH SCLK tDVCH tCHCL tCHDX tCLCH LSB MSB SI High-Z SO Figure 3. Output Timing CS# tCH SCLK tCLQV tCLQX tCL tCLQV tSHQZ tCLQX LSB SO SI ADDR.LSB IN Figure 4. Hold Timing CS# tHLCH tCHHL tHHCH SCLK tCHHH tHLQZ tHHQX SO HOLD# P/N: PM2329 14 Rev. 1.2, July 17, 2017 MX25V1035F 9. HOLD FEATURE HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the operation of write status register, programming, or erasing in progress. The operation of HOLD requires Chip Select (CS#) keeping low and starts on falling edge of HOLD# pin signal while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Serial Clock(SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not end until Serial Clock being low). ≈ SI/SIO0 ≈ ≈ SO/SIO1 (internal) SO/SIO1 (External) Don’t care Valid Data Valid Data High_Z Bit 6 Bit 5 Bit 6 ≈ ≈ ≈ SO/SIO1 (internal) SO/SIO1 (External) High_Z Bit 7 Bit 5 ≈ ≈ SI/SIO0 ≈ HOLD# ≈ ≈ SCLK Valid Data Bit 6 Bit 7 CS# Don’t care Bit 7 ≈ HOLD# ≈ ≈ SCLK ≈ CS# ≈ Figure 5. Hold Condition Operation Don’t care Valid Data Bit 7 Bit 7 Valid Data Bit 6 High_Z Don’t care Bit 5 Bit 6 Bit 5 Valid Data Bit 4 High_Z Bit 3 Bit 4 Bit 3 During the HOLD operation, the Serial Data Output (SO) is high impedance when Hold# pin goes low and will keep high impedance until Hold# pin goes high. The Serial Data Input (SI) is don't care if both Serial Clock (SCLK) and Hold# pin goes low and will keep the state until SCLK goes low and Hold# pin goes high. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and CS# must be at low. Note: The HOLD feature is disabled during Quad I/O mode. P/N: PM2329 15 Rev. 1.2, July 17, 2017 MX25V1035F 10. COMMAND DESCRIPTION Table 5. Command Set Read/Write Array Commands I/O 1 1 2 2 DREAD (1I / 2O read command) 3B (hex) ADD1 1st byte 03 (hex) 0B (hex) 2READ (2 x I/O read command) BB (hex) 2nd byte ADD1 ADD1 ADD1 Command (byte) READ FAST READ (normal read) (fast read data) 4 4 4READ (4 x I/O read) QREAD (1I/4O read) EB (hex) 6B (hex) ADD1 ADD1 3rd byte ADD2 ADD2 ADD2 ADD2 ADD2 ADD2 4th byte ADD3 ADD3 ADD3 ADD3 ADD3 ADD3 Action n bytes read out until CS# goes high Dummy n bytes read out until CS# goes high I/O 1 4 Command (byte) PP (page program) 1st byte 02 (hex) 4PP (quad page program) 38 (hex) 2nd byte ADD1 3rd byte ADD2 4th byte ADD3 5th byte Dummy Dummy Dummy Dummy n bytes read n bytes read Quad I/O read n bytes read out by 2 x I/O out by Dual with 6 dummy out by Quad output until until CS# goes Output until cycles CS# goes high high CS# goes high 1 1 1 20 (hex) BE 32K (block erase 32KB) 52 (hex) BE (block erase 64KB) D8 (hex) ADD1 ADD1 ADD1 ADD1 ADD1 ADD2 ADD2 ADD2 ADD2 ADD2 ADD3 ADD3 ADD3 ADD3 SE (sector erase) 1 1 CE (chip erase) RDSFDP (Read SFDP) 60 or C7 (hex) 5A (hex) ADD3 5th byte to program the selected page Action P/N: PM2329 quad input to to erase the to erase the to erase the to erase whole chip program the selected sector selected 32KB selected block selected page block 16 Dummy Read SFDP mode Rev. 1.2, July 17, 2017 MX25V1035F Register/Setting Commands Command (byte) WREN (write enable) WRDI (write disable) RDSR (read status register) RDCR (read configuration register) WRSR (write status register) 1st byte 06 (hex) 04 (hex) 05 (hex) 15 (hex) 01 (hex) 2nd byte Values 3rd byte Values PGM/ERS Suspend (Suspends Program/Erase) 75 or B0 (hex) 4th byte 5th byte Action Command (byte) 1st byte sets the (WEL) resets the (WEL) write enable latch write enable latch bit bit PGM/ERS Resume (Resumes Program/Erase) 7A or 30 (hex) to read out the values of the status register DP (Deep power down) SBL (Set Burst Length) B9 (hex) C0 (hex) 2nd byte to read out the values of the configuration register to write new values of the configuration/ status register program/erase operation is interrupted by suspend command Value 3rd byte 4th byte 5th byte Action P/N: PM2329 to continue performing the suspended program/erase sequence enters deep power down mode to set Burst length 17 Rev. 1.2, July 17, 2017 MX25V1035F ID/Reset Commands Command (byte) 1st byte RDID RES (read (read identificelectronic ID) ation) 9F (hex) AB (hex) REMS (read RDSCUR WRSCUR electronic ENSO (enter EXSO (exit (read security (write security manufacturer secured OTP) secured OTP) register) register) & device ID) 90 (hex) B1 (hex) C1 (hex) 2B (hex) 2F (hex) 2nd byte x x 3rd byte x x 4th byte x ADD (Note 1) 5th byte Action COMMAND (byte) 1st byte outputs JEDEC to read out output the to enter the to exit the to read value to set the lockID: 1-byte 1-byte Device Manufacturer 8K-bit secured 8K-bit secured of security down bit as Manufacturer ID ID & Device ID OTP mode OTP mode register "1" (once lockID & 2-byte down, cannot Device ID be update) NOP RSTEN (No Operation) (Reset Enable) 00 (hex) 66 (hex) RST (Reset Memory) 99 (hex) 2nd byte 3rd byte 4th byte 5th byte Action (Note 3) Note 1: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first. Note 2: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden mode. Note 3: The RSTEN command must be executed before executing the RST command. If any other command is issued in-between RSTEN and RST, the RST command will be ignored. P/N: PM2329 18 Rev. 1.2, July 17, 2017 MX25V1035F 10-1. Write Enable (WREN) The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP, SE, BE32K, BE, CE, and WRSR, which are intended to change the device content WEL bit should be set every time after the WREN instruction setting the WEL bit. The sequence of issuing WREN instruction is: CS# goes low→sending WREN instruction code→ CS# goes high. The SIO[3:1] are "don't care" . Figure 6. Write Enable (WREN) Sequence CS# Mode 3 0 1 2 3 4 5 6 7 SCLK Mode 0 Command SI SO P/N: PM2329 06h High-Z 19 Rev. 1.2, July 17, 2017 MX25V1035F 10-2. Write Disable (WRDI) The Write Disable (WRDI) instruction is to reset Write Enable Latch (WEL) bit. The sequence of issuing WRDI instruction is: CS# goes low→sending WRDI instruction code→CS# goes high. The SIO[3:1] are "don't care". The WEL bit is reset by following situations: - Power-up - Completion of Write Disable (WRDI) instruction - Completion of Write Status Register (WRSR) instruction - Completion of Page Program (PP) instruction - Completion of Quad Page Program (4PP) instruction - Completion of Sector Erase (SE) instruction - Completion of Block Erase 32KB (BE32K) instruction - Completion of Block Erase (BE) instruction - Completion of Chip Erase (CE) instruction - Program/Erase Suspend - Completion of Softreset command - Completion of Write Security Register (WRSCUR) command Figure 7. Write Disable (WRDI) Sequence CS# Mode 3 0 1 2 3 4 5 6 7 SCLK Mode 0 Command SI SO P/N: PM2329 04h High-Z 20 Rev. 1.2, July 17, 2017 MX25V1035F 10-3. Read Identification (RDID) The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Macronix Manufacturer ID and Device ID are listed as "Table 6. ID Definitions". The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code→24-bits ID data out on SO→ to end RDID operation can drive CS# to high at any time during data out. While Program/Erase operation is in progress, it will not decode the RDID instruction, therefore there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage. Figure 8. Read Identification (RDID) Sequence CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31 SCLK Mode 0 Command SI 9Fh Manufacturer Identification SO High-Z 7 6 5 3 MSB P/N: PM2329 2 1 Device Identification 0 15 14 13 3 2 1 0 MSB 21 Rev. 1.2, July 17, 2017 MX25V1035F 10-4. Read Electronic Signature (RES) RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as "Table 6. ID Definitions". This is not the same as RDID instruction. It is not recommended to use for new design. For new design, please use RDID instruction. The SIO[3:1] are "don't care". The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. Figure 9. Read Electronic Signature (RES) Sequence CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 SCLK Mode 0 Command SI ABh 3 Dummy Bytes 23 22 21 3 2 1 0 MSB SO Electronic Signature Out High-Z 7 6 5 4 3 2 1 0 MSB P/N: PM2329 22 Rev. 1.2, July 17, 2017 MX25V1035F 10-5. Read Electronic Manufacturer ID & Device ID (REMS) The REMS instruction returns both the JEDEC assigned manufacturer ID and the device ID. The Device ID values are listed in "Table 6. ID Definitions". The REMS instruction is initiated by driving the CS# pin low and sending the instruction code "90h" followed by two dummy bytes and one address byte (A7-A0). After which the manufacturer ID for Macronix (C2h) and the device ID are shifted out on the falling edge of SCLK with the most significant bit (MSB) first. If the address byte is 00h, the manufacturer ID will be output first, followed by the device ID. If the address byte is 01h, then the device ID will be output first, followed by the manufacturer ID. While CS# is low, the manufacturer and device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high. Figure 10. Read Electronic Manufacturer & Device ID (REMS) Sequence CS# SCLK Mode 3 0 1 2 Mode 0 3 4 5 6 7 8 Command SI 9 10 2 Dummy Bytes 15 14 13 90h 3 2 1 0 High-Z SO CS# 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK ADD (1) SI 7 6 5 4 3 2 1 0 Manufacturer ID SO 7 6 5 4 3 2 1 Device ID 0 7 6 5 4 3 2 MSB MSB 1 0 7 MSB Notes: (1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first. P/N: PM2329 23 Rev. 1.2, July 17, 2017 MX25V1035F 10-6. ID Read User can execute this ID Read instruction to identify the Device ID and Manufacturer ID. The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code→24-bits ID data out on SO→ to end RDID operation can drive CS# to high at any time during data out. After the command cycle, the device will immediately output data on the falling edge of SCLK. The manufacturer ID, memory type, and device ID data byte will be output continuously, until the CS# goes high. While Program/Erase operation is in progress, it will not decode the RDID instruction, therefore there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage. Table 6. ID Definitions Command Type RDID MX25V1035F Manufacturer ID C2 RES REMS P/N: PM2329 Manufacturer ID C2 Memory type 23 Electronic ID 11 Device ID 11 Memory density 11 24 Rev. 1.2, July 17, 2017 MX25V1035F 10-7. Read Status Register (RDSR) The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in program/erase/write status register condition). It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in progress. The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register data out on SO. The SIO[3:1] are "don't care". Figure 11. Read Status Register (RDSR) Sequence CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK Mode 0 command 05h SI SO High-Z Status Register Out 7 6 5 4 2 1 0 7 6 5 4 3 2 1 0 7 MSB MSB P/N: PM2329 3 Status Register Out 25 Rev. 1.2, July 17, 2017 MX25V1035F For user to check if Program/Erase operation is finished or not, RDSR instruction flow are shown as follows: Figure 12. Program/Erase flow with read array data start WREN command RDSR command* WEL=1? No Yes Program/erase command Write program data/address (Write erase address) RDSR command WIP=0? No Yes RDSR command Read WEL=0, BP[3:0], QE, and SRWD data Read array data (same address of PGM/ERS) Verify OK? No Yes Program/erase successfully Program/erase another block? Program/erase fail Yes * Issue RDSR to check BP[3:0]. No Program/erase completed P/N: PM2329 26 Rev. 1.2, July 17, 2017 MX25V1035F Figure 13. Program/Erase flow without read array data (read P_FAIL/E_FAIL flag) start WREN command RDSR command* WEL=1? No Yes Program/erase command Write program data/address (Write erase address) RDSR command WIP=0? No Yes RDSR command Read WEL=0, BP[3:0], QE, and SRWD data RDSCUR command Yes P_FAIL/E_FAIL =1 ? No Program/erase fail Program/erase successfully Program/erase another block? No Yes * Issue RDSR to check BP[3:0]. Program/erase completed P/N: PM2329 27 Rev. 1.2, July 17, 2017 MX25V1035F Status Register The definition of the status register bits is as below: WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. WEL bit. The Write Enable Latch (WEL) bit is a volatile bit that is set to “1” by the WREN instruction. WEL needs to be set to “1” before the device can accept program and erase instructions, otherwise the program and erase instructions are ignored. WEL automatically clears to “0” when a program or erase operation completes. To ensure that both WIP and WEL are “0” and the device is ready for the next program or erase operation, it is recommended that WIP be confirmed to be “0” before checking that WEL is also “0”. If a program or erase instruction is applied to a protected memory area, the instruction will be ignored and WEL will clear to “0”. BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area (as defined in "Table 2. Protected Area Sizes") of the device to against the program/erase instruction without hardware protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE/BE32K) and Chip Erase (CE) instructions (only if Block Protect bits (BP3:BP0) set to 0, the CE instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as default, which is un-protected. QE bit. The Quad Enable (QE) bit, non-volatile bit, while it is "0" (factory default), it performs non-Quad and WP# and HOLD# are enabled. While QE is "1", it performs Quad I/O mode and WP#, HOLD# are disabled. In the other words, if the system goes into four I/O mode (QE=1), the feature of HPM and HOLD will be disabled. SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection (WP#/SIO2) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are read only. The SRWD bit defaults to be "0". Table 7. Status Register bit7 bit6 SRWD (status register write protect) QE (Quad Enable) 1=status register write 1=Quad disabled Enable 0=status 0=not Quad register write Enable enabled Non-volatile bit Non-volatile bit bit5 BP3 (level of protected block) bit4 BP2 (level of protected block) bit3 BP1 (level of protected block) bit2 BP0 (level of protected block) (note 1) (note 1) (note 1) (note 1) Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit bit1 bit0 WEL WIP (write enable (write in latch) progress bit) 1=write 1=write enable operation 0=not write 0=not in write enable operation volatile bit volatile bit Note 1: Please refer to the "Table 2. Protected Area Sizes". P/N: PM2329 28 Rev. 1.2, July 17, 2017 MX25V1035F Configuration Register The Configuration Register is able to change the default status of Flash memory. Flash memory will be configured after the CR bit is set. TB bit The Top/Bottom (TB) bit is a non-volatile OTP bit. The Top/Bottom (TB) bit is used to configure the Block Protect area by BP bit (BP3, BP2, BP1, BP0), starting from TOP or Bottom of the memory array. The TB bit is defaulted as “0”, which means Top area protect. When it is set as “1”, the protect area will change to Bottom area of the memory device. To write the TB bit requires the Write Status Register (WRSR) instruction to be executed. Table 8. Configuration Register bit7 bit6 bit5 DC Reserved (Dummy Reserved Cycle) bit4 Reserved x 2READ/ 4READ Dummy Cycle x x x Volatile bit x x bit3 TB (top/bottom selected) 0=Top area protect 1=Bottom area protect (Default=0) OTP bit2 bit1 bit0 Reserved Reserved Reserved x x x x x x Table 9. Dummy Cycle Table 2READ 4READ P/N: PM2329 DC Numbers of Dummy Cycles 0 (default) 4 1 8 0 (default) 6 1 10 29 Rev. 1.2, July 17, 2017 MX25V1035F 10-8. Read Configuration Register (RDCR) The RDCR instruction is for reading Configuration Register Bits. The Read Configuration Register can be read at any time (even in program/erase/write configuration register condition). It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write configuration register operation is in progress. The sequence of issuing RDCR instruction is: CS# goes low→ sending RDCR instruction code→ Configuration Register data out on SO. The SIO[3:1] are don't care. Figure 14. Read Configuration Register (RDCR) Sequence CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK Mode 0 command 15h SI SO High-Z Configuration register Out 7 6 5 4 2 1 0 7 6 5 4 3 2 1 0 7 MSB MSB P/N: PM2329 3 Configuration register Out 30 Rev. 1.2, July 17, 2017 MX25V1035F 10-9. Write Status Register (WRSR) The WRSR instruction is for changing the values of Status Register Bits and Configuration Register Bits. Before sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1, BP0) bits to define the protected area of memory (as shown in "Table 2. Protected Area Sizes"). The WRSR also can set or reset the Quad enable (QE) bit and set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#/SIO2) pin signal, but has no effect on bit1(WEL) and bit0 (WIP) of the status register. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered. The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register data on SI→CS# goes high. The CS# must go high exactly at the 8 bits or 16 bits data boundary; otherwise, the instruction will be rejected and not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset. For more detail please check "Table 18. AC Characteristics". Figure 15. Write Status Register (WRSR) Sequence CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCLK Mode 0 SI SO P/N: PM2329 command 01h High-Z Status Register In 7 6 5 4 3 2 Configuration Register In 1 0 15 14 13 12 11 10 9 8 MSB 31 Rev. 1.2, July 17, 2017 MX25V1035F Software Protected Mode (SPM): - When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM). - When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM) Note: If SRWD bit=1 but WP#/SIO2 is low, it is impossible to write the Status Register even if the WEL bit has previously been set. It is rejected to write the Status Register and not be executed. Hardware Protected Mode (HPM): - When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2, BP1, BP0 and hardware protected mode by the WP#/SIO2 to against data modification. Note: To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is entered. If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via BP3, BP2, BP1, BP0. Table 10. Protection Modes Mode Software protection mode (SPM) Hardware protection mode (HPM) Status register condition WP# and SRWD bit status Memory Status register can be written in (WEL bit is set to "1") and the SRWD, BP0-BP3 bits can be changed WP#=1 and SRWD bit=0, or WP#=0 and SRWD bit=0, or WP#=1 and SRWD=1 The protected area cannot be program or erase. The SRWD, BP0-BP3 of status register bits cannot be changed WP#=0, SRWD bit=1 The protected area cannot be program or erase. Note: 1. As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in "Table 2. Protected Area Sizes". P/N: PM2329 32 Rev. 1.2, July 17, 2017 MX25V1035F Figure 16. WRSR flow start WREN command RDSR command WEL=1? No Yes WRSR command Write status register data RDSR command WIP=0? No Yes RDSR command Read WEL=0, BP[3:0], QE, and SRWD data Verify OK? No Yes WRSR successfully P/N: PM2329 WRSR fail 33 Rev. 1.2, July 17, 2017 MX25V1035F Figure 17. WP# Setup Timing and Hold Timing during WRSR when SRWD=1 WP# tSHWL tWHSL CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK 01h SI SO High-Z Note: WP# must be kept high until the embedded operation finish. P/N: PM2329 34 Rev. 1.2, July 17, 2017 MX25V1035F 10-10. Read Data Bytes (READ) The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing READ instruction is: CS# goes low→sending READ instruction code→ 3-byte address on SI→ data out on SO→to end READ operation can use CS# to high at any time during data out. Figure 18. Read Data Bytes (READ) Sequence CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK Mode 0 SI command 03h 24-Bit Address 23 22 21 3 2 1 0 MSB SO Data Out 1 High-Z 7 6 5 4 3 2 Data Out 2 1 0 7 MSB P/N: PM2329 35 Rev. 1.2, July 17, 2017 MX25V1035F 10-11. Read Data Bytes at Higher Speed (FAST_READ) The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ instruction code→ 3-byte address on SI→1-dummy byte (default) address on SI→ data out on SO→ to end FAST_READ operation can use CS# to high at any time during data out. While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. Figure 19. Read at Higher Speed (FAST_READ) Sequence CS# SCLK Mode 3 0 1 2 Mode 0 3 5 6 7 8 9 10 Command SI SO 4 28 29 30 31 24-Bit Address 23 22 21 0Bh 3 2 1 0 High-Z CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Cycle SI 7 6 5 4 3 2 1 0 DATA OUT 2 DATA OUT 1 SO 7 6 5 4 2 1 0 7 MSB MSB P/N: PM2329 3 36 6 5 4 3 2 1 0 7 MSB Rev. 1.2, July 17, 2017 MX25V1035F 10-12. Dual Read Mode (DREAD) The DREAD instruction enable double throughput of Serial NOR Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruction, the following data out will perform as 2-bit instead of previous 1-bit. The sequence of issuing DREAD instruction is: CS# goes low → sending DREAD instruction → 3-byte address on SI → 8-bit dummy cycle → data out interleave on SIO1 & SIO0 → to end DREAD operation can use CS# to high at any time during data out. While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. Figure 20. Dual Read Mode Sequence (Command 3B) CS# 0 1 2 3 4 5 6 7 8 … Command SI/SIO0 SO/SIO1 P/N: PM2329 30 31 32 9 SCLK 3B … 24 ADD Cycle A23 A22 … 39 40 41 42 43 44 45 A1 A0 High Impedance 8 dummy cycle Data Out 1 Data Out 2 D6 D4 D2 D0 D6 D4 D7 D5 D3 D1 D7 D5 37 Rev. 1.2, July 17, 2017 MX25V1035F 10-13. 2 x I/O Read Mode (2READ) The 2READ instruction enables Double Transfer Rate of Serial NOR Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit. The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 24-bit address interleave on SIO1 & SIO0→ 4-bit dummy cycle on SIO1 & SIO0→ data out interleave on SIO1 & SIO0→ to end 2READ operation can use CS# to high at any time during data out. While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. Figure 21. 2 x I/O Read Mode Sequence (Command BB) CS# 0 1 2 3 4 5 6 7 8 SCLK … Command SI/SIO0 SO/SIO1 18 19 20 21 22 23 24 25 26 27 28 29 9 BB(hex) High Impedance 12 ADD Cycle 4 dummy cycle Data Out 1 Data Out 2 A22 A20 … A2 A0 P2 P0 D6 D4 D2 D0 D6 D4 A23 A21 … A3 A1 P3 P1 D7 D5 D3 D1 D7 D5 Note: SI/SIO0 or SO/SIO1 should be kept "0h" or "Fh" in the first two dummy cycles. In other words, P2=P0 or P3=P1 is necessary. P/N: PM2329 38 Rev. 1.2, July 17, 2017 MX25V1035F 10-14. Quad Read Mode (QREAD) The QREAD instruction enable quad throughput of Serial NOR Flash in read mode. A Quad Enable (QE) bit of status Register must be set to "1" before sending the QREAD instruction. The address is latched on rising edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single QREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing QREAD instruction, the following data out will perform as 4-bit instead of previous 1-bit. The sequence of issuing QREAD instruction is: CS# goes low→ sending QREAD instruction → 3-byte address on SI → 8-bit dummy cycle → data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end QREAD operation can use CS# to high at any time during data out. While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. Figure 22. Quad Read Mode Sequence (Command 6B) CS# 0 1 2 3 4 5 6 7 8 SCLK … Command SI/SIO0 SO/SIO1 SIO2 SIO3 P/N: PM2329 29 30 31 32 33 9 6B … 24 ADD Cycles A23 A22 … High Impedance 38 39 40 41 42 A2 A1 A0 8 dummy cycles Data Data Out 1 Out 2 Data Out 3 D4 D0 D4 D0 D4 D5 D1 D5 D1 D5 High Impedance D6 D2 D6 D2 D6 High Impedance D7 D3 D7 D3 D7 39 Rev. 1.2, July 17, 2017 MX25V1035F 10-15. 4 x I/O Read Mode (4READ) The 4READ instruction enable quad throughput of Serial NOR Flash in read mode. A Quad Enable (QE) bit of status Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit. The sequence of issuing 4READ instruction is: CS# goes low→ sending 4READ instruction→ 24-bit address interleave on SIO3, SIO2, SIO1 & SIO0→2+4 dummy cycles→data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end 4READ operation can use CS# to high at any time during data out. Another sequence of issuing 4READ instruction especially useful in random access is: CS# goes low→sending 4READ instruction→3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 →performance enhance toggling bit P[7:0]→ 4 dummy cycles →data out still CS# goes high → CS# goes low (reduce 4READ instruction) →24-bit random access address. In the performance-enhancing mode, P[7:4] must be toggling with P[3:0]; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh can make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0]; likewise P[7:0]=FFh, 00h, AAh or 55h and afterwards CS# is raised and then lowered, the system then will escape from performance enhance mode and return to normal operation. While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. P/N: PM2329 40 Rev. 1.2, July 17, 2017 MX25V1035F Figure 23. 4 x I/O Read Mode Sequence CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Mode 3 SCLK Mode 0 Command EBh 6 ADD Cycles Performance enhance indicator (Note) 4 Dummy Cycles Data Out 1 Data Out 2 Data Out 3 A20 A16 A12 A8 A4 A0 P4 P0 D4 D0 D4 D0 D4 D0 SIO1 A21 A17 A13 A9 A5 A1 P5 P1 D5 D1 D5 D1 D5 D1 SIO2 A22 A18 A14 A10 A6 A2 P6 P2 D6 D2 D6 D2 D6 D2 SIO3 A23 A19 A15 A11 A7 A3 P7 P3 D7 D3 D7 D3 D7 D3 SIO0 Mode 0 Note: 1. Hi-impedance is inhibited for the two clock cycles. 2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited. P/N: PM2329 41 Rev. 1.2, July 17, 2017 MX25V1035F 10-16. Burst Read The Burst Read feature allows applications to fill a cache line with a fixed length of data without using multiple read commands. Burst Read is disabled by default at power-up or reset. Burst Read is enabled by setting the Burst Length. When the Burst Length is set, reads will wrap on the selected boundary (8/16/32/64-bytes) containing the initial target address. For example if an 8-byte Wrap Depth is selected, reads will wrap on the 8-byte-page-aligned boundary containing the initial read address. To set the Burst Length, drive CS# low → send SET BURST LENGTH instruction code → send WRAP CODE → drive CS# high. Refer to the table below for valid 8-bit Wrap Codes and their corresponding Wrap Depth. Data 00h 01h 02h 03h 1xh Wrap Around Yes Yes Yes Yes No Wrap Depth 8-byte 16-byte 32-byte 64-byte X Once Burst Read is enabled, it will remain enabled until the device is power-cycled or reset. The 4READ command supports the wrap around feature after Burst Read is enabled. To change the wrap depth, resend the Burst Read instruction with the appropriate Wrap Code. To disable Burst Read, send the Burst Read instruction with Wrap Code 1xh. “EBh” support wrap around feature after wrap around is enabled. Figure 24. Burst Read CS# Mode 3 0 1 2 3 4 5 6 7 8 9 D7 D6 10 11 12 13 14 15 SCLK Mode 0 SIO P/N: PM2329 C0h 42 D5 D4 D3 D2 D1 D0 Rev. 1.2, July 17, 2017 MX25V1035F 10-17. Performance Enhance Mode The device could waive the command cycle bits if the two cycle bits after address cycle toggles. “EBh” command supports enhance mode. The performance enhance mode is not supported in dual I/O mode. After entering enhance mode, following CS# go high, the device will stay in the read mode and treat CS# go low of the first clock as address instead of command cycle. To exit enhance mode, a new fast read command whose first two dummy cycles is not toggle then exit. Or issue ”FFh” data cycle to exit enhance mode. P/N: PM2329 43 Rev. 1.2, July 17, 2017 MX25V1035F Figure 25. 4 x I/O Read enhance performance Mode Sequence CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 n SCLK Mode 0 Data Out 2 Data Out n A20 A16 A12 A8 A4 A0 P4 P0 D4 D0 D4 D0 D4 D0 SIO1 A21 A17 A13 A9 A5 A1 P5 P1 D5 D1 D5 D1 D5 D1 SIO2 A22 A18 A14 A10 A6 A2 P6 P2 D6 D2 D6 D2 D6 D2 SIO3 A23 A19 A15 A11 A7 A3 P7 P3 D7 D3 D7 D3 D7 D3 Command EBh SIO0 6 ADD Cycles Performance enhance indicator (Note) 4 Dummy Cycles Data Out 1 CS# n+1 ........... n+7 ...... n+9 ........... n+13 ........... Mode 3 SCLK 6 ADD Cycles Performance enhance indicator (Note) 4 Dummy Cycles Data Out 1 Data Out 2 Data Out n SIO0 A20 A16 A12 A8 A4 A0 P4 P0 D4 D0 D4 D0 D4 D0 SIO1 A21 A17 A13 A9 A5 A1 P5 P1 D5 D1 D5 D1 D5 D1 SIO2 A22 A18 A14 A10 A6 A2 P6 P2 D6 D2 D6 D2 D6 D2 SIO3 A23 A19 A15 A11 A7 A3 P7 P3 D7 D3 D7 D3 D7 D3 Mode 0 Note: 1. Performance enhance mode, if P7≠P3 & P6≠P2 & P5≠P1 & P4≠P0 (Toggling), ex: A5, 5A, 0F, if not using performance enhance recommend to keep 1 or 0 in performance enhance indicator. 2. Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF P/N: PM2329 44 Rev. 1.2, July 17, 2017 MX25V1035F 10-18. Sector Erase (SE) The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector (as shown in "Table 4. Memory Organization") is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. Address bits [Am-A12] (Am is the most significant address) select the sector address. The sequence of issuing SE instruction is: CS# goes low→ sending SE instruction code→ 3-byte address on SI→ CS# goes high. The SIO[3:1] are "don't care". The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked during the Sector Erase cycle is in progress. The WIP sets 1 during the tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the sector is protected by BP3, BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the sector. Figure 26. Sector Erase (SE) Sequence CS# Mode 3 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK Mode 0 SI 24-Bit Address Command 23 22 20h 2 1 0 MSB P/N: PM2329 45 Rev. 1.2, July 17, 2017 MX25V1035F 10-19. Block Erase (BE32K) The Block Erase (BE32K) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 32K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE32K). Any address of the block (as shown in "Table 4. Memory Organization") is a valid address for Block Erase (BE32K) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of address byte has been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing BE32K instruction is: CS# goes low → sending BE32K instruction code → 3-byte address on SI → CS# goes high. The SIO[3:1] are don't care. The self-timed Block Erase Cycle time (tBE32K) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets during the tBE32K timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the block is protected by BP3-0, the array data will be protected (no change) and the WEL bit still be reset. Figure 27. Block Erase 32KB (BE32K) Sequence (Command 52) CS# 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK Command SI 24 Bit Address 23 22 52h 2 1 0 MSB P/N: PM2329 46 Rev. 1.2, July 17, 2017 MX25V1035F 10-20. Block Erase (BE) The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 64K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (Please refer to "Table 4. Memory Organization") is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing BE instruction is: CS# goes low→ sending BE instruction code→ 3-byte address on SI→ CS# goes high. The SIO[3:1] are "don't care". The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked during the Block Erase cycle is in progress. The WIP sets 1 during the tBE timing, and sets 0 when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the block is protected by BP3, BP2, BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the block. Figure 28. Block Erase (BE) Sequence CS# Mode 3 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK Mode 0 SI Command 24-Bit Address 23 22 D8h 2 1 0 MSB P/N: PM2329 47 Rev. 1.2, July 17, 2017 MX25V1035F 10-21. Chip Erase (CE) The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not executed. The sequence of issuing CE instruction is: CS# goes low→sending CE instruction code→CS# goes high. The SIO[3:1] are "don't care". The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is protected by BP3, BP2, BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when BP3, BP2, BP1, BP0 all set to "0". Figure 29. Chip Erase (CE) Sequence CS# Mode 3 0 1 2 3 4 5 6 7 SCLK Mode 0 SI P/N: PM2329 Command 60h or C7h 48 Rev. 1.2, July 17, 2017 MX25V1035F 10-22. Page Program (PP) The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device programs only the last 256 data bytes sent to the device. The last address byte (the 8 least significant address bits, A7-A0) should be set to 0 for 256 bytes page program. If A7-A0 are not all zero, transmitted data that exceed page length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently selected page. If the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the request page and previous data will be disregarded. If the data bytes sent to the device has not exceeded 256, the data will be programmed at the request address of the page. There will be no effort on the other data bytes of the same page. The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→ at least 1-byte on data on SI→ CS# goes high. The CS# must be kept low during the whole Page Program cycle; The CS# must go high exactly at the byte boundary (the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed. The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked during the Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP3, BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed. The SIO[3:1] are "don't care". Figure 30. Page Program (PP) Sequence CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK 1 0 7 6 5 3 2 1 0 2079 2 2078 3 2077 23 22 21 02h SI Data Byte 1 24-Bit Address 2076 Command 2075 Mode 0 4 1 0 MSB MSB 2074 2073 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2072 CS# SCLK Data Byte 2 SI 7 6 MSB P/N: PM2329 5 4 3 2 Data Byte 3 1 0 7 6 5 MSB 4 3 2 Data Byte 256 1 0 7 6 5 4 3 2 MSB 49 Rev. 1.2, July 17, 2017 MX25V1035F 10-23. 4 x I/O Page Program (4PP) The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1" before sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1, SIO2, and SIO3 as address and data input, which can improve programmer performance and the effectiveness of application. The 4PP operation frequency supports as fast as f4PP. The other function descriptions are as same as standard page program. The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on SIO[3:0]→ at least 1-byte on data on SIO[3:0]→CS# goes high. Figure 31. 4 x I/O Page Program (4PP) Sequence CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 SCLK Mode 0 SIO0 P/N: PM2329 Command 38h 6 ADD cycles Data Data Data Data Byte 1 Byte 2 Byte 3 Byte 4 A20 A16 A12 A8 A4 A0 D4 D0 D4 D0 D4 D0 D4 D0 SIO1 A21 A17 A13 A9 A5 A1 D5 D1 D5 D1 D5 D1 D5 D1 SIO2 A22 A18 A14 A10 A6 A2 D6 D2 D6 D2 D6 D2 D6 D2 SIO3 A23 A19 A15 A11 A7 A3 50 D7 D3 D7 D3 D7 D3 D7 D3 Rev. 1.2, July 17, 2017 MX25V1035F 10-24. Deep Power-down (DP) The Deep Power-down (DP) instruction places the device into a minimum power consumption state, Deep Power down mode, in which the quiescent current is reduced from ISB1 to ISB2. The sequence of issuing DP instruction: CS# goes low→ send DP instruction code→ CS# goes high. The CS# must go high at the byte boundary; otherwise the instruction will not be executed. SIO[3:1] are "don't care". After CS# goes high there is a delay of tDP before the device transitions from Stand-by mode to Deep Power-down mode and the current reduces from ISB1 to ISB2. Once in Deep Power-down mode, all instructions will be ignored. CS# must not be pulsed low until the device has been in Deep Power-down mode for a minimum of tDPDD. The device exits Deep Power-down mode and returns to Stand-by mode if CS# pulses low for tCRDP or if the device is power-cycled or hardware reset. After CS# goes high, there is a delay of tRDP before the device transitions from Deep Power-down mode back to Stand-by mode. Figure 32. Deep Power-down (DP) Sequence and Release from Deep Power-down Sequence tCRDP CS# tDP Mode 3 0 1 2 3 4 5 6 tDPDD tRDP 7 SCLK Mode 0 SI Command B9h Stand-by Mode P/N: PM2329 Deep Power-down Mode 51 Stand-by Mode Rev. 1.2, July 17, 2017 MX25V1035F 10-25. Enter Secured OTP (ENSO) The ENSO instruction is for entering the additional 8K-bit secured OTP mode. While the device is in 8K-bit Secured OTP mode, array access is not available. The additional 8K-bit secured OTP is independent from main array, and may be used to store unique serial number for system identifier. After entering the Secured OTP mode, follow standard read or program procedure to read out the data or update data. The Secured OTP data cannot be updated again once it is lock-down. The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP mode→ CS# goes high. The SIO[3:1] are "don't care". Please note that WRSR/WRSCUR commands are not acceptable during the access of secure OTP region, once security OTP is lock down, only read related commands are valid. 10-26. Exit Secured OTP (EXSO) The EXSO instruction is for exiting the additional 8K-bit secured OTP mode. The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP mode→ CS# goes high. The SIO[3:1] are "don't care". 10-27. Read Security Register (RDSCUR) The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read at any time (even in program/erase/write status register/write security register condition) and continuously. The sequence of issuing RDSCUR instruction is : CS# goes low→sending RDSCUR instruction→Security Register data out on SO→ CS# goes high. The SIO[3:1] are "don't care". The definition of the Security Register bits is as below: Secured OTP Indicator bit. The Secured OTP indicator bit shows the secured OTP area is locked by factory or not. When it is "0", it indicates non-factory lock; "1" indicates factory- lock. Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for customer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 1st 4K-bit Secured OTP area cannot be updated any more. Program Suspend Status bit. Program Suspend Bit (PSB) indicates the status of Program Suspend operation. Users may use PSB to identify the state of flash memory. After the flash memory is suspended by Program Suspend command, PSB is set to "1". PSB is cleared to "0" after program operation resumes. Erase Suspend Status bit. Erase Suspend Bit (ESB) indicates the status of Erase Suspend operation. Users may use ESB to identify the state of flash memory. After the flash memory is suspended by Erase Suspend command, ESB is set to "1". ESB is cleared to "0" after erase operation resumes. P/N: PM2329 52 Rev. 1.2, July 17, 2017 MX25V1035F Program Fail Flag bit. The Program Fail bit shows the status of the last Program operation. The bit will be set to "1" if the program operation failed or the program region was protected. It will be automatically cleared to "0" if the next program operation succeeds. Please note that it will not interrupt or stop any operation in the flash memory. Erase Fail Flag bit. The Erase Fail bit shows the status of last Erase operation. The bit will be set to "1" if the erase operation failed or the erase region was protected. It will be automatically cleared to "0" if the next erase operation succeeds. Please note that it will not interrupt or stop any operation in the flash memory. Table 11. Security Register Definition bit7 Reserved bit6 bit5 E_FAIL P_FAIL 0=normal Erase succeed 0=normal Program succeed 1=indicate Erase failed (default=0) 1=indicate Program failed (default=0) non-volatile bit volatile bit volatile bit Reserved Read Only Read Only Reserved bit4 bit3 bit2 Reserved ESB (Erase Suspend status) PSB (Program Suspend status) 0=Erase is not suspended Reserved 1=Erase is suspended (default=0) volatile bit bit1 bit0 LDSO Secured OTP (lock-down Indicator bit 1st 4K-bit (2nd 4K-bit Secured Secured OTP) OTP) 0 = not 0=Program 0= lockdown is not 1 = lock-down nonfactory suspended lock (cannot 1 = factory program/ 1=Program erase lock is suspended OTP) (default=0) volatile bit volatile bit non-volatile bit non-volatile bit Read Only Read Only OTP Read Only 10-28. Write Security Register (WRSCUR) The WRSCUR instruction is for changing the values of Security Register Bits. The WREN (Write Enable) instruction is required before issuing WRSCUR instruction. The WRSCUR instruction may change the values of bit1 (LDSO bit) for customer to lock-down the 1st 4K-bit Secured OTP area. Once the LDSO bit is set to "1", the 1st 4K-bit Secured OTP area cannot be updated any more. The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high. The SIO[3:1] are "don't care". The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. P/N: PM2329 53 Rev. 1.2, July 17, 2017 MX25V1035F 10-29. Program/Erase Suspend/Resume The Suspend instruction interrupts a Page Program, Sector Erase, or Block Erase operation to allow access to the memory array. After the program or erase operation has entered the suspended state, the memory array can be read except for the page being programmed or the sector or block being erased ("Table 12. Readable Area of Memory While a Program or Erase Operation is Suspended"). Table 12. Readable Area of Memory While a Program or Erase Operation is Suspended Suspended Operation Readable Region of Memory Array Page Program All but the Page being programmed Sector Erase (4KB) All but the 4KB Sector being erased Block Erase (32KB) All but the 32KB Block being erased Block Erase (64KB) All but the 64KB Block being erased When the Serial NOR Flash receives the Suspend instruction, there is a latency of tPSL or tESL ("Figure 34. Suspend to Read/Program Latency") before the Write Enable Latch (WEL) bit clears to “0” and the PSB or ESB sets to “1”, after which the device is ready to accept one of the commands listed in "Table 13. Acceptable Commands During Program/Erase Suspend after tPSL/tESL" (e.g. FAST READ). Refer to "Table 18. AC Characteristics" for tPSL and tESL timings. "Table 14. Acceptable Commands During Suspend (tPSL/tESL not required)" lists the commands for which the tPSL and tESL latencies do not apply. For example, RDSR, RDSCUR, RSTEN, and RST can be issued at any time after the Suspend instruction. Security Register bit 2 (PSB) and bit 3 (ESB) can be read to check the suspend status. The PSB (Program Suspend Bit) sets to “1” when a program operation is suspended. The ESB (Erase Suspend Bit) sets to “1” when an erase operation is suspended. The PSB or ESB clears to “0” when the program or erase operation is resumed. Table 13. Acceptable Commands During Program/Erase Suspend after tPSL/tESL Command Name Command Code READ 03h FAST READ 0Bh DREAD 3Bh QREAD 6Bh 2READ BBh 4READ EBh RDSFDP 5Ah RDID 9Fh REMS 90h SBL C0h ENSO B1h EXSO C1h WREN 06h RESUME 7Ah or 30h PP 02h 4PP 38h P/N: PM2329 Suspend Type Program Suspend Erase Suspend • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 54 Rev. 1.2, July 17, 2017 MX25V1035F Table 14. Acceptable Commands During Suspend (tPSL/tESL not required) Command Name Command Code WRDI 04h RDSR 05h RDCR 15h RDSCUR 2Bh RES ABh RSTEN 66h RST 99h NOP 00h Suspend Type Program Suspend Erase Suspend • • • • • • • • • • • • • • • • Figure 33. Resume to Suspend Latency CS# Resume Command tPRS / tERS Suspend Command tPRS: Program Resume to another Suspend tERS: Erase Resume to another Suspend P/N: PM2329 55 Rev. 1.2, July 17, 2017 MX25V1035F 10-29-1. Erase Suspend to Program The “Erase Suspend to Program” feature allows Page Programming while an erase operation is suspended. Page Programming is permitted in any unprotected memory except within the sector of a suspended Sector Erase operation or within the block of a suspended Block Erase operation. The Write Enable (WREN) instruction must be issued before any Page Program instruction. A Page Program operation initiated within a suspended erase cannot itself be suspended and must be allowed to finish before the suspended erase can be resumed. The Status Register can be polled to determine the status of the Page Program operation. The WEL and WIP bits of the Status Register will remain “1” while the Page Program operation is in progress and will both clear to “0” when the Page Program operation completes. Figure 34. Suspend to Read/Program Latency CS# Suspend Command tPSL / tESL Read/Program Command tPSL: Program latency tESL: Erase latency Notes: 1. Please note that Program only available after the Erase-Suspend operation 2. To check suspend ready information, please read security register bit2(PSB) and bit3(ESB) 10-30. Program Resume and Erase Resume The Resume instruction resumes a suspended Page Program, Sector Erase, or Block Erase operation. Before issuing the Resume instruction to restart a suspended erase operation, make sure that there is no Page Program operation in progress. Immediately after the Serial NOR Flash receives the Resume instruction, the WEL and WIP bits are set to “1” and the PSB or ESB is cleared to “0”. The program or erase operation will continue until finished ("Figure 35. Resume to Read Latency") or until another Suspend instruction is received. A resume-to-suspend latency of tPRS or tERS must be observed before issuing another Suspend instruction ("Figure 33. Resume to Suspend Latency"). Please note that the Resume instruction will be ignored if the Serial NOR Flash is in “Performance Enhance Mode”. Make sure the Serial NOR Flash is not in “Performance Enhance Mode” before issuing the Resume instruction. Figure 35. Resume to Read Latency CS# P/N: PM2329 Resume Command tSE / tBE / tPP Read Command 56 Rev. 1.2, July 17, 2017 MX25V1035F 10-31. No Operation (NOP) The "No Operation" command is only able to terminate the Reset Enable (RSTEN) command and will not affect any other command. The SIO[3:1] are don't care. 10-32. Software Reset (Reset-Enable (RSTEN) and Reset (RST)) The Software Reset operation combines two instructions: Reset-Enable (RSTEN) command and Reset (RST) command. It returns the device to a standby mode. All the volatile bits and settings will be cleared then, which makes the device return to the default status as power on. To execute Reset command (RST), the Reset-Enable (RSTEN) command must be executed first to perform the Reset operation. If there is any other command to interrupt after the Reset-Enable command, the Reset-Enable will be invalid. The SIO[3:1] are "don't care". If the Reset command is executed during program or erase operation, the operation will be disabled, the data under processing could be damaged or lost. The reset time is different depending on the last operation. Longer latency time is required to recover from a program operation than from other operations. P/N: PM2329 57 Rev. 1.2, July 17, 2017 MX25V1035F Figure 36. Software Reset Recovery Stand-by Mode 66 CS# 99 tReady2 Mode Note: Refer to "Table 18. AC Characteristics" for tREADY2 data. Figure 37. Reset Sequence tSHSL CS# SCLK Mode 3 Mode 3 Mode 0 Mode 0 Command SIO0 P/N: PM2329 Command 99h 66h 58 Rev. 1.2, July 17, 2017 MX25V1035F 10-33. High Voltage Operation The flash device supports High Voltage Operation. This opeartion allows user can have better performance in following Program/Erase operation. To enable High Voltage Opeartion, WP#/SIO2 need to apply Vhv during whole operation. If the voltage can not sustain in Vhv range, the Program/Erase opeation might be failed. CS# can only go low after tVSL1+tVhv +tVhv2 timing during High Voltage Operation. WP# can only start to go low after whole Erase/Program Operation has been done. To check the operation status, user may check the status of WIP bit. Figure 38. High Voltage Operation Diagram Vcc (min.) Vcc GND GND tVSL1 Vhv (7.5V - 8V) WP# tVhv2 Vcc tVhv2 tVhv(Note 1) CS# Vcc tVhv(Note 2) GND GND Vcc Vcc Standby Mode GND GND Note 1: Please note that the CS# can only go low after tVSL1+tVhv +tVhv2 timing during High Voltage Operation. Note 2: Please note that the WP# can only start to go low after whole Erase/Program Operation has been done. To check the operation status, user may check the status of WIP bit. Note 3: tVhv(min.) = 250ns, tVSL 1(min.) = 800us; tVhv2(min.) = 0ns Note 4: Vhv range is 7.5V(min.) ≤ Vhv ≤ 8V(max.) Note 5: The High Voltage Operation can only work during Vcc(min.) ≤ Vcc ≤ 2.7V P/N: PM2329 59 Rev. 1.2, July 17, 2017 MX25V1035F 10-34. Read SFDP Mode (RDSFDP) The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on CFI. The sequence of issuing RDSFDP instruction is same as FAST_READ: CS# goes low→send RDSFDP instruction (5Ah)→send 3 address bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP operation can use CS# to high at any time during data out. SFDP is a JEDEC Standard, JESD216B. For SFDP register values detail, please contact local Macronix sales channel for Application Note. Figure 39. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI SO 24 BIT ADDRESS 23 22 21 5Ah 3 2 1 0 High-Z CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Cycle SI 7 6 5 4 3 2 1 0 DATA OUT 2 DATA OUT 1 SO 7 6 5 3 2 1 0 7 MSB MSB P/N: PM2329 4 60 6 5 4 3 2 1 0 7 MSB Rev. 1.2, July 17, 2017 MX25V1035F 11. POWER-ON STATE The device is at the following states when power-up: - Standby mode (please note it is not deep power-down mode) - Write Enable Latch (WEL) bit is reset The device must not be selected during power-up and power-down stage until the VCC reaches the following levels: - VCC minimum at power-up stage and then after a delay of tVSL - GND at power-down Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level. An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change during power up state. When VCC is lower than VWI (POR threshold voltage value), the internal logic is reset and the flash device has no response to any command. For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The write, erase, and program command should be sent after the below time delay: - tVSL after VCC reached VCC minimum level The device can accept read command after VCC reached VCC minimum and a time delay of tVSL. Please refer to the "Figure 47. Power-up Timing". Note: - To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended. (generally around 0.1uF) - At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response to any command. The data corruption might occur during this stage if a write, program, erase cycle is in progress. P/N: PM2329 61 Rev. 1.2, July 17, 2017 MX25V1035F 12. ELECTRICAL SPECIFICATIONS Table 15. Absolute Maximum Ratings Rating Value Ambient Operating Temperature Industrial grade -40°C to 85°C Storage Temperature -65°C to 150°C Applied Input Voltage -0.5V to VCC+0.5V Applied Output Voltage -0.5V to VCC+0.5V VCC to Ground Potential -0.5V to 4.0V NOTICE: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. 2. Specifications contained within the following tables are subject to change. 3. During voltage transitions, all pins may overshoot to VCC+1.0V or -1.0V for period up to 20ns. Figure 41. Maximum Positive Overshoot Waveform Figure 40. Maximum Negative Overshoot Waveform 20ns 0V VCC+1.0V -1.0V VCC 20ns Table 16. Capacitance TA = 25°C, f = 1.0 MHz Symbol Parameter CIN COUT P/N: PM2329 Min. Typ. Max. Unit Input Capacitance 6 pF VIN = 0V Output Capacitance 8 pF VOUT = 0V 62 Conditions Rev. 1.2, July 17, 2017 MX25V1035F Figure 42. Input Test Waveforms and Measurement Level Input timing reference level 0.8VCC Output timing reference level 0.7VCC AC Measurement Level 0.3VCC 0.2VCC 0.5VCC Note: Input pulse rise and fall time are