MX25V1606FM2I03

MX25V1606F MX25V1606F 2.3V-3.6V, 16M-BIT [x 1/x 2] CMOS MXSMIO® (SERIAL MULTI I/O) FLASH MEMORY Key Features • 2.3V-3.6V for Read, Erase and Program Operations • Multi I/O Support - Single I/O and Dual I/O P/N: PM2728 Macronix Proprietary 1 Rev. 1.0, January 15, 2020 MX25V1606F Contents 1. FEATURES............................................................................................................................................................... 4 2. GENERAL DESCRIPTION...................................................................................................................................... 5 Table 1. Additional Feature...........................................................................................................................5 3. PIN CONFIGURATIONS .......................................................................................................................................... 6 4. PIN DESCRIPTION................................................................................................................................................... 6 5. BLOCK DIAGRAM.................................................................................................................................................... 7 6. DATA PROTECTION................................................................................................................................................. 8 Table 2. Protected Area Sizes......................................................................................................................9 7. MEMORY ORGANIZATION.................................................................................................................................... 10 Table 3. Memory Organization...................................................................................................................10 8. DEVICE OPERATION............................................................................................................................................. 11 9. COMMAND DESCRIPTION.................................................................................................................................... 13 9-1. 9-2. 9-3. 9-4. 9-5. 9-6. 9-7. 9-8. 9-9. 9-10. 9-11. 9-12. 9-13. 9-14. 9-15. 9-16. 9-17. 9-18. 9-19. 9-20. 9-21. 9-22. 9-23. 9-24. P/N: PM2728 Table 4. Command Set...............................................................................................................................13 Write Enable (WREN)............................................................................................................................... 14 Write Disable (WRDI)................................................................................................................................ 15 Read Identification (RDID)........................................................................................................................ 16 Read Electronic Signature (RES)............................................................................................................. 17 Factory Mode Enable (FMEN).................................................................................................................. 18 Read Electronic Manufacturer ID & Device ID (REMS)............................................................................ 19 ID Read..................................................................................................................................................... 20 Table 5. ID Definitions ...............................................................................................................................20 Read Status Register (RDSR).................................................................................................................. 21 Table 6. Status Register.............................................................................................................................23 Write Status Register (WRSR).................................................................................................................. 24 Table 7. Protection Modes..........................................................................................................................25 Read Data Bytes (READ)......................................................................................................................... 28 Read Data Bytes at Higher Speed (FAST_READ)................................................................................... 29 Dual Read Mode (DREAD)....................................................................................................................... 30 Sector Erase (SE)..................................................................................................................................... 31 Block Erase (BE32K)................................................................................................................................ 32 Block Erase (BE)...................................................................................................................................... 33 Chip Erase (CE)........................................................................................................................................ 34 Page Program (PP).................................................................................................................................. 35 Deep Power-down (DP)............................................................................................................................ 36 Release from Deep Power-down (RDP), Read Electronic Signature (RES)............................................ 37 Read SFDP Mode (RDSFDP)................................................................................................................... 39 Factory Mode Sector Erase...................................................................................................................... 40 Factory Mode 32KB Block Erase.............................................................................................................. 41 Factory Mode 64KB Block Erase.............................................................................................................. 42 Factory Mode Chip Erase......................................................................................................................... 43 Macronix Proprietary 2 Rev. 1.0, January 15, 2020 MX25V1606F 10. POWER-ON STATE.............................................................................................................................................. 44 11. ELECTRICAL SPECIFICATIONS......................................................................................................................... 45 Table 8. Absolute Maximum Ratings..........................................................................................................45 Table 9. Capacitance..................................................................................................................................45 Table 10. DC Characteristics......................................................................................................................47 Table 11. AC Characteristics .....................................................................................................................48 12. OPERATING CONDITIONS.................................................................................................................................. 50 Table 12. Power-Up/Down Voltage and Timing..........................................................................................52 12-1. Initial Delivery State.................................................................................................................................. 52 13. ERASE AND PROGRAMMING PERFORMANCE............................................................................................... 53 14. ERASE AND PROGRAMMING PERFORMANCE (Factory Mode).................................................................... 53 15. LATCH-UP CHARACTERISTICS......................................................................................................................... 54 16. ORDERING INFORMATION................................................................................................................................. 55 17. PART NAME DESCRIPTION................................................................................................................................ 56 18. PACKAGE INFORMATION................................................................................................................................... 57 18-1. 8-pin SOP (150mil)................................................................................................................................... 57 18-2. 8-pin SOP (200mil)................................................................................................................................... 58 18-3. 8-land WSON (6x5mm)............................................................................................................................ 59 19. REVISION HISTORY ............................................................................................................................................ 60 P/N: PM2728 Macronix Proprietary 3 Rev. 1.0, January 15, 2020 MX25V1606F 1. FEATURES 2.3V-3.6V 16M-BIT [x 1/x 2/x 4] CMOS MXSMIO® (SERIAL MULTI I/O) FLASH MEMORY GENERAL • Supports Serial Peripheral Interface -- Mode 0 and Mode 3 • 16,777,216 x 1 bit structure or 8,388,608 x 2 bits (two I/O mode) structure • Equal Sectors with 4K byte each, Equal Blocks with 32K byte each, or Equal Blocks with 64K byte each - Any Block can be erased individually • Single Power Supply Operation - Operation Voltage: 2.3V-3.6V for Read, Erase and Program Operations • Latch-up protected to 100mA from -1V to Vcc +1V • Status Register Feature • Electronic Identification - JEDEC 1-byte manufacturer ID and 2-byte device ID - RES command for 1-byte Device ID - REMS command for 1-byte manufacturer ID and 1-byte device ID • Support Serial Flash Discoverable Parameters (SFDP) mode HARDWARE FEATURES • SCLK Input - Serial clock input • SI/SIO0 - Serial Data Input or Serial Data Input/Output for 2 x I/O read mode • SO/SIO1 - Serial Data Output or Serial Data Input/Output for 2 x I/O read mode • WP# - Hardware write protection • PACKAGE - 8-pin SOP (150mil) - 8-pin SOP (200mil) - 8-land WSON (6x5mm) - All devices are RoHS Compliant and Halogenfree PERFORMANCE • High Performance - Fast read (2.7V-3.6V) - 1 I/O: 104MHz with 8 dummy cycles - 1I/2O: 104MHz with 8 dummy cycles, equivalent to 208MHz - Fast program and erase time • Low Power Consumption • Typical 100,000 erase/program cycles • 20 years data retention SOFTWARE FEATURES • Input Data Format - 1-byte Command code • Advanced Security Features - Block lock protection The BP0-BP3 status bit defines the size of the area to be software protection against program and erase instructions • Auto Erase and Auto Program Algorithm - Automatically erases and verifies data at selected sector or block - Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (Any page to be programed should have page in the erased state first) P/N: PM2728 Macronix Proprietary 4 Rev. 1.0, January 15, 2020 MX25V1606F 2. GENERAL DESCRIPTION MX25V1606F is 16Mb bits Serial NOR Flash memory, which is configured as 2,097,152 x 8 internally. MX25V1606F features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single I/O mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input. When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and data output. The MX25V1606F MXSMIO® (Serial Multi I/O) provides sequential read operation on the whole chip. After program/erase command is issued, auto program/erase algorithms which program/erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256 bytes) basis, or word basis. Erase command is executed on 4K-byte sector, or 32KB block (32K-byte), or 64K-byte block, or whole chip basis. To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. Advanced security features enhance the protection and security functions, please see security features section for more details. The MX25V1606F utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after typical 100,000 program and erase cycles. Table 1. Additional Feature Protection and Security MX25V1606F Flexible Block Protection (BP0-BP3) V Fast Read Performance I/O 1 I/O 1I/2O Dummy Cycle 8 8 Voltage Range 2.3V-2.7V 2.7V-3.6V 2.3V-2.7V 2.7V-3.6V Frequency 50MHz 104MHz 50MHz 104MHz P/N: PM2728 Macronix Proprietary 5 Rev. 1.0, January 15, 2020 MX25V1606F 3. PIN CONFIGURATIONS 4. PIN DESCRIPTION SYMBOL CS# 8-PIN SOP (150mil) / 8-PIN SOP (200mil) CS# SO/SIO1 WP# GND 1 2 3 4 8 7 6 5 VCC NC SCLK SI/SIO0 SI/SIO0 SO/SIO1 SCLK WP# VCC GND NC 8-LAND WSON (6x5mm) CS# SO/SIO1 WP# GND P/N: PM2728 1 2 3 4 8 7 6 5 VCC NC SCLK SI/SIO0 DESCRIPTION Chip Select Serial Data Input (for 1 x I/O)/ Serial Data Input & Output (for 2xI/O read mode) Serial Data Output (for 1 x I/O)/ Serial Data Input & Output (for 2xI/O read mode) Clock Input Write Protection Active Low Power Supply Ground No Connection Note: The pin of WP# will remain internal pull up function while this pin is not physically connected in system configuration. However, the internal pull up function will be disabled if the system has physical connection to WP# pin. Macronix Proprietary 6 Rev. 1.0, January 15, 2020 MX25V1606F 5. BLOCK DIAGRAM X-Decoder Address Generator Memory Array Y-Decoder SI/SIO0 SO/SIO1 Data Register WP# Mode Logic SCLK Sense Amplifier SRAM Buffer CS# State Machine HV Generator Clock Generator Output Buffer P/N: PM2728 Macronix Proprietary 7 Rev. 1.0, January 15, 2020 MX25V1606F 6. DATA PROTECTION During power transition, there may be some false system level signals which result in inadvertent erasure or programming. The device is designed to protect itself from these accidental write cycles. The state machine will be reset as standby mode automatically during power up. In addition, the control register architecture of the device constrains that the memory contents can only be changed after specific command sequences have completed successfully. In the following, there are several features to protect the system from the accidental write cycles during VCC powerup and power-down or from system noise. • Power-on reset: to avoid sudden power switch by system power supply transition, the power-on reset may protect the Flash. • Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary. • Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before issuing other commands to change data. • Deep Power Down Mode: By entering deep power down mode, the flash device is under protected from writing all commands except toggling the CS#. For more detail please see "9-18. Deep Power-down (DP)". • Advanced Security Features: there are some protection and security features which protect content from inadvertent write and hostile access. I. Block lock protection - The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected as read only. The protected area definition is shown as "Table 2. Protected Area Sizes", the protected areas are more flexible which may protect various area by setting value of BP0-BP3 bits. - The Hardware Protected Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and Status Register Write Protect (SRWD) bit. If the system goes into four I/O mode, the feature of HPM will be disabled. P/N: PM2728 Macronix Proprietary 8 Rev. 1.0, January 15, 2020 MX25V1606F Table 2. Protected Area Sizes Protected Area Sizes Status bit BP3 BP2 BP1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 BP0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Protect Level 16Mb 0 (none) 1 (1block, block 31st) 2 (2blocks, block 30th-31st) 3 (4blocks, block 28th-31st) 4 (8blocks, block 24th-31st) 5 (16blocks, block 16th-31st) 6 (32blocks, protect all) 7 (32blocks, protect all) 8 (32blocks, protect all) 9 (32blocks, protect all) 10 (16blocks, 0th-15th) 11 (24blocks, 0th-23rd) 12 (28blocks, 0th-27th) 13 (30blocks, 0th-29th) 14 (31blocks, 0th-30th) 15 (32blocks, protect all) Note: The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP3, BP2, BP1, BP0) are 0. P/N: PM2728 Macronix Proprietary 9 Rev. 1.0, January 15, 2020 MX25V1606F 7. MEMORY ORGANIZATION Table 3. Memory Organization … 1F7FFFh 1F0FFFh 1EF000h 1EFFFFh 1E8FFFh 487 1E7000h 1E7FFFh 1E0000h 1E0FFFh 479 1DF000h 1DFFFFh 29 472 1D8000h 1D8FFFh 471 1D7000h 1D7FFFh … 58 … 480 … 59 … 1E8000h … 60 488 1D0000h 1D0FFFh 02F000h 02FFFFh … 39 027000h 027FFFh 020FFFh 01F000h 01FFFFh 017FFFh 010000h 010FFFh 15 00F000h 00FFFFh 008000h 008FFFh 7 007000h 007FFFh … 0 8 0 P/N: PM2728 Macronix Proprietary 10 000000h … 0 … 16 … 1 … 018FFFh 017000h … 018000h 23 … 2 24 … 1 … 020000h 31 … 32 … 3 … 028FFFh … 028000h … 4 40 … 2 … 47 5 … ∼ 464 … 30 … 1F0000h 495 … 496 … 61 … 1F8FFFh 1F7000h … 1F8000h 503 … 62 1FFFFFh 504 … 31 … 63 Address Range 1FF000h … 511 … Sector (4K-byte) … Block(64K-byte) Block(32K-byte) 000FFFh Rev. 1.0, January 15, 2020 MX25V1606F 8. DEVICE OPERATION 1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation. 2. When incorrect command is inputted to this device, it enters standby mode and remains in standby mode until next CS# falling edge. In standby mode, SO pin of the device is High-Z. 3. When correct command is inputted to this device, it enters active mode and remains in active mode until next CS# rising edge. 4. Input data is latched on the rising edge of Serial Clock (SCLK) and data shifts out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as "Figure 1. Serial Modes Supported". 5. For the following instructions: RDID, RDSR, READ, FAST_READ, DREAD, RDSFDP, RES, REMS, the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE32K, BE, CE, PP, DP the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. While a Write Status Register, Program or Erase operation is in progress, access to the memory array is neglected and will not affect the current operation of Write Status Register, Program, Erase. Figure 1. Serial Modes Supported CPOL CPHA shift in (Serial mode 0) 0 0 SCLK (Serial mode 3) 1 1 SCLK SI shift out MSB SO MSB Note: CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is supported. P/N: PM2728 Macronix Proprietary 11 Rev. 1.0, January 15, 2020 MX25V1606F Figure 2. Serial Input Timing tSHSL CS# tCHSL tSLCH tCHSH tSHCH SCLK tDVCH tCHCL tCHDX tCLCH LSB MSB SI High-Z SO Figure 3. Output Timing CS# tCH SCLK tCLQV tCLQX tCL tCLQV tCLQX LSB SO SI P/N: PM2728 tSHQZ ADDR.LSB IN Macronix Proprietary 12 Rev. 1.0, January 15, 2020 MX25V1606F 9. COMMAND DESCRIPTION Table 4. Command Set Command Address Byte Command Code Total ADD Byte Byte 1 Byte 2 Byte 3 Dummy Cycle Data Byte 03 (hex) 3 ADD1 ADD2 ADD3 0 1- ∞ 0B (hex) 3 ADD1 ADD2 ADD3 8* 1- ∞ 3B (hex) 3 ADD1 ADD2 ADD3 8* 1- ∞ 02 (hex) 3 ADD1 ADD2 ADD3 0 1-256 20 (hex) 3 ADD1 ADD2 ADD3 0 0 52 (hex) 3 ADD1 ADD2 ADD3 0 0 D8 (hex) 3 ADD1 ADD2 ADD3 0 0 60 or C7 (hex) 0 0 0 5A (hex) 3 8 1- ∞ 06 (hex) 0 0 0 04 (hex) 0 0 0 B9 (hex) 0 0 0 41 (hex) 0 0 0 9F (hex) 0 0 3 AB (hex) 0 0 1 AB (hex) 0 0 0 90 (hex) 1 0 2 05 (hex) 0 0 1 01 (hex) 0 0 1 Array access READ (normal read) FAST READ (fast read data) DREAD (1I 2O read) PP (page program) SE (sector erase) BE 32K (block erase 32KB) BE (block erase 64KB) CE (chip erase) RDSFDP (Read SFDP) ADD1 ADD2 ADD3 Device operation WREN (write enable) WRDI (write disable) DP (Deep power down) FMEN (factory mode enable) Register Access RDID (read identification) RES (read electronic ID) RES (release from deep power down) REMS (read electronic manufacturer & device ID) RDSR (read status register) WRSR (write status register) Dummy Dummy Dummy Dummy Dummy ADD Note1 Note 1: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first. Note 2: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden mode. P/N: PM2728 Macronix Proprietary 13 Rev. 1.0, January 15, 2020 MX25V1606F 9-1. Write Enable (WREN) The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP, SE, BE32K, BE, CE, and WRSR, which are intended to change the device content WEL bit should be set every time after the WREN instruction setting the WEL bit. The sequence of issuing WREN instruction is: CS# goes low→sending WREN instruction code→ CS# goes high. The SIO[3:1] are "don't care" . Figure 4. Write Enable (WREN) Sequence CS# Mode 3 0 1 2 3 4 5 6 7 SCLK Mode 0 Command SI SO P/N: PM2728 06h High-Z Macronix Proprietary 14 Rev. 1.0, January 15, 2020 MX25V1606F 9-2. Write Disable (WRDI) The Write Disable (WRDI) instruction is to reset Write Enable Latch (WEL) bit. The sequence of issuing WRDI instruction is: CS# goes low→sending WRDI instruction code→CS# goes high. The SIO[3:1] are "don't care". The WEL bit is reset by following situations: - Power-up - Completion of Write Disable (WRDI) instruction - Completion of Write Status Register (WRSR) instruction - Completion of Page Program (PP) instruction - Completion of Sector Erase (SE) instruction - Completion of Block Erase 32KB (BE32K) instruction - Completion of Block Erase (BE) instruction - Completion of Chip Erase (CE) instruction Figure 5. Write Disable (WRDI) Sequence CS# Mode 3 0 1 2 3 4 5 6 7 SCLK Mode 0 Command SI SO P/N: PM2728 04h High-Z Macronix Proprietary 15 Rev. 1.0, January 15, 2020 MX25V1606F 9-3. Read Identification (RDID) The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Macronix Manufacturer ID and Device ID are listed as "Table 5. ID Definitions". The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code→24-bits ID data out on SO→ to end RDID operation can drive CS# to high at any time during data out. While Program/Erase operation is in progress, it will not decode the RDID instruction, therefore there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage. Figure 6. Read Identification (RDID) Sequence CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31 SCLK Mode 0 Command SI 9Fh Manufacturer Identification SO High-Z 7 6 5 3 2 1 MSB P/N: PM2728 Device Identification 0 15 14 13 3 2 1 0 MSB Macronix Proprietary 16 Rev. 1.0, January 15, 2020 MX25V1606F 9-4. Read Electronic Signature (RES) RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as "Table 5. ID Definitions". This is not the same as RDID instruction. It is not recommended to use for new design. For new design, please use RDID instruction. The SIO[3:1] are "don't care". The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. Figure 7. Read Electronic Signature (RES) Sequence CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 SCLK Mode 0 Command SI ABh 3 Dummy Bytes 23 22 21 3 2 1 0 MSB SO Electronic Signature Out High-Z 7 6 5 4 3 2 1 0 MSB P/N: PM2728 Macronix Proprietary 17 Rev. 1.0, January 15, 2020 MX25V1606F 9-5. Factory Mode Enable (FMEN) The Factory Mode Enable (FMEN) instruction is for enhance Program and Erase performance for increase factory production throughput. The FMEN instruction need to combine with the instructions which are intended to change the device content, like SE, BE32K, BE, and CE. The sequence of issuing FMEN instruction is: CS# goes low→sending FMEN instruction code→ CS# goes high. A valid factory mode operation need to included three sequences: WREN instruction → FMEN instruction→ Erase instruction. The FMEN is reset by following situations - Power-up - SE command completion - BE32K command completion - BE command completion - CE command completion - PGM command completion Figure 8. Factory Mode Enable (FMEN) Sequence CS# Mode 3 0 1 2 3 4 5 6 7 SCLK Mode 0 Command SI SO P/N: PM2728 41h High-Z Macronix Proprietary 18 Rev. 1.0, January 15, 2020 MX25V1606F 9-6. Read Electronic Manufacturer ID & Device ID (REMS) The REMS instruction returns both the JEDEC assigned manufacturer ID and the device ID. The Device ID values are listed in "Table 5. ID Definitions". The REMS instruction is initiated by driving the CS# pin low and sending the instruction code "90h" followed by two dummy bytes and one address byte (A7-A0). After which the manufacturer ID for Macronix (C2h) and the device ID are shifted out on the falling edge of SCLK with the most significant bit (MSB) first. If the address byte is 00h, the manufacturer ID will be output first, followed by the device ID. If the address byte is 01h, then the device ID will be output first, followed by the manufacturer ID. While CS# is low, the manufacturer and device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high. Figure 9. Read Electronic Manufacturer & Device ID (REMS) Sequence CS# SCLK Mode 3 0 1 2 Mode 0 3 4 5 6 7 8 Command SI 9 10 2 Dummy Bytes 15 14 13 90h 3 2 1 0 High-Z SO CS# 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK ADD (1) SI 7 6 5 4 3 2 1 0 Manufacturer ID SO 7 6 5 4 3 2 1 Device ID 0 7 6 5 4 3 2 MSB MSB 1 0 7 MSB Notes: (1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first. P/N: PM2728 Macronix Proprietary 19 Rev. 1.0, January 15, 2020 MX25V1606F 9-7. ID Read User can execute this ID Read instruction to identify the Device ID and Manufacturer ID. The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code→24-bits ID data out on SO→ to end RDID operation can drive CS# to high at any time during data out. After the command cycle, the device will immediately output data on the falling edge of SCLK. The manufacturer ID, memory type, and device ID data byte will be output continuously, until the CS# goes high. While Program/Erase operation is in progress, it will not decode the RDID instruction, therefore there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage. Table 5. ID Definitions Command Type RDID MX25V1606F Manufacturer ID C2 RES REMS P/N: PM2728 Manufacturer ID C2 Memory type 20 Electronic ID 14 Device ID 14 Memory density 15 Macronix Proprietary 20 Rev. 1.0, January 15, 2020 MX25V1606F 9-8. Read Status Register (RDSR) The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in program/erase/write status register condition). It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in progress. The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register data out on SO. The SIO[3:1] are "don't care". Figure 10. Read Status Register (RDSR) Sequence CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK Mode 0 command 05h SI SO High-Z Status Register Out 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 MSB MSB P/N: PM2728 Status Register Out Macronix Proprietary 21 Rev. 1.0, January 15, 2020 MX25V1606F For user to check if Program/Erase operation is finished or not, RDSR instruction flow are shown as follows: Figure 11. Program/Erase flow with read array data start WREN command RDSR command* WEL=1? No Yes Program/erase command Write program data/address (Write erase address) RDSR command WIP=0? No Yes RDSR command Read WEL=0, BP[3:0], QE, and SRWD data Read array data (same address of PGM/ERS) Verify OK? No Yes Program/erase successfully Program/erase another block? Program/erase fail Yes * Issue RDSR to check BP[3:0]. No Program/erase completed P/N: PM2728 Macronix Proprietary 22 Rev. 1.0, January 15, 2020 MX25V1606F Status Register The definition of the status register bits is as below: WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. The program/erase command will be ignored if it is applied to a protected memory area. To ensure both WIP bit & WEL bit are both set to 0 and available for next program/erase/operations, WIP bit needs to be confirm to be 0 before polling WEL bit. After WIP bit confirmed, WEL bit needs to be confirmed as 0. BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area (as defined in "Table 2. Protected Area Sizes") of the device to against the program/erase instruction without hardware protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE/BE32K) and Chip Erase (CE) instructions (only if Block Protect bits (BP3:BP0) set to 0, the CE instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as default, which is un-protected. SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection (WP#/SIO2) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are read only. The SRWD bit defaults to be "0". Table 6. Status Register bit7 bit6 SRWD (status register write protect) Reserved bit5 BP3 (level of protected block) bit4 BP2 (level of protected block) bit3 BP1 (level of protected block) 1=status register write disabled Reserved (note 1) (note 1) (note 1) 0=status register write enabled Non-volatile Non-volatile Non-volatile Non-volatile Non-volatile bit bit bit bit bit Note 1: Please refer to the "Table 2. Protected Area Sizes". P/N: PM2728 Macronix Proprietary 23 bit2 BP0 (level of protected block) (note 1) Non-volatile bit bit1 bit0 WEL WIP (write enable (write in latch) progress bit) 1=write 1=write enable operation 0=not write 0=not in write enable operation volatile bit volatile bit Rev. 1.0, January 15, 2020 MX25V1606F 9-9. Write Status Register (WRSR) The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1, BP0) bits to define the protected area of memory (as shown in "Table 2. Protected Area Sizes"). The WRSR also can set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#) pin signal, but has no effect on bit1(WEL) and bit0 (WIP) of the status register. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered. The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register data on SI→CS# goes high. The CS# must go high exactly at the 8 bits or 16 bits data boundary; otherwise, the instruction will be rejected and not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset. For more detail please check "Table 11. AC Characteristics". Figure 12. Write Status Register (WRSR) Sequence CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCLK Mode 0 SI SO P/N: PM2728 command 01h High-Z Status Register In 7 6 5 4 3 2 Status Register In 1 0 15 14 13 12 11 10 9 8 MSB Macronix Proprietary 24 Rev. 1.0, January 15, 2020 MX25V1606F Software Protected Mode (SPM): - When SRWD bit=0, no matter WP# is low or high, the WREN instruction may set the WEL bit and can change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM). - When SRWD bit=1 and WP# is high, the WREN instruction may set the WEL bit can change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM) Note: If SRWD bit=1 but WP#/SIO2 is low, it is impossible to write the Status Register even if the WEL bit has previously been set. It is rejected to write the Status Register and not be executed. Hardware Protected Mode (HPM): - When SRWD bit=1, and then WP# is low (or WP# is low before SRWD bit=1), it enters the hardware protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2, BP1, BP0 and hardware protected mode by the WP# to against data modification. Note: To exit the hardware protected mode requires WP# driving high once the hardware protected mode is entered. If the WP# pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via BP3, BP2, BP1, BP0. Table 7. Protection Modes Mode Software protection mode (SPM) Hardware protection mode (HPM) Status register condition WP# and SRWD bit status Memory Status register can be written in (WEL bit is set to "1") and the SRWD, BP0-BP3 bits can be changed WP#=1 and SRWD bit=0, or WP#=0 and SRWD bit=0, or WP#=1 and SRWD=1 The protected area cannot be program or erase. The SRWD, BP0-BP3 of status register bits cannot be changed WP#=0, SRWD bit=1 The protected area cannot be program or erase. Note: 1. As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in "Table 2. Protected Area Sizes". P/N: PM2728 Macronix Proprietary 25 Rev. 1.0, January 15, 2020 MX25V1606F Figure 13. WRSR flow start WREN command RDSR command No WEL=1? Yes WRSR command Write status register data RDSR command No WIP=0? Yes RDSR command Read WEL=0, BP[3:0], QE, and SRWD data No Verify OK? Yes WRSR successfully P/N: PM2728 WRSR fail Macronix Proprietary 26 Rev. 1.0, January 15, 2020 MX25V1606F Figure 14. WP# Setup Timing and Hold Timing during WRSR when SRWD=1 WP# tSHWL tWHSL CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK 01h SI SO High-Z Note: WP# must be kept high until the embedded operation finish. P/N: PM2728 Macronix Proprietary 27 Rev. 1.0, January 15, 2020 MX25V1606F 9-10. Read Data Bytes (READ) The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing READ instruction is: CS# goes low→sending READ instruction code→ 3-byte address on SI→ data out on SO→to end READ operation can use CS# to high at any time during data out. Figure 15. Read Data Bytes (READ) Sequence CS# Mode 3 0 1 2 3 4 5 6 7 8 28 29 30 31 32 33 34 35 36 37 38 39 9 10 SCLK Mode 0 SI command 03h 24-Bit Address 23 22 21 3 2 1 0 MSB SO Data Out 1 High-Z 7 6 5 4 3 2 Data Out 2 1 0 7 MSB P/N: PM2728 Macronix Proprietary 28 Rev. 1.0, January 15, 2020 MX25V1606F 9-11. Read Data Bytes at Higher Speed (FAST_READ) The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ instruction code→ 3-byte address on SI→1-dummy byte (default) address on SI→ data out on SO→ to end FAST_READ operation can use CS# to high at any time during data out. While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. Figure 16. Read at Higher Speed (FAST_READ) Sequence CS# SCLK Mode 3 0 1 2 Mode 0 3 5 6 7 8 9 10 Command SI SO 4 28 29 30 31 24-Bit Address 23 22 21 0Bh 3 2 1 0 High-Z CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Cycle SI 7 6 5 4 3 2 1 0 DATA OUT 2 DATA OUT 1 SO 7 6 5 4 3 2 1 7 MSB MSB P/N: PM2728 0 Macronix Proprietary 29 6 5 4 3 2 1 0 7 MSB Rev. 1.0, January 15, 2020 MX25V1606F 9-12. Dual Read Mode (DREAD) The DREAD instruction enable double throughput of Serial NOR Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruction, the following data out will perform as 2-bit instead of previous 1-bit. The sequence of issuing DREAD instruction is: CS# goes low → sending DREAD instruction → 3-byte address on SI → 8-bit dummy cycle → data out interleave on SIO1 & SIO0 → to end DREAD operation can use CS# to high at any time during data out. While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. Figure 17. Dual Read Mode Sequence (Command 3Bh) CS# 0 1 2 3 4 5 6 7 8 … Command SI/SIO0 SO/SIO1 P/N: PM2728 30 31 32 9 SCLK 3B … 24 ADD Cycle A23 A22 … 39 40 41 42 43 44 45 8 dummy cycle A1 A0 High Impedance Data Out 1 Data Out 2 D6 D4 D2 D0 D6 D4 D7 D5 D3 D1 D7 D5 Macronix Proprietary 30 Rev. 1.0, January 15, 2020 MX25V1606F 9-13. Sector Erase (SE) The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector (see "Table 3. Memory Organization") is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. Address bits [Am-A12] (Am is the most significant address) select the sector address. The sequence of issuing SE instruction is: CS# goes low→ sending SE instruction code→ 3-byte address on SI→ CS# goes high. The SIO[3:1] are "don't care". The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked during the Sector Erase cycle is in progress. The WIP sets 1 during the tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the sector is protected by BP3, BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the sector. Figure 18. Sector Erase (SE) Sequence CS# Mode 3 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK Mode 0 SI 24-Bit Address Command 23 22 20h 2 1 0 MSB P/N: PM2728 Macronix Proprietary 31 Rev. 1.0, January 15, 2020 MX25V1606F 9-14. Block Erase (BE32K) The Block Erase (BE32K) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 32K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE32K). Any address of the block (see "Table 3. Memory Organization") is a valid address for Block Erase (BE32K) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of address byte has been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing BE32K instruction is: CS# goes low → sending BE32K instruction code → 3-byte address on SI → CS# goes high. The SIO[3:1] are don't care. The self-timed Block Erase Cycle time (tBE32K) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets during the tBE32K timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the block is protected by BP3-0, the array data will be protected (no change) and the WEL bit still be reset. Figure 19. Block Erase 32KB (BE32K) Sequence (Command 52) CS# 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK Command SI 24 Bit Address 23 22 52h 2 1 0 MSB P/N: PM2728 Macronix Proprietary 32 Rev. 1.0, January 15, 2020 MX25V1606F 9-15. Block Erase (BE) The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 64K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (Please refer to "Table 3. Memory Organization") is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing BE instruction is: CS# goes low→ sending BE instruction code→ 3-byte address on SI→ CS# goes high. The SIO[3:1] are "don't care". The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked during the Block Erase cycle is in progress. The WIP sets 1 during the tBE timing, and sets 0 when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the block is protected by BP3, BP2, BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the block. Figure 20. Block Erase (BE) Sequence CS# Mode 3 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK Mode 0 SI Command 24-Bit Address 23 22 D8h 2 1 0 MSB P/N: PM2728 Macronix Proprietary 33 Rev. 1.0, January 15, 2020 MX25V1606F 9-16. Chip Erase (CE) The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not executed. The sequence of issuing CE instruction is: CS# goes low→sending CE instruction code→CS# goes high. The SIO[3:1] are "don't care". The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is protected by BP3, BP2, BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when BP3, BP2, BP1, BP0 all set to "0". Figure 21. Chip Erase (CE) Sequence CS# Mode 3 0 1 2 3 4 5 6 7 SCLK Mode 0 SI P/N: PM2728 Command 60h or C7h Macronix Proprietary 34 Rev. 1.0, January 15, 2020 MX25V1606F 9-17. Page Program (PP) The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device programs only the last 256 data bytes sent to the device. The last address byte (the 8 least significant address bits, A7-A0) should be set to 0 for 256 bytes page program. If A7-A0 are not all zero, transmitted data that exceed page length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently selected page. If the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the request page and previous data will be disregarded. If the data bytes sent to the device has not exceeded 256, the data will be programmed at the request address of the page. There will be no effort on the other data bytes of the same page. The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→ at least 1-byte on data on SI→ CS# goes high. The CS# must be kept low during the whole Page Program cycle; The CS# must go high exactly at the byte boundary (the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed. The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked during the Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP3, BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed. The SIO[3:1] are "don't care". Figure 22. Page Program (PP) Sequence CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK 1 0 7 6 5 3 2 1 0 2079 2 2078 3 2077 23 22 21 02h SI Data Byte 1 24-Bit Address 2076 Command 2075 Mode 0 4 1 0 MSB MSB 2074 2073 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2072 CS# SCLK Data Byte 2 SI 7 6 MSB P/N: PM2728 5 4 3 2 Data Byte 3 1 0 7 6 5 4 3 2 Data Byte 256 1 MSB 0 7 6 5 4 3 2 MSB Macronix Proprietary 35 Rev. 1.0, January 15, 2020 MX25V1606F 9-18. Deep Power-down (DP) The Deep Power-down (DP) instruction places the device into a minimum power consumption state, Deep Powerdown mode, in which the quiescent current is reduced from ISB1 to ISB2. The sequence of issuing DP instruction: CS# goes low→ send DP instruction code→ CS# goes high. The CS# must go high at the byte boundary (after exactly eighth bits of the instruction code have been latched-in); otherwise the instruction will not be executed. SIO[3:1] are "don't care". After CS# goes high there is a delay of tDP before the device transitions from Stand-by mode to Deep Powerdown mode and before the current reduces from ISB1 to ISB2. Once in Deep Power-down mode, all instructions will be ignored except Release from Deep Power-down (RDP). The device exits Deep Power-down mode and returns to Stand-by mode if it receives a Release from Deep Power-down (RDP) instruction, power-cycle. Please refer to "Figure 25. Release from Deep Power-down (RDP) Sequence". Figure 23. Deep Power-down (DP) Sequence CS# 0 1 2 3 4 5 6 tDP 7 SCLK Command SI B9h Stand-by Mode P/N: PM2728 Macronix Proprietary 36 Deep Power-down Mode Rev. 1.0, January 15, 2020 MX25V1606F 9-19. Release from Deep Power-down (RDP), Read Electronic Signature (RES) The Release from Deep Power-down (RDP) instruction is completed by driving Chip Select (CS#) High. When Chip Select (CS#) is driven High, the device is put in the standby Power mode. If the device was not previously in the Deep Power-down mode, the transition to the standby Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the standby Power mode is delayed by tRES1, and Chip Select (CS#) must remain High for at least tRES1(max). Once in the standby mode, the device waits to be selected, so that it can receive, decode and execute instructions. RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as "Table 5. ID Definitions". This is not the same as RDID instruction. It is not recommended to use for new design. For new design, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device is in progress of program/erase/write cycles; there's no effect on the current program/erase/ write cycles in progress. The SIO[1:0] are don't care when during this mode. The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least tRES2(max). Once in the standby mode, the device waits to be selected, so it can receive, decode, and execute instruction. The RDP instruction is for releasing from Deep Power-down Mode. Figure 24. Read Electronic Signature (RES) Sequence CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 SCLK Command SI ABh tRES2 3 Dummy Bytes 23 22 21 3 2 1 0 MSB SO Electronic Signature Out High-Z 7 6 5 4 3 2 1 0 MSB Deep Power-down Mode P/N: PM2728 Macronix Proprietary 37 Stand-by Mode Rev. 1.0, January 15, 2020 MX25V1606F Figure 25. Release from Deep Power-down (RDP) Sequence CS# Mode 3 0 1 2 3 4 5 6 tRES1 7 SCLK Mode 0 Command SI SO ABh High-Z Deep Power-down Mode P/N: PM2728 Macronix Proprietary 38 Stand-by Mode Rev. 1.0, January 15, 2020 MX25V1606F 9-20. Read SFDP Mode (RDSFDP) The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on CFI. The sequence of issuing RDSFDP instruction is same as FAST_READ: CS# goes low→send RDSFDP instruction (5Ah)→send 3 address bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP operation can use CS# to high at any time during data out. SFDP is a JEDEC Standard, JESD216. For SFDP register values detail, please contact local Macronix sales channel for Application Note. Figure 26. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI SO 24 BIT ADDRESS 23 22 21 5Ah 3 2 1 0 High-Z CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Cycle SI 7 6 5 4 3 2 1 0 DATA OUT 2 DATA OUT 1 SO 7 6 5 4 3 2 P/N: PM2728 1 0 7 MSB MSB Macronix Proprietary 39 6 5 4 3 2 1 0 7 MSB Rev. 1.0, January 15, 2020 MX25V1606F 9-21. Factory Mode Sector Erase To apply Factory Mode Sector Erase, customers need to follow the operation below: Factory Mode Enable (FMEN): The Factory Mode Enable (FMEN) instruction is for enhancing Sector Erase performance, which increase factory production throughput. The FMEN instruction will need to be combined with the SE instruction when user intends to change the device content. A valid factory mode operation need to include three sequences: WREN instruction → FMEN instruction→ Sector Erase instruction. The sequence of issuing FMEN instruction is: CS# goes low→send FMEN instruction code→ CS# goes high. The FMEN will be reset in following situations: Power-up, Sector Erase command completion. Figure 27. Factory Mode Sector Erase Flow Start WREN Command RDSR Command WEL=1? No Yes FMEN Command Sector Erase Command* Factory Mode Sector Erase Completed Note: * Please reference Program/Erase flow chart in datasheet. P/N: PM2728 Macronix Proprietary 40 Rev. 1.0, January 15, 2020 MX25V1606F 9-22. Factory Mode 32KB Block Erase To apply Factory Mode 32KB Block Erase, customers need to follow the operation below: Factory Mode Enable (FMEN): The Factory Mode Enable (FMEN) instruction is for enhancing 32KB Block Erase performance, which increase factory production throughput. The FMEN instruction will need to be combined with the BE32K instruction when user intends to change the device content. A valid factory mode operation need to include three sequences: WREN instruction → FMEN instruction→ BE32K instruction. The sequence of issuing FMEN instruction is: CS# goes low→send FMEN instruction code→ CS# goes high. The FMEN will be reset in following situations: Power-up, BE32K command completion. Figure 28. Factory Mode 32KB Block Erase Flow Start WREN Command RDSR Command WEL=1? No Yes FMEN Command 32KB Block Erase Command* Factory Mode BE32K Completed Note: * Please reference Program/Erase flow chart in datasheet. P/N: PM2728 Macronix Proprietary 41 Rev. 1.0, January 15, 2020 MX25V1606F 9-23. Factory Mode 64KB Block Erase To apply Factory Mode 64KB Block Erase, customers need to follow the operation below: Factory Mode Enable (FMEN): The Factory Mode Enable (FMEN) instruction is for enhancing 64KB Block Erase performance, which increase factory production throughput. The FMEN instruction will need to be combined with the BE instruction when user intends to change the device content. A valid factory mode operation need to include three sequences: WREN instruction → FMEN instruction→ BE instruction. The sequence of issuing FMEN instruction is: CS# goes low→send FMEN instruction code→ CS# goes high. The FMEN will be reset in following situations: Power-up, BE command completion. Figure 29. Factory Mode Block Erase Flow Start WREN Command RDSR Command WEL=1? No Yes FMEN Command 64KB Block Erase Command* Factory Mode BE Completed Note: * Please reference Program/Erase flow chart in datasheet. P/N: PM2728 Macronix Proprietary 42 Rev. 1.0, January 15, 2020 MX25V1606F 9-24. Factory Mode Chip Erase To apply Factory Mode Chip Erase, customers need to follow the operation below: Factory Mode Enable (FMEN): The Factory Mode Enable (FMEN) instruction is for enhancing Chip Erase performance, which increase factory production throughput. The FMEN instruction will need to be combined with the CE instruction when user intends to change the device content. A valid factory mode operation need to include three sequences: WREN instruction → FMEN instruction→ CE instruction. The sequence of issuing FMEN instruction is: CS# goes low→send FMEN instruction code→ CS# goes high. The FMEN will be reset in following situations: Power-up, CE command completion. Figure 30. Factory Mode Chip Erase Flow Start WREN Command RDSR Command WEL=1? No Yes FMEN Command Chip Erase Command* Factory Mode CE Completed Note: * Please reference Program/Erase flow chart in datasheet. P/N: PM2728 Macronix Proprietary 43 Rev. 1.0, January 15, 2020 MX25V1606F 10. POWER-ON STATE The device is at the following states when power-up: - Standby mode (please note it is not deep power-down mode) - Write Enable Latch (WEL) bit is reset The device must not be selected during power-up and power-down stage until the VCC reaches the following levels: - VCC minimum at power-up stage and then after a delay of tVSL - GND at power-down Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level. An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change during power up state. When VCC is lower than VWI (POR threshold voltage value), the internal logic is reset and the flash device has no response to any command. For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The write, erase, and program command should be sent after the below time delay: - tVSL after VCC reached VCC minimum level The device can accept read command after VCC reached VCC minimum and a time delay of tVSL. Please refer to the "Figure 38. Power-up Timing". Note: - To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended. (generally around 0.1uF) - At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response to any command. The data corruption might occur during this stage if a write, program, erase cycle is in progress. P/N: PM2728 Macronix Proprietary 44 Rev. 1.0, January 15, 2020 MX25V1606F 11. ELECTRICAL SPECIFICATIONS Table 8. Absolute Maximum Ratings Rating Value Ambient Operating Temperature Industrial grade -40°C to 85°C Storage Temperature -65°C to 150°C Applied Input Voltage -0.5V to VCC+0.5V Applied Output Voltage -0.5V to VCC+0.5V VCC to Ground Potential -0.5V to 4.0V NOTICE: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. 2. Specifications contained within the following tables are subject to change. 3. During voltage transitions, all pins may overshoot to VCC+1.0V or -1.0V for period up to 20ns. Figure 32. Maximum Positive Overshoot Waveform Figure 31. Maximum Negative Overshoot Waveform 20ns 0V VCC+1.0V -1.0V VCC 20ns Table 9. Capacitance TA = 25°C, f = 1.0 MHz Symbol Parameter CIN COUT P/N: PM2728 Min. Typ. Max. Unit Input Capacitance 6 pF VIN = 0V Output Capacitance 8 pF VOUT = 0V Macronix Proprietary 45 Conditions Rev. 1.0, January 15, 2020 MX25V1606F Figure 33. Data Input Test Waveforms and Measurement Level Input timing reference level 0.8VCC Output timing reference level 0.7VCC AC Measurement Level 0.3VCC 0.2VCC 0.5VCC Note: Input pulse rise and fall time are