MX26C1000BMI-10

ADVANCE INFORMATION MX26C1000B FEATURES 1M-BIT [128K x 8] CMOS MULTIPLE-TIME-PROGRAMMABLE-EPROM • • • • • 50 minimum erase/program cycles Chip erase time: 1 (typ.) Chip program time: 6.25 (typ.) Typical fast programming cycle duration 10us/byte Package type: - 32 pin plastic DIP - 32 pin PLCC - 32 pin TSOP - 32 pin SOP • 128Kx 8 organization • Single +5V power supply • +12V programming voltage • Fast access time:90/100/120/150 ns • Totally static operation • Completely TTL compatible • Operating current:30mA • Standby current: 100uA GENERAL DESCRIPTION The MX26C1000B is a 5V only, 1M-bit, MTP EPROMTM (Multiple Time Programmable Read Only Memory). It is organized as 128K words by 8 bits per word, operates from a single + 5 volt supply, has a static standby mode, and features fast single address location programming. All programming signals are TTL levels, requiring a single pulse. It is design to be programmed and erased by an EPROM programmer or on-board. The MX26C1000B supports a intelligent fast programming algorithm which can result in programming time of less than one minute. This MTP EPROMTM is packaged in industry standard 32 pin dual-in-line packages, 32 lead PLCC, 32 lead SOP and 32 lead TSOP packages. PIN CONFIGURATIONS VCC VPP A12 A15 A16 WE Q1 Q2 GND Q3 Q4 Q5 32 TSOP PIN DESCRIPTION A11 A9 A8 A13 A14 NC WE VCC VPP A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE Q7 Q6 Q5 Q4 Q3 GND Q2 Q1 Q0 A0 A1 A2 A3 SYMBOL A0~A16 Q0~Q7 CE OE WE VPP NC VCC GND PIN NAME Address Input Data Input/Output Chip Enable Input Output Enable Input Write Enable Input Program Supply Voltage No Internal Connection Power Supply Pin (+5V) Ground Pin REV. 0.7, NOV. 20, 2002 MX26C1000B P/N: PM0767 1 Q6 VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE NC A14 A13 A8 A9 A11 OE A10 CE Q7 Q6 Q5 Q4 Q3 A7 A6 A5 A4 A3 A2 A1 A0 Q0 5 4 1 32 30 29 NC 32 PDIP/SOP 32 PLCC A14 A13 A8 A9 MX26C1000B 9 MX26C1000B 25 A11 OE A10 CE 13 14 17 21 20 Q7 MX26C1000B BLOCK DIAGRAM WRITE CE OE WE CONTROL INPUT LOGIC HIGH VOLTAGE PROGRAM/ERASE STATE MACHINE (WSM) X-DECODER MX26C1000B FLASH ARRAY ARRAY STATE REGISTER ADDRESS LATCH A0-A16 AND BUFFER SENSE AMPLIFIER Y-DECODER Y-PASS GATE SOURCE HV COMMAND DATA DECODER PGM DATA HV COMMAND DATA LATCH PROGRAM DATA LATCH Q0-Q7 I/O BUFFER P/N: PM0767 2 REV. 0.7, NOV. 20, 2002 MX26C1000B FUNCTIONAL DESCRIPTION The set-up Program command (40H) is the only command that requires a two sequence reset cycle. The first Reset command is interpreted as program data. How ever, FFH data is considered null data during programming operations (memory cells are only programmed from logica "1" to "0". The second Reset command safely aborts the programming operation and resets the device to the Read mode. This detailed information is for your reference. It may prove esier to always issue the Reset command two consecutive times. This eliminates the need to determine if you are in the set-up Program state or not. When the MX26C1000B is delivered, or it is erased, the chip has all 1000K bits in the "ONE", or HIGH state. "ZEROs" are loaded into the MX26C1000B through the procedure of programming. ERASE ALGORITHM The MX26C1000B do not required preprogramming before an erase operation. The erase algorithm is a close loop flow to simultaneously erase all bits in the entire array. Erase operation starts with the initial erase operation. Erase verification begins at address 0000H by reading data FFH from each byte. If any byte fails to erase. the entire chip is reerased. to a maximum for 30 pulse counts of 100ms duration for each pulse. The maximum cumulative erase time is 3s. However. the device is usually erased in no more than 3 pulses. Erase verification time can be reduced by storing the address of the last byte that failed. Following the next erase operation verification may start at the stored address location. JEDEC standard erase algorithm can also be used. But erase time will increase by performing the unnecessary preprogramming. SET-UP PROGRAM/PROGRAM A three-step sequence of commands is required to perform a complete program operation: Set Up ProgramProgram-Program Verify. The device is bulk erased and byte by byte programming. The command 40H is written to the command register to initiate Set Up Program operation. Address and data to be programmed into the byte are provided on the second WE pulse. Addresses are latched on the falling edge of the WE pulse, data are latched on the rising edge of the WE pulse. Program operation begins on the rising edge of the second WE pulse, and terminate of the next rising edge of the WE pulse. Refer to AC Characteristics and Waveforms for specific timing parameters. PROGRAM ALGORITHM The device is programmed byte by byte. A maximum of 25 pulses. each of 10us duration is allowed for each byte being programmed. The byte may be programmed sequentially or by random. After each program pulse, a program verify is done to determine if the byte has been successfully programmed. Programming then proceeds to the next desired byte location. JEDEC standard program algorithms can be used. COMMAND REGISTER When high voltage is applied to VPP the command register is enabled. Read, write, standby, output disable modes are available. The read, erase, erase verify, program, program verify and Device ID are accessed via the command register. Standard microprocessor write timings are used to input a command to the register. This register serves as the input to an internal state machine which controls the operation mode of the device. An internal latch is used for write cycles, addresses and data for programming and erase operations. RESET The Reset command initializes the MTP EPROMTM device to the Read mode. In addition, it also provides the user with a safe method to abort any device operation (including program or erase). The Reset command must be written two consecutive times after the set-up Program command (40H). This will safely abort any previous operation and initialize the device to the Read mode. NO INTEGRATED STOP TIMER FOR ERASE Leading industry flash technology requires a stop timer built into the flash chip to prevent the memory cells from going into depletion due to over erase. The 1 Mbit MTP P/N: PM0767 3 REV. 0.7, NOV. 20, 2002 MX26C1000B EPROMTM is built on an innovative cell concept in which over erasing the memory cell is impossible. force 12.0 ± 0.5 V on address line A9 of the device. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address lines must be held at VIL during auto identify mode. Byte 0 ( A0 = VIL) represents the manufacturer code, and byte 1 (A0 = VIH), the device identifier code. For the MX26C1000B, these two identifier bytes are given in the Mode Select Table. All identifiers for manufacturer and device codes will possess odd parity, with the MSB (DQ7) defined as the parity bit. DATA WRITE PROTECTION The design of the device protects against accidental erasure or programming. The internal state machine is automatically reset to the read mode on power-up. Using control register architecture, alteration of memory can only occur after completion of proper command sequences. The command register is only active when V is at high voltage. when V PP = V PPL , the device defaults PP to the Read Mode. Robust design features prevent inadvertent write cycles resulting from VCC power-up and power-down transitions or system noise. To avoid initiation of write cycle during VCC power-up, a write cycle is locked out for VCC less than 4V. The two- command program and erase write sequence to the command register provide additional software protection against spurious data changes. READ MODE The MX26C1000B has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the outputs tOE after the falling edge of OE, assuming that CE has been LOW and addresses have been stable for at least tACC - tOE. PROGRAM VERIFY MODE Verification should be performed on the programmed bits to determine that they were correctly programmed. Verification should be performed with OE and CE, at VIL, WE at VIH, and VPP at its programming voltage. STANDBY MODE ERASE VERIFY MODE Verification should be performed on the erased chip to determine that the whole chip(all bits) was correctly erased. Verification should be performed with OE and CE at VIL, WE at VIH, and VCC = 5V, VPP = 12.5V The MX26C1000B has a CMOS standby mode which reduces the maximum VCC current to 100 uA. It is placed in CMOS standby when CE is at VCC ± 0.3 V. The MX26C1000B also has a TTL-standby mode which reduces the maximum VCC current to 1.5 mA. It is placed in TTL-standby when CE is at VIH. When in standby mode, the outputs are in a high-impedance state, independent of the OE input. AUTO IDENTIFY MODE The auto identify mode allows the reading out of a binary code from MTP EPROM that will identify its manufacturer and device type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25° ± 5° ambient temperature C C range that is required when programming the MX26C1000B. To activate this mode, the programming equipment must SYSTEM CONSIDERATIONS During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. At a minimum, a 0.1 uF ceramic capacitor (high frequency, low inherent inductance) should be used on each device between VCC and GND to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive P/N: PM0767 4 REV. 0.7, NOV. 20, 2002 MX26C1000B effects of the printed circuit board traces on EPROM arrays, a 4.7 uF bulk electrolytic capacitor should be used between VCC and GND for each of the eight devices. The location of the capacitor should be close to where the power supply is connected to the array. OUTPUT DISABLE Output is disabled when OE is at logre high. When in output disabled all circuitry is enabled. Except the output pins are in a high impedance state(TRI-ATATE). Table 1: BUS OPERATIONS Mode Read READ-ONLY MODE Output Disable Standby Manufacturer Identification Device Identification Read COMMAND MODE Output Disable Standby(4) Program VPP(1) VPPL VPPL VPPL VPPL VPPL VPPH VPPH VPPH VPPH A0 A0 X X VIL VIH A0 X X A0 A9 A9 X X CE VIL VIL VIH OE VIL VIH X VIL VIL VIL VIH X VIH WE VIH VIH X VIH VIH VIH VIH X VIL Q0~Q7 Data Out Tri-State Tri-State Data=C2H Data=CFH Data Out(3) Tri-State Tri-State Data Inb VID(2) VIL VID(2) VIL A9 X X(5) A9 VIL VIL VIH VIL Note: 1. Refer to DC Characteristics. When VPP=VPPL memory contents can be read but not written or erased. 2. VID is the intelligent identifier high voltage. Refer to DC Characteristics. 3. Read operations with VPP=VPPH may access array data or the intelligent identifier codes. 4. With VPP at high voltage the standby current equals ICC+IPP(standby). 5. Refer to Table 2 for vaild data-in during a write operation. 6. X can be VIL or VIH. P/N: PM0767 5 REV. 0.7, NOV. 20, 2002 MX26C1000B COMMAND MODE The 1 Mbit MTP EPROMTM is in Command mode when high voltage VPPH is applied to the VPP pin. In this state the available functions are Read, Program, Program Verify, Erase and Erase Verify. Reset are selected by writing commands to the input register. Data from the register are input to the state machine. The output from the state machine determines the function of the device. The command register serves as a latch to store data for executing commands. It does not occupy address- able memory location. Standard microprocessor write timing is used. Table 2 defines the register commands. The command register is written by bringing WE to a logic-low Level (V IL), while CE is low. Addresses are latched on the falling edge of WE, while data is latched on the rising edge of the WE pulse. Standby and Output disable functions are the same as in Read Mode, controlled by CE and OE. If the device is deselected during erasure, programming, or erase/ program verification, the device draws active current until the operations terminate. erase operation. The two-step command prevents accidental alteration to memory array. Erase operation starts with the rising edge of the WE pulse and terminates with the rising edge of the next WE pulse, which in this case is the erase verify command. ERASE VERIFY Each erase operation is followed by an erase verify. The command A0H is written into the command register. The address of the bytes to be verified is supplied with the command. The address is latched on the falling edge of the WE pulse. A reading FFH is returned to confirm all bits in the byte are erased. This sequence of Set Up Erase- Erase continues for each address until FFH is returned. This indicates the entire memory array is erased and completes the operation. Erase verify operation starts at address 0000H and ends at the last address. Maximum erase pulse duration for the 1Mbit MTP EPROMTM is 100ms with a maximum 30 pulses. Refer to AC Characteristics and Waveforms for specific timing parameters. READ COMMAND To read memory content, write 00H into the command register while high voltage is applied to V PP pin (VPP = VPPH ). Microprocessor read cycle retrieves the data . The device remains enable for read until the data in the command register are altered. The device is default in read mode when power up. This is to ensure no accidental alteration of the memory occurs during power transition. Refer to AC Read Characteristics and Waveforms for specific timing parameters. SET UP ERASE/ERASE Preprogram operation is not required prior to the erase operation. A sequence of commands is required to perform a complete erase operation: set up erase, erase, and erase verify. High voltage is applied to the V PP pin (VPP=VPPH). The command 20H is written to the command register to initiate the set-up erase mode. ERASE OPERATION The same command, 20H, is again written to the command register. This second command starts bulk P/N: PM0767 REV. 0.7, NOV. 20, 2002 6 MX26C1000B PROGRAMMING ALGORITHM FLOW CHART Start Programming Apply VPPH PLSCNT=0 Write Set-up Program CMD Write Program Cmd(A/D) Time Out 10us Write Program Verify Cmd Time out 6us Read Data From Device NO Verify Data ? NO Inc PLSNT=25 ? YES YES NO Increment Address Last Address ? YES Write Read CMD Apply VPPL Apply VPPL Programming Completed Programming Error P/N: PM0767 7 REV. 0.7, NOV. 20, 2002 MX26C1000B ERASE ALGORITHM FLOW CHART Start Erasure Apply VPPH Address=00H PLSCNT=0 Write Set-up Erase and Erase Cmd Time Out 100ms Write Erase Verify Cmd Time out 6us Read Data From Device NO Data=FFH ? NO Inc PLSNT=30 ? YES YES NO Increment Address Last Address ? YES Write Read CMD Apply VPPL Apply VPPL Erasure Completed Erasure Error P/N: PM0767 8 REV. 0.7, NOV. 20, 2002 MX26C1000B SWITCHING TEST CIRCUITS DEVICE UNDER TEST 1.8K ohm +5V CL 6.2K ohm DIODES = IN3064 OR EQUIVALENT CL = 100 pF including jig capacitance SWITCHING TEST WAVEFORMS 2.0V AC driving levels 2.0V TEST POINTS 0.8V OUTPUT 0.8V INPUT AC TESTING: AC driving levels are 2.4V/0.4V for commercial grade. Input pulse rise and fall times are equal to or less than 10ns. P/N: PM0767 9 REV. 0.7, NOV. 20, 2002 MX26C1000B ABSOLUTE MAXIMUM RATINGS RATING Storage Temperature Applied Input Voltage Applied Output Voltage VCC to Ground Potential A9 & VPP VALUE -65oC to 125oC -0.5V to 7.0V -0.5V to VCC + 0.5V -0.5V to 7.0V -0.5V to 13.5V Ambient Operating Temperature -40oC to 85oC NOTICE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. NOTICE: Specifications contained within the following tables are subject to change. DC/AC OPERATING CONDITION FOR READ OPERATION MX26C1000B -90 Operating Temperature Industrial Vcc Power Supply -40° to 85°C C 5V ± 10% -100 -40°C to 85°C 5V ± 10% -120 -40°C to 85°C 5V ± 10% -150 -40° to 85° C C 5V ± 10% CAPACITANCE TA = 25oC, f = 1.0 MHz (Sampled only) SYMBOL CIN COUT CVPP PARAMETER Input Capacitance Output Capacitance VPP Capacitance TYP. 8 8 18 MAX. 12 12 25 UNIT pF pF pF CONDITIONS VIN = 0V VOUT = 0V VPP = 0V DC CHARACTERISTICS TA = -45°C ~ 85°C, VCC=5V±10% SYMBOL VIL VIH VOL VOH ICC1 ISB ISB IPP IPP2 ILI ILO VCC1 VPP1 PARAMETER Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VCC Active Current VCC Standby Current (CMOS) VCC Standby Current (TTL) VPP Read Current VPP Supply Current (Program/Erase) Input Leakage Current Output Leakage Current Fast Programming Supply Voltage Fast Programming Voltage -10 -10 6.0 12.5 10 10 6.5 13.0 uA uA V V VIN = 0 to 5.5V VOUT = 0 to 5.5V 2.4 30 100 1.5 100 30 MIN. -0.3 2.0 MAX. 0.8 VCC + 0.5 0.4 UNIT CONDITIONS V V V V mA uA mA uA mA IOL = 2.1mA, VCC=VCC MIN IOH = -0.4mA CE = VIL, OE=VIH, f=5MHz CE=VCC+0.2V, VCC=VCC MAX CE=VIH, VCC=VCC MAX CE = OE = VIL, VPP = 5.5V CE=WE=VIL, OE=VIH P/N: PM0767 10 REV. 0.7, NOV. 20, 2002 MX26C1000B AC RAED CHARACTERISTICS OVER OPERATING RANGE WITH VPP=VCC Symbol Jeded STD tAVAV TRC tELQV TCE tAVQV TACC tGLQV TOE tELQX TLZ tEHQZ TDF tGLQX TOLZ tGHQZ TDF tAXQX TOH Read Cycle Time CE Access Time Address Access Time OE Access Time CE to Output in Low Z(Note 1) OE to Output in Low Z (Note 1) Output Disable to Output in High Z (Note 1) Output Hold from Address, CE or OE, change tWHGL TWHGL Write Recovery Time Before Read tVCS TVCS VCC Setup Time to Valid Read (Note 2) 6 50 6 50 6 50 6 50 us us 0 0 0 0 ns Parameter 90 0 0 0 0 30 30 0 0 90 90 40 90 MIN 100 MAX MIN 100 0 0 0 0 0 0 0 35 35 100 100 45 120 MAX MIN 120 0 0 0 0 0 0 0 35 35 120 120 50 150 MAX MIN MAX 150 0 0 0 0 0 0 0 50 50 ns 150 ns 150 ns 65 ns ns ns ns ns Unit Chip Disable to Output in High Z(Note 2) 0 Note: 1. Sampled: not 100% tested. 2. Guaranteed by design. not tested. P/N: PM0767 11 REV. 0.7, NOV. 20, 2002 MX26C1000B AC CHARACTERISTICS - WRITE/ERASE/PROGRAM OPERATIONS Symbol JEDED tAVAV tAVWL tWLAX tDVWH tWHDX tWHGL tGHWL tELWL tWHEH tWLWH tWHWL tWHWH1 tWHWH2 tVPEL tVCS tVPPR tVPPF STD TWC TAS TAH TDS TDH TWR tCS tCH tWP Write Cycle Time (Note 3) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Write Recovery Time Before Read CE Setup Time Before Write CE Hold Time Write Pulse Width Duration of Programming Operation (Note2) Duration of Erase Operation(Note2) VPP Setup Time to Chip Enable Low (Note 3) VCC Setup Time to Chip Enable Low (Note 3) VPP Rise Time (Note 3) 90% VPPH VPP Fall Time (Note 3) 10% VPPH 500 500 500 500 500 500 500 500 ns ns 50 50 50 50 us 100 1 100 1 100 1 100 1 ms us Parameter 90 0 40 40 10 6 0 0 0 50 20 10 90 100 100 0 40 40 10 6 0 0 0 50 20 10 120 120 0 40 40 10 6 0 0 0 50 20 10 150 150 0 40 40 10 6 0 0 0 50 20 10 Unit ns ns ns ns ns us us ns ns ns ns us MIN MAX MIN MAX MIN MAX MIN MAX TDES Read Recovery Time Before Write tWPH Write Pulse Width High Note: 1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Characteristics for Read Only Operations. 2. Maximum pulse widths not required because the on-chip program/erase circuitry will terminate the pulse widths internally on the device. 3. Not 100% tested. P/N: PM0767 12 REV. 0.7, NOV. 20, 2002 MX26C1000B Table 2: Command Definitions Command Bus Cycles. Req Read Memory Setup Erase/Erase Erase Verify Setup Program/Program Program Verify Reset 1 2 2 2 2 2 Operation Write Write Write Write Write Write Address1 X X EA X X X Data2 00H 20H A0H 40H C0H FFH Write Read Write Read Write X X PA X X 20H EVD PD PVD FFH Operation Address1 Data2 First Bus Cycle Second Bus Cycle 1 EA=Erase Address: address of memory location to be read during erase verify. PA=Program Address: address of memory location to be Programmed. Address are latched on the falling edge of the WE pulse. 2 EVD=Erase Verify Data: data read from location EA during erase verify. PD=Program Data: data to be programmed at location PA. Data is latched on the rising edge of WE. PVD=Program Verify Data: data read from location PA during program verify. PA is latched on the Program command. P/N: PM0767 13 REV. 0.7, NOV. 20, 2002 MX26C1000B AC WAVEFORMS FOR READ OPERATIONS Power-Up Standby Device and Address Selection Outputs enabled Data Valid Standby Power-Up Address Addresses Stable tAVAV(tRC) CE tEHQZ(tDF) OE tWHGL tGHQZ(tDF) WE tGLQV(tOE) tELQV(tCE) tELQX(tLZ) tGLQX(tOLZ) Output Valid tAVQV(tACC) tAXQX(tOH) High Z Data High Z tVCS 5.0V VCC 0V P/N: PM0767 14 REV. 0.7, NOV. 20, 2002 MX26C1000B AC WAVEFORMS FOR ERASE OPERATIONS Program Command Latch Program Address Programming and Data Setup Program Power-Up Standby Verify Command Programming Standby Verification Power-Down Addresses tAVAV(tWC) tAVWL(tAS) tWLAX(tAH) tAVWL(tAS) tAVAV(tRC) CE tELWL(tCS) tWHEH(tCH) tEHQZ(tDF) OE tWHWH1 tGHWL(tDES) tWHGL tGHQZ(tDF) tGLQV(tOE) tAXQX(tOH) tDVWH(tDS) tWHDX(tDH) DATA IN=40h DATA IN=PD DATA IN=C0h WE tWHWL(tWPH) tWLWH(tWP) tGLQX(tOLZ) VALID DATA OUT Data tVCS 5V tELQX(tLZ) tELQV(tCE) VCC 0V VPPH tVPEL VPP VPPL P/N: PM0767 15 REV. 0.7, NOV. 20, 2002 MX26C1000B AC WAVEFORMS FOR PROGRAMMING OPERATIONS Program Command Latch Address Programming Setup Program and Data Power-Up Standby Verify Command Programming Standby Verification Power-Down Addresses tAVAV(tWC) tAVWL(tAS) tWLAX(tAH) tAVWL(tAS) tAVAV(tRC) CE tELWL(tCS) tWHEH(tCH) tEHQZ(tDF) OE tWHWH1 tGHWL(tDES) tWHGL tGHQZ(tDF) tGLQV(tOE) tAXQX(tOH) tDVWH(tDS) tWHDX(tDH) DATA IN=20h DATA IN=20h DATA IN=C0h WE tWHWL(tWPH) tWLWH(tWP) tGLQX(tOLZ) VALID DATA OUT Data tVCS 5V tELQX(tLZ) tELQV(tCE) VCC 0V VPPH tVPEL VPP VPPL P/N: PM0767 16 REV. 0.7, NOV. 20, 2002 MX26C1000B ORDERING INFORMATION PLASTIC PACKAGE PART NO. ACCESS TIME(ns) OPERATING Current MAX.(mA) MX26C1000BPC-90 MX26C1000BQC-90 MX26C1000BMC-90 MX26C1000BTC-90 MX26C1000BPC-10 MX26C1000BQC-10 MX26C1000BMC-10 MX26C1000BTC-10 MX26C1000BPC-12 MX26C1000BQC-12 MX26C1000BMC-12 MX26C1000BTC-12 MX26C1000BPC-15 MX26C1000BQC-15 MX26C1000BMC-15 MX26C1000BTC-15 MX26C1000BPI-90 MX26C1000BQI-90 MX26C1000BMI-90 MX26C1000BTI-90 MX26C1000BPI-10 MX26C1000BQI-10 MX26C1000BMI-10 MX26C1000BTI-10 MX26C1000BPI-12 MX26C1000BQI-12 MX26C1000BMI-12 MX26C1000BTI-12 MX26C1000BPI-15 MX26C1000BQI-15 MX26C1000BMI-15 MX26C1000BTI-15 90 90 90 90 100 100 100 100 120 120 120 120 150 150 150 150 90 90 90 90 100 100 100 100 120 120 120 120 150 150 150 150 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 STANDBY Current MAX.(uA) 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 OPERATING TEMPERATURE 0° to 70° C C 0° to 70° C C 0° to 70° C C 0° to 70° C C 0° to 70° C C 0° to 70° C C 0° to 70° C C 0° to 70° C C 0° to 70° C C 0° to 70° C C 0° to 70° C C 0° to 70° C C 0° to 70° C C 0° to 70° C C 0° to 70° C C 0° to 70° C C -40°C to 85° C -40°C to 85° C -40°C to 85° C -40°C to 85° C -40°C to 85° C -40°C to 85° C -40°C to 85° C -40°C to 85° C -40°C to 85° C -40°C to 85° C -40°C to 85° C -40°C to 85° C -40°C to 85° C -40°C to 85° C -40°C to 85° C -40°C to 85° C 32 Pin DIP 32 Pin PLCC 32 Pin SOP 32 Pin TSOP 32 Pin DIP 32 Pin PLCC 32 Pin SOP 32 Pin TSOP 32 Pin DIP 32 Pin PLCC 32 Pin SOP 32 Pin TSOP 32 Pin DIP 32 Pin PLCC 32 Pin SOP 32 Pin TSOP 32 Pin DIP 32 Pin PLCC 32 Pin SOP 32 Pin TSOP 32 Pin DIP 32 Pin PLCC 32 Pin SOP 32 Pin TSOP 32 Pin DIP 32 Pin PLCC 32 Pin SOP 32 Pin TSOP 32 Pin DIP 32 Pin PLCC 32 Pin SOP 32 Pin TSOP PACKAGE P/N: PM0767 17 REV. 0.7, NOV. 20, 2002 MX26C1000B PACKAGE INFORMATION P/N: PM0767 18 REV. 0.7, NOV. 20, 2002 MX26C1000B P/N: PM0767 19 REV. 0.7, NOV. 20, 2002 MX26C1000B P/N: PM0767 20 REV. 0.7, NOV. 20, 2002 MX26C1000B P/N: PM0767 21 REV. 0.7, NOV. 20, 2002 MX26C1000B REVISION HISTORY Revision No. Description 0.1 Change title from MX26C1000A to MX26C1000B To add erase/program cycle 0.2 Change Device ID code from 30H to CEH 0.3 To added 32SOP/TSOP types package and access time 150ns Modify device ID old CEH-->New CFH Modify read ID method Modify erase/program cycle from 100ns to 50ns Modify VCC Standby Current(TTL) from 1mA to 1.5mA 0.4 To added VCC1 & VPP1 to DC Characteristics Table Modify Package Information 0.5 To added chip erase time / chip program time Modify Package Information 0.6 Modify the Programming Operations Timing Waveforms 0.7 To modify Package Information Page All P1 P5 P1,11,12,17,18 P5 P4,5,6,13 P10 P10 P10 P18~21 P1 P18~21 P15 P18~21 Date DEC/11/2000 DEC/28/2000 MAR/27/2001 APR/23/2001 JUL/04/2001 OCT/04/2001 NOV/20/2002 P/N: PM0767 22 REV. 0.7, NOV. 20, 2002 MX26C1000B MACRONIX INTERNATIONAL CO., LTD. HEADQUARTERS: TEL:+886-3-578-6688 FAX:+886-3-563-2888 EUROPE OFFICE: TEL:+32-2-456-8020 FAX:+32-2-456-8021 JAPAN OFFICE: TEL:+81-44-246-9100 FAX:+81-44-246-9105 SINGAPORE OFFICE: TEL:+65-348-8385 FAX:+65-348-8096 TAIPEI OFFICE: TEL:+886-2-2509-3300 FAX:+886-2-2509-2200 MACRONIX AMERICA, INC. TEL:+1-408-453-8088 FAX:+1-408-453-8488 CHICAGO OFFICE: TEL:+1-847-963-1900 FAX:+1-847-963-1909 http : //www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.