MX26LV800ABTC-70

MX26LV800AT/AB Macronix NBit TM M emory Family 8M-BIT [1Mx8/512K x16] CMOS SINGLE VOLTAGE 3V ONLY HIGH SPEED eLiteFlashTM MEMORY FEATURES • Extended single - supply voltage range 3.0V to 3.6V • 1,048,576 x 8/524,288 x 16 switchable • Single power supply operation - 3.0V only operation for read, erase and program operation • Fast access time: 55/70ns • Low power consumption - 30mA maximum active current - 30uA typical standby current • Command register architecture - Byte/word Programming (55us/70us typical) - Sector Erase (Sector structure 16K-Bytex1, 8K-Bytex2, 32K-Bytex1, and 64K-Byte x15) • Auto Erase (chip & sector) and Auto Program - Automatically erase any combination of sectors with Erase verify capability. - Automatically program and verify data at specified address • Status Reply - Data# polling & Toggle bit for detection of program and erase operation completion Ready/Busy# pin (RY/BY#) - Provides a hardware method of detecting program or erase operation completion CFI (Common Flash Interface) compliant - Flash device parameters stored on the device and provide the host system to access 2,000 minimum erase/program cycles Latch-up protected to 100mA from -1V to VCC+1V Boot Sector Architecture - T = Top Boot Sector - B = Bottom Boot Sector Package type: - 48-pin TSOP - 48-ball CSP Compatibility with JEDEC standard - Pinout and software compatible with single-power supply Flash 20 years data retention • • • • • • • • GENERAL DESCRIPTION The MX26LV800AT/AB is a 8-mega bit high speed Flash memory organized as 1M bytes of 8 bits or 512K words of 16 bits. MXIC's high speed Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX26LV800AT/AB is packaged in 48-pin TSOP, and 48-ball CSP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers. The standard MX26LV800AT/AB offers access time as fast as 55ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX26LV800AT/AB has separate chip enable (CE#) and output enable (OE#) controls. MXIC's high speed Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX26LV800AT/AB uses a command register to manage this functionality. The command register alP/N:PM1128 lows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility. MXIC high speed Flash technology reliably stores memory contents even after 2,000 erase and program cycles. The MXIC cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produces reliable cycling. The MX26LV800AT/AB uses a 3.0V~3.6V VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamperes on address and data pin from -1V to VCC + 1V. REV. 1.1, MAR. 28, 2005 1 MX26LV800AT/AB PIN CONFIGURATIONS 48 TSOP (Standard Type) (12mm x 20mm) A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# RESET# NC NC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE# GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC Q11 Q3 Q10 Q2 Q9 Q1 Q8 Q0 OE# GND CE# A0 PIN DESCRIPTION SYMBOL PIN NAME A0~A18 Q0~Q14 Q15/A-1 CE# WE# BYTE# RESET# OE# RY/BY# VCC GND Address Input Data Input/Output Q15(Word mode)/LSB addr(Byte mode) Chip Enable Input Write Enable Input Word/Byte Selection input Hardware Reset Pin Output Enable Input Ready/Busy Output Power Supply Pin (3.0V~3.6V) Ground Pin MX26LV800AT/AB 48-Ball CSP Ball Pitch = 0.8 mm, Top View, Balls Facing Down A 6 5 4 3 2 1 A13 A9 WE# RY/BY# A7 A3 B A12 A8 RESET# NC A17 A4 C A14 A10 NC A18 A6 A2 D A15 A11 NC NC A5 A1 E A16 Q7 Q5 Q2 Q0 A0 F G H GND Q6 Q4 Q3 Q1 GND BYTE# Q15/A-1 Q14 Q12 Q10 Q8 CE# Q13 Vcc Q11 Q9 OE# P/N:PM1128 REV. 1.1, MAR. 28, 2005 2 MX26LV800AT/AB BLOCK STRUCTURE TABLE 1: MX26LV800AT SECTOR ARCHITECTURE Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 Sector Size Byte Mode Word Mode 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 32Kbytes 8Kbytes 8Kbytes 16Kbytes 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 16Kwords 4Kwords 4Kwords 8Kwords Address range Byte Mode (x8) 00000h-0FFFFh 10000h-1FFFFh 20000h-2FFFFh 30000h-3FFFFh 40000h-4FFFFh 50000h-5FFFFh 60000h-6FFFFh 70000h-7FFFFh 80000h-8FFFFh 90000h-9FFFFh A0000h-AFFFFh B0000h-BFFFFh C0000h-CFFFFh D0000h-DFFFFh E0000h-EFFFFh F0000h-F7FFFh F8000h-F9FFFh FA000h-FBFFFh FC000h-FFFFFh Word Mode (x16) 00000h-07FFFh 08000h-0FFFFh 10000h-17FFFh 18000h-1FFFFh 20000h-27FFFh 28000h-2FFFFh 30000h-37FFFh 38000h-3FFFFh 40000h-47FFFh 48000h-4FFFFh 50000h-57FFFh 58000h-5FFFFh 60000h-67FFFh 68000h-6FFFFh 70000h-77FFFh 78000h-7BFFFh 7C000h-7CFFFh 7D000h-7DFFFh 7E000h-7FFFFh 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 Sector Address A18 A17 A16 A15 A14 A13 A12 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 X X X X X X X X X X X X X X X 0 1 1 1 X X X X X X X X X X X X X X X X 0 0 1 X X X X X X X X X X X X X X X X 0 1 X Note: Byte mode:address range A18:A-1, word mode:address range A18:A0. P/N:PM1128 REV. 1.1, MAR. 28, 2005 3 MX26LV800AT/AB TABLE 2: MX26LV800AB SECTOR ARCHITECTURE Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 Sector Size Byte Mode Word Mode 16Kbytes 8Kbytes 8Kbytes 32Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 8Kwords 4Kwords 4Kwords 16Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords Address range Byte Mode (x8) 00000h-03FFFh 04000h-05FFFh 06000h-07FFFh 08000h-0FFFFh 10000h-1FFFFh 20000h-2FFFFh 30000h-3FFFFh 40000h-4FFFFh 50000h-5FFFFh 60000h-6FFFFh 70000h-7FFFFh 80000h-8FFFFh 90000h-9FFFFh A0000h-AFFFFh B0000h-BFFFFh C0000h-CFFFFh D0000h-DFFFFh E0000h-EFFFFh F0000h-FFFFFh Word Mode (x16) 00000h-01FFFh 02000h-02FFFh 03000h-03FFFh 04000h-07FFFh 08000h-0FFFFh 10000h-17FFFh 18000h-1FFFFh 20000h-27FFFh 28000h-2FFFFh 30000h-37FFFh 38000h-3FFFFh 40000h-47FFFh 48000h-4FFFFh 50000h-57FFFh 58000h-5FFFFh 60000h-67FFFh 68000h-6FFFFh 70000h-77FFFh 78000h-7FFFFh 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Sector Address A18 A17 A16 A15 A14 A13 A12 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 1 X X X X X X X X X X X X X X X 0 1 1 X X X X X X X X X X X X X X X X X 0 1 X X X X X X X X X X X X X X X X Note: Byte mode:address range A18:A-1, word mode:address range A18:A0. P/N:PM1128 REV. 1.1, MAR. 28, 2005 4 MX26LV800AT/AB BLOCK DIAGRAM CE# OE# WE# RESET# CONTROL INPUT LOGIC PROGRAM/ERASE HIGH VOLTAGE WRITE STATE MACHINE (WSM) STATE REGISTER FLASH ARRAY ARRAY SOURCE HV X-DECODER ADDRESS LATCH A0-A18 AND BUFFER Y-PASS GATE COMMAND DATA DECODER Y-DECODER SENSE AMPLIFIER PGM DATA HV COMMAND DATA LATCH PROGRAM DATA LATCH Q0-Q15/A-1 I/O BUFFER P/N:PM1128 REV. 1.1, MAR. 28, 2005 5 MX26LV800AT/AB AUTOMATIC PROGRAMMING The MX26LV800AT/AB is word/byte programmable using the Automatic Programming algorithm. The Automatic Programming algorithm makes the external system do not need to have time out sequence nor to verify the data programmed. The typical chip programming time at room temperature of the MX26LV800AT/AB is less than 35 seconds. write commands to the command register using standard microprocessor write timings. The device will automatically pre-program and verify the entire array. Then the device automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. A status bit toggling between consecutive read cycles provides feedback to the user as to the status of the erasing operation. Register contents serve as inputs to an internal statemachine which controls the erase and programming circuitry. During write cycles, the command register internally latches address and data needed for the programming and erase operations. During a system write cycle, addresses are latched on the falling edge, and data are latched on the rising edge of WE# or CE#, whichever happens first. MXIC's high speed Flash technology combines years of EPROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The MX26LV800AT/AB electrically erases all bits simultaneously using Fowler-Nordheim tunneling. The bytes are programmed by using the EPROM programming mechanism of hot electron injection. During a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. After the state machine has completed its task, it will allow the command register to respond to its full command set. AUTOMATIC PROGRAMMING ALGORITHM MXIC's Automatic Programming algorithm requires the user to only write program set-up commands (including 2 unlock write cycle and A0H) and a program command (program data and address). The device automatically times the programming pulse width, provides the program verification, and counts the number of sequences. A status bit similar to DATA# polling and a status bit toggling between consecutive read cycles, provide feedback to the user as to the status of the programming operation. Refer to write operation status, table 7, for more information on these status bits. AUTOMATIC CHIP ERASE The entire chip is bulk erased using 10 ms erase pulses according to MXIC's Automatic Chip Erase algorithm. Typical erasure at room temperature is accomplished in less than 40 second. The Automatic Erase algorithm automatically programs the entire array prior to electrical erase. The timing and verification of electrical erase are controlled internally within the device. AUTOMATIC SELECT The auto select mode provides manufacturer and device identification, through identifier codes output on Q7~Q0. This mode is mainly adapted for programming equipment on the device to be programmed with its programming algorithm. When programming by high voltage method, automatic select mode requires VID (11V to 12V) on address pin A9 and other address pin A6, A1 and A0 as referring to Table 3. In addition, to access the automatic select codes in-system, the host can issue the automatic select command through the command register without requiring VID, as shown in table 4. AUTOMATIC SECTOR ERASE The MX26LV800AT/AB is sector(s) erasable using MXIC's Auto Sector Erase algorithm. The Automatic Sector Erase algorithm automatically programs the specified sector(s) prior to electrical erase. The timing and verification of electrical erase are controlled internally within the device. An erase operation can erase one sector, multiple sectors, or the entire device. AUTOMATIC ERASE ALGORITHM MXIC's Automatic Erase algorithm requires the user to P/N:PM1128 REV. 1.1, MAR. 28, 2005 6 MX26LV800AT/AB TABLE 3. MX26LV800AT/AB AUTO SELECT MODE OPERATION A18 A11 Description Manufacturer Code Read ID Device ID Device ID (Bottom Boot Block) Word Byte Word Byte Silicon (Top Boot Block) Mode CE# OE# WE# L L L L L L L L L L H H H H H | X X X X X | X X X X X VID VID VID VID VID A12 A10 A9 A8 | A7 X X X X X L L L L L A6 A5 A1 A0 | A2 X X X X X L L L L L L H H H H C2H 22DAH XXDAH 225BH XX5BH Q15~Q0 NOTE:SA=Sector Address, X=Don't Care, L=Logic Low, H=Logic High P/N:PM1128 REV. 1.1, MAR. 28, 2005 7 MX26LV800AT/AB TABLE 4. MX26LV800AT/AB COMMAND DEFINITIONS Command Bus First Bus Cycle Second Bus Cycle Third Bus Cycle Fourth Bus Cycle Data Fifth Bus Cycle Addr Sixth Bus Cycle Data Addr Data Cycle Addr Reset Read Read Silicon ID Word Byte Program Word Byte Chip Erase Word Byte Sector Erase Word Byte CFI Query Word Byte 1 1 4 4 4 4 6 6 6 6 1 1 Data Addr Data Addr Data Addr XXXH F0H RA RD 55H 55H 55H 55H 55H 55H 55H 55H 555H AAAH 555H AAAH 555H AAAH 555H AAAH 90H ADI 90H ADI A0H PA A0H PA DDI DDI PD PD 2AAH 55H 555H 55H 2AAH 55H 555H 55H 555H 10H AAAH 10H SA SA 30H 30H 555H AAH 2AAH AAAH AAH 555H 555H AAH 2AAH AAAH AAH 555H 555H AAH 2AAH AAAH AAH 555H 555H AAH 2AAH AAAH AAH 555H 555H 98 AAAH 98 80H 555H AAH 80H AAAH AAH 80H 555H AAH 80H AAAH AAH Note: 1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacturer code,A1=0, A0 = 1 for device code. A2-A18=do not care. (Refer to table 3) DDI = Data of Device identifier : C2H for manufacture code, 22DA/DA(Top), and 225B/5B(Bottom) for device code. X = X can be VIL or VIH RA=Address of memory location to be read. RD=Data to be read at location RA. 2. PA = Address of memory location to be programmed. PD = Data to be programmed at location PA. SA = Address of the sector. 3. The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 in word mode/AAAH or 555H to Address A10~A-1 in byte mode. Address bit A11~A18=X=Don't care for all address commands except for Program Address (PA) and Sector Address (SA). Write Sequence may be initiated with A11~A18 in either state. P/N:PM1128 REV. 1.1, MAR. 28, 2005 8 MX26LV800AT/AB COMMAND DEFINITIONS Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. Table 5 defines the valid register command sequences. TABLE 5. MX26LV800AT/AB BUS OPERATION ADDRESS DESCRIPTION CE# OE# WE# RESET# A18 A10 A9 A8 A6 A5 A1 A0 A12 A11 Read L L H H A7 AIN A2 Dout Q0~Q7 Q8~Q15 BYTE =VIH Dout BYTE =VIL Q8~Q14 =High Z Q15=A-1 Write Reset Output Disable Standby L X L Vcc ± 0.3V H X H X L X H X H L H Vcc ± 0.3V AIN X X X DIN(3) High Z High Z High Z DIN High Z High Z High Z High Z High Z High Z NOTES: 1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 4. 2. VID is the Silicon-ID-Read high voltage, 11V to 12V. 3. Refer to Table 5 for valid Data-In during a write operation. 4. X can be VIL or VIH. P/N:PM1128 REV. 1.1, MAR. 28, 2005 9 MX26LV800AT/AB REQUIREMENTS FOR READING ARRAY DATA To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid address on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. Characteristics" section contains timing specification table and timing diagrams for write operations. STANDBY MODE When using both pins of CE# and RESET#, the device enter CMOS Standby with both pins held at Vcc ± 0.3V. If CE# and RESET# are held at VIH, but not within the range of VCC ± 0.3V, the device will still be in the standby mode, but the standby current will be larger. During Auto Algorithm operation, Vcc active current (Icc2) is required even CE# = "H" until the operation is completed. The device can be read with standard access time (tCE) from either of these standby modes, before it is ready to read data. OUTPUT DISABLE WRITE COMMANDS/COMMAND SEQUENCES To program data to the device or erase sectors of memory , the system must drive WE# and CE# to VIL, and OE# to VIH. The "word/byte Program Command Sequence" section has details on programming data to the device. An erase operation can erase one sector, multiple sectors , or the entire device. Table indicates the address space that each sector occupies. A "sector address" consists of the address bits required to uniquely select a sector. The "Writing specific address and data commands or sequences into the command register initiates device operations. Table 1 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. Section has details on erasing a sector or the entire chip. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on Q7-Q0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence section for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC With the OE# input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins to be in a high impedance state. RESET# OPERATION The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3V, the standby current will be greater. The RESET# pin may be tied to system reset circuitry. A system reset would that also reset the high speed Flash, enabling the system to read the boot-up firmware from the high speed Flash. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a "0" (busy) until the inter- P/N:PM1128 REV. 1.1, MAR. 28, 2005 10 MX26LV800AT/AB nal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# parameters and to Figure 14 for the timing diagram. SET-UP AUTOMATIC CHIP/SECTOR ERASE COMMANDS Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command 80H. Two more "unlock" write cycles are then followed by the chip erase command 10H or sector erase command 30H. The Automatic Chip Erase does not require the device to be entirely pre-programmed prior to executing the Automatic Chip Erase. Upon executing the Automatic Chip Erase, the device will automatically program and verify the entire memory for an all-zero data pattern. When the device is automatically verified to contain an all-zero pattern, a self-timed chip erase and verify begin. The erase and verify operations are completed when the data on Q7 is "1" at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations. When using the Automatic Chip Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required). If the Erase operation was unsuccessful, the data on Q5 is "1" (see Table 7), indicating the erase operation exceed internal timing limit. The automatic erase begins on the rising edge of the last WE# or CE# pulse, whichever happens first in the command sequence and terminates when the data on Q7 is "1" at which time the device returns to the Read mode, or the data on Q6 stops toggling for two consecutive read cycles at which time the device returns to the Read mode. READ/RESET COMMAND The read or reset operation is initiated by writing the read/reset command sequence into the command register. Microprocessor read cycles retrieve array data. The device remains enabled for reads until the command register contents are altered. If program-fail or erase-fail happen, the write of F0H will reset the device to abort the operation. A valid command must then be written to place the device in the desired state. SILICON-ID READ COMMAND High speed Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacturer and device codes must be accessible while the device resides in the target system. PROM programmers typically access signature codes by raising A9 to a high voltage (VID). However, multiplexing high voltage onto address lines is not generally desired system design practice. The MX26LV800AT/AB contains a Silicon-ID-Read operation to supple traditional PROM programming methodology. The operation is initiated by writing the read silicon ID command sequence into the command register. Following the command write, a read cycle with A1=VIL, A0=VIL retrieves the manufacturer code of C2H/ 00C2H. A read cycle with A1=VIL, A0=VIH returns the device code of DAH/22DAH for MX26LV800AT, 5BH/ 225BH for MX26LV800AB. P/N:PM1128 REV. 1.1, MAR. 28, 2005 11 MX26LV800AT/AB TABLE 6. SILICON ID CODE Pins Manufacture code Device code for MX26LV800AT Device code for MX26LV800AB Byte Byte Byte A0 Word VIL VIL VIH VIH Word VIH Word VIH A1 VIL VIL VIL VIL VIL VIL Q15~Q8 Q7 Q6 Q5 00H X 22H X 22H X 1 1 1 1 0 0 1 1 1 1 1 1 0 0 0 0 0 0 Q4 Q3 Q2 Q1 Q0 Code (Hex) 0 0 1 1 1 1 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 00C2H C2H 22DAH DAH 225BH 5BH READING ARRAY DATA The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Automatic Program or Automatic Erase algorithm. The system must issue the reset command to re-enable the device for reading array data if Q5 goes high, or while in the autoselect mode. See the "Reset Command" section, next. RESET COMMAND Writing the reset command to the device resets the device to reading array data. Address bits are don't care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an SILICON ID READ command sequence. Once in the SILICON ID READ mode, the reset command must be written to return to reading array data. If Q5 goes high during a program or erase operation, writing the reset command returns the device to reading array data. P/N:PM1128 REV. 1.1, MAR. 28, 2005 12 MX26LV800AT/AB SECTOR ERASE COMMANDS The Automatic Sector Erase does not require the device to be entirely pre-programmed prior to executing the Automatic Sector Erase Set-up command and Automatic Sector Erase command. Upon executing the Automatic Sector Erase command, the device will automatically program and verify the sector(s) memory for an all-zero data pattern. The system is not required to provide any control or timing during these operations. When the sector(s) is automatically verified to contain an all-zero pattern, a self-timed sector erase and verify begin. The erase and verify operations are complete when either the data on Q7 is "1" at which time the device returns to the Read mode, or the data on Q6 stops toggling for two consecutive read cycles at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations. When using the Automatic sector Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required). Sector erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the set-up command 80H. Two more "unlock" write cycles are then followed by the sector erase command 30H. The sector address is latched on the falling edge of WE# or CE#, whichever happens later, while the command (data) is latched on the rising edge of WE# or CE#, whichever happens first. Sector addresses selected are loaded into internal register on the sixth falling edge of WE# or CE#, whichever happens later. Each successive sector load cycle started by the falling edge of WE# or CE#, whichever happens later must begin within 50us from the rising edge of the preceding WE# or CE#, whichever happens first. Otherwise, the loading period ends and internal auto sector erase cycle starts. (Monitor Q3 to determine if the sector erase timer window is still open, see section Q3, Sector Erase Timer.) Any command other than Sector Erase (30H) during the time-out period resets the device to read mode. followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically generates the program pulses and verifies the programmed cell margin. Table 1 shows the address and data requirements for the word/byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using Q7, Q6, or RY/BY#. See "Write Operation Status" for information on these status bits. Any commands written to the device during the Em-bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming operation. The word/byte Program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a "0" back to a "1". Attempting to do so may halt the operation and set Q5 to "1", or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still "0". Only erase operations can convert a "0" to a "1". WRITE OPERATION STATUS The device provides several bits to determine the status of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/ BY#. Table 7 and the following subsections describe the functions of these bits. Q7, RY/BY#, and Q6 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first. WORD/BYTE PROGRAM COMMAND SEQUENCE The device programs one byte of data for each program operation. The command sequence requires four bus cycles, and is initiated by writing two unlock write cycles, P/N:PM1128 REV. 1.1, MAR. 28, 2005 13 MX26LV800AT/AB Q7: Data# Polling The Data# Polling bit, Q7, indicates to the host system whether an Automatic Algorithm is in progress or completed. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command sequence. During the Automatic Program algorithm, the device outputs on Q7 the complement of the datum programmed to Q7. When the Automatic Program algorithm is complete, the device outputs the datum programmed to Q7. The system must provide the program address to read valid status information on Q7. During the Automatic Erase algorithm, Data# Polling produces a "0" on Q7. When the Automatic Erase algorithm is complete, Data# Polling produces a "1" on Q7. This is analogous to the complement/true datum out-put described for the Automatic Program algorithm: the erase function changes all the bits in a sector to "1" prior to this, the device outputs the "complement," or "0". The system must provide an address within any of the sectors selected for erasure to read valid status information on Q7. When the system detects Q7 has changed from the complement to true data, it can read valid data at Q7-Q0 on the following read cycles. This is because Q7 may change asynchronously with Q0-Q6 while Output Enable (OE#) is asserted low. Q6:Toggle BIT I Toggle Bit I on Q6 indicates whether an Automatic Program or Erase algorithm is in progress or complete. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# or CE#, whichever happens first, in the command sequence (prior to the program or erase operation), and during the sector time-out. During an Automatic Program or Erase algorithm operation, successive read cycles to any address cause Q6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, Q6 stops toggling. When the device is actively erasing (that is, the Automatic Erase algorithm is in progress), Q6 toggling. However, the system must also use Q2 to determine which sectors are erasing. Alternatively, the system can use Q7. Q6 stops toggling once the Automatic Program algorithm is complete. Table 7 shows the outputs for Toggle Bit I on Q6. Q2:Toggle Bit II The "Toggle Bit II" on Q2, when used with Q6, indicates whether a particular sector is actively erasing (that is, the Automatic Erase algorithm is in process). Toggle Bit II is valid after the rising edge of the final WE# or CE#, whichever happens first, in the command sequence. Q2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But Q2 cannot distinguish when the sector is actively erasing. Q6, by comparison, indicates when the device is actively erasing, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sectors and mode information. Refer to Table 7 to compare outputs for Q2 and Q6. RY/BY# : Ready/Busy The RY/BY# is a dedicated, open-drain output pin that indicates whether an Automatic Erase/Program algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# or CE#, whichever happens first, in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. If the output is high (Ready), the device is ready to read array data, or is in the standby mode. Table 7 shows the outputs for RY/BY# during write operation. Reading Toggle Bits Q6/ Q2 Whenever the system initially begins reading toggle bit status, it must read Q7-Q0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit REV. 1.1, MAR. 28, 2005 P/N:PM1128 14 MX26LV800AT/AB after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on Q7-Q0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of Q5 is high (see the section on Q5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as Q5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that system initially determines that the toggle bit is toggling and Q5 has not gone high. The system may continue to monitor the toggle bit and Q5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. operation, it specifies that the entire chip is bad or combination of sectors are bad. If this time-out condition occurs during the word/byte programming operation, it specifies that the entire sector containing that byte is bad and this sector may not be reused, (other sectors are still functional and can be reused). The time-out condition will not appear if a user tries to program a non blank location without erasing. Please note that this is not a device failure condition since the device was incorrectly used. Q5 Exceeded Timing Limits Q5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions Q5 will produce a "1". This time-out condition indicates that the program or erase cycle was not successfully completed. Data# Polling and Toggle Bit are the only operating functions of the device under this condition. If this time-out condition occurs during sector erase operation, it specifies that a particular sector is bad and it may not be reused. However, other sectors are still functional and may be used for the program or erase operation. The device must be reset to use other sectors. Write the Reset command sequence to the device, and then execute program or erase command sequence. This allows the system to continue to use the other active sectors in the device. If this time-out condition occurs during the chip erase P/N:PM1128 REV. 1.1, MAR. 28, 2005 15 MX26LV800AT/AB TABLE 7. WRITE OPERATION STATUS Status Q7 (Note1) In Progress Word/Byte Program in Auto Program Algorithm Q7# Toggle Q6 Q5 (Note2) 0 N/A No Toggle Auto Erase Algorithm Exceeded Time Limits Auto Erase Algorithm 0 Toggle 1 1 Word/Byte Program in Auto Program Algorithm 0 Q7# Toggle Toggle 0 1 1 N/A Toggle No Toggle Toggle 0 0 0 0 Q3 Q2 RY/BY# Note: 1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits. See "Q5:Exceeded Timing Limits " for more information. P/N:PM1128 REV. 1.1, MAR. 28, 2005 16 MX26LV800AT/AB Q3 Sector Erase Timer After the completion of the initial sector erase command sequence, the sector erase time-out will begin. Q3 will remain low until the time-out is complete. Data# Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data# Polling or the Toggle Bit indicates the device has been written with a valid erase command, Q3 may be used to determine if the sector erase timer window is still open. If Q3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data# Polling or Toggle Bit. If Q3 is low ("0"), the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of Q3 prior to and following each subsequent sector erase command. If Q3 were high on the second status check, the command may not have been accepted. POWER SUPPLY DECOUPLING In order to reduce power switching effect, each device should have a 0.1uF ceramic capacitor connected between its VCC and GND. POWER-UP SEQUENCE The MX26LV800AT/AB powers up in the Read only mode. In addition, the memory contents may only be altered after successful completion of the predefined command sequences. DATA PROTECTION The MX26LV800AT/AB is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise. WRITE PULSE "GLITCH" PROTECTION Noise pulses of less than 5ns(typical) on CE# or WE# will not initiate a write cycle. LOGICAL INHIBIT Writing is inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle CE# and WE# must be a logical zero while OE# is a logical one. P/N:PM1128 REV. 1.1, MAR. 28, 2005 17 MX26LV800AT/AB ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . ..... -65oC to +150oC Ambient Temperature with Power Applied. . . . . . . . . . . . . .... -65oC to +125oC Voltage with Respect to Ground VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V A9, OE#, and RESET# (Note 2) . . . . . . . . . . . . . . . . -0.5 V to +12 V All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V Output Short Circuit Current (Note 3) . . . . . . 200 mA Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. 2. Minimum DC input voltage on pins A9, OE#, and RESET# is -0.5 V. During voltage transitions, A9, OE#, and RESET# may overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on pin A9 is +12 V which may overshoot to 13.5V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. OPERATING RATINGS Commercial (C) Devices Ambient Temperature (TA ). . . . . . . . . . . . 0° C to +70° C VCC Supply Voltages VCC for full voltage range. . . . . . . . . . . +3.0 V to 3.6 V Operating ranges define those limits between which the functionality of the device is guaranteed. P/N:PM1128 REV. 1.1, MAR. 28, 2005 18 MX26LV800AT/AB CAPACITANCE TA = 25oC, f = 1.0 MHz SYMBOL CIN1 CIN2 COUT PARAMETER Input Capacitance Control Pin Capacitance Output Capacitance MIN. TYP MAX. 8 12 12 UNIT pF pF pF CONDITIONS VIN = 0V VIN = 0V VOUT = 0V TABLE 8. DC CHARACTERISTICS TA = 0oC to 70oC, VCC = 3.0V~3.6V MX26LV800AT/AB Symbol ILI ILIT ILO ICC1 ICC2 ICC3 ICC4 VIL VIH VID VOL VOH1 VOH2 PARAMETER Input Leakage Current A9 Input Leakage Current Output Leakage Current VCC Active Read Current VCC Active write Current VCC Standby Current VCC Standby Current During Reset Input Low Voltage (Note 1) Input High Voltage Voltage for Automatic Select Output Low Voltage Output High Voltage (TTL) Output High Voltage (CMOS) NOTES: 1. VIL min. = -1.0V for pulse width is equal to or less than 50 ns. VIL min. = -2.0V for pulse width is equal to or less than 20 ns. 2. VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns If VIH is over the specified maximum value, read operation cannot be guaranteed. 3. Automatic sleep mode enable the low power mode when addresses remain stable for tACC +30ns. 0.85xVCC VCC-0.4 0.45 V IOL = 4.0mA, VCC= VCC min IOH = -2mA, VCC=VCC min IOH = -100uA, VCC min -0.5 0.7xVCC 11 0.8 VCC+0.3 12 V V V VCC=3.3V 20 8 26 30 30 MIN. TYP ±1 35 MAX. ±3 200 ±1 30 14 30 100 100 UNIT uA uA uA mA mA mA uA uA CONDITIONS VIN = VSS to VCC VCC=VCC max; A9=12V VOUT = VSS to VCC, VCC=VCC max CE#=VIL, OE#=VIH @5MHz @1MHz CE#=VIL, OE#=VIH CE#; RESET#=VCC ± 0.3V RESET#=VSS ± 0.3V P/N:PM1128 REV. 1.1, MAR. 28, 2005 19 MX26LV800AT/AB AC CHARACTERISTICS TA = 0oC to 70oC, VCC = 3.0V~3.6V TABLE 9. READ OPERATIONS 26LV800AT/AB-55 26LV800AT/AB-70 SYMBOLPARAMETER tRC tACC tCE tOE tDF tOEH Read Cycle Time (Note 1) Address to Output Delay CE# to Output Delay OE# to Output Delay OE# High to Output Float (Note1) Output Enable Hold Time tOH Read Toggle and Data# Polling 0 NOTE: MIN. 55 MAX. 55 55 25 MIN. 70 MAX. UNIT ns 70 70 30 ns ns ns ns ns ns ns CONDITIONS CE#=OE#=VIL OE#=VIL CE#=VIL CE#=VIL 0 0 10 25 0 0 10 0 25 Address to Output hold CE#=OE#=VIL TEST CONDITIONS: • Input pulse levels: 0V/3.0V. • Input rise and fall times is equal to or less than 5ns. • Output load: 1 TTL gate + 100pF (Including scope and jig), for 26LV800AT/AB-70. 1 TTL gate + 30pF (Including scope and jig) for 26LV800AT/AB-55. • Reference levels for measuring timing: 1.5V. 1. Not 100% tested. 2. tDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. P/N:PM1128 REV. 1.1, MAR. 28, 2005 20 MX26LV800AT/AB SWITCHING TEST CIRCUITS DEVICE UNDER TEST 2.7K ohm +3.3V CL 6.2K ohm DIODES=IN3064 OR EQUIVALENT CL= 100pF Including jig capacitance for MX26LV800T/B-70 (30pF for MX26LV800T/B-55) SWITCHING TEST WAVEFORMS 3.0V TEST POINTS 0V INPUT OUTPUT AC TESTING: Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0". Input pulse rise and fall times are < 5ns. P/N:PM1128 REV. 1.1, MAR. 28, 2005 21 MX26LV800AT/AB FIGURE 1. READ TIMING WAVEFORMS tRC VIH Addresses VIL ADD Valid tACC tCE CE# VIH VIL WE# VIH VIL tOEH VIH tOE tDF OE# VIL tACC tOH Outputs VOH VOL HIGH Z DATA Valid HIGH Z VIH RESET# VIL P/N:PM1128 REV. 1.1, MAR. 28, 2005 22 MX26LV800AT/AB AC CHARACTERISTICS TA = 0oC to 70oC, VCC = 3.0V~3.6V TABLE 10. Erase/Program Operations 26LV800AT/AB-55 SYMBOL tWC tAS tAH tDS tDH tOES tGHWL tCS tCH tWP tWPH tWHWH1 tWHWH2 tVCS tRB tBUSY tBAL NOTES: 26LV800AT/AB-70 MIN. 70 0 45 35 0 0 0 0 0 35 30 55/70(TYP.) 2.4(TYP.) 50 0 MAX. UNIT ns ns ns ns ns ns ns ns ns ns ns us sec us ns 90 50 ns us PARAMETER Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Read Recovery Time Before Write (OE# High to WE# Low) CE# Setup Time CE# Hold Time Write Pulse Width Write Pulse Width High Programming Operation (Note 2) (Byte/Word program time) Sector Erase Operation (Note 2) VCC Setup Time (Note 1) Recovery Time from RY/BY# Program/Erase Valid to RY/BY# Delay Sector Address Load Time MIN. 55 0 45 35 0 0 0 0 0 35 30 MAX. 55/70(TYP.) 2.4(TYP.) 50 0 90 50 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information. P/N:PM1128 REV. 1.1, MAR. 28, 2005 23 MX26LV800AT/AB AC CHARACTERISTICS TA = 0oC to 70oC, VCC = 3.0V~3.6V TABLE 11. Alternate CE# Controlled Erase/Program Operations 26LV800AT/AB-55 SYMBOL tWC tAS tAH tDS tDH tOES tGHEL tWS tWH tCP tCPH tWHWH1 tWHWH2 NOTE: 26LV800AT/AB-70 MIN. 70 0 45 35 0 0 0 0 0 35 30 55(Typ.) 70(Typ.) 2.4(Typ.) MAX. UNIT ns ns ns ns ns ns ns ns ns ns ns us us sec PARAMETER Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Read Recovery Time Before Write WE# Setup Time WE# Hold Time CE# Pulse Width CE# Pulse Width High Programming Operation(note2) Byte Word MIN. 55 0 45 35 0 0 0 0 0 35 30 55(Typ.) 70(Typ.) 2.4(Typ.) MAX. Sector Erase Operation (note2) 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information. P/N:PM1128 REV. 1.1, MAR. 28, 2005 24 MX26LV800AT/AB FIGURE 2. COMMAND WRITE TIMING WAVEFORM VCC 3V Addresses VIH ADD Valid VIL tAS tAH WE# VIH VIL tOES tWPH tCWC tWP CE# VIH VIL tCS tCH OE# VIH VIL VIH tDS tDH Data VIL DIN P/N:PM1128 REV. 1.1, MAR. 28, 2005 25 MX26LV800AT/AB AUTOMATIC PROGRAMMING TIMING WAVEFORM One byte data is programmed. Verify in fast algorithm and additional verification by external control are not required because these operations are executed automatically by internal control circuit. Programming completion can be verified by DATA# polling and toggle bit checking after automatic programming starts. Device outputs DATA# during programming and DATA# after programming on Q7. (Q6 is for toggle bit; see toggle bit, DATA# polling, timing waveform) FIGURE 3. AUTOMATIC PROGRAMMING TIMING WAVEFORM Program Command Sequence(last two cycle) tWC tAS Read Status Data (last two cycle) Address 555h PA tAH PA PA CE# tCH tGHWL OE# tWP tWHWH1 WE# tCS tDS tDH tWPH A0h Data PD Status DOUT tBUSY tRB RY/BY# tVCS VCC NOTES: 1.PA=Program Address, PD=Program Data, DOUT is the true data the program address P/N:PM1128 REV. 1.1, MAR. 28, 2005 26 MX26LV800AT/AB FIGURE 4. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data A0H Address 555H Write Program Data/Address Increment Address Data Poll from system No Verify Word Ok ? YES No Last Address ? YES Auto Program Completed P/N:PM1128 REV. 1.1, MAR. 28, 2005 27 MX26LV800AT/AB FIGURE 5. CE# CONTROLLED PROGRAM TIMING WAVEFORM PA for program SA for sector erase 555 for chip erase 555 for program 2AA for erase Data# Polling Address tWC tWH tAS tAH PA WE# tGHEL OE# tCP tWHWH1 or 2 CE# tWS tDS tDH tCPH tBUSY DQ7 DOUT Data tRH A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase RESET# RY/BY# NOTES: 1.PA=Program Address, PD=Program Data, DOUT=Data Out, DQ7=complement of data written to device. 2.Figure indicates the last two bus cycles of the command sequence. P/N:PM1128 REV. 1.1, MAR. 28, 2005 28 MX26LV800AT/AB AUTOMATIC CHIP ERASE TIMING WAVEFORM All data in chip are erased. External erase verification is not required because data is verified automatically by internal control circuit. Erasure completion can be verified by DATA# polling and toggle bit checking after automatic erase starts. Device outputs 0 during erasure and 1 after erasure on Q7. (Q6 is for toggle bit; see toggle bit, DATA# polling, timing waveform) FIGURE 6. AUTOMATIC CHIP ERASE TIMING WAVEFORM Erase Command Sequence(last two cycle) tWC tAS Read Status Data Address 2AAh 555h tAH VA VA CE# tCH tGHWL OE# tWP tWHWH2 WE# tCS tDS tDH tWPH 55h Data 10h In Progress Complete tBUSY tRB RY/BY# tVCS VCC NOTES: SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status"). P/N:PM1128 REV. 1.1, MAR. 28, 2005 29 MX26LV800AT/AB FIGURE 7. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 10H Address 555H Data Pall from System NO Data=FFh ? YES Auto Chip Erase Completed P/N:PM1128 REV. 1.1, MAR. 28, 2005 30 MX26LV800AT/AB AUTOMATIC SECTOR ERASE TIMING WAVEFORM Sector indicated by A12 to A18 are erased. External erase verify is not required because data are verified automatically by internal control circuit. Erasure completion can be verified by DATA# polling and toggle bit checking after automatic erase starts. Device outputs 0 during erasure and 1 after erasure on Q7. (Q6 is for toggle bit; see toggle bit, DATA# polling, timing waveform) FIGURE 8. AUTOMATIC SECTOR ERASE TIMING WAVEFORM Erase Command Sequence(last two cycle) tWC tAS Read Status Data Address 2AAh Sector Address 0 tAH Sector Address 1 Sector Address n VA VA CE# tCH tGHWL OE# tBAL tWHWH2 tWP WE# tCS tDS tDH tWPH 55h Data 30h 30h 30h In Progress Complete tBUSY tRB RY/BY# tVCS VCC NOTES: SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status"). P/N:PM1128 REV. 1.1, MAR. 28, 2005 31 MX26LV800AT/AB FIGURE 9. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 30H Sector Address Last Sector to Erase YES Data Poll from System NO Data=FFh NO YES Auto Sector Erase Completed P/N:PM1128 REV. 1.1, MAR. 28, 2005 32 MX26LV800AT/AB WRITE OPERATION STATUS FIGURE 10. DATA# POLLING ALGORITHM Start Read Q7~Q0 Add.=VA(1) Q7 = Data ? Yes No No Q5 = 1 ? Yes Read Q7~Q0 Add.=VA Q7 = Data ? (2) No FAIL Yes Pass NOTE : 1.VA=Valid address for programming 2.Q7 should be re-checked even Q5="1" because Q7 may change simultaneously with Q5. P/N:PM1128 REV. 1.1, MAR. 28, 2005 33 MX26LV800AT/AB FIGURE 11. TOGGLE BIT ALGORITHM Start Read Q7-Q0 Read Q7-Q0 (Note 1) Toggle Bit Q6 = Toggle ? NO YES NO Q5= 1? YES Read Q7~Q0 Twice (Note 1,2) Toggle bit Q6= Toggle? NO YES Program/Erase Operation Not Complete,Write Reset Command Program/Erase operation Complete Note:1.Read toggle bit twice to determine whether or not it is toggling. 2. Recheck toggle bit because it may stop toggling as Q5 change to "1". P/N:PM1128 REV. 1.1, MAR. 28, 2005 34 MX26LV800AT/AB FIGURE 12. Data# Polling Timings (During Automatic Algorithms) tRC Address VA tACC tCE VA VA CE# tCH tOE OE# tOEH tDF WE# tOH Q7 Q0-Q6 tBUSY Complement Complement True Valid Data High Z Status Data Status Data True Valid Data High Z RY/BY# NOTES: 1. VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data read cycle. 2. CE# must be toggled when DATA# polling. P/N:PM1128 REV. 1.1, MAR. 28, 2005 35 MX26LV800AT/AB FIGURE 13. Toggle Bit Timings (During Automatic Algorithms) tRC Address VA tACC tCE VA VA VA CE# tCH tOE OE# tOEH tDF WE# tOH Q6/Q2 High Z Valid Status (first raed) Valid Status (second read) Valid Data (stops toggling) Valid Data tBUSY RY/BY# NOTES: 1. VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read cycle, and array data read cycle. 2. CE# must be toggled when toggle bit toggling. P/N:PM1128 REV. 1.1, MAR. 28, 2005 36 MX26LV800AT/AB TABLE 12. AC CHARACTERISTICS Parameter Std tREADY1 Description RESET# PIN Low (During Automatic Algorithms) to Read or Write (See Note) tREADY2 RESET# PIN Low (NOT During Automatic Algorithms) to Read or Write (See Note) tRP tRH tRB RESET# Pulse Width (During Automatic Algorithms) RESET# High Time Before Read (See Note) RY/BY# Recovery Time (to CE#, OE# go low) MIN MIN MIN 500 50 0 ns ns ns MAX 500 ns Test Setup All Speed Options Unit MAX 20 us Note: Not 100% tested FIGURE 14. RESET# TIMING WAVEFORM RY/BY# CE#, OE# tRH RESET# tRP tReady2 Reset Timing NOT during Automatic Algorithms tReady1 RY/BY# tRB CE#, OE# RESET# tRP Reset Timing during Automatic Algorithms P/N:PM1128 REV. 1.1, MAR. 28, 2005 37 MX26LV800AT/AB AC CHARACTERISTICS TABLE 13. WORD/BYTE CONFIGURATION (BYTE#) Parameter JEDEC Std tELFL/tELFH tFLQZ tFHQV CE# to BYTE# Switching Low or High BYTE# Switching Low to Output HIGH Z BYTE# Switching High to Output Active Max Max Min 25 55 Description Speed Options -55 5 25 70 -70 ns ns ns Unit FIGURE 15. BYTE# TIMING WAVEFORM FOR READ OPERATIONS (BYTE# switching from byte mode to word mode) CE# OE# tELFH BYTE# Q0~Q14 DOUT (Q0-Q7) DOUT (Q0-Q14) Q15/A-1 VA tFHQV DOUT (Q15) P/N:PM1128 REV. 1.1, MAR. 28, 2005 38 MX26LV800AT/AB FIGURE 16. BYTE# TIMING WAVEFORM FOR READ OPERATIONS (BYTE# switching from word mode to byte mode) CE# OE# tELFH BYTE# Q0~Q14 DOUT (Q0-Q14) DOUT (Q0-Q7) Q15/A-1 DOUT (Q15) tFLQZ VA FIGURE 17. BYTE# TIMING WAVEFORM FOR PROGRAM OPERATIONS CE# The falling edge of the last WE# signal WE# BYTE# tAS tAH P/N:PM1128 REV. 1.1, MAR. 28, 2005 39 MX26LV800AT/AB FIGURE 18. ID CODE READ TIMING WAVEFORM VCC 3V VID VIH VIL VIH VIL tACC VIH tACC ADD A9 ADD A0 A1 VIL ADD A2-A8 A10-A18 CE# VIH VIL VIH VIL WE# VIH VIL tCE OE# VIH VIL tOE tDF tOH tOH VIH DATA Q0-Q15 DATA OUT VIL DATA OUT DAH/5BH (Byte) 22DAH/225BH (Word) C2H/00C2H P/N:PM1128 REV. 1.1, MAR. 28, 2005 40 MX26LV800AT/AB QUERY COMMAND AND COMMON FLASH INTERFACE (CFI) MODE ( for MX26LV800AT/ AB) MX26LV800AT/AB is capable of operating in the CFI mode. This mode all the host system to determine the manufacturer of the device such as operating parameters and configuration. Two commands are required in CFI mode. Query command of CFI mode is placed first, then the Reset command exits CFI mode. These are described in Table 14. The single cycle Query command is valid only when the device is in the Read mode, including Erase Suspend, Standby mode, and Read ID mode; however, it is ignored otherwise. The Reset command exits from the CFI mode to the Read mode, or Erase Suspend mode, or read ID mode. The command is valid only when the device is in the CFI mode. TABLE 14-1. CFI mode: Identification Data Values (All values in these tables are in hexadecimal) Description Address (Byte Mode) Query-unique ASCII string "QRY" 20 22 24 Primary vendor command set and control interface ID code 26 28 Address for primary algorithm extended query table 2A 2C Alternate vendor command set and control interface ID code (none) 2E 30 Address for secondary algorithm extended query table (none) 32 34 Address (Word Mode) 10 11 12 13 14 15 16 17 18 19 1A Data 0051 0052 0059 0002 0000 0040 0000 0000 0000 0000 0000 TABLE 14-2. CFI Mode: System Interface Data Values (All values in these tables are in hexadecimal) Description VCC supply, minimum (3.0V) VCC supply, maximum (3.6V) VPP supply, minimum (none) VPP supply, maximum (none) Typical timeout for single word/byte write (2N us) Typical timeout for Minimum size buffer write (2N us) Typical timeout for individual block erase (2N ms) Typical timeout for full chip erase (2N ms) Maximum timeout for single word/byte write times (2N X Typ) Maximum timeout for buffer write times (2N X Typ) Maximum timeout for individual block erase times (2N X Typ) Maximum timeout for full chip erase times (not supported) P/N:PM1128 Address (Byte Mode) 36 38 3A 3C 3E 40 42 44 46 48 4A 4C Address (Word Mode) 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 Data 0030 0036 0000 0000 0004 0000 000A 0000 0005 0000 0004 0000 REV. 1.1, MAR. 28, 2005 41 MX26LV800AT/AB TABLE 14-3. CFI Mode: Device Geometry Data Values (All values in these tables are in hexadecimal) Description Device size (2N bytes) Flash device interface code (refer to the CFI publication 100) Maximum number of bytes in multi-byte write (not supported) Number of erase block regions Erase block region 1 information (refer to the CFI publication 100) Address (Byte Mode) 4E 50 52 54 56 58 5A 5C 5E 60 62 64 66 68 6A 6C 6E 70 72 74 76 78 Address (Word Mode) 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C Data 0014 0002 0000 0000 0000 0004 0000 0000 0040 0000 0001 0000 0020 0000 0000 0000 0080 0000 000E 0000 0000 0001 Erase block region 2 information Erase block region 3 information Erase block region 4 information TABLE 14-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values (All values in these tables are in hexadecimal) Description Query-unique ASCII string "PRI" Address (Byte Mode) 80 82 84 86 88 8A 8C 8E 90 92 94 96 98 Address (Word Mode) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C Data 0050 0052 0049 0031 0030 0000 0000 0001 0001 0004 0000 0000 0000 Major version number, ASCII Minor version number, ASCII Address sensitive unlock (0=required, 1= not required) Erase suspend (2= to read and write) Sector protect (N= # of sectors/group) Temporary sector unprotected (1=supported) Sector protect/unprotected scheme Simultaneous R/W operation (0=not supported) Burst mode type (0=not supported) Page mode type (0=not supported) P/N:PM1128 REV. 1.1, MAR. 28, 2005 42 MX26LV800AT/AB TABLE 15. ERASE AND PROGRAMMING PERFORMANCE (1) LIMITS PARAMETER Sector Erase Time Chip Erase Time Byte Programming Time Word Programming Time Chip Programming Time (Word/Byte Mode) Erase/Program Cycles 2K (6) MIN. TYP. (2) 2.4 40 55 70 35 MAX. (3) 15 160 220 280 70 UNITS sec sec us us sec Cycles Note: 1. Not 100% tested. 2. Typical program and erase times assume the following conditions : 25° C, 3.3V VCC. Programming spec. assume that all bits are programmed to checkerboard pattern. 3. Maximum values are measured at VCC=3.0V, worst case temperature. Maximum values are up to including 2K program/erase cycles. 4. System-level overhead is the time required to execute the command sequences for the all program command. 5. Excludes 00H programming prior to erasure. (In the pre-programming step of the embedded erase algorithm, all bits are programmed to 00H before erasure) 6. Min. erase/program cycles is under : 3.3V VCC, 25° C, checkerboard pattern conditions, and without baking process. TABLE 16. LATCH-UP CHARACTERISTICS MIN. Input Voltage with respect to GND on ACC, OE#, RESET#, A9 Input Voltage with respect to GND on all power pins, Address pins, CE# and WE# Input Voltage with respect to GND on all I/O pins Current Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. -1.0V -1.0V -1.0V -100mA MAX. 12V VCC + 1.0V VCC + 1.0V +100mA P/N:PM1128 REV. 1.1, MAR. 28, 2005 43 MX26LV800AT/AB ORDERING INFORMATION PLASTIC PACKAGE PART NO. MX26LV800ATTC-55 MX26LV800ABTC-55 MX26LV800ATTC-70 MX26LV800ABTC-70 MX26LV800ATXBC-55 MX26LV800ABXBC-55 MX26LV800ATXBC-70 MX26LV800ABXBC-70 MX26LV800ATXEC-55 MX26LV800ABXEC-55 MX26LV800ATXEC-70 MX26LV800ABXEC-70 ACCESS TIME (ns) 55 55 70 70 55 55 70 70 55 55 70 70 OPERATING Current MAX. (mA) 30 30 30 30 30 30 30 30 30 30 30 30 STANDBY Current MAX. (uA) 100 100 100 100 100 100 100 100 100 100 100 100 PACKAGE 48 Pin TSOP (Normal Type) 48 Pin TSOP (Normal Type) 48 Pin TSOP (Normal Type) 48 Pin TSOP (Normal Type) 48 Ball CSP (Ball size:0.3mm) 48 Ball CSP (Ball size:0.3mm) 48 Ball CSP (Ball size:0.3mm) 48 Ball CSP (Ball size:0.3mm) 48 Ball CSP (Ball size:0.4mm) 48 Ball CSP (Ball size:0.4mm) 48 Ball CSP (Ball size:0.4mm) 48 Ball CSP (Ball size:0.4mm) Remark P/N:PM1128 REV. 1.1, MAR. 28, 2005 44 MX26LV800AT/AB PART NO. MX26LV800ATTC-55G MX26LV800ABTC-55G MX26LV800ATTC-70G MX26LV800ABTC-70G MX26LV800ATXBC-55G MX26LV800ABXBC-55G MX26LV800ATXBC-70G MX26LV800ABXBC-70G MX26LV800ATXEC-55G MX26LV800ABXEC-55G MX26LV800ATXEC-70G MX26LV800ABXEC-70G ACCESS TIME (ns) 55 55 70 70 55 55 70 70 55 55 70 70 OPERATING Current MAX. (mA) 30 30 30 30 30 30 30 30 30 30 30 30 STANDBY Current MAX. (uA) 100 100 100 100 100 100 100 100 100 100 100 100 PACKAGE 48 Pin TSOP (Normal Type) 48 Pin TSOP (Normal Type) 48 Pin TSOP (Normal Type) 48 Pin TSOP (Normal Type) 48 Ball CSP (Ball size:0.3mm) 48 Ball CSP (Ball size:0.3mm) 48 Ball CSP (Ball size:0.3mm) 48 Ball CSP (Ball size:0.3mm) 48 Ball CSP (Ball size:0.4mm) 48 Ball CSP (Ball size:0.4mm) 48 Ball CSP (Ball size:0.4mm) 48 Ball CSP (Ball size:0.4mm) Remark Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free P/N:PM1128 REV. 1.1, MAR. 28, 2005 45 MX26LV800AT/AB PACKAGE INFORMATION P/N:PM1128 REV. 1.1, MAR. 28, 2005 46 MX26LV800AT/AB 48-Ball CSP (for MX26LV800ATXBC/ABXBC) P/N:PM1128 REV. 1.1, MAR. 28, 2005 47 MX26LV800AT/AB 48-Ball CSP (for MX26LV800ATXEC/ABXEC) P/N:PM1128 REV. 1.1, MAR. 28, 2005 48 MX26LV800AT/AB REVISION HISTORY Revision No. Description 1.0 1. Removed "Preliminary" 1.1 1. Added Pb-free package option 2. Revised EPN description for 48-ball CSP package outline Page P1 P45 P47,48 Date NOV/08/2004 MAR/28/2005 P/N:PM1128 REV. 1.1, MAR. 28, 2005 49 M X26LV800AT/AB MACRONIX INTERNATIONAL CO., LTD. Headquarters: TEL:+886-3-578-6688 FAX:+886-3-563-2888 Europe Office : TEL:+32-2-456-8020 FAX:+32-2-456-8021 Hong Kong Office : TEL:+86-755-834-335-79 FAX:+86-755-834-380-78 Japan Office : Kawasaki Office : TEL:+81-44-246-9100 FAX:+81-44-246-9105 Osaka Office : TEL:+81-6-4807-5460 FAX:+81-6-4807-5461 Singapore Office : TEL:+65-6346-5505 FAX:+65-6348-8096 Taipei Office : TEL:+886-2-2509-3300 FAX:+886-2-2509-2200 MACRONIX AMERICA, INC. TEL:+1-408-262-8887 FAX:+1-408-262-8810 http : //www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.