MX28F640C3TXAC-90

ADVANCED INFORMATION MX28F640C3T/B 64M-BIT [4M x16] CMOS SINGLE VOLTAGE 3V ONLY FLASH MEMORY FEATURES • Bit Organization: 4,194,304 x 16 • Single power supply operation - 3.0V only operation for read, erase and program operation - VCC=VCCQ=2.7~3.6V - Operating temperature:-40° C~85° C • Fast access time : 90/120ns • Low power consumption - 9mA maximum active read current, f=5MHz (CMOS input) - 21mA program erase current maximum (VPP=1.65~3.6V) - 7uA typical standby current under power saving mode • Sector architecture - Sector Erase (Sector structure : 4Kword x 2 (boot sectors), 4Kword x 6 (parameter sectors), 32Kword x 127 (parameter sectors) - Top/Bottom Boot • Auto Erase (chip & sector) and Auto Program - Automatically program and verify data at specified address • Automatic Suspend Enhance - Word write suspend to read - Sector erase suspend to word write - Sector erase suspend to read register report • Automatic sector erase, full chip erase, word write and sector lock/unlock configuration • Status Reply - Detection of program and erase operation completion. - Command User Interface (CUI) - Status Register (SR) • Data Protection Performance - Include boot sectors and parameter and main sectors to be block/unblock • 100,000 minimum erase/program cycles • Common Flash Interface (CFI) • 128-bit Protection Register - 64-bit Unique Device Identifier - 64-bit User-Programmable • Latch-up protected to 100mA from -1V to VCC+1V • Package type: - 48-pin TSOP (12mm x 20mm) - 48-ball CSP (11mm x 12mm) GENERAL DESCRIPTION The MX28F640C3T/B is a 64-mega bit Flash memory organized as 4M words of 16 bits. The 1M word of data is arranged in eight 4Kword boot and parameter sectors, and 127 32Kword main sector which are individually erasable. MXIC's Flash memories offer the most costeffective and reliable read/write non-volatile random access memory. The MX28F640C3T/B is packaged in 48pin TSOP and 48-ball CSP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers. The standard MX28F640C3T/B offers access time as fast as 90ns, allowing operation of high-speed microprocessors without wait states. MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX28F640C3T/B uses a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility. MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and programming P/N:PM0900 REV. 0.6, AUG. 20, 2003 1 MX28F640C3T/B mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produces reliable cycling. The MX28F640C3T/B uses a 2.7V~3.6V VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V. The dedicated VPP pin gives complete data protection when VPP< VPPLK. A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for erase, full chip erase, word write and sector lock/unlock configuration operations. A sector erase operation erases one of the device's 32Kword sectors typically within 1.0s, 4K-word sectors typically within 0.5s independent of other sectors. Each sector can be independently erased minimum 100,000 times. Sector erase suspend mode allows system software to suspend sector erase to read or write data from any other sector. Writing memory data is performed in word increments of the device's 32K-word sectors typically within 0.8s and 4K-word sectors typically within 0.1s. Word program suspend mode enables the system to read data or execute code from any other memory array location. MX28F640C3T/B features with individual sectors locking by using a combination of bits thirty-nine sector lockbits and WP, to lock and unlock sectors. The status register indicates when the WSM's sector erase, full chip erase, word program or lock configuration operation is done. The access time is 90/120ns (tELQV) over the operating temperature range (-40° to +80° and VCC supply C C) voltage range of 2.7V~3.6V. MX28F640C3T/B's power saving mode feature substantially reduces active current when the device is in static mode (addresses not switching). In this mode, the typical ICCS current is 7uA (CMOS) at 3.0V VCC. As CE and RESET are at VCC, ICC CMOS standby mode is enabled. When RESET is at GND, the reset mode is enabled which minimize power consumption and provide data write protection. A reset time (tPHQV) is required from RESET switching high until outputs are valid. Similarly, the device has a wake time (tPHEL) from RESET-high until writes to the CUI are recognized. With RESET at GND, the WSM is reset and the status register is cleared. P/N:PM0900 REV. 0.6, AUG. 20, 2003 2 MX28F640C3T/B BLOCK DIAGRAM Q0~Q7 Output Buffer Input Buffer I/O Logic VCC Output Multiplexer Identifier Register Data Register CE Command User Interface WE OE RESET WP Status Register Data Comparator Write State Machine A0~A21 Input Buffer Y Decoder Y-Gating Program/Erase Voltage Switch VPP VCC Main Sector 125 Boot Sector 0 Boot Sector 1 Parameter Sector Parameter Sector Parameter Sector Parameter Sector Parameter Sector Parameter Sector Main Sector 126 GND 0 1 2 3 4 5 Main Sector 0 Main Sector 1 Address Latch X Decoder 32K-Word Main Sector x127 ....... Address Counter ....... P/N:PM0900 REV. 0.6, AUG. 20, 2003 3 MX28F640C3T/B PIN CONFIGURATIONS 48 TSOP (Standard Type) (12mm x 20mm) A15 A14 A13 A12 A11 A10 A9 A8 A21 A20 WE RESET VPP WP A19 A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 VCCQ GND Q15 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC Q11 Q3 Q10 Q2 Q9 Q1 Q8 Q0 OE GND CE A0 MX28F640C3T/B 48 Ball CSP (11 mm x 12 mm) Top View, Ball Down (Ball Pitch=0.75mm, Ball Width=0.35mm) A1 A13 B1 A14 C1 A15 D1 A16 E1 VCCQ F1 GND A2 A11 B2 A10 C2 A12 D2 Q14 E2 Q15 F2 Q7 A3 A8 B3 WE C3 A9 D3 Q5 E3 Q6 F3 Q13 A4 VPP B4 RESET C4 A21 D4 Q11 E4 Q12 F4 Q4 A5 WP B5 A18 C5 A20 D5 Q2 E5 Q3 F5 VCC A6 A19 B6 A17 C6 A6 D6 Q8 E6 Q9 F6 Q10 A7 A7 B7 A5 C7 A3 D7 CE E7 Q0 F7 Q1 A8 A4 B8 A2 C8 A1 12 mm D8 A0 E8 GND F8 OE 11 mm P/N:PM0900 REV. 0.6, AUG. 20, 2003 4 MX28F640C3T/B Table 1. Pin Description Symbol A0-A21 Type input Description and Function Address inputs for memory address. Data pin float to high-impedance when the chip is deselected or outputs are disable. Addresses are internally latched during a write or erase cycle. Data inputs/outputs: Inputs array data on the second CE and WE cycle during a program command. Data is internally latched. Outputs array and configuration data. The data pin float to tri-state when the chip is de-selected. Activates the device's control logic, input buffers, and sense amplifiers. CE high deselects the memory device and reduce power consumption to standby level. CE is active low. Reset Deep Power Down: when RESET=VIL, the device is in reset/deep power down mode, which drives the outputs to High Z, resets the WSM and minimizes current level. When RESET=VIH, the device is normal operation. When RESET transition the device defaults to the read array mode. Write Enable: to control write to CUI and array sector. WR=VIL becomes active. The data and address is latched WE on the rising edge of the second WE pulse. Program/Erase Power Supply:(1.65V~3.6V) Lower VPP2 2 2 1 2 2 1 1 2 2 2 2 6 5 3,4 2,7 3 3 Notes (1) Write Write Write Write Write Write Write Write Write Write Write Write Write First Bus Cycle Operation Address (2) X X X X X X X X X X X X X Data (3) FFH 90H 98H 70H 50H 20H 40H/10H B0H D0H 60H 60H 60H C0H Write Write Write Write BA BA BA PA 01H D0H 2FH PPH Write Write BA WA D0H WD Read Read Read IA QA X ID QD SRD Second Bus Cycle Operation Address (1) (2) Data (3) Notes: 1. Bus operation are defined in Table 2 and referred to AC Timing Waveform. 2. X=Any address within device IA=ID-Code Address (refer to Table 4) BA=Sector within the sector being erased WA=Address of memory location to be written QA=Query Address, QD=Query Data 3. Data is latched from the rising edge of WE or CE (whichever goes high first) SRD=Data read from status register, see Table 6 for description of the status register bits. WD=Data to be written at location WA. ID=Data read from identifier codes 4. Following the Read configuration codes command, read operation access manufacturer, device codes, sector lock/unlock codes, see chapter 4.2. 5. Either 40H or 10H are recognized by the WSM as word write setup. 6. The sector unlock operation simultaneously clear all sector lock. 7. Read Query Command is read for CFI query information. P/N:PM0900 REV. 0.6, AUG. 20, 2003 13 MX28F640C3T/B 4.1 Read Array Command Upon initial device power-up and after exit from reset mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written. Once the internal WSM has started a sector erase, word write or sector lock configuration the device will not recognize the Read Array command until the WSM completes its operation unless the WSM is suspended via a Sector Erase Suspend or Word Write Suspend command. If RESET=VIL device is in read Read Array command mode, this read operation no longer requires VPP. The Read Array command functions independently of the VPP voltage and RESET can be VIH. 4.3 Read Status Register Command CUI writes read status command (70H). The status register may be read to determine when a sector erase, word write or lock-bit configuration is complete and whether the operation completed successfully. (refer to table 6) It may be read at any time by writing the Read Status Register command. After writing this command, all subsequent read operations output data from the status register until another valid command is written. The status register contents are latched on the falling edge of CE or OE, whichever occurs. CE or OE must toggle to VIH before further reads to update the status register latch. The Read Status Register command functions independently of the VPP voltage. RESET can be VIH. 4.4 Clear Status Register Command 4.2 Read Configuration Codes Command The configuration code operation is initiated by writing the Read Configuration Codes command (90H). To return to read array mode, write the Read Array Command (FFH). Following the command write, read cycles from addresses shown in Table 4 retrieve the manufacturer, device, sector lock configuration codes (see Table 4 for configuration code values). To terminate the operation, write another valid command. Like the Read Array command, the Read Configuration Codes command functions independently of the VPP voltage and RESET can be VIH. Following the Read Configuration Codes command, the information is shown: Status register bits SR.5, SR.4, SR.3 or SR.1 are set to "1"s by the WSM and can only be reset by the Clear Status Register command (50H). These bits indicate various failure conditions (see Table 6). By allowing system software to reset these bits, several operations (such as cumulatively erasing multiple sectors or writing several words in sequence) may be performed. The status register may be polled to determine if an error occurred during the sequence. To clear the status register, the Clear Status Register command (50H) is written on CUI. It functions independently of the applied VPP Voltage. RESET can be VIH. This command is not functional during sector erase or word write suspend modes. Table 4: ID Code Code Manufacturer Code Device Code - Sector is unlocked - Sector is locked - Sector is locked-down Protection Register Lock Protection Register 80 81-88 Address (A19-A0) 00000H 00001H Data (Q15-Q0) 00C2H 88CC/88CDH LocK Q0=0 Q0=1 Q1=1 PR-LK PR Sector Lock Configuration XX002H P/N:PM0900 REV. 0.6, AUG. 20, 2003 14 MX28F640C3T/B 4.5 Sector Erase Command Erase is executed one sector at a time and initiated by a two-cycle command. A sector erase setup is first written (20H), followed by a sector erase confirm (D0H). This command sequence requires appropriate sequencing and an address within the sector to be erased. Sector preconditioning, erase, and verify are handled internally by the WSM. After the two-cycle sector erase sequence is written, the device automatically outputs status register data when read (see Figure 8). The CPU can detect sector erase completion by analyzing the output data of the status register bit SR.7. When the sector erase is complete, status register bit SR.5 should be checked. If a sector erase error is detected, the status register should be cleared before system software attempts corrective actions. The CUI remains in read status register mode until a new command is issued. This two-step command sequence of set-up followed by execution ensures that sector contents are not accidentally erased. An invalid sector Erase command sequence will result in both status register bits SR.4 and SR.5 being set to "1". Also, reliable sector erasure can only occur when 2.7V~3.6V and VPP=VPPH1/2. In the absence of this high voltage, sector contents are protected against erasure. If sector erase is attempted while VPP