MX29F040CQI-70

MX29F040C 4M-BIT [512K x 8] CMOS SINGLE VOLTAGE 5V ONLY EQUAL SECTOR FLASH MEMORY FEATURES • 524,288 x 8 only • Single power supply operation - 5.0V only operation for read, erase and program operation • Fast access time: 55/70/90ns • Compatible with MX29F040 device • Low power consumption - 30mA maximum active current(5MHz) - 1uA typical standby current • Command register architecture - Byte Programming (9us typical) - Sector Erase 8 equal sectors of 64K-Byte each • Auto Erase (chip & sector) and Auto Program - Automatically erase any combination of sectors with Erase Suspend capability - Automatically program and verify data at specified address • Erase suspend/Erase Resume - Suspends an erase operation to read data from, or program data to, another sector that is not being erased, then resumes the erase • Status Reply - Data# Polling & Toggle bit for detection of program and erase cycle completion • Sector protect/chip unprotect for 5V only system • Sector protection - Hardware method to disable any combination of sectors from program or erase operations - Temporary sector unprotect allows code changes in previously locked sectors • 100,000 minimum erase/program cycles • 100,000 minimum erase/program cycles • Latch-up protected to 100mA from -1V to VCC+1V • Low VCC write inhibit is equal to or less than 3.2V • Package type: - 32-pin PLCC, TSOP or PDIP - All Pb-free devices are RoHS Compliant • Compatibility with JEDEC standard - Pinout and software compatible with single-power supply Flash • 20 years data retention GENERAL DESCRIPTION The MX29F040C is a 4-mega bit Flash memory organized as 512K bytes of 8 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write nonvolatile random access memory. The MX29F040C is packaged in 32-pin PLCC, TSOP, PDIP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers. The standard MX29F040C offers access time as fast as 55ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX29F040C has separate chip enable (CE#) and output enable (OE#) controls. MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29F040C uses a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility. MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and program mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The MX29F040C uses a 5.0V±10% VCC supply to perform the High Reliability Erase and auto Program/ Erase algorithms. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V. P/N:PM1201 REV. 1.0, DEC. 20, 2005 1 MX29F040C PIN CONFIGURATIONS 32 PDIP A18 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE# A17 A14 A13 A8 A9 A11 OE# A10 CE# Q7 Q6 Q5 Q4 Q3 32 PLCC WE# VCC A12 A15 A16 A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 Q0 5 4 1 32 30 29 A14 A13 A8 A9 MX29F040C 9 MX29F040C 25 A11 OE# A10 CE# 13 14 Q1 Q2 GND 17 Q3 Q4 Q5 21 20 Q6 Q7 32 TSOP (Standard Type) (8mm x 20mm) A11 A9 A8 A13 A14 A17 WE# VCC A18 A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE# A10 CE# Q7 Q6 Q5 Q4 Q3 GND Q2 Q1 Q0 A0 A1 A2 A3 MX29F040C PIN DESCRIPTION SYMBOL A0~A18 Q0~Q7 CE# WE# OE# GND VCC PIN NAME Address Input Data Input/Output Chip Enable Input Write Enable Input Output Enable Input Ground Pin +5.0V single power supply SECTOR STRUCTURE MX29F040C SECTOR ADDRESS TABLE Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 A18 0 0 0 0 1 1 1 1 A17 0 0 1 1 0 0 1 1 A16 0 1 0 1 0 1 0 1 Address Range 00000h-0FFFFh 10000h-1FFFFh 20000h-2FFFFh 30000h-3FFFFh 40000h-4FFFFh 50000h-5FFFFh 60000h-6FFFFh 70000h-7FFFFh Note: All sectors are 64 Kbytes in size. P/N:PM1201 REV. 1.0, DEC. 20, 2005 2 MX29F040C BLOCK DIAGRAM WRITE CE# OE# WE# CONTROL INPUT LOGIC HIGH VOLTAGE MACHINE (WSM) PROGRAM/ERASE STATE X-DECODER STATE FLASH ARRAY ARRAY REGISTER ADDRESS LATCH A0-A18 AND BUFFER SENSE AMPLIFIER Y-DECODER Y-PASS GATE SOURCE HV COMMAND DATA DECODER PGM DATA HV COMMAND DATA LATCH PROGRAM DATA LATCH Q0-Q7 I/O BUFFER P/N:PM1201 REV. 1.0, DEC. 20, 2005 3 MX29F040C AUTOMATIC PROGRAMMING The MX29F040C is byte programmable using the Automatic Programming algorithm. The Automatic Programming algorithm makes the external system do not need to have time out sequence nor to verify the data programmed. The typical chip programming time at room temperature of the MX29F040C is less than 4.5 seconds. the device automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. A status bit toggling between consecutive read cycles provides feedback to the user as to the status of the programming operation. Register contents serve as inputs to an internal statemachine which controls the erase and programming circuitry. During write cycles, the command register internally latches address and data needed for the programming and erase operations. During a system write cycle, addresses are latched on the falling edge of WE# or CE#, whichever happens later, and data are latched on the rising edge of WE# or CE#, whichever happens first. MXIC's Flash technology combines years of EPROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The MX29F040C electrically erases all bits simultaneously using Fowler-Nordheim tunneling. The bytes are programmed by using the EPROM programming mechanism of hot electron injection. During a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. During a Sector Erase cycle, the command register will only respond to Erase Suspend command. After Erase Suspend is completed, the device stays in read mode. After the state machine has completed its task, it will allow the command register to respond to its full command set. AUTOMATIC CHIP ERASE The entire chip is bulk erased using 10 ms erase pulses according to MXIC's Automatic Chip Erase algorithm. Typical erasure at room temperature is accomplished in less than 4 second. The Automatic Erase algorithm automatically programs the entire array prior to electrical erase. The timing and verification of electrical erase are controlled internally within the device. AUTOMATIC SECTOR ERASE The MX29F040C is sector(s) erasable using MXIC's Auto Sector Erase algorithm. Sector erase modes allow sectors of the array to be erased in one erase cycle. The Automatic Sector Erase algorithm automatically programs the specified sector(s) prior to electrical erase. The timing and verification of electrical erase are controlled internally within the device. AUTOMATIC PROGRAMMING ALGORITHM MXIC's Automatic Programming algorithm require the user to only write program set-up commands (including 2 unlock write cycle and A0H) and a program command (program data and address). The device automatically times the programming pulse width, provides the program verification, and counts the number of sequences. A status bit similar to Data# Polling and a status bit toggling between consecutive read cycles, provide feedback to the user as to the status of the programming operation. AUTOMATIC ERASE ALGORITHM MXIC's Automatic Erase algorithm requires the user to write commands to the command register using standard microprocessor write timings. The device will automatically pre-program and verify the entire array. Then P/N:PM1201 REV. 1.0, DEC. 20, 2005 4 MX29F040C TABLE 1. SOFTWARE COMMAND DEFINITIONS First Bus Command Reset Read Read Silicon ID Sector Protect Verify Program Chip Erase Sector Erase Sector Erase Suspend Sector Erase Resume Unlock for sector protect/unprotect Bus Cycle 1 1 4 4 4 6 6 1 1 6 Cycle Addr XXXH RA 555H 555H 555H 555H 555H XXXH XXXH 555H Data F0H RD AAH AAH AAH AAH AAH B0H 30H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 20H 2AAH 55H 2AAH 55H 2AAH 55H 2AAH 55H 2AAH 55H 555H 90H 555H 90H 555H A0H 555H 80H 555H 80H ADI 02 PA DDI 01H PD 2AAH 55H 2AAH 55H 555H 10H SA 30H (SA)X 00H Second Bus Cycle Addr Third Bus Cycle Data Addr Fourth Bus Cycle Data Addr Fifth Bus Cycle Data Addr Data Sixth Bus Cycle Addr Data 555H AAH 555H AAH Note: 1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacture code,A1=0, A0 = 1 for device code A2-A18=Do not care. (Refer to table 3) DDI = Data of Device identifier : C2H for manufacture code, A4H for device code. X = X can be VIL or VIH RA=Address of memory location to be read. RD=Data to be read at location RA. 2. PA = Address of memory location to be programmed. PD = Data to be programmed at location PA. SA = Address to the sector to be erased. 3. The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 . Address bit A11~A18=X=Don't care for all address commands except for Program Address (PA) and Sector Address (SA). Write Sequence may be initiated with A11~A18 in either state. 4. For Sector Protect Verify Operation : If read out data is 01H, it means the sector has been protected. If read out data is 00H, it means the sector is still not being protected. COMMAND DEFINITIONS Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. Table 1 defines the valid register command sequences. Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Either of the two reset command sequences will reset the device (when applicable). P/N:PM1201 REV. 1.0, DEC. 20, 2005 5 MX29F040C TABLE 2. MX29F040C BUS OPERATION Pins Mode Read Silicon ID Manufacturer Code(1) Read Silicon ID Device Code(1) Read Standby Output Disable Write Sector Protect without 12V system (6) Chip Unprotect without 12V system (6) Verify Sector Protect/Unprotect without 12V system (7) Reset X X X X X X X HIGH Z L L H X H X H Code(5) L H L X X H H X L H L L L L X H H H H X H L L A0 X X A0 X A1 X X A1 X A6 X X A6 L A9 X X A9 H DOUT HIGH Z HIGH Z DIN(3) X L L H H L X VID(2) A4H CE# L OE# L WE# H A0 L A1 L A6 X A9 VID(2) Q0 ~ Q7 C2H Notes : 1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1. 2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V. 3. Refer to Table 1 for valid Data-In during a write operation. 4. X can be VIL or VIH. 5. Code=00H means unprotected. Code=01H means protected. A18~A16=Sector address for sector protect. 6. Refer to sector protect/unprotect algorithm and waveform. Must issue "unlock for sector protect/unprotect" command before "sector protect/unprotect without 12V system" command. 7. The "verify sector protect/unprotect without 12V system" is only following "Sector protect/unprotect without 12V system" command. P/N:PM1201 REV. 1.0, DEC. 20, 2005 6 MX29F040C READ/RESET COMMAND The read or reset operation is initiated by writing the read/ reset command sequence into the command register. Microprocessor read cycles retrieve array data. The device remains enabled for reads until the command register contents are altered. If program-fail or erase-fail happen, the write of F0H will reset the device to abort the operation. A valid command must then be written to place the device in the desired state. SET-UP AUTOMATIC CHIP/SECTOR ERASE Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command 80H. Two more "unlock" write cycles are then followed by the chip erase command 10H. The Automatic Chip Erase does not require the device to be entirely pre-programmed prior to executing the Automatic Chip Erase. Upon executing the Automatic Chip Erase, the device will automatically program and verify the entire memory for an all-zero data pattern. When the device is automatically verified to contain an all-zero pattern, a self-timed chip erase and verify begin. The erase and verify operations are completed when the data on Q7 is "1" at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations. When using the Automatic Chip Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required). If the Erase operation was unsuccessful, the data on Q5 is "1"(see Table 4), indicating the erase operation exceed internal timing limit. The automatic erase begins on the rising edge of the last WE# or CE#, whichever happens first pulse in the command sequence and terminates when the data on Q7 is "1" and the data on Q6 stops toggling for two consecutive read cycles, at which time the device returns to the Read mode. SILICON-ID-READ COMMAND Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacturer and device codes must be accessible while the device resides in the target system. PROM programmers typically access signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto address lines is not generally desired system design practice. The MX29F040C contains a Silicon-ID-Read operation to supplement traditional PROM programming methodology. The operation is initiated by writing the read silicon ID command sequence into the command register. Following the command write, a read cycle with A1=VIL,A0=VIL retrieves the manufacturer code of C2H. A read cycle with A1=VIL, A0=VIH returns the device code of A4H for MX29F040C. TABLE 3. EXPANDED SILICON ID CODE Pins Manufacture code Device code for MX29F040C Sector Protection Verification A0 VIL VIH X X A1 VIL VIL VIH VIH Q7 1 1 0 0 Q6 1 0 0 0 Q5 0 1 0 0 Q4 0 0 0 0 Q3 0 0 0 0 Q2 0 1 0 0 Q1 1 0 0 0 Q0 0 0 1 0 Code (Hex) C2H A4H 01H (Protected) 00H(Unprotected) P/N:PM1201 REV. 1.0, DEC. 20, 2005 7 MX29F040C SECTOR ERASE COMMANDS The Automatic Sector Erase does not require the device to be entirely pre-programmed prior to executing the Automatic Set-up Sector Erase command and Automatic Sector Erase command. Upon executing the Automatic Sector Erase command, the device will automatically program and verify the sector(s) memory for an all-zero data pattern. The system is not required to provide any control or timing during these operations. When the sector(s) is automatically verified to contain an all-zero pattern, a self-timed sector erase and verify begin. The erase and verify operations are complete when the data on Q7 is "1" and the data on Q6 stops toggling for two consecutive read cycles, at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations. When using the Automatic Sector Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required). Sector erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the set-up command 80H. Two more "unlock" write cycles are then followed by the sector erase command 30H. The sector address is latched on the falling edge of WE# or CE#, whichever happens later, while the command (data) is latched on the rising edge of WE# or CE#, whichever happens first. Sector addresses selected are loaded into internal register on the sixth falling edge of WE# or CE#, whichever happens later. Each successive sector load cycle started by the falling edge of WE# or CE#, whichever happens later must begin within 30us from the rising edge of the preceding WE# or CE#, whichever happens first. Otherwise, the loading period ends and internal auto sector erase cycle starts. (Monitor Q3 to determine if the sector erase timer window is still open, see section Q3, Sector Erase Timer.) Any command other than Sector Erase (30H) or Erase Suspend (B0H) during the time-out period resets the device to read mode. TABLE 4. Write Operation Status Status Q7 Note1 Byte Program in Auto Program Algorithm Auto Erase Algorithm Erase Suspend Read In Progress Erase Suspended Mode (Erase Suspended Sector) Erase Suspend Read (Non-Erase Suspended Sector) Erase Suspend Program Byte Program in Auto Program Algorithm Exceeded Auto Erase Algorithm Time Limits Erase Suspend Program Q7# Toggle Q7# Toggle 0 Toggle Q7# Toggle 0 1 1 1 N/A N/A 1 N/A N/A No Toggle Toggle N/A Data Q7# Toggle 0 1 Toggle No Toggle Data Data Data Data Q6 Q5 Note2 0 0 0 N/A 1 N/A No Toggle Toggle Toggle Q3 Q2 Note: 1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits. See "Q5:Exceeded Timing Limits " for more information. P/N:PM1201 REV. 1.0, DEC. 20, 2005 8 MX29F040C ERASE SUSPEND This command only has meaning while the state machine is executing Automatic Sector Erase operation, and therefore will only be responded during Automatic Sector Erase operation. When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20us to suspend the erase operations. However, When the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After this command has been executed, the command register will initiate erase suspend mode. The state machine will return to read mode automatically after suspend is ready. At this time, state machine only allows the command register to respond to the Read Memory Array, Erase Resume and program commands. The system can determine the status of the program operation using the Q7 or Q6 status bits, just as in the standard program operation. After an erase-suspend program operation is complete, the system can once again read array data within non-suspended sectors. Once the Automatic Program command is initiated, the next WE# or CE# pulse causes a transition to an active programming operation. Addresses are latched on the falling edge, and data are internally latched on the rising edge of the WE# or CE#, whichever happens first pulse. The rising edge of WE# or CE#, whichever happens first also begins the programming operation. The system is not required to provide further controls or timings. The device will automatically provide an adequate internally generated program pulse and verify margin. If the program operation was unsuccessful, the data on Q5 is "1"(see Table 4), indicating the program operation exceed internal timing limit. The automatic programming operation is completed when the data read on Q6 stops toggling for two consecutive read cycles and the data on Q7 and Q6 are equivalent to data written to these two bits, at which time the device returns to the Read mode (no program verify command is required). DATA# POLLING-Q7 The MX29F040C also features Data# Polling as a method to indicate to the host system that the Automatic Program or Erase algorithms are either in progress or completed. While the Automatic Programming algorithm is in operation, an attempt to read the device will produce the complement data of the data last written to Q7. Upon completion of the Automatic Program Algorithm an attempt to read the device will produce the true data last written to Q7. The Data# Polling feature is valid after the rising edge of the fourth WE# or CE#, whichever happens first pulse of the four write pulse sequences for automatic program. While the Automatic Erase algorithm is in operation, Q7 will read "0" until the erase operation is competed. Upon completion of the erase operation, the data on Q7 will read "1". The Data# Polling feature is valid after the rising edge of the sixth WE# or CE#, whichever happens first pulse of six write pulse sequences for automatic chip/sector erase. The Data# Polling feature is active during Automatic Program/Erase algorithm or sector erase time-out. (see section Q3 Sector Erase Timer) ERASE RESUME This command will cause the command register to clear the suspend state and return back to Sector Erase mode but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect in all other conditions. Another Erase Suspend command can be written after the chip has resumed erasing. However, a 400us time delay must be required after the erase resume command, if the system implements an endless erase suspend/resume loop, or the number of erase suspend/resume is exceeded 1024 times. The erase times will be expended if the erase behavior always be suspended. SET-UP AUTOMATIC PROGRAM COMMANDS To initiate Automatic Program mode, A three-cycle command sequence is required. There are two "unlock" write cycles. These are followed by writing the Automatic Program command A0H. P/N:PM1201 REV. 1.0, DEC. 20, 2005 9 MX29F040C Q6:Toggle BIT I Toggle Bit I on Q6 indicates whether an Automatic Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# or CE#, whichever happens first pulse in the command sequence (prior to the program or erase operation), and during the sector time-out. During an Automatic Program or Erase algorithm operation, successive read cycles to any address cause Q6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, Q6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, Q6 toggles and returns to reading array data. If not all selected sectors are protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use Q6 and Q2 together to determine whether a sector is actively erasing or is erase suspended. When the device is actively erasing (that is, the Automatic Erase algorithm is in progress), Q6 toggling. When the device enters the Erase Suspend mode, Q6 stops toggling. However, the system must also use Q2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use Q7. If a program address falls within a protected sector, Q6 toggles for approximately 2us after the program command sequence is written, then returns to reading array data. Q6 also toggles during the erase-suspend-program mode, and stops toggling once the Automatic Program algorithm is complete. Table 4 shows the outputs for Toggle Bit I on Q6. the rising edge of the final WE# or CE#, whichever happens first pulse in the command sequence. Q2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But Q2 cannot distinguish whether the sector is actively erasing or is erase-suspended. Q6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sectors and mode information. Refer to Table 4 to compare outputs for Q2 and Q6. Reading Toggle Bits Q6/ Q2 Whenever the system initially begins reading toggle bit status, it must read Q7-Q0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on Q7-Q0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of Q5 is high (see the section on Q5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as Q5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that system initially determines that the toggle bit is toggling and Q5 has not gone high. The system may continue to monitor the toggle bit and Q5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. Q2:Toggle Bit II The "Toggle Bit II" on Q2, when used with Q6, indicates whether a particular sector is actively erasing (that is, the Automatic Erase algorithm is in process), or whether that sector is erase-suspended. Toggle Bit I is valid after P/N:PM1201 REV. 1.0, DEC. 20, 2005 10 MX29F040C Q5 Exceeded Timing Limits Q5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions Q5 will produce a "1". This time-out condition indicates that the program or erase cycle was not successfully completed. Data# Polling and Toggle Bit are the only operating functions of the device under this condition. If this time-out condition occurs during sector erase operation, it specifies that a particular sector is bad and it may not be reused. However, other sectors are still functional and may be used for the program or erase operation. The device must be reset to use other sectors. Write the Reset command sequence to the device, and then execute program or erase command sequence. This allows the system to continue to use the other active sectors in the device. If this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad or combination of sectors are bad. If this time-out condition occurs during the byte programming operation, it specifies that the entire sector containing that byte is bad and this sector may not be reused, (other sectors are still functional and can be reused). The time-out condition may also appear if a user tries to program a non blank location without erasing. In this case the device locks out and never completes the Automatic Algorithm operation. Hence, the system never reads a valid data on Q7 bit and Q6 never stops toggling. Once the Device has exceeded timing limits, the Q5 bit will indicate a "1". Please note that this is not a device failure condition since the device was incorrectly used. several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise. Q3 Sector Erase Timer After the completion of the initial sector erase command sequence, the sector erase time-out will begin. Q3 will remain low until the time-out is complete. Data# Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data# Polling or the Toggle Bit indicates the device has been written with a valid erase command, Q3 may be used to determine if the sector erase timer window is still open. If Q3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data# Polling or Toggle Bit. If Q3 is low ("0"), the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of Q3 prior to and following each subsequent sector erase command. If Q3 were high on the second status check, the command may not have been accepted. WRITE PULSE "GLITCH" PROTECTION Noise pulses of less than 5ns (typical) on CE# or WE# will not initiate a write cycle. LOGICAL INHIBIT Writing is inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle CE# and WE# must be a logical zero while OE# is a logical one. DATA PROTECTION The MX29F040C is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates POWER SUPPLY DECOUPLING In order to reduce power switching effect, each device should have a 0.1uF ceramic capacitor connected between its VCC and GND. P/N:PM1201 REV. 1.0, DEC. 20, 2005 11 MX29F040C POWER-UP SEQUENCE The MX29F040C powers up in the Read only mode. In addition, the memory contents may only be altered after successful completion of the predefined command sequences. SECTOR PROTECTION WITHOUT 12V SYSTEM The MX29F040C also feature a sector protection method in a system without 12V power supply. The programming equipment do not need to supply 12 volts to protect sectors. The details are shown in sector protect algorithm and waveform. CHIP UNPROTECT WITHOUT 12V SYSTEM The MX29F040C also feature a chip unprotection method in a system without 12V power supply. The programming equipment do not need to supply 12 volts to unprotect all sectors. The details are shown in chip unprotect algorithm and waveform. P/N:PM1201 REV. 1.0, DEC. 20, 2005 12 MX29F040C CAPACITANCE (TA = 25oC, f = 1.0 MHz) SYMBOL CIN1 CIN2 COUT PARAMETER Input Capacitance Control Pin Capacitance Output Capacitance MIN. TYP MAX. 8 12 12 UNIT pF pF pF CONDITIONS VIN = 0V VIN = 0V VOUT = 0V READ OPERATION DC CHARACTERISTICS (TA = -40oC to 85oC, VCC = 5V±10%) SYMBOL ILI ILO ISB1 ISB2 ICC1 ICC2 VIL VIH VOL VOH1 VOH2 Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage(TTL) Output High Voltage(CMOS) 2.4 VCC-0.4 -0.3(NOTE 1) 0.7xVCC Operating VCC current PARAMETER Input Leakage Current Output Leakage Current Standby VCC current 1 MIN. TYP MAX. 1 10 1 5 30 50 0.8 VCC + 0.3 0.45 UNIT uA uA mA uA mA mA V V V V V IOL = 2.1mA, VCC=VCC MIN IOH = -2mA, VCC=VCC MIN IOH = -100uA,VCC=VCC MIN CONDITIONS VIN = GND to VCC VOUT = GND to VCC CE# = VIH CE# = VCC + 0.3V IOUT = 0mA, f=5MHz IOUT = 0mA, f=10MHz Notes : 1. VIL min. = -1.0V for pulse width is equal to or less than 50 ns. VIL min. = -2.0V for pulse width is equal to or less than 20 ns. 2. VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns. If VIH is over the specified maximum value, read operation cannot be guaranteed. P/N:PM1201 REV. 1.0, DEC. 20, 2005 13 MX29F040C AC CHARACTERISTICS (TA =-40oC to 85oC, VCC = 5V±10%) 29F040C-55 29F040C-70 29F040C-90 SYMBOL PARAMETER tACC tCE tOE tDF tOH Address to Output Delay CE# to Output Delay OE# to Output Delay OE# High to Output Float (Note 1) Address to Output hold MIN. MAX. MIN. 55 55 30 MAX. 70 70 30 MIN. MAX. 90 90 35 0 0 20 UNIT ns ns ns ns ns Conditions CE#=OE#=VIL OE#=VIL CE#=VIL CE#=VIL CE#=OE#=VIL 0 0 20 0 0 20 TEST CONDITIONS: • Input pulse levels: 0.45V/0.7xVCC for 70ns & 90ns, 0V/0.7xVCC for 55ns • Input rise and fall times: is equal to or less than 10ns for 70ns & 90ns, 5ns for 55ns • Output load: 1 TTL gate + 100pF (Including scope and jig) for 70ns & 90ns, 1TTLgate+30pF for 55ns max. • Reference levels for measuring timing: 0.8V, 2.0V for 70ns & 90ns,1.5V for 55ns Note : 1. tDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. P/N:PM1201 REV. 1.0, DEC. 20, 2005 14 MX29F040C ABSOLUTE MAXIMUM RATINGS RATING Ambient Operating Temperature Storage Temperature Applied Applied Input Voltage Applied Output Voltage VCC to Ground Potential A9 -0.5V to 7.0V -0.5V to 7.0V -0.5V to 7.0V -0.5V to 13.5V VALUE -40oC to 85oC -65oC to 125oC NOTICE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. NOTICE: Specifications contained within the following tables are subject to change. Ambient Temperature with Power -55oC to 125oC READ TIMING WAVEFORMS VIH Addresses VIL ADD Valid tCE VIH CE# VIL WE# VIH VIL VIH VIL tACC tOH tOE tDF OE# Outputs VOH VOL HIGH Z DATA Valid HIGH Z COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION DC CHARACTERISTICS (TA = -40oC to 85oC, VCC = 5V±10%) SYMBOL ICC1 (Read) ICC2 ICC3 (Program) ICC4 (Erase) ICCES NOTES: 1. VIL min. = -0.6V for pulse width is equal to or less than 20ns. 2. If VIH is over the specified maximum value, programming operation cannot be guaranteed. 3. ICCES is specified with the device de-selected. If the device is read during erase suspend mode, current draw is the sum of ICCES and ICC1 or ICC2. 4. All current are in RMS unless otherwise noted. P/N:PM1201 REV. 1.0, DEC. 20, 2005 PARAMETER Operating VCC Current MIN. TYP MAX. 30 50 50 50 UNIT mA mA mA mA mA CONDITIONS IOUT=0mA, f=5MHz IOUT=0mA, f=10MHz In Programming In Erase CE#=VIH, Erase Suspended VCC Erase Suspend Current 2 15 MX29F040C AC CHARACTERISTICS TA = -40oC to 85oC, VCC = 5V ± 10% Speed Option SYMBOL tOES tCWC tCEP tCEPH tAS tAH tDS tDH tCESC tDF tAETC tAETB tAVT tBAL tCH tCS PARAMETER OE# setup time Command programming cycle WE# programming pulse width WE# programming pulse width High Address setup time Address hold time Data setup time Data hold time CE# setup time before command write Output disable time (Note 1) Erase time in auto chip erase Erase time in auto sector erase Programming time in auto verify Sector address load time CE# Hold Time CE# setup to WE# going low MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MAX. TYP. MAX. TYP. MAX. TYP. MAX. MIN. MIN. MIN. 55(Note 2) 0 55 35 20 0 45 30 0 0 20 4 32 0.7 15 9 300 50 0 0 70 0 70 35 20 0 45 30 0 0 20 4 32 0.7 15 9 300 50 0 0 90 0 90 45 20 0 45 45 0 0 20 4 32 0.7 15 9 300 50 0 0 UNIT ns ns ns ns ns ns ns ns ns ns s s s s us us us ns ns Notes: 1. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven. 2. Under condition of VCC=5V±10%,CL=30pF,VIH/VIL=0.7xVCC/0V,VOH/VOL=1.5V/1.5V,IOL=2mA,IOH=2mA. P/N:PM1201 REV. 1.0, DEC. 20, 2005 16 MX29F040C SWITCHING TEST CIRCUITS DEVICE UNDER TEST 2.7K ohm +5V CL 6.2K ohm DIODES=IN3064 OR EQUIVALENT CL=100pF Including jig capacitance for 70ns and 90ns CL=30pF Including jig capacitance for 55ns SWITCHING TEST WAVEFORMS for 29F040C-70 and 29F040C-90 0.7xVCC 2.0V 2.0V TEST POINTS 0.8V 0.45V INPUT 0.8V OUTPUT AC TESTING: Inputs are driven at 0.7xVCC for a logic "1" and 0.45V for a logic "0". Input pulse rise and fall times are < 10ns. SWITCHING TEST WAVEFORMS for 29F040C-55 0.7xVCC 1.5V TEST POINTS 1.5V 0V INPUT OUTPUT AC TESTING: Inputs are driven at 0.7xVCC for a logic "1" and 0V for a logic "0". Input pulse rise and fall times are < 5ns. P/N:PM1201 REV. 1.0, DEC. 20, 2005 17 MX29F040C COMMAND WRITE TIMING WAVEFORM VCC 5V Addresses VIH ADD Valid VIL tAS tAH WE# VIH VIL tOES tCEPH1 tCWC tCEP CE# VIH VIL tCS tCH OE# VIH VIL VIH tDS tDH Data VIL DIN P/N:PM1201 REV. 1.0, DEC. 20, 2005 18 MX29F040C AUTOMATIC PROGRAMMING TIMING WAVEFORM One byte data is programmed. Verify in fast algorithm and additional programming by external control are not required because these operations are executed automatically by internal control circuit. Programming completion can be verified by Data# Polling and toggle bit checking after automatic verification starts. Device outputs DATA# during programming and DATA# after programming on Q7.(Q6 is for toggle bit; see toggle bit, Data# Polling, timing waveform) AUTOMATIC PROGRAMMING TIMING WAVEFORM VCC 5V A11~A18 ADD Valid A0~A10 WE# 555H 2AAH 555H ADD Valid tAS tAH tCWC tCEPH tAVT tCESC CE# tCEP OE# tDS tDH Q0,Q1,Q2 Q4(Note 1) Q7 Command In Command #AAH (Q0~Q7) Command In Command #55H Command In Command #A0H Data In Command In Command In Command In Data In DATA tDF DATA# polling DATA# DATA tOE Note : (1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit P/N:PM1201 REV. 1.0, DEC. 20, 2005 19 MX29F040C AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data A0H Address 555H Write Program Data/Address Toggle Bit Checking Q6 not Toggled YES NO Invalid Command NO Verify Byte Ok YES NO Auto Program Completed Q5 = 1 YES . Reset Auto Program Exceed Timing Limit P/N:PM1201 REV. 1.0, DEC. 20, 2005 20 MX29F040C AUTOMATIC CHIP ERASE TIMING WAVEFORM All data in chip are erased. External erase verification is not required because data is erased automatically by internal control circuit. Erasure completion can be verified by Data# Polling and toggle bit checking after automatic erase starts. Device outputs 0 during erasure and 1 after erasure on Q7.(Q6 is for toggle bit; see toggle bit, Data# Polling, timing waveform) AUTOMATIC CHIP ERASE TIMING WAVEFORM VCC 5V A11~A18 A0~A10 WE# 555H 2AAH 555H 555H 2AAH 555H tAS tAH tCWC tCEPH tAETC CE# tCEP OE# tDS tDH Q0,Q1, Q4(Note 1) Q7 Command In Command #AAH Command In Command #55H Command In Command #80H Command In Command #AAH Command In Command #55H Command In Command #10H Command In Command In Command In Command In Command In Command In Data# Polling (Q0~Q7) Note : (1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit P/N:PM1201 REV. 1.0, DEC. 20, 2005 21 MX29F040C AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 10H Address 555H Toggle Bit Checking Q6 not Toggled YES NO Invalid Command NO Data# Polling Q7 = 1 YES . Q5 = 1 Auto Chip Erase Completed YES Reset Auto Chip Erase Exceed Timing Limit P/N:PM1201 REV. 1.0, DEC. 20, 2005 22 MX29F040C AUTOMATIC SECTOR ERASE TIMING WAVEFORM Sector data indicated by A16 to A18 are erased. External erase verify is not required because data are erased automatically by internal control circuit. Erasure completion can be verified by Data# Polling and toggle bit checking after automatic erase starts. Device outputs 0 during erasure and 1 after erasure on Q7.(Q6 is for toggle bit; see toggle bit, Data# Polling, timing waveform) AUTOMATIC SECTOR ERASE TIMING WAVEFORM VCC 5V A16-A18 Sector Address0 Sector Address1 Sector Addressn A0~A10 555H tAS tAH 2AAH 555H 555H 2AAH tCWC WE# tCEPH tBAL tAETB CE# tCEP OE# tDS tDH Q0,Q1, Q4(Note 1) Command In Command In Command In Command In Command In Command In Command In Command In Data# Polling Q7 Command In Command In Command In Command In Command In Command In Command In Command #30H Command In Command #30H Command #AAH Command #55H Command #80H Command #AAH Command #55H Command #30H (Q0~Q7) Note : (1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit P/N:PM1201 REV. 1.0, DEC. 20, 2005 23 MX29F040C AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 30H Sector Address Toggle Bit Checking Q6 Toggled ? NO Invalid Command YES Load Other Sector Addrss If Necessary (Load Other Sector Address) Last Sector to Erase YES NO Time-out Bit Checking Q3=1 ? NO YES NO Toggle Bit Checking Q6 not Toggled YES . Data# Polling Q7 = 1 Q5 = 1 Auto Sector Erase Completed Reset Auto Sector Erase Exceed Timing Limit P/N:PM1201 REV. 1.0, DEC. 20, 2005 24 MX29F040C ERASE SUSPEND/ERASE RESUME FLOWCHART START Write Data B0H ERASE SUSPEND Toggle Bit checking Q6 not toggled YES Read Array or Program NO Reading or Programming End YES Write Data 30H NO Delay 400us (note) ERASE RESUME Continue Erase Another Erase Suspend ? YES NO Note: If the system implements an endless erase suspend/resume loop, or the number of erase suspend/resume is exceeded 1024 times, then the 400us time delay must be put into consideration. P/N:PM1201 REV. 1.0, DEC. 20, 2005 25 MX29F040C TIMING WAVEFORM FOR SECTOR PROTECTION FOR SYSTEM WITHOUT 12V A1 A6 Toggle bit polling Verify 5V OE# tCEP WE# * See the following Note! CE# Data Don't care (Note 2) tOE 01H F0H A18-A16 Sector Address Note1: Must issue "unlock for sector protect/unprotect" command before sector protection for a system without 12V provided. Note2: Except F0H P/N:PM1201 REV. 1.0, DEC. 20, 2005 26 MX29F040C TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITHOUT 12V A1 A6 Toggle bit polling Verify 5V OE# tCEP WE# * See the following Note! CE# Data Don't care (Note 2) tOE 00H F0H Note1: Must issue "unlock for sector protect/unprotect" command before sector unprotection for a system without 12V provided. Note2: Except F0H P/N:PM1201 REV. 1.0, DEC. 20, 2005 27 MX29F040C SECTOR PROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V START PLSCNT=1 Write "unlock for sector protect/unprotect" Command(Table1) Set Up Sector Addr (A18, A17, A16) OE#=VIH,A9=VIH CE#=VIL,A6=VIL Activate WE# Pulse to start Data don't care Toggle bit checking Q6 not Toggled Yes Increment PLSCNT Set CE#=OE#=VIL A9=VIH No . No Read from Sector Addr=SA, A1=1 PLSCNT=32? No Data=01H? Yes Device Failed Protect Another Sector? Yes Write Reset Command Sector Protection Complete P/N:PM1201 REV. 1.0, DEC. 20, 2005 28 MX29F040C CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V START Protect All Sectors PLSCNT=1 Write "unlock for sector protect/unprotect" Command (Table 1) Set OE#=A9=VIH CE#=VIL,A6=1 Activate WE# Pulse to start Data do'nt care No Toggle bit checking Q6 not Toggled Yes Set OE#=CE#=VIL A9=VIH,A1=1 Increment PLSCNT Set Up First Sector Addr Read Data from Device No Increment Sector Addr Data=00H? No PLSCNT=1000? Yes No Yes Device Failed All sectors have been verified? Yes Write Reset Command Chip Unprotect Complete * It is recommended before unprotect whole chip, all sectors should be protected in advance. P/N:PM1201 REV. 1.0, DEC. 20, 2005 29 MX29F040C ID CODE READ TIMING WAVEFORM VCC 5V VID ADD A9 VIH VIL VIH VIL ADD A0 A1 tACC VIH VIL tACC ADD A2-A8 A10-A18 CE# VIH VIL VIH VIL WE# VIH VIL tCE OE# VIH VIL tOE tDF tOH tOH VIH DATA Q0-Q7 DATA OUT VIL DATA OUT A4H C2H P/N:PM1201 REV. 1.0, DEC. 20, 2005 30 MX29F040C ERASE AND PROGRAMMING PERFORMANCE (1) PARAMETER Sector Erase Time Chip Erase Time Byte Programming Time Chip Programming Time Erase/Program Cycles Note: 100,000 MIN. LIMITS TYP.(2) 0.7 4 9 4.5 MAX.(3) 15 32 300 13.5 UNITS sec sec us sec Cycles 1.Not 100% Tested, Excludes external system level over head. 2.Typical values measured at 25° C,5V. 3.Maximunm values measured at 25° C,4.5V. LATCH-UP CHARACTERISTICS MIN. Input Voltage with respect to GND on all pins except I/O pins Input Voltage with respect to GND on all I/O pins Current Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time. -1.0V -1.0V -100mA MAX. 13.5V Vcc + 1.0V +100mA DATA RETENTION PARAMETER Data Retention Time MIN. 20 UNIT Years P/N:PM1201 REV. 1.0, DEC. 20, 2005 31 MX29F040C ORDERING INFORMATION PART NO. Access Time Operating Current Standby Current Temperature (ns) MX29F040CQI-55 MX29F040CQI-70 MX29F040CQI-90 MX29F040CTI-55 55 70 90 55 MAX.(mA) 30 30 30 30 MAX.(uA) 5 5 5 5 Range -40oC~85oC -40oC~85oC -40oC~85oC -40oC~85oC 32 Pin PLCC 32 Pin PLCC 32 Pin PLCC 32 Pin TSOP (Normal Type) MX29F040CTI-70 70 30 5 -40oC~85oC 32 Pin TSOP (Normal Type) MX29F040CTI-90 90 30 5 -40oC~85oC 32 Pin TSOP (Normal Type) MX29F040CPI-55 MX29F040CPI-70 MX29F040CPI-90 MX29F040CQI-55G MX29F040CQI-70G MX29F040CQI-90G MX29F040CTI-55G 55 70 90 55 70 90 55 30 30 30 30 30 30 30 5 5 5 5 5 5 5 -40oC~85oC -40oC~85oC -40oC~85oC 32 Pin PDIP 32 Pin PDIP 32 Pin PDIP PB free PB free PB free PB free PACKAGE Remark -40oC~85oC 32 Pin PLCC -40oC~85oC 32 Pin PLCC -40oC~85oC 32 Pin PLCC -40oC~85oC 32 Pin TSOP (Normal Type) MX29F040CTI-70G 70 30 5 -40oC~85oC 32 Pin TSOP (Normal Type) PB free MX29F040CTI-90G 90 30 5 -40oC~85oC 32 Pin TSOP (Normal Type) PB free MX29F040CPI-55G MX29F040CPI-70G MX29F040CPI-90G 55 70 90 30 30 30 5 5 5 -40oC~85oC 32 Pin PDIP -40oC~85oC 32 Pin PDIP -40oC~85oC 32 Pin PDIP PB free PB free PB free P/N:PM1201 REV. 1.0, DEC. 20, 2005 32 MX29F040C PART NAME DESCRIPTION MX 29 F 040 C TI 70 G OPTION: G: Lead-free package blank: normal SPEED: 55:55ns 70:70ns 90: 90ns TEMPERATURE RANGE: I: Industrial (-40˚aC to 85˚ C PACKAGE: P: PDIP Q: PLCC T: TSOP REVISION: C DENSITY & MODE: 040: 4, x8 Equal Sector TYPE: F: 5V DEVICE: 29: Flash P/N:PM1201 REV. 1.0, DEC. 20, 2005 33 MX29F040C PACKAGE INFORMATION P/N:PM1201 REV. 1.0, DEC. 20, 2005 34 MX29F040C P/N:PM1201 REV. 1.0, DEC. 20, 2005 35 MX29F040C P/N:PM1201 REV. 1.0, DEC. 20, 2005 36 MX29F040C REVISION HISTORY Revision No. Description 1.0 1. Removed "Preliminary" title 2. Removed commercial grade 3. Added access time: 55ns; Removed access time: 120ns Page P1 All All Date DEC/20/2005 P/N:PM1201 REV. 1.0, DEC. 20, 2005 37 M X29F040C MACRONIX INTERNATIONAL CO., LTD. Headquarters: TEL:+886-3-578-6688 FAX:+886-3-563-2888 Europe Office : TEL:+32-2-456-8020 FAX:+32-2-456-8021 Hong Kong Office : TEL:+86-755-834-335-79 FAX:+86-755-834-380-78 Japan Office : Kawasaki Office : TEL:+81-44-246-9100 FAX:+81-44-246-9105 Osaka Office : TEL:+81-6-4807-5460 FAX:+81-6-4807-5461 Singapore Office : TEL:+65-6346-5505 FAX:+65-6348-8096 Taipei Office : TEL:+886-2-2509-3300 FAX:+886-2-2509-2200 MACRONIX AMERICA, INC. TEL:+1-408-262-8887 FAX:+1-408-262-8810 http : //www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.