MX29F040CQI-90G

MX29F040C 4M-BIT [512K x 8] SINGLE VOLTAGE 5V ONLY FLASH MEMORY FEATURES GENERAL FEATURES • Single Power Supply Operation - 4.5 to 5.5 volt for read, erase, and program operations • 524288 x 8 only • Sector Structure - 64K-Byte x 8 • Latch-up protected to 100mA from -1V to Vcc + 1V • Compatible with JEDEC standard - Pinout and software compatible to single power supply Flash PERFORMANCE • High Performance - Access time: 70/90ns - Program time: 9us (typical) - Erase time: 0.7s/sector, 4s/chip (typical) • Low Power Consumption - Low active read current: 30mA (maximum) at 5MHz - Low standby current: 1uA (typical) • Minimum 100,000 erase/program cycle • 20 years data retention SOFTWARE FEATURES • Erase Suspend/ Erase Resume - Suspends sector erase operation to read data from or program data to another sector which is not being erased • Status Reply - Data# Polling & Toggle bits provide detection of program and erase operation completion PACKAGE • 32-Pin PLCC • 32-Pin TSOP • All devices are RoHS Compliant P/N:PM1201 REV. 2.2, DEC. 04, 2012 1 MX29F040C Contents FEATURES................................................................................................................................................................... 1 GENERAL FEATURES................................................................................................................................1 SOFTWARE FEATURES.............................................................................................................................1 PACKAGE ...................................................................................................................................................1 PIN CONFIGURATIONS............................................................................................................................................... 4 PIN DESCRIPTION....................................................................................................................................................... 5 LOGIC SYMBOL..........................................................................................................................................5 BLOCK DIAGRAM........................................................................................................................................................ 6 Table 1. SECTOR STRUCTURE.................................................................................................................................. 7 MX29F040C SECTOR ADDRESS TABLE...................................................................................................7 Table 2. BUS OPERATION........................................................................................................................................... 7 REQUIREMENTS FOR READING ARRAY DATA.......................................................................................8 WRITE COMMANDS/COMMAND SEQUENCES........................................................................................8 AUTOMATIC SELECT OPERATION...........................................................................................................8 DATA PROTECTION....................................................................................................................................9 WRITE PULSE "GLITCH" PROTECTION...................................................................................................9 LOGICAL INHIBIT........................................................................................................................................9 POWER-UP SEQUENCE............................................................................................................................9 POWER-UP WRITE INHIBIT.......................................................................................................................9 POWER SUPPLY DECOUPLING................................................................................................................9 TABLE 3. MX29F040C COMMAND DEFINITIONS.................................................................................................... 10 RESET ...................................................................................................................................................... 11 AUTOMATIC SELECT COMMAND SEQUENCE...................................................................................... 11 AUTOMATIC PROGRAMMING.................................................................................................................12 CHIP ERASE............................................................................................................................................13 SECTOR ERASE.......................................................................................................................................13 SECTOR ERASE SUSPEND.....................................................................................................................14 SECTOR ERASE RESUME.......................................................................................................................14 ABSOLUTE MAXIMUM STRESS RATINGS.............................................................................................................. 15 OPERATING TEMPERATURE AND VOLTAGE......................................................................................................... 15 DC CHARACTERISTICS ......................................................................................................................................... 16 SWITCHING TEST CIRCUITS.................................................................................................................................... 17 AC CHARACTERISTICS .......................................................................................................................................... 18 Figure 1. COMMAND WRITE OPERATION..............................................................................................19 READ/RESET OPERATION....................................................................................................................................... 20 Figure 2. READ TIMING WAVEFORMS....................................................................................................20 ERASE/PROGRAM OPERATION.............................................................................................................................. 21 Figure 3. AUTOMATIC CHIP ERASE TIMING WAVEFORM.....................................................................21 Figure 4. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART...........................................................22 Figure 5. AUTOMATIC SECTOR ERASE TIMING WAVEFORM...............................................................23 P/N:PM1201 REV. 2.2, DEC. 04, 2012 2 MX29F040C Figure 6. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART...................................................24 Figure 7. ERASE SUSPEND/RESUME FLOWCHART.............................................................................25 Figure 8. AUTOMATIC PROGRAM TIMING WAVEFORMS......................................................................26 Figure 9. CE# CONTROLLED WRITE TIMING WAVEFORM...................................................................27 Figure 10. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART..................................................28 Figure 11. SILICON ID READ TIMING WAVEFORM.................................................................................29 WRITE OPERATION STATUS.................................................................................................................................... 30 Figure 12. DATA# POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS).................30 Figure 13. DATA# POLLING ALGORITHM................................................................................................31 Figure 14. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)......................32 Figure 15. TOGGLE BIT ALGORITHM ....................................................................................................33 RECOMMENDED OPERATING CONDITIONS.......................................................................................................... 34 Figure A. AC Timing at Device Power-Up..................................................................................................34 ERASE AND PROGRAMMING PERFORMANCE..................................................................................................... 35 DATA RETENTION..................................................................................................................................................... 35 LATCH-UP CHARACTERISTICS............................................................................................................................... 35 ORDERING INFORMATION....................................................................................................................................... 36 PACKAGE INFORMATION......................................................................................................................................... 38 REVISION HISTORY .................................................................................................................................................. 40 P/N:PM1201 REV. 2.2, DEC. 04, 2012 3 MX29F040C PIN CONFIGURATIONS 32 A17 1 WE# A16 4 VCC 5 A18 A7 A15 A12 32 PLCC 30 29 A14 A6 A13 A5 A8 A4 A3 A9 9 MX29F040C 25 A11 A2 OE# A1 A10 A0 CE# 21 20 Q5 Q4 Q3 GND Q2 17 Q7 Q6 13 14 Q1 Q0 32 TSOP (Standard Type) (8mm x 20mm) A11 A9 A8 A13 A14 A17 WE# VCC A18 A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MX29F040C P/N:PM1201 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE# A10 CE# Q7 Q6 Q5 Q4 Q3 GND Q2 Q1 Q0 A0 A1 A2 A3 REV. 2.2, DEC. 04, 2012 4 MX29F040C PIN DESCRIPTION LOGIC SYMBOL 19 SYMBOL PIN NAME A0~A18 Address Input Q0~Q7 Data Input/Output CE# Chip Enable Input WE# Write Enable Input OE# Output Enable Input GND Ground Pin OE# VCC +5.0V single power supply WE# A0-A18 Q0-Q7 8 CE# P/N:PM1201 REV. 2.2, DEC. 04, 2012 5 MX29F040C BLOCK DIAGRAM CE# OE# WE# CONTROL INPUT LOGIC WRITE PROGRAM/ERASE STATE HIGH VOLTAGE MACHINE (WSM) LATCH A0-AM BUFFER Y-DECODER AND X-DECODER ADDRESS STATE FLASH REGISTER ARRAY ARRAY Y-PASS GATE SOURCE HV COMMAND DATA DECODER SENSE AMPLIFIER PGM DATA HV COMMAND DATA LATCH PROGRAM DATA LATCH Q0-Q7 I/O BUFFER AM: MSB address P/N:PM1201 REV. 2.2, DEC. 04, 2012 6 MX29F040C Table 1. SECTOR STRUCTURE MX29F040C SECTOR ADDRESS TABLE Sector Sector Address Address Range A18 A17 A16 SA0 0 0 0 00000h-0FFFFh SA1 0 0 1 10000h-1FFFFh SA2 0 1 0 20000h-2FFFFh SA3 0 1 1 30000h-3FFFFh SA4 1 0 0 40000h-4FFFFh SA5 1 0 1 50000h-5FFFFh SA6 1 1 0 60000h-6FFFFh SA7 1 1 1 70000h-7FFFFh Note: All sectors are 64 Kbytes in size. Table 2. BUS OPERATION Mode Read Silicon ID Manufacture Code Read Silicon ID Device Code Read Standby Output Disable Write Pins CE# OE# WE# A0 A1 A6 A9 Q0 ~ Q7 L L H L L X Vhv C2H L L H H L X Vhv A4H L H L L L X H H H X H L A0 X X A0 A1 X X A1 A6 X X A6 A9 X X A9 DOUT HIGH Z HIGH Z DIN Notes: 1. Vhv is the very high voltage, 11.5V to 12.5V. 2. X means input high (Vih) or input low (Vil). P/N:PM1201 REV. 2.2, DEC. 04, 2012 7 MX29F040C REQUIREMENTS FOR READING ARRAY DATA Read array action is to read the data stored in the array out. While the memory device is in powered up or has been reset, it will automatically enter the status of read array. If the microprocessor wants to read the data stored in array, it has to drive CE# (device enable control pin) and OE# (Output control pin) as Vil, and input the address of the data to be read into address pin at the same time. After a period of read cycle (Tce or Taa), the data being read out will be displayed on output pin for microprocessor to access. If CE# or OE# is Vih, the output will be in tri-state, and there will be no data displayed on output pin at all. After the memory device completes embedded operation (automatic Erase or Program), it will automatically return to the status of read array, and the device can read the data in any address in the array. In the process of erasing, if the device receives the Erase suspend command, erase operation will be stopped after a period of time no more than Treadyand the device will return to the status of read array. At this time, the device can read the data stored in any address except the sector being erased in the array. In the status of erase suspend, if user wants to read the data in the sectors being erased, the device will output status data onto the output. Similarly, if program command is issued after erase suspend, after program operation is completed, system can still read array data in any address except the sectors to be erased. The device needs to issue reset command to enable read array operation again in order to arbitrarily read the data in the array in the following two situations: 1. In program or erase operation, the programming or erasing failure causes Q5 to go high. 2. The device is in auto select mode. In the two situations above, if reset command is not issued, the device is not in read array mode and system must issue reset command before reading array data. WRITE COMMANDS/COMMAND SEQUENCES To write a command to the device, system must drive WE# and CE# to Vil, and OE# to Vih. In a command cycle, all address are latched at the later falling edge of CE# and WE#, and all data are latched at the earlier rising edge of CE# and WE#. "Figure 1. COMMAND WRITE OPERATION" illustrates the AC timing waveform of a write command, and "TABLE 3. MX29F040C COMMAND DEFINITIONS" defines all the valid command sets of the device. System is not allowed to write invalid commands not defined in this datasheet. Writing an invalid command will bring the device to an undefined state. AUTOMATIC SELECT OPERATION When the device is in Read array mode or erase-suspended read array mode, user can issue read silicon ID command to enter read silicon ID mode. After entering read silicon ID mode, user can query several silicon IDs continuously and does not need to issue read silicon ID mode again. When A0 is Low, device will output Macronix Manufacture ID C2. When A0 is high, device will output Device ID. In read silicon ID mode, issuing reset command will reset device back to read array mode or erase-suspended read array mode. Another way to enter read silicon ID is to apply high voltage on A9 pin with CE#, OE# and A1 at Vil. While the high voltage of A9 pin is discharged, device will automatically leave read silicon ID mode and go back to read array mode or erase-suspended read array mode. When A0 is Low, device will output Macronix Manufacture ID C2. When A0 is high, device will output Device ID. P/N:PM1201 REV. 2.2, DEC. 04, 2012 8 MX29F040C DATA PROTECTION To avoid accidental erasure or programming of the device, the device is automatically reset to read array mode during power up. Besides, only after successful completion of the specified command sets will the device begin its erase or program operation. Other features to protect the data from accidental alternation are described as followed. WRITE PULSE "GLITCH" PROTECTION CE#, WE#, OE# pulses shorter than 5ns are treated as glitches and will not be regarded as an effective write cycle. LOGICAL INHIBIT A valid write cycle requires both CE# and WE# at Vil with OE# at Vih. Write cycle is ignored when either CE# at Vih, WE# a Vih, or OE# at Vil. POWER-UP SEQUENCE Upon power up, MX29F040C is placed in read array mode. Furthermore, program or erase operation will begin only after successful completion of specified command sequences. POWER-UP WRITE INHIBIT When WE#, CE# is held at Vil and OE# is held at Vih during power up, the device ignores the first command on the rising edge of WE#. POWER SUPPLY DECOUPLING A 0.1uF capacitor should be connected between the Vcc and GND to reduce the noise effect. P/N:PM1201 REV. 2.2, DEC. 04, 2012 9 MX29F040C TABLE 3. MX29F040C COMMAND DEFINITIONS Command 1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle 4th Bus Cycle 5th Bus Cycle 6th Bus Cycle Addr Data Addr Data Addr Data Addr Data Read Mode Addr Data Automatic Select Reset Mode Manufacturer ID Device ID XXX 555 555 F0 AA AA 2AA 2AA 55 55 555 555 90 90 X00 X01 C2 ID Addr Data Addr Data 555 AA 2AA 55 555 A0 Addr Chip Erase 555 AA 2AA 55 555 80 555 Sector Erase 555 AA 2AA 55 555 80 555 Data AA AA 2AA 55 555 10 2AA 55 Sector 30 Program Erase Suspend XXX B0 Erase Resume XXX 30 Notes: 1. Device ID: A4H. 2. It is not allowed to adopt any other code which is not in the above command definition table. P/N:PM1201 REV. 2.2, DEC. 04, 2012 10 MX29F040C RESET In the following situations, executing reset command will reset device back to read array mode: • Among erase command sequence (before the full command set is completed) • Sector erase time-out period • Erase fail (while Q5 is high) • Among program command sequence (before the full command set is completed, erase-suspended program included) • Program fail (while Q5 is high, and erase-suspended program fail is included) • Read silicon ID mode While device is at the status of program fail or erase fail (Q5 is high), user must issue reset command to reset device back to read array mode. While the device is in read silicon ID mode, user must issue reset command to reset device back to read array mode. When the device is in the progress of programming (not program fail) or erasing (not erase fail), device will ignore reset command. AUTOMATIC SELECT COMMAND SEQUENCE Automatic Select mode is used to access the manufacturer ID, device ID. The automatic select mode has four command cycles. The first two are unlock cycles, and followed by a specific command. The fourth cycle is a normal read cycle, and user can read at any address any number of times without entering another command sequence. The reset command is necessary to exit the Automatic Select mode and back to read array. The following table shows the identification code with corresponding address. Address Data (Hex) Manufacturer ID X00 C2 Device ID X01 A4 There is an alternative method to that shown in "Table 2. BUS OPERATION", which is intended for EPROM programmers and requires Vhv on address bit A9. P/N:PM1201 REV. 2.2, DEC. 04, 2012 11 MX29F040C AUTOMATIC PROGRAMMING The MX29F040Ccan provide the user program function. As long as the users enter the right cycle defined in the "TABLE 3. MX29F040C COMMAND DEFINITIONS" (including 2 unlock cycles and A0H), any data user inputs will automatically be programmed into the array. Once the program function is executed, the internal write state controller will automatically execute the algorithms and timings necessary for program and verification, which includes generating suitable program pulse, verifying whether the threshold voltage of the programmed cell is high enough and repeating the program pulse if any of the cells does not pass verification. Meanwhile, the internal control will prohibit the programming to cells that pass verification while the other cells fail in verification in order to avoid over-programming. Programming will only change the bit status from "1" to "0". That is to say, it is impossible to convert the bit status from "0" to "1" by programming. Meanwhile, the internal write verification only detects the errors of the "1" that is not successfully programmed to "0". Any command written to the device during programming will be ignored except hardware reset, which will terminate the program operation after a period of time no more than Tready. When the embedded program algorithm is complete or the program operation is terminated by hardware reset, the device will return to the reading array data mode. With the internal write state controller, the device requires the user to write the program command and data only. The typical chip program time at room temperature of the MX29F040C is 4.5 seconds. When the embedded program operation is on going, user can confirm if the embedded operation is finished or not by the following methods: Status Q7 Q6 Q5 In progress*1 Q7# togging 0 Finished Q7 Stop toggling 0 Exceed time limit Q7# Toggling 1 *1: The status "in progress" means both program mode and erase-suspended program mode. P/N:PM1201 REV. 2.2, DEC. 04, 2012 12 MX29F040C CHIP ERASE Chip Erase is to erase all the data with "1" and "0" as all "1". It needs 6 cycles to write the action in, and the first two cycles are "unlock" cycles, the third one is a configuration cycle, the fourth and fifth are also "unlock" cycles, and the sixth cycle is the chip erase operation. During chip erasing, all the commands will not be accepted except hardware rests or the working voltage is too low that chip erase will be interrupted. After Chip Erase, the chip will return to the state of Read Array. When the embedded chip erase operation is on going, user can confirm if the embedded operation is finished or not by the following methods: Status Q7 Q6 Q5 Q2 In progress 0 Togging 0 Toggling Finished 1 Stop toggling 0 1 Exceed time limit 0 Toggling 1 Toggling SECTOR ERASE Sector Erase is to erase all the data in a sector with "1" and "0" as all "1". It requires six command cycles to issue. The first two cycles are "unlock cycles", the third one is a configuration cycle, the fourth and fifth are also "unlock cycles" and the sixth cycle is the sector erase command. After the sector erase command sequence is issued, there is a time-out period of 50us counted internally. During the time-out period, additional sector address and sector erase command can be written multiply. Once user enters another sector erase command, the time-out period of 50us is recounted. If user enters any command other than sector erase or erase suspend during time-out period, the erase command would be aborted and the device is reset to read array condition. The number of sectors could be from one sector to all sectors. After time-out period passing by, additional erase command is not accepted and erase embedded operation begins. During sector erasing, all commands will not be accepted except hardware reset and erase suspend and user can check the status as chip erase. When the embedded erase operation is on going, user can confirm if the embedded operation is finished or not by the following methods: Status Q7 Q6 Q5 Q3 Q2 Time-out period 0 Toggling 0 0 Toggling In progress 0 Togging 0 1 Toggling Finished 1 Stop toggling 0 1 1 Exceed time limit 0 Toggling 1 1 Toggling *1: The status Q3 is the time-out period indicator. When Q3=0, the device is in time-out period and is acceptible to another sector address to be erased. When Q3=1, the device is in erase operation and only erase suspend is valid. P/N:PM1201 REV. 2.2, DEC. 04, 2012 13 MX29F040C SECTOR ERASE SUSPEND During sector erasure, sector erase suspend is the only valid command. If user issue erase suspend command in the time-out period of sector erasure, device time-out period will be over immediately and the device will go back to erase-suspended read array mode. If user issue erase suspend command during the sector erase is being operated, device will suspend the ongoing erase operation, and after the Tready1(