MX29F400CBMI-90G

MX29F400C T/B 4M-BIT [512K x 8 / 256K x 16] SINGLE VOLTAGE 5V ONLY FLASH MEMORY FEATURES GENERAL FEATURES • Single Power Supply Operation - 4.5 to 5.5 volt for read, erase, and program operations • 524,288 x 8 / 262,144 x 16 switchable • Boot Sector Architecture - T = Top Boot Sector - B = Bottom Boot Sector • Sector Structure - 16K-Byte x 1, 8K-Byte x 2, 32K-Byte x 1, and 64K-Byte x 7 • Sector protection - Hardware method to disable any combination of sectors from program or erase operations - Temporary sector unprotected allows code changes in previously locked sectors • Latch-up protected to 100mA from -1V to Vcc + 1V • Compatible with JEDEC standard - Pinout and software compatible to single power supply Flash PERFORMANCE • High Performance - Access time: 70/90ns - Byte/Word program time: 9us/11us (typical) - Erase time: 0.7s/sector, 4s/chip (typical) • Low Power Consumption - Low active read current: 40mA (maximum) at 5MHz - Low standby current: 1uA (typical) • Minimum 100,000 erase/program cycle • 20 years data retention SOFTWARE FEATURES • Erase Suspend/ Erase Resume - Suspends sector erase operation to read data from or program data to another sector which is not being erased • Status Reply - Data# Polling & Toggle bits provide detection of program and erase operation completion HARDWARE FEATURES • Ready/Busy# (RY/BY#) Output - Provides a hardware method of detecting program and erase operation completion • Hardware Reset (RESET#) Input - Provides a hardware method to reset the internal state machine to read mode PACKAGE • 44-Pin SOP • 48-Pin TSOP • All devices are RoHS Compliant • All non RoHS Compliant devices are not recommeded for new design in P/N:PM1200 REV. 2.2, NOV. 29, 2010 1 MX29F400C T/B PIN CONFIGURATIONS 44 SOP(500mil) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 MX29F400CT/CB NC RY/BY# A17 A7 A6 A5 A4 A3 A2 A1 A0 CE# GND OE# Q0 Q8 Q1 Q9 Q2 Q10 Q3 Q11 RESET# WE# A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE# GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC 48 TSOP(TYPE I) (12mm x 20mm) A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# RESET# NC NC RY/BY# NC A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 MX29F400C T/B P/N:PM1200 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE# GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC Q11 Q3 Q10 Q2 Q9 Q1 Q8 Q0 OE# GND CE# A0 REV. 2.2, NOV. 29, 2010 2 MX29F400C T/B PIN DESCRIPTION SYMBOL PIN NAME A0~A17 Address Input Q0~Q14 Data Input/Output Q15/A-1 Q15(Word mode)/LSB addr(Byte mode) CE# Chip Enable Input WE# Write Enable Input BYTE# Word/Byte Selection input RESET# Hardware Reset Pin/Sector Protect Unlock OE# Output Enable Input RY/BY# Ready/Busy Output VCC Power Supply Pin (+5V) GND Ground Pin LOGIC SYMBOL 18 A0-A17 Q0-Q15 (A-1) 16 or 8 CE# OE# WE# RESET# BYTE# P/N:PM1200 RY/BY# REV. 2.2, NOV. 29, 2010 3 MX29F400C T/B BLOCK DIAGRAM CE# OE# WE# RESET# BYTE# CONTROL INPUT LOGIC PROGRAM/ERASE STATE HIGH VOLTAGE MACHINE (WSM) LATCH BUFFER FLASH REGISTER ARRAY ARRAY Y-DECODER AND STATE X-DECODER ADDRESS A0-AM WRITE Y-PASS GATE SOURCE HV COMMAND DATA DECODER SENSE AMPLIFIER PGM DATA HV COMMAND DATA LATCH PROGRAM DATA LATCH Q0-Q15/A-1 I/O BUFFER AM: MSB address P/N:PM1200 REV. 2.2, NOV. 29, 2010 4 MX29F400C T/B Table 1. SECTOR STRUCTURE MX29F400CT TOP BOOT SECTOR ADDRESS TABLE Sector A17 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 0 0 0 0 1 1 1 1 1 1 1 A16 A15 A14 A13 A12 0 0 1 1 0 0 1 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 X X X X X X X 0 1 1 1 X X X X X X X X 0 0 1 X X X X X X X X 0 1 X Sector Size (Kbytes/ Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 32/16 8/4 8/4 16/8 Address Range (in hexadecimal) (x8) (x16) Address Range Address Range 00000h-0FFFFh 00000h-07FFFh 10000h-1FFFFh 08000h-0FFFFh 20000h-2FFFFh 10000h-17FFFh 30000h-3FFFFh 18000h-1FFFFh 40000h-4FFFFh 20000h-27FFFh 50000h-5FFFFh 28000h-2FFFFh 60000h-6FFFFh 30000h-37FFFh 70000h-77FFFh 38000h-3BFFFh 78000h-79FFFh 3C000h-3CFFFh 7A000h-7BFFFh 3D000h-3DFFFh 7C000h-7FFFFh 3E000h-3FFFFh MX29F400CB BOTTOM BOOT SECTOR ADDRESS TABLE Sector A17 A16 A15 A14 A13 A12 Sector Size Address Range (in hexadecimal) (Kbytes/ (x8) (x16) Kwords) Address Range Address Range SA0 0 0 0 0 0 X 16/8 00000h-03FFFh 00000h-01FFFh SA1 0 0 0 0 1 0 8/4 04000h-05FFFh 02000h-02FFFh SA2 0 0 0 0 1 1 8/4 06000h-07FFFh 03000h-03FFFh SA3 0 0 0 1 X X 32/16 08000h-0FFFFh 04000h-07FFFh SA4 0 0 1 X X X 64/32 10000h-1FFFFh 08000h-0FFFFh SA5 0 1 0 X X X 64/32 20000h-2FFFFh 10000h-17FFFh SA6 0 1 1 X X X 64/32 30000h-3FFFFh 18000h-1FFFFh SA7 1 0 0 X X X 64/32 40000h-4FFFFh 20000h-27FFFh SA8 1 0 1 X X X 64/32 50000h-5FFFFh 28000h-2FFFFh SA9 1 1 0 X X X 64/32 60000h-6FFFFh 30000h-37FFFh SA10 1 1 1 X X X 64/32 70000h-7FFFFh 38000h-3FFFFh Note: Address range is A17~A-1 in byte mode and A17~A0 in word mode. P/N:PM1200 REV. 2.2, NOV. 29, 2010 5 MX29F400C T/B Table 2. BUS OPERATION Mode Pins CE# Read Silicon ID Manufacture Code Read Silicon ID OE# WE# RESET# A0 A1 A6 A9 Q0 ~ Q15 L L H H L L X Vhv X Vhv C2H (Byte mode) 00C2H (Word mode) 23H/ABH (Byte mode) Device Code Read Standby Output Disable Write Sector Protect Chip Unprotect Ve r i f y S e c t o r P r o t e c t / L L H H H L L H L L L L L L X H H H H L H X H L L L H H H H H Vhv Vhv H A0 X X A0 L L L A1 X X A1 H H H A6 A9 X X X X A6 A9 L X H X L Vhv 2223H/22ABH (Word mode) DOUT HIGH Z HIGH Z DIN DIN DIN Code(4) Unprotect Reset X X X L X X X HIGH Z X Notes: 1. Vhv is the very high voltage, 11.5V to 12.5V. 2. X means input high (Vih) or input low (Vil). 3. SA means sector address: A12~A17. 4. Code=00H/XX00H means unprotected. Code=01H/XX01H means protected. P/N:PM1200 REV. 2.2, NOV. 29, 2010 6 MX29F400C T/B REQUIREMENTS FOR READING ARRAY DATA Read array action is to read the data stored in the array out. While the memory device is in powered up or has been reset, it will automatically enter the status of read array. If the microprocessor wants to read the data stored in array, it has to drive CE# (device enable control pin) and OE# (Output control pin) as Vil, and input the address of the data to be read into address pin at the same time. After a period of read cycle (Tce or Taa), the data being read out will be displayed on output pin for microprocessor to access. If CE# or OE# is Vih, the output will be in tri-state, and there will be no data displayed on output pin at all. After the memory device completes embedded operation (automatic Erase or Program), it will automatically return to the status of read array, and the device can read the data in any address in the array. In the process of erasing, if the device receives the Erase suspend command, erase operation will be stopped after a period of time no more than Treadyand the device will return to the status of read array. At this time, the device can read the data stored in any address except the sector being erased in the array. In the status of erase suspend, if user wants to read the data in the sectors being erased, the device will output status data onto the output. Similarly, if program command is issued after erase suspend, after program operation is completed, system can still read array data in any address except the sectors to be erased. The device needs to issue reset command to enable read array operation again in order to arbitrarily read the data in the array in the following two situations: 1. In program or erase operation, the programming or erasing failure causes Q5 to go high. 2. The device is in auto select mode. In the two situations above, if reset command is not issued, the device is not in read array mode and system must issue reset command before reading array data. WRITE COMMANDS/COMMAND SEQUENCES To write a command to the device, system must drive WE# and CE# to Vil, and OE# to Vih. In a command cycle, all address are latched at the later falling edge of CE# and WE#, and all data are latched at the earlier rising edge of CE# and WE#. Figure 1 illustrates the AC timing waveform of a write command, and Table 3 defines all the valid command sets of the device. System is not allowed to write invalid commands not defined in this datasheet. Writing an invalid command will bring the device to an undefined state. RESET# OPERATION Driving RESET# pin low for a period more than Trp will reset the device back to read mode. If the device is in program or erase operation, the reset operation will take at most a period of Tready for the device to return to read array mode. Before the device returns to read array mode, the RY/BY# pin remains low (busy status). When RESET# pin is held at GND±0.3V, the device consumes standby current(Isb).However, device draws larger current if RESET# pin is held at Vil but not within GND±0.3V. It is recommended that the system to tie its reset signal to RESET# pin of flash memory, so that the flash memory will be reset during system reset and allows system to read boot code from flash memory. P/N:PM1200 REV. 2.2, NOV. 29, 2010 7 MX29F400C T/B SECTOR PROTECT OPERATION When a sector is protected, program or erase operation will be disabled on these sectors. MX29F400C T/B provides one method for sector protection. Once the sector is protected, the sector remains protected until next chip unprotect, or is temporarily unprotected by asserting RESET# pin at Vhv. Refer to temporary sector unprotect operation for further details. This method is by applying Vhv on RESET# pin. Refer to Figure 12 for timing diagram and Figure 13 for the algorithm for this method. CHIP UNPROTECT OPERATION MX29F400C T/B provides one method for chip unprotect. The chip unprotect operation unprotects all sectors within the device. It is recommended to protect all sectors before activating chip unprotect mode. All sector are unprotected when shipped from the factory. This method is by applying Vhv on RESET# pin. Refer to Figure 12 for timing diagram and Figure 13 for algorithm of the operation. TEMPORARY SECTOR UNPROTECT OPERATION System can apply RESET# pin at Vhv to place the device in temporary unprotect mode. In this mode, previously protected sectors can be programmed or erased just as it is unprotected. The devices returns to normal operation once Vhv is removed from RESET# pin and previously protected sectors are again protected. AUTOMATIC SELECT OPERATION When the device is in Read array mode or erase-suspended read array mode, user can issue read silicon ID command to enter read silicon ID mode. After entering read silicon ID mode, user can query several silicon IDs continuously and does not need to issue read silicon ID mode again. When A0 is Low, device will output Macronix Manufacture ID C2. When A0 is high, device will output Device ID. In read silicon ID mode, issuing reset command will reset device back to read array mode or erase-suspended read array mode. Another way to enter read silicon ID is to apply high voltage on A9 pin with CE#, OE# and A1 at Vil. While the high voltage of A9 pin is discharged, device will automatically leave read silicon ID mode and go back to read array mode or erase-suspended read array mode. When A0 is Low, device will output Macronix Manufacture ID C2. When A0 is high, device will output Device ID. P/N:PM1200 REV. 2.2, NOV. 29, 2010 8 MX29F400C T/B VERIFY SECTOR PROTECT STATUS OPERATION MX29F400C T/B provides hardware sector protection against Program and Erase operation for protected sectors. The sector protect status can be read through Sector Protect Verify command. This method requires Vhv on A9 pin, Vih on WE# and A1 pins, Vil on CE#, OE#, A6 and A0 pins, and sector address on A12 to A17 pins. If the read out data is 01H, the designated sector is protected. Oppositely, if the read out data is 00H, the designated sector is still not being protected. DATA PROTECTION To avoid accidental erasure or programming of the device, the device is automatically reset to read array mode during power up. Besides, only after successful completion of the specified command sets will the device begin its erase or program operation. Other features to protect the data from accidental alternation are described as followed. WRITE PULSE "GLITCH" PROTECTION CE#, WE#, OE# pulses shorter than 5ns are treated as glitches and will not be regarded as an effective write cycle. LOGICAL INHIBIT A valid write cycle requires both CE# and WE# at Vil with OE# at Vih. Write cycle is ignored when either CE# at Vih, WE# a Vih, or OE# at Vil. POWER-UP SEQUENCE Upon power up, MX29F400C T/B is placed in read array mode. Furthermore, program or erase operation will begin only after successful completion of specified command sequences. POWER-UP WRITE INHIBIT When WE#, CE# is held at Vil and OE# is held at Vih during power up, the device ignores the first command on the rising edge of WE#. POWER SUPPLY DECOUPLING A 0.1uF capacitor should be connected between the Vcc and GND to reduce the noise effect. P/N:PM1200 REV. 2.2, NOV. 29, 2010 9 MX29F400C T/B TABLE 3. MX29F400C T/B COMMAND DEFINITIONS Read Mode Command 1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle 4th Bus Cycle 5th Bus Cycle 6th Bus Cycle Hex Addr Data Addr Data Addr Data 2nd Bus Cycle 3rd Bus Cycle 4th Bus Cycle 5th Bus Cycle 6th Bus Cycle XXX F0 Manufacturer ID Word Byte 555 AAA AA AA 2AA 555 55 55 555 AAA 90 90 Automatic Select Device ID Word 555 AA 2AA 55 555 90 Byte AAA AA 555 55 AAA 90 Addr X00 X00 X01 X02 Data 00C2 C2 ID ID Program Sector Protect Verify Word Byte Word Byte 555 AAA 555 AAA AA AA AA AA 2AA 555 2AA 555 55 55 55 55 555 AAA 555 AAA 90 90 A0 A0 (Sector) (Sector) Addr Addr X02 X04 XX00/ 00/01 Data Data XX01 Addr Data Addr Data Command 1st Bus Cycle Addr Data Reset Mode Sector Erase Hex Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Word 555 AA 2AA 55 555 80 555 AA 2AA 55 Sector 30 Byte AAA AA 555 55 AAA 80 AAA AA 555 55 Sector 30 Erase Suspend Erase Resume Sector B0 Sector 30 Chip Erase Word 555 AA 2AA 55 555 80 Byte AAA AA 555 55 AAA 80 555 AAA AA AA 2AA 55 555 10 555 55 AAA 10 Sector Protect Word XXX 60 Sector 60 Sector 40 Sector 00/01 Byte XXX 60 Sector 60 Sector 40 Sector 00/01 Notes: 1. Device ID: 2223H/23H for Top Boot Sector device. 22ABH/ABH for Bottom Boot Sector device. 2. For sector protect verify result, XX00H/00H means sector is not protected, XX01H/01H means sector has been protected. 3. Sector Protect command is valid during Vhv at RESET# pin, Vih at A1 pin and Vil at A0, A6 pins. The last Bus cyc is for protect verify. 4. It is not allowed to adopt any other code which is not in the above command definition table. P/N:PM1200 REV. 2.2, NOV. 29, 2010 10 MX29F400C T/B RESET In the following situations, executing reset command will reset device back to read array mode: • Among erase command sequence (before the full command set is completed) • Sector erase time-out period • Erase fail (while Q5 is high) • Among program command sequence (before the full command set is completed, erase-suspended program included) • Program fail (while Q5 is high, and erase-suspended program fail is included) • Read silicon ID mode • Sector protect verify While device is at the status of program fail or erase fail (Q5 is high), user must issue reset command to reset device back to read array mode. While the device is in read silicon ID mode or sector protect verify mode, user must issue reset command to reset device back to read array mode. When the device is in the progress of programming (not program fail) or erasing (not erase fail), device will ignore reset command. AUTOMATIC SELECT COMMAND SEQUENCE Automatic Select mode is used to access the manufacturer ID, device ID and to verify whether or not a sector is protected. The automatic select mode has four command cycles. The first two are unlock cycles, and followed by a specific command. The fourth cycle is a normal read cycle, and user can read at any address any number of times without entering another command sequence. The reset command is necessary to exit the Automatic Select mode and back to read array. The following table shows the identification code with corresponding address. Manufacturer ID Device ID Sector Protect Verify Address Data (Hex) Representation Word X00 00C2 Byte X00 C2 Word X01 2223/22AB Top/Bottom Boot Sector Byte X02 23/AB Top/Bottom Boot Sector Word (Sector address) X 02 00/01 Unprotected/protected Byte (Sector address) X 04 00/01 Unprotected/protected There is an alternative method to that shown in Table 2, which is intended for EPROM programmers and requires Vhv on address bit A9. P/N:PM1200 REV. 2.2, NOV. 29, 2010 11 MX29F400C T/B AUTOMATIC PROGRAMMING The MX29F400C T/B can provide the user program function by the form of Byte-Mode or Word-Mode. As long as the users enter the right cycle defined in the Table.3 (including 2 unlock cycles and A0H), any data user inputs will automatically be programmed into the array. Once the program function is executed, the internal write state controller will automatically execute the algorithms and timings necessary for program and verification, which includes generating suitable program pulse, verifying whether the threshold voltage of the programmed cell is high enough and repeating the program pulse if any of the cells does not pass verification. Meanwhile, the internal control will prohibit the programming to cells that pass verification while the other cells fail in verification in order to avoid over-programming. Programming will only change the bit status from "1" to "0". That is to say, it is impossible to convert the bit status from "0" to "1" by programming. Meanwhile, the internal write verification only detects the errors of the "1" that is not successfully programmed to "0". Any command written to the device during programming will be ignored except hardware reset, which will terminate the program operation after a period of time no more than Tready. When the embedded program algorithm is complete or the program operation is terminated by hardware reset, the device will return to the reading array data mode. With the internal write state controller, the device requires the user to write the program command and data only. The typical chip program time at room temperature of the MX29F400C T/B is 3 seconds. (Word-Mode) When the embedded program operation is on going, user can confirm if the embedded operation is finished or not by the following methods: Status Q7 Q6 Q5 RY/BY#*2 In progress*1 Q7# Toggling 0 0 Finished Q7 Stop toggling 0 1 Exceed time limit Q7# Toggling 1 0 *1: The status "in progress" means both program mode and erase-suspended program mode. *2: RY/BY# is an open drain output pin and should be weakly connected to VDD through a pull-up resistor. *3: When an attempt is made to program a protected sector, Q7 will output its complement data or Q6 continues to toggle for about 1us and the device returns to read array state without programing the data in the protected sector. P/N:PM1200 REV. 2.2, NOV. 29, 2010 12 MX29F400C T/B CHIP ERASE Chip Erase is to erase all the data with "1" and "0" as all "1". It needs 6 cycles to write the action in, and the first two cycles are "unlock" cycles, the third one is a configuration cycle, the fourth and fifth are also "unlock" cycles, and the sixth cycle is the chip erase operation. During chip erasing, all the commands will not be accepted except hardware rests or the working voltage is too low that chip erase will be interrupted. After Chip Erase, the chip will return to the state of Read Array. When the embedded chip erase operation is on going, user can confirm if the embedded operation is finished or not by the following methods: Status Q7 Q6 Q5 Q2 RY/BY# In progress 0 Toggling 0 Toggling 0 Finished 1 Stop toggling 0 1 1 Exceed time limit 0 Toggling 1 Toggling 0 SECTOR ERASE Sector Erase is to erase all the data in a sector with "1" and "0" as all "1". It requires six command cycles to issue. The first two cycles are "unlock cycles", the third one is a configuration cycle, the fourth and fifth are also "unlock cycles" and the sixth cycle is the sector erase command. After the sector erase command sequence is issued, there is a time-out period of 50us counted internally. During the time-out period, additional sector address and sector erase command can be written multiply. Once user enters another sector erase command, the time-out period of 50us is recounted. If user enters any command other than sector erase or erase suspend during time-out period, the erase command would be aborted and the device is reset to read array condition. The number of sectors could be from one sector to all sectors. After time-out period passing by, additional erase command is not accepted and erase embedded operation begins. During sector erasing, all commands will not be accepted except hardware reset and erase suspend and user can check the status as chip erase. When the embedded erase operation is on going, user can confirm if the embedded operation is finished or not by the following methods: Status Q7 Q6 Q5 Q3 Q2 RY/BY#*2 Time-out period 0 Toggling 0 0 Toggling 0 In progress 0 Toggling 0 1 Toggling 0 Finished 1 Stop toggling 0 1 1 1 Exceed time limit 0 Toggling 1 1 Toggling 0 *1: The status Q3 is the time-out period indicator. When Q3=0, the device is in time-out period and is acceptible to another sector address to be erased. When Q3=1, the device is in erase operation and only erase suspend is valid. *2: RY/BY# is open drain output pin and should be weakly connected to VDD through a pull-up resistor. *3: When an attempt is made to erase a protected sector, Q7 will output its complement data or Q6 continues to toggle for 100us and the device returned to read array status without erasing the data in the protected sector. P/N:PM1200 REV. 2.2, NOV. 29, 2010 13 MX29F400C T/B SECTOR ERASE SUSPEND During sector erasure, sector erase suspend is the only valid command. If user issue erase suspend command in the time-out period of sector erasure, device time-out period will be over immediately and the device will go back to erase-suspended read array mode. If user issue erase suspend command during the sector erase is being operated, device will suspend the ongoing erase operation, and after the Tready1(