MX29GL640EHXFI-90G

MX29GL640E T/B MX29GL640E H/L MX29GL640E T/B, MX29GL640E H/L DATASHEET P/N:PM1494 REV. 1.6, OCT. 30, 2013 1 MX29GL640E T/B MX29GL640E H/L Contents FEATURES.............................................................................................................................................................. 5 PIN CONFIGURATION for MX29GL640E T/B........................................................................................................ 6 PIN CONFIGURATION for MX29GL640E H/L........................................................................................................ 7 PIN DESCRIPTION.................................................................................................................................................. 8 BLOCK DIAGRAM................................................................................................................................................... 9 BLOCK DIAGRAM DESCRIPTION....................................................................................................................... 10 BLOCK STRUCTURE............................................................................................................................................ 11 Table 1-1. MX29GL640ET SECTOR ARCHITECTURE .............................................................................. 11 Table 1-2. MX29GL640EB SECTOR ARCHITECTURE .............................................................................. 15 Table 1-3. MX29GL640E H/L SECTOR ARCHITECTURE ......................................................................... 19 FUNCTIONAL OPERATION DESCRIPTION........................................................................................................ 24 READ OPERATION..................................................................................................................................... 24 PAGE READ................................................................................................................................................. 24 WRITE OPERATION.................................................................................................................................... 24 DEVICE RESET........................................................................................................................................... 24 STANDBY MODE......................................................................................................................................... 24 OUTPUT DISABLE...................................................................................................................................... 25 BYTE/WORD SELECTION.......................................................................................................................... 25 HARDWARE WRITE PROTECT.................................................................................................................. 25 ACCELERATED PROGRAMMING OPERATION ....................................................................................... 25 WRITE BUFFER PROGRAMMING OPERATION....................................................................................... 25 SECTOR PROTECT OPERATION.............................................................................................................. 26 AUTOMATIC SELECT BUS OPERATIONS................................................................................................. 26 SECTOR LOCK STATUS VERIFICATION................................................................................................... 26 READ SILICON ID MANUFACTURER CODE............................................................................................. 27 READ INDICATOR BIT (Q7) FOR SECURITY SECTOR............................................................................ 27 INHERENT DATA PROTECTION................................................................................................................. 27 COMMAND COMPLETION.......................................................................................................................... 27 LOW VCC WRITE INHIBIT.......................................................................................................................... 27 WRITE PULSE "GLITCH" PROTECTION.................................................................................................... 27 LOGICAL INHIBIT........................................................................................................................................ 27 POWER-UP SEQUENCE............................................................................................................................ 28 POWER-UP WRITE INHIBIT....................................................................................................................... 28 POWER SUPPLY DECOUPLING................................................................................................................ 28 COMMAND OPERATIONS.................................................................................................................................... 29 READING THE MEMORY ARRAY............................................................................................................... 29 AUTOMATIC PROGRAMMING OF THE MEMORY ARRAY...................................................................... 29 ERASING THE MEMORY ARRAY............................................................................................................... 30 SECTOR ERASE......................................................................................................................................... 30 CHIP ERASE............................................................................................................................................... 31 P/N:PM1494 REV. 1.6, OCT. 30, 2013 2 MX29GL640E T/B MX29GL640E H/L ERASE SUSPEND/RESUME...................................................................................................................... 32 SECTOR ERASE RESUME......................................................................................................................... 32 PROGRAM SUSPEND/RESUME................................................................................................................ 33 PROGRAM RESUME.................................................................................................................................. 33 BUFFER WRITE ABORT............................................................................................................................. 33 AUTOMATIC SELECT OPERATIONS......................................................................................................... 34 AUTOMATIC SELECT COMMAND SEQUENCE........................................................................................ 34 READ MANUFACTURER ID OR DEVICE ID.............................................................................................. 35 RESET ........................................................................................................................................................ 35 ADVANCED SECTOR PROTECTION/UN-PROTECTION.......................................................................... 36 Figure 1. Advance Sector Protection/Unprotection SPB Program Algorithm............................................... 36 Figure 2. Lock Register Program Algorithm................................................................................................. 37 Figure 3. SPB Program Algorithm................................................................................................................ 39 SECURITY SECTOR FLASH MEMORY REGION...................................................................................... 42 TABLE 3. COMMAND DEFINITIONS.......................................................................................................... 43 COMMON FLASH MEMORY INTERFACE (CFI) MODE...................................................................................... 46 QUERY COMMAND AND COMMAND FLASH MEMORY INTERFACE (CFI) MODE................................ 46 Table 4-1. CFI mode: Identification Data Values (Note 1) ................................................................................. 46 Table 4-2. CFI mode: System Interface Data Values................................................................................... 46 Table 4-3. CFI mode: Device Geometry Data Values................................................................................... 47 Table 4-4. CFI mode: Primary Vendor-Specific Extended Query Data Values............................................. 48 ELECTRICAL CHARACTERISTICS..................................................................................................................... 49 ABSOLUTE MAXIMUM STRESS RATINGS................................................................................................ 49 OPERATING TEMPERATURE AND VOLTAGE........................................................................................... 49 DC CHARACTERISTICS............................................................................................................................. 50 SWITCHING TEST CIRCUITS..................................................................................................................... 51 SWITCHING TEST WAVEFORMS............................................................................................................. 51 AC CHARACTERISTICS............................................................................................................................. 52 Figure 4. COMMAND WRITE OPERATION................................................................................................. 53 READ/RESET OPERATION.................................................................................................................................. 54 Figure 5. READ TIMING WAVEFORMS...................................................................................................... 54 Figure 6. RESET# TIMING WAVEFORM.................................................................................................... 55 ERASE/PROGRAM OPERATION......................................................................................................................... 56 Figure 7. AUTOMATIC CHIP ERASE TIMING WAVEFORM....................................................................... 56 Figure 8. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART............................................................. 57 Figure 9. AUTOMATIC SECTOR ERASE TIMING WAVEFORM................................................................. 58 Figure 10. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART.................................................... 59 Figure 11. ERASE SUSPEND/RESUME FLOWCHART.............................................................................. 60 Figure 12. AUTOMATIC PROGRAM TIMING WAVEFORMS...................................................................... 61 Figure 13. ACCELERATED PROGRAM TIMING DIAGRAM....................................................................... 61 Figure 14. CE# CONTROLLED WRITE TIMING WAVEFORM.................................................................... 62 Figure 15. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART..................................................... 63 P/N:PM1494 REV. 1.6, OCT. 30, 2013 3 MX29GL640E T/B MX29GL640E H/L Figure 16. SILICON ID READ TIMING WAVEFORM................................................................................... 64 WRITE OPERATION STATUS............................................................................................................................... 65 Figure 17. DATA# POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)................... 65 Figure 18. STATUS POLLING FOR WORD PROGRAM/ERASE................................................................ 66 Figure 19. STATUS POLLING FOR WRITE BUFFER PROGRAM.............................................................. 67 Figure 20. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)........................ 68 Figure 21. TOGGLE BIT ALGORITHM........................................................................................................ 69 Figure 22. BYTE# TIMING WAVEFORM FOR READ OPERATIONS (BYTE# switching from byte mode to word mode).................................................................................................................................................. 70 Figure 23. PAGE READ TIMING WAVEFORM............................................................................................ 70 Figure 24. DEEP POWER DOWN MODE WAVEFORM ............................................................................. 71 Figure 25. WRITE BUFFER PROGRAM FLOWCHART.............................................................................. 72 RECOMMENDED OPERATING CONDITIONS..................................................................................................... 73 ERASE AND PROGRAMMING PERFORMANCE................................................................................................ 74 DATA RETENTION................................................................................................................................................ 74 LATCH-UP CHARACTERISTICS.......................................................................................................................... 74 PIN CAPACITANCE............................................................................................................................................... 74 ORDERING INFORMATION.................................................................................................................................. 75 PART NAME DESCRIPTION................................................................................................................................. 76 PACKAGE INFORMATION.................................................................................................................................... 77 REVISION HISTORY ............................................................................................................................................. 81 P/N:PM1494 REV. 1.6, OCT. 30, 2013 4 MX29GL640E T/B MX29GL640E H/L FEATURES SINGLE VOLTAGE 3V ONLY FLASH MEMORY GENERAL FEATURES • Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations - V I/O voltage must tight with VCC - VI/O=VCC=2.7V~3.6V • Byte/Word mode switchable - 8,388,608 x 8 / 4,194,304 x 16 • Sector architecture - MX29GL640E T/B: 127 x 32Kword(64KB) + 8 x 4Kword(8KB) boot sector - MX29GL640E H/L: 128 x 32Kword(64KB) Uniform sector • 16-byte/8-word page read buffer • 32-byte/16-word write buffer • Extra 128-word sector for security - Features factory locked and identifiable, and customer lockable • Advanced sector protection function (Solid and Password Protect) • Latch-up protected to 100mA from -1V to 1.5xVcc • Low Vcc write inhibit : Vcc ≤ VLKO • Compatible with JEDEC standard - Pinout and software compatible to single power supply Flash • Deep power down mode PERFORMANCE • High Performance - Fast access time: 70ns - Page access time: 25ns - Fast program time: 10us/word - Fast erase time: 0.5s/secter (typical) • Low Power Consumption - Low active read current: 10mA (typical) at 5MHz - Low standby current: 20uA (typical) • Typical 100,000 erase/program cycle • 20 years data retention SOFTWARE FEATURES • Program/Erase Suspend & Program/Erase Resume - Suspends sector erase operation to read data from or program data to another sector which is not being erased - Suspends sector program operation to read data from another sector which is not being program • Status Reply - Data# Polling & Toggle bits provide detection of program and erase operation completion • Support Common Flash Interface (CFI) HARDWARE FEATURES • Ready/Busy# (RY/BY#) Output - Provides a hardware method of detecting program and erase operation completion • Hardware Reset (RESET#) Input - Provides a hardware method to reset the internal state machine to read mode • WP#/ACC input pin - Hardware write protect pin/Provides accelerated program capability - MX29GL640E T/B: Protect Top or Bottom two sectors if WP#/ACC=Vil - MX29GL640E H/L: Protect first or last sector if WP#/ACC=Vil PACKAGE • MX29GL640E T/B - 48-pin TSOP - 48-ball LFBGA (6x8mm) • MX29GL640E H/L - 56-pin TSOP - 64-ball LFBGA (11x13mm) • All devices are RoHS Compliant and Halogen-free P/N:PM1494 REV. 1.6, OCT. 30, 2013 5 MX29GL640E T/B MX29GL640E H/L PIN CONFIGURATION for MX29GL640E T/B 48 TSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RESET# A21 WP#/ACC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE# GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC Q11 Q3 Q10 Q2 Q9 Q1 Q8 Q0 OE# GND CE# A0 48 LFBGA A B C D E F G H BYTE# Q15/ A-1 GND 6 A13 A12 A14 A15 A16 5 A9 A8 A10 A11 Q7 Q14 Q13 Q6 4 WE# RESET# A21 A19 Q5 Q12 VCC Q4 3 RY/ BY# WP#/ ACC A18 A20 Q2 Q10 Q11 Q3 2 A7 A17 A6 A5 Q0 Q8 Q9 Q1 1 A3 A4 A2 A1 A0 CE# OE# GND 6.0 mm 8.0 mm P/N:PM1494 REV. 1.6, OCT. 30, 2013 6 MX29GL640E T/B MX29GL640E H/L PIN CONFIGURATION for MX29GL640E H/L 56 TSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 NC NC A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RESET# A21 WP#/ACC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 NC NC NC NC A16 BYTE# GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC Q11 Q3 Q10 Q2 Q9 Q1 Q8 Q0 OE# GND CE# A0 NC VI/O 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 64 LFBGA 8 NC NC NC VIO GND NC NC NC 7 A13 A12 A14 A15 A16 BYTE# Q15/ A-1 GND 6 A9 A8 A10 A11 Q7 Q14 Q13 Q6 5 WE# RESET# A21 A19 Q5 Q12 VCC Q4 4 RY/ BY# WP#/ ACC A18 A20 Q2 Q10 Q11 Q3 3 A7 A17 A6 A5 Q0 Q8 Q9 Q1 2 A3 A4 A2 A1 A0 CE# OE# GND 1 NC NC NC NC NC VIO NC NC C D E F G H A B P/N:PM1494 REV. 1.6, OCT. 30, 2013 7 MX29GL640E T/B MX29GL640E H/L PIN DESCRIPTION LOGIC SYMBOL SYMBOL PIN NAME A0~A21 Address Input Q0~Q14 Q15/A-1 CE# WE# OE# RESET# Data Inputs/Outputs Q15(Word Mode)/LSB addr(Byte Mode) Chip Enable Input Write Enable Input Output Enable Input Hardware Reset Pin, Active Low 22 A0-A21 Q0-Q15 (A-1) 16 or 8 CE# OE# Hardware Write Protect/Programming WP#/ACC* Acceleration input RY/BY# Read/Busy Output BYTE# Selects 8 bits or 16 bits mode VCC +3.0V single power supply GND Device Ground NC Pin Not Connected Internally VI/O Power Supply for Input/Output WE# RESET# WP#/ACC RY/BY# BYTE# VI/O Notes: 1. WP#/ACC has internal pull up. 2. VI/O voltage must tight with VCC. VI/O = VCC =2.7V~3.6V. P/N:PM1494 REV. 1.6, OCT. 30, 2013 8 MX29GL640E T/B MX29GL640E H/L BLOCK DIAGRAM CE# OE# WE# RESET# BYTE# WP#/ACC CONTROL INPUT LOGIC PROGRAM/ERASE STATE HIGH VOLTAGE MACHINE (WSM) LATCH BUFFER FLASH REGISTER ARRAY ARRAY Y-DECODER AND STATE X-DECODER ADDRESS A0-AM WRITE Y-PASS GATE SOURCE HV COMMAND DATA DECODER SENSE AMPLIFIER PGM DATA HV COMMAND DATA LATCH PROGRAM DATA LATCH Q0-Q15/A-1 I/O BUFFER AM: MSB address P/N:PM1494 REV. 1.6, OCT. 30, 2013 9 MX29GL640E T/B MX29GL640E H/L BLOCK DIAGRAM DESCRIPTION The block diagram illustrates a simplified architecture of this device. Each block in the block diagram represents one or more circuit modules in the real chip used to access, erase, program, and read the memory array. The "CONTROL INPUT LOGIC" block receives input pins CE#, OE#, WE#, RESET#, BYTE#, and WP#/ACC. It creates internal timing control signals according to the input pins and outputs to the "ADDRESS LATCH AND BUFFER" to latch the external address pins A0-AM. The internal addresses are output from this block to the main array and decoders composed of "X-DECODER", "Y-DECODER", "Y-PASS GATE", AND "FLASH ARRAY". The X-DECODER decodes the word-lines of the flash array, while the Y-DECODER decodes the bit-lines of the flash array. The bit lines are electrically connected to the "SENSE AMPLIFIER" and "PGM DATA HV" selectively through the Y-PASS GATES. SENSE AMPLIFIERS are used to read out the contents of the flash memory, while the "PGM DATA HV" block is used to selectively deliver high power to bit-lines during programming. The "I/O BUFFER" controls the input and output on the Q0-Q15/A-1 pads. During read operation, the I/O BUFFER receives data from SENSE AMPLIFIERS and drives the output pads accordingly. In the last cycle of program command, the I/O BUFFER transmits the data on Q0-Q15/A-1 to "PROGRAM DATA LATCH", which controls the high power drivers in "PGM DATA HV" to selectively program the bits in a word or byte according to the user input pattern. The "PROGRAM/ERASE HIGH VOLTAGE" block comprises the circuits to generate and deliver the necessary high voltage to the X-DECODER, FLASH ARRAY, and "PGM DATA HV" blocks. The logic control module comprises of the "WRITE STATE MACHINE, WSM", "STATE REGISTER", "COMMAND DATA DECODER", and "COMMAND DATA LATCH". When the user issues a command by toggling WE#, the command on Q0-A15/A-1 is latched in the COMMAND DATA LATCH and is decoded by the COMMAND DATA DECODER. The STATE REGISTER receives the command and records the current state of the device. The WSM implements the internal algorithms for program or erase according to the current command state by controlling each block in the block diagram. ARRAY ARCHITECTURE The main flash memory array can be organized as Byte mode (x8) or Word mode (x16). The details of the address ranges and the corresponding sector addresses are shown in Table 1. P/N:PM1494 REV. 1.6, OCT. 30, 2013 10 MX29GL640E T/B MX29GL640E H/L BLOCK STRUCTURE Table 1-1. MX29GL640ET SECTOR ARCHITECTURE Sector Size Kbytes Kwords 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 Sector Address A21-A12 0000000xxx 0000001xxx 0000010xxx 0000011xxx 0000100xxx 0000101xxx 0000110xxx 0000111xxx 0001000xxx 0001001xxx 0001010xxx 0001011xxx 0001100xxx 0001101xxx 0001110xxx 0001111xxx 0010000xxx 0010001xxx 0010010xxx 0010011xxx 0010100xxx 0010101xxx 0010110xxx 0010111xxx 0011000xxx 0011001xxx 0011010xxx 0011011xxx 0011100xxx 0011101xxx 0011110xxx 0011111xxx 0100000xxx 0100001xxx 0100010xxx 0100011xxx 0100100xxx 0100101xxx 0100110xxx 0100111xxx P/N:PM1494 (x8) Address Range 000000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 200000h-20FFFFh 210000h-21FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 260000h-26FFFFh 270000h-27FFFFh (x16) Address Range 000000h-07FFFh 008000h-0FFFFh 010000h-17FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh REV. 1.6, OCT. 30, 2013 11 MX29GL640E T/B MX29GL640E H/L Sector Size Kbytes Kwords 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 Sector SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 Sector Address A21-A12 0101000xxx 0101001xxx 0101010xxx 0101011xxx 0101100xxx 0101101xxx 0101110xxx 0101111xxx 0110000xxx 0110001xxx 0110010xxx 0110011xxx 0110100xxx 0110101xxx 0110110xxx 0110111xxx 0111000xxx 0111001xxx 0111010xxx 0111011xxx 0111100xxx 0111101xxx 0111110xxx 0111111xxx 1000000xxx 1000001xxx 1000010xxx 1000011xxx 1000100xxx 1000101xxx 1000110xxx 1000111xxx 1001000xxx 1001001xxx 1001010xxx 1001011xxx 1001100xxx 1001101xxx 1001110xxx 1001111xxx 1010000xxx 1010001xxx 1010010xxx P/N:PM1494 (x8) Address Range 280000h-28FFFFh 290000h-29FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3FFFFFh 400000h-40FFFFh 410000h-41FFFFh 420000h-42FFFFh 430000h-43FFFFh 440000h-44FFFFh 450000h-45FFFFh 460000h-46FFFFh 470000h-47FFFFh 480000h-48FFFFh 490000h-49FFFFh 4A0000h-4AFFFFh 4B0000h-4BFFFFh 4C0000h-4CFFFFh 4D0000h-4DFFFFh 4E0000h-4EFFFFh 4F0000h-4FFFFFh 500000h-50FFFFh 510000h-51FFFFh 520000h-52FFFFh (x16) Address Range 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-147FFFh 168000h-14FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh 200000h-207FFFh 208000h-20FFFFh 210000h-217FFFh 218000h-21FFFFh 220000h-227FFFh 228000h-22FFFFh 230000h-237FFFh 238000h-23FFFFh 240000h-247FFFh 248000h-24FFFFh 250000h-257FFFh 258000h-25FFFFh 260000h-247FFFh 268000h-24FFFFh 270000h-277FFFh 278000h-27FFFFh 280000h-287FFFh 288000h-28FFFFh 290000h-297FFFh REV. 1.6, OCT. 30, 2013 12 MX29GL640E T/B MX29GL640E H/L Sector Size Kbytes Kwords 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 Sector SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 Sector Address A21-A12 1010011xxx 1010100xxx 1010101xxx 1010110xxx 1010111xxx 1011000xxx 1011001xxx 1011010xxx 1011011xxx 1011100xxx 1011101xxx 1011110xxx 1011111xxx 1100000xxx 1100001xxx 1100010xxx 1100011xxx 1100100xxx 1100101xxx 1100110xxx 1100111xxx 1101000xxx 1101001xxx 1101010xxx 1101011xxx 1101100xxx 1101101xxx 1101110xxx 1101111xxx 1110000xxx 1110001xxx 1110010xxx 1110011xxx 1110100xxx 1110101xxx 1110110xxx 1110111xxx 1111000xxx 1111001xxx 1111010xxx 1111011xxx 1111100xxx 1111101xxx P/N:PM1494 (x8) Address Range 530000h-53FFFFh 540000h-54FFFFh 550000h-55FFFFh 560000h-56FFFFh 570000h-57FFFFh 580000h-58FFFFh 590000h-59FFFFh 5A0000h-5AFFFFh 5B0000h-5BFFFFh 5C0000h-5CFFFFh 5D0000h-5DFFFFh 5E0000h-5EFFFFh 5F0000h-5FFFFFh 600000h-60FFFFh 610000h-61FFFFh 620000h-62FFFFh 630000h-63FFFFh 640000h-64FFFFh 650000h-65FFFFh 660000h-66FFFFh 670000h-67FFFFh 680000h-68FFFFh 690000h-69FFFFh 6A0000h-6AFFFFh 6B0000h-6BFFFFh 6C0000h-6CFFFFh 6D0000h-6DFFFFh 6E0000h-6EFFFFh 6F0000h-6FFFFFh 700000h-70FFFFh 710000h-71FFFFh 720000h-72FFFFh 730000h-73FFFFh 740000h-74FFFFh 750000h-75FFFFh 760000h-76FFFFh 770000h-77FFFFh 780000h-78FFFFh 790000h-79FFFFh 7A0000h-7AFFFFh 7B0000h-7BFFFFh 7C0000h-7CFFFFh 7D0000h-7DFFFFh (x16) Address Range 298000h-29FFFFh 2A0000h-2A7FFFh 2A8000h-2AFFFFh 2B0000h-2B7FFFh 2B8000h-2BFFFFh 2C0000h-2C7FFFh 2C8000h-2CFFFFh 2D0000h-2D7FFFh 2D8000h-2DFFFFh 2E0000h-2E7FFFh 2E8000h-2EFFFFh 2F0000h-2F7FFFh 2F8000h-2FFFFFh 300000h-307FFFh 308000h-30FFFFh 310000h-317FFFh 318000h-31FFFFh 320000h-327FFFh 328000h-32FFFFh 330000h-337FFFh 338000h-33FFFFh 340000h-347FFFh 348000h-34FFFFh 350000h-357FFFh 358000h-35FFFFh 360000h-347FFFh 368000h-34FFFFh 370000h-377FFFh 378000h-37FFFFh 380000h-387FFFh 388000h-38FFFFh 390000h-397FFFh 398000h-39FFFFh 3A0000h-3A7FFFh 3A8000h-3AFFFFh 3B0000h-3B7FFFh 3B8000h-3BFFFFh 3C0000h-3C7FFFh 3C8000h-3CFFFFh 3D0000h-3D7FFFh 3D8000h-3DFFFFh 3E0000h-3E7FFFh 3E8000h-3EFFFFh REV. 1.6, OCT. 30, 2013 13 MX29GL640E T/B MX29GL640E H/L Sector Size Kbytes Kwords 64 32 8 4 8 4 8 4 8 4 8 4 8 4 8 4 8 4 Sector SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 Sector Address A21-A12 1111110xxx 1111111000 1111111001 1111111010 1111111011 1111111100 1111111101 1111111110 1111111111 P/N:PM1494 (x8) Address Range 7E0000h-7EFFFFh 7F0000h-7F1FFFh 7F2000h-7F3FFFh 7F4000h-7F5FFFh 7F6000h-7F7FFFh 7F8000h-7F9FFFh 7FA000h-7FBFFFh 7FC000h-7FDFFFh 7FE000h-7FFFFFh (x16) Address Range 3F0000h-3F7FFFh 3F8000h-3FFFFFh 3F9000h-3F9FFFh 3FA000h-3FAFFFh 3FB000h-3FBFFFh 3FC000h-3FCFFFh 3FD000h-3FDFFFh 3FE000h-3FEFFFh 3FF000h-3FFFFFh REV. 1.6, OCT. 30, 2013 14 MX29GL640E T/B MX29GL640E H/L Table 1-2. MX29GL640EB SECTOR ARCHITECTURE Sector Size Kbytes Kwords 8 4 8 4 8 4 8 4 8 4 8 4 8 4 8 4 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 Sector Address A21-A12 0000000000 0000000001 0000000010 0000000011 0000000100 0000000101 0000000110 0000000111 0000001xxx 0000010xxx 0000011xxx 0000100xxx 0000101xxx 0000110xxx 0000111xxx 0001000xxx 0001001xxx 0001010xxx 0001011xxx 0001100xxx 0001101xxx 0001110xxx 0001111xxx 0010000xxx 0010001xxx 0010010xxx 0010011xxx 0010100xxx 0010101xxx 0010110xxx 0010111xxx 0011000xxx 0011001xxx 0011010xxx 0011011xxx 0011100xxx 0011101xxx 0011110xxx 0011111xxx 0100000xxx 0100001xxx P/N:PM1494 (x8) Address Range 000000h-001FFFh 002000h-003FFFh 004000h-005FFFh 006000h-007FFFh 008000h-009FFFh 00A000h-00BFFFh 00C000h-00DFFFh 00E000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 200000h-20FFFFh 210000h-21FFFFh (x16) Address Range 000000h-000FFFh 001000h-001FFFh 002000h-002FFFh 003000h-003FFFh 004000h-004FFFh 005000h-005FFFh 006000h-006FFFh 007000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 100000h-107FFFh 108000h-10FFFFh REV. 1.6, OCT. 30, 2013 15 MX29GL640E T/B MX29GL640E H/L Sector Size Kbytes Kwords 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 Sector SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 Sector Address A21-A12 0100010xxx 0100011xxx 0100100xxx 0100101xxx 0100110xxx 0100111xxx 0101000xxx 0101001xxx 0101010xxx 0101011xxx 0101100xxx 0101101xxx 0101110xxx 0101111xxx 0110000xxx 0110001xxx 0110010xxx 0110011xxx 0110100xxx 0110101xxx 0110110xxx 0110111xxx 0111000xxx 0111001xxx 0111010xxx 0111011xxx 0111100xxx 0111101xxx 0111110xxx 0111111xxx 1000000xxx 1000001xxx 1000010xxx 1000011xxx 1000100xxx 1000101xxx 1000110xxx 1000111xxx 1001000xxx 1001001xxx 1001010xxx 1001011xxx P/N:PM1494 (x8) Address Range 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3FFFFFh 400000h-40FFFFh 410000h-41FFFFh 420000h-42FFFFh 430000h-43FFFFh 440000h-44FFFFh 450000h-45FFFFh 460000h-46FFFFh 470000h-47FFFFh 480000h-48FFFFh 490000h-49FFFFh 4A0000h-4AFFFFh 4B0000h-4BFFFFh (x16) Address Range 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh 200000h-207FFFh 208000h-20FFFFh 210000h-217FFFh 218000h-21FFFFh 220000h-227FFFh 228000h-22FFFFh 230000h-237FFFh 238000h-23FFFFh 240000h-247FFFh 248000h-24FFFFh 250000h-257FFFh 258000h-25FFFFh REV. 1.6, OCT. 30, 2013 16 MX29GL640E T/B MX29GL640E H/L Sector Size Kbytes Kwords 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 Sector SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 Sector Address A21-A12 1001100xxx 1001101xxx 1001110xxx 1001111xxx 1010000xxx 1010001xxx 1010010xxx 1010011xxx 1010100xxx 1010101xxx 1010110xxx 1010111xxx 1011000xxx 1011001xxx 1011010xxx 1011011xxx 1011100xxx 1011101xxx 1011110xxx 1011111xxx 1100000xxx 1100001xxx 1100010xxx 1100011xxx 1100100xxx 1100101xxx 1100110xxx 1100111xxx 1101000xxx 1101001xxx 1101010xxx 1101011xxx 1101100xxx 1101101xxx 1101110xxx 1101111xxx 1110000xxx 1110001xxx 1110010xxx 1110011xxx 1110100xxx 1110101xxx P/N:PM1494 (x8) Address Range 4C0000h-4CFFFFh 4D0000h-4DFFFFh 4E0000h-4EFFFFh 4F0000h-4FFFFFh 500000h-50FFFFh 510000h-51FFFFh 520000h-52FFFFh 530000h-53FFFFh 540000h-54FFFFh 550000h-55FFFFh 560000h-56FFFFh 570000h-57FFFFh 580000h-58FFFFh 590000h-59FFFFh 5A0000h-5AFFFFh 5B0000h-5BFFFFh 5C0000h-5CFFFFh 5D0000h-5DFFFFh 5E0000h-5EFFFFh 5F0000h-5FFFFFh 600000h-60FFFFh 610000h-61FFFFh 620000h-62FFFFh 630000h-63FFFFh 640000h-64FFFFh 650000h-65FFFFh 660000h-66FFFFh 670000h-67FFFFh 680000h-68FFFFh 690000h-69FFFFh 6A0000h-6AFFFFh 6B0000h-6BFFFFh 6C0000h-6CFFFFh 6D0000h-6DFFFFh 6E0000h-6EFFFFh 6F0000h-6FFFFFh 700000h-70FFFFh 710000h-71FFFFh 720000h-72FFFFh 730000h-73FFFFh 740000h-74FFFFh 750000h-75FFFFh (x16) Address Range 260000h-267FFFh 268000h-26FFFFh 270000h-277FFFh 278000h-27FFFFh 280000h-287FFFh 288000h-28FFFFh 290000h-297FFFh 298000h-29FFFFh 2A0000h-2A7FFFh 2A8000h-2AFFFFh 2B0000h-2B7FFFh 2B8000h-2BFFFFh 2C0000h-2C7FFFh 2C8000h-2CFFFFh 2D0000h-2D7FFFh 2D8000h-2DFFFFh 2E0000h-2E7FFFh 2E8000h-2EFFFFh 2F0000h-2F7FFFh 2F8000h-2FFFFFh 300000h-307FFFh 308000h-30FFFFh 310000h-317FFFh 318000h-31FFFFh 320000h-327FFFh 328000h-32FFFFh 330000h-337FFFh 338000h-33FFFFh 340000h-347FFFh 348000h-34FFFFh 350000h-357FFFh 358000h-35FFFFh 360000h-367FFFh 368000h-36FFFFh 370000h-377FFFh 378000h-37FFFFh 380000h-387FFFh 388000h-38FFFFh 390000h-397FFFh 398000h-39FFFFh 3A0000h-3A7FFFh 3A8000h-3AFFFFh REV. 1.6, OCT. 30, 2013 17 MX29GL640E T/B MX29GL640E H/L Sector Size Kbytes Kwords 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 Sector SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 Sector Address A21-A12 1110110xxx 1110111xxx 1111000xxx 1111001xxx 1111010xxx 1111011xxx 1111100xxx 1111101xxx 1111110xxx 1111111xxx P/N:PM1494 (x8) Address Range 760000h-76FFFFh 770000h-77FFFFh 780000h-78FFFFh 790000h-79FFFFh 7A0000h-7AFFFFh 7B0000h-7BFFFFh 7C0000h-7CFFFFh 7D0000h-7DFFFFh 7E0000h-7EFFFFh 7F0000h-7FFFFFh (x16) Address Range 3B0000h-3B7FFFh 3B8000h-3BFFFFh 3C0000h-3C7FFFh 3C8000h-3CFFFFh 3D0000h-3D7FFFh 3D8000h-3DFFFFh 3E0000h-3E7FFFh 3E8000h-3EFFFFh 3F0000h-3F7FFFh 3F8000h-3FFFFFh REV. 1.6, OCT. 30, 2013 18 MX29GL640E T/B MX29GL640E H/L Table 1-3. MX29GL640E H/L SECTOR ARCHITECTURE Sector Size Kbytes Kwords 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 Sector Address A21-A15 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 0010010 0010011 0010100 0010101 0010110 0010111 0011000 0011001 0011010 0011011 0011100 0011101 0011110 0011111 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 P/N:PM1494 (x8) Address Range 000000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 200000h-20FFFFh 210000h-21FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 2A0000h-2AFFFFh (x16) Address Range 000000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh REV. 1.6, OCT. 30, 2013 19 MX29GL640E T/B MX29GL640E H/L Sector Size Kbytes Kwords 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 Sector SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 Sector Address A21-A15 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 1010000 1010001 1010010 1010011 1010100 1010101 P/N:PM1494 (x8) Address Range 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3FFFFFh 400000h-40FFFFh 410000h-41FFFFh 420000h-42FFFFh 430000h-43FFFFh 440000h-44FFFFh 450000h-45FFFFh 460000h-46FFFFh 470000h-47FFFFh 480000h-48FFFFh 490000h-49FFFFh 4A0000h-4AFFFFh 4B0000h-4BFFFFh 4C0000h-4CFFFFh 4D0000h-4DFFFFh 4E0000h-4EFFFFh 4F0000h-4FFFFFh 500000h-50FFFFh 510000h-51FFFFh 520000h-52FFFFh 530000h-53FFFFh 540000h-54FFFFh 550000h-55FFFFh (x16) Address Range 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh 200000h-207FFFh 208000h-20FFFFh 210000h-217FFFh 218000h-21FFFFh 220000h-227FFFh 228000h-22FFFFh 230000h-237FFFh 238000h-23FFFFh 240000h-247FFFh 248000h-24FFFFh 250000h-257FFFh 258000h-25FFFFh 260000h-267FFFh 268000h-26FFFFh 270000h-277FFFh 278000h-27FFFFh 280000h-287FFFh 288000h-28FFFFh 290000h-297FFFh 298000h-29FFFFh 2A0000h-2A7FFFh 2A8000h-2AFFFFh REV. 1.6, OCT. 30, 2013 20 MX29GL640E T/B MX29GL640E H/L Sector Size Kbytes Kwords 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 Sector SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 Sector Address A21-A15 1010110 1010111 1011000 1011001 1011010 1011011 1011100 1011101 1011110 1011111 1100000 1100001 1100010 1100011 1100100 1100101 1100110 1100111 1101000 1101001 1101010 1101011 1101100 1101101 1101110 1101111 1110000 1110001 1110010 1110011 1110100 1110101 1110110 1110111 1111000 1111001 1111010 1111011 1111100 1111101 1111110 1111111 P/N:PM1494 (x8) Address Range 560000h-56FFFFh 570000h-57FFFFh 580000h-58FFFFh 590000h-59FFFFh 5A0000h-5AFFFFh 5B0000h-5BFFFFh 5C0000h-5CFFFFh 5D0000h-5DFFFFh 5E0000h-5EFFFFh 5F0000h-5FFFFFh 600000h-60FFFFh 610000h-61FFFFh 620000h-62FFFFh 630000h-63FFFFh 640000h-64FFFFh 650000h-65FFFFh 660000h-66FFFFh 670000h-67FFFFh 680000h-68FFFFh 690000h-69FFFFh 6A0000h-6AFFFFh 6B0000h-6BFFFFh 6C0000h-6CFFFFh 6D0000h-6DFFFFh 6E0000h-6EFFFFh 6F0000h-6FFFFFh 700000h-70FFFFh 710000h-71FFFFh 720000h-72FFFFh 730000h-73FFFFh 740000h-74FFFFh 750000h-75FFFFh 760000h-76FFFFh 770000h-77FFFFh 780000h-78FFFFh 790000h-79FFFFh 7A0000h-7AFFFFh 7B0000h-7BFFFFh 7C0000h-7CFFFFh 7D0000h-7DFFFFh 7E0000h-7EFFFFh 7F0000h-7FFFFFh (x16) Address Range 2B0000h-2B7FFFh 2B8000h-2BFFFFh 2C0000h-2C7FFFh 2C8000h-2CFFFFh 2D0000h-2D7FFFh 2D8000h-2DFFFFh 2E0000h-2E7FFFh 2E8000h-2EFFFFh 2F0000h-2F7FFFh 2F8000h-2FFFFFh 300000h-307FFFh 308000h-30FFFFh 310000h-317FFFh 318000h-31FFFFh 320000h-327FFFh 328000h-32FFFFh 330000h-337FFFh 338000h-33FFFFh 340000h-347FFFh 348000h-34FFFFh 350000h-357FFFh 358000h-35FFFFh 360000h-367FFFh 368000h-36FFFFh 370000h-377FFFh 378000h-37FFFFh 380000h-387FFFh 388000h-38FFFFh 390000h-397FFFh 398000h-39FFFFh 3A0000h-3A7FFFh 3A8000h-3AFFFFh 3B0000h-3B7FFFh 3B8000h-3BFFFFh 3C0000h-3C7FFFh 3C8000h-3CFFFFh 3D0000h-3D7FFFh 3D8000h-3DFFFFh 3E0000h-3E7FFFh 3E8000h-3EFFFFh 3F0000h-3F7FFFh 3F8000h-3FFFFFh REV. 1.6, OCT. 30, 2013 21 MX29GL640E T/B MX29GL640E H/L BUS OPERATION Table 2-1. BUS OPERATION OE# Address (Note4) Data I/O Q7~Q0 X X X HighZ Byte# Vil Vih Data (I/O) Q15~Q8 HighZ HighZ X X X HighZ HighZ HighZ H H H X HighZ HighZ HighZ L/H L H L AIN DOUT DOUT L/H H L L H AIN DIN DIN Note1,2 H L L H AIN DIN DIN Vhv RESET# CE# WE# L Vcc ± 0.3V H X Vcc± 0.3V L Read Mode H Write Accelerate Program Mode Select Device Reset Standby Mode Output Disable Q8-Q14= HighZ, Q15=A1 WP#/ ACC L/H Notes: 1. MX29GL640E T/B: Protect Top or Bottom two sectors if WP#/ACC=Vil. MX29GL640E H/L: Protect first or last sector if WP#/ACC=Vil. 2. When WP#/ACC = Vih, the protection conditions of the outmost sector depends on previous protection conditions. Refer to the advanced protect feature. 3. Q0~Q15 are input (DIN) or output (DOUT) pins according to the requests of command sequence, sector protection, or data polling algorithm. 4. In Word Mode (Byte#=Vih), the addresses are AM to A0, AM: MSB of address. In Byte Mode (Byte#=Vil), the addresses are AM to A-1 (Q15), AM: MSB of address. P/N:PM1494 REV. 1.6, OCT. 30, 2013 22 MX29GL640E T/B MX29GL640E H/L Table 2-2. BUS OPERATION Item AM A11 to to A9 CE# WE# OE# A12 A10 Control Input A8 to A7 A6 A5 to A4 A3 to A2 A1 A0 Q7 ~ Q0 Q15 ~ Q8 Sector Lock Status Verification L H L SA X Vhv X L X L H L 01h or 00h (Note 1) X Read Silicon ID Manufacturer Code L H L X X Vhv X L X L L L C2H X Read Silicon ID -- MX29GL640E T/B Cycle 1 L H L X X Vhv X L X L L H Cycle 2 L H L X X Vhv X L X H H L Cycle 3 L H L X X Vhv X L X H H H 22H(Word), XXH(Byte) 22H(Word), 10H XXH(Byte) 01H (Top) 22H(Word), 00H (Bottom) XXH(Byte) 7EH Read Silicon ID -- MX29GL640E H/L Cycle 1 L H L X X Vhv X L X L L H 7EH 22H(Word), XXH(Byte) Cycle 2 L H L X X Vhv X L X H H L 0CH 22H(Word), XXH(Byte) Cycle 3 L H L X X Vhv X L X H H H 01H 22H(Word), XXH(Byte) Notes: 1. Sector unprotected code:00h. Sector protected code:01h. 2. Factory locked code: WP# protects high address sector: 9Ah. WP# protects low address sector: 8Ah Factory unlocked code: WP# protects high address sector: 1Ah. WP# protects low address sector: 0Ah 3. AM: MSB of address. P/N:PM1494 REV. 1.6, OCT. 30, 2013 23 MX29GL640E T/B MX29GL640E H/L FUNCTIONAL OPERATION DESCRIPTION READ OPERATION To perform a read operation, the system addresses the desired memory array or status register location by providing its address on the address pins and simultaneously enabling the chip by driving CE# & OE# LOW, and WE# HIGH. After the Tce and Toe timing requirements have been met, the system can read the contents of the addressed location by reading the Data (I/O) pins. If either the CE# or OE# is held HIGH, the outputs will remain tri-stated and no data will appear on the output pins. PAGE READ This device is able to conduct MXIC MaskROM compatible high performance page read. Page size is 16 bytes or 8 words. The higher address Amax ~ A3 select the certain page, while A2~A0 for word mode, A2~A-1 for byte mode select the particular word or byte in a page. The page access time is Taa or Tce, following by Tpa for the rest of the page read time. When CE# toggles, access time is Taa or Tce. Page mode can be turned on by keeping "page-read address" constant and changing the "intra-read page" addresses. WRITE OPERATION To perform a write operation, the system provides the desired address on the address pins, enables the chip by asserting CE# LOW, and disables the Data (I/O) pins by holding OE# HIGH. The system then places data to be written on the Data (I/O) pins and pulses WE# LOW. The device captures the address information on the falling edge of WE# and the data on the rising edge of WE#. To see an example, please refer to the timing diagram in Figure 4. The system is not allowed to write invalid commands (commands not defined in this datasheet) to the device. Writing an invalid command may put the device in an undefined state. DEVICE RESET Driving the RESET# pin LOW for a period of Trp or more will return the device to Read mode. If the device is in the middle of a program or erase operation, the reset operation will take at most a period of Tready1 before the device returns to Read mode. Until the device does returns to Read mode, the RY/BY# pin will remain Low (Busy Status). When the RESET# pin is held at GND±0.3V, the device only consumes standby (Isbr) current. However, the device draws larger current if the RESET# pin is held at a voltage greater than GND+0.3V and less than or equal to Vil. It is recommended to tie the system reset signal to the RESET# pin of the flash memory. This allows the device to be reset with the system and puts it in a state where the system can immediately begin reading boot code from it. STANDBY MODE The device enters Standby mode whenever the RESET# and CE# pins are both held High except in the embedded mode. While in this mode, WE# and OE# will be ignored, all Data Output pins will be in a high impedance state, and the device will draw minimal (Isb) current. P/N:PM1494 REV. 1.6, OCT. 30, 2013 24 MX29GL640E T/B MX29GL640E H/L FUNCTIONAL OPERATION DESCRIPTION (cont'd) OUTPUT DISABLE While in active mode (RESET# HIGH and CE# LOW), the OE# pin controls the state of the output pins. If OE# is held HIGH, all Data (I/O) pins will remain tri-stated. If held LOW, the Byte or Word Data (I/O) pins will drive data. BYTE/WORD SELECTION The BYTE# input pin is used to select the organization of the array data and how the data is input/output on the Data (I/O) pins. If the BYTE# pin is held HIGH, Word mode will be selected and all 16 data lines (Q0 to Q15) will be active. If BYTE# is forced LOW, Byte mode will be active and only data lines Q0 to Q7 will be active. Data lines Q8 to Q14 will remain in a high impedance state and Q15 becomes the A-1 address input pin. HARDWARE WRITE PROTECT By driving the WP#/ACC pin LOW. The Top or Bottom two sectors (for MX29GL640E T/B) and the highest or lowest sector (for MX29GL640E H/L) was protected from all erase/program operations. If WP#/ACC is held HIGH (Vih to VCC), these sectors revert to their previously protected/unprotected status. ACCELERATED PROGRAMMING OPERATION By applying high voltage (Vhv) to the WP#/ACC pin, the device will enter the Accelerated Programming mode. This mode permits the system to skip the normal command unlock sequences and program byte/word locations directly. During accelerated programming, the current drawn from the WP#/ACC pin is no more than ICP1. WRITE BUFFER PROGRAMMING OPERATION Programs 32bytes/16words in a programming operation. To trigger the Write Buffer Programming, start by the first two unlock cycles, then third cycle writes the Write Buffer Load command at the destined programming Sector Address. The forth cycle writes the "word locations subtract one" number. Following above operations, system starts to write the mingling of address and data. After the programming of the first address or data, the "write-buffer-page" is selected. The following data should be within the above mentioned page. The "write-buffer-page" is selected by choosing address Amax-A4. "Write-Buffer-Page" address has to be the same for all address/ data write into the write buffer. If not, operation will ABORT. To program the content of the write buffer page this command must be followed by a write to buffer Program confirm command. The operation of write-buffer can be suspended or resumed by the standard commands, once the write buffer programming operation is finished, it’ll return to normal READ mode. P/N:PM1494 REV. 1.6, OCT. 30, 2013 25 MX29GL640E T/B MX29GL640E H/L FUNCTIONAL OPERATION DESCRIPTION (cont'd) WRITE BUFFER PROGRAMMING OPERATION (cont'd) ABORT will be executed for the Write Buffer Programming Sequence if following condition occurs: • The value loaded is bigger than the page buffer size during "Number of Locations to Program" • Address written in a sector is not the same as the one assigned during the Write-Buffer-Load command. • Address/ Data pair written to a different write-buffer-page than the one assigned by the "Starting Address" during the "write buffer data loading" operation. • Writing not "Confirm Command" after the assigned number of "data load" cycles. At Write Buffer Abort mode, the status register will be Q1=1, Q7=DATA# (last address written), Q6=toggle. A Write-to-Buffer-Abort Reset command sequence has to be written to reset the device for the next operation. Write buffer programming can be conducted in any sequence. However the CFI functions, autoselect, Secured Silicon sector are not functional when program operation is in progress. Multiple write buffer programming operations on the same write buffer address range without intervening erases is available. Any bit in a write buffer address range can’t be programmed from 0 back to 1. SECTOR PROTECT OPERATION The device provides user programmable protection operations for selected sectors. Please refer to Table 1 which show all Sector assignments. During the protection operation, the sector address of any sector may be used to specify the Sector being protected. AUTOMATIC SELECT BUS OPERATIONS The following five bus operations require A9 to be raised to Vhv. Please see AUTOMATIC SELECT COMMAND SEQUENCE in the COMMAND OPERATIONS section for details of equivalent command operations that do not require the use of Vhv. SECTOR LOCK STATUS VERIFICATION To determine the protected state of any sector using bus operations, the system performs a READ OPERATION with A9 raised to Vhv, the sector address applied to address pins A21 to A12, address pins A6, A3, A2 & A0 held LOW, and address pin A1 held HIGH. If data bit Q0 is LOW, the sector is not protected, and if Q0 is HIGH, the sector is protected. P/N:PM1494 REV. 1.6, OCT. 30, 2013 26 MX29GL640E T/B MX29GL640E H/L FUNCTIONAL OPERATION DESCRIPTION (cont'd) READ SILICON ID MANUFACTURER CODE To determine the Silicon ID Manufacturer Code, the system performs a READ OPERATION with A9 raised to Vhv and address pins A6, A3, A2, A1, & A0 held LOW. The Macronix ID code of C2h should be present on data bits Q0 to Q7. READ INDICATOR BIT (Q7) FOR SECURITY SECTOR To determine if the Security Sector has been locked at the factory, the system performs a READ OPERATION with A9 raised to Vhv, address pin A6, A3 & A2 held LOW, and address pins A1 & A0 held HIGH. If the Security Sector has been locked at the factory, the code 99h(H)/89h(L) will be present on data bits Q0 to Q7. Otherwise, the factory unlocked code of 19h(H)/09h(L) will be present. INHERENT DATA PROTECTION To avoid accidental erasure or programming of the device, the device is automatically reset to Read mode during power up. Additionally, the following design features protect the device from unintended data corruption. COMMAND COMPLETION Only after the successful completion of the specified command sets will the device begin its erase or program operation. The failure in observing valid command sets will result in the memory returning to read mode. LOW VCC WRITE INHIBIT The device refuses to accept any write command when Vcc is less than VLKO. This prevents data from spuriously being altered during power-up, power-down, or temporary power interruptions. The device automatically resets itself when Vcc is lower than VLKO and write cycles are ignored until Vcc is greater than VLKO. The system must provide proper signals on control pins after Vcc rises above VLKO to avoid unintentional program or erase operations. WRITE PULSE "GLITCH" PROTECTION CE#, WE#, OE# pulses shorter than 5ns are treated as glitches and will not be regarded as an effective write cycle. LOGICAL INHIBIT A valid write cycle requires both CE# and WE# at Vil with OE# at Vih. Write cycle is ignored when either CE# at Vih, WE# at Vih, or OE# at Vil. P/N:PM1494 REV. 1.6, OCT. 30, 2013 27 MX29GL640E T/B MX29GL640E H/L FUNCTIONAL OPERATION DESCRIPTION (cont'd) POWER-UP SEQUENCE Upon power up, the device is placed in Read mode. Furthermore, program or erase operation will begin only after successful completion of specified command sequences. POWER-UP WRITE INHIBIT When WE#, CE# is held at Vil and OE# is held at Vih during power up, the device ignores the first command on the rising edge of WE#. POWER SUPPLY DECOUPLING A 0.1uF capacitor should be connected between the Vcc and GND to reduce the noise effect. P/N:PM1494 REV. 1.6, OCT. 30, 2013 28 MX29GL640E T/B MX29GL640E H/L COMMAND OPERATIONS READING THE MEMORY ARRAY Read mode is the default state after power up or after a reset operation. To perform a read operation, please refer to READ OPERATION in the BUS OPERATIONS section above. If the device receives an Erase Suspend command while in the Sector Erase state, the erase operation will pause (after a time delay not exceeding 20us) and the device will enter Erase-Suspended Read mode. While in the Erase-Suspended Read mode, data can be programmed or read from any sector not being erased. Reading from addresses within sector(s) being erased will only return the contents of the status register, which is in fact how the current status of the device can be determined. If a program command is issued to any inactive (not currently being erased) sector during Erase-Suspended Read mode, the device will perform the program operation and automatically return to Erase-Suspended Read mode after the program operation completes successfully. While in Erase-Suspended Read mode, an Erase Resume command must be issued by the system to reactivate the erase operation. The erase operation will resume from where is was suspended and will continue until it completes successfully or another Erase Suspend command is received. After the memory device completes an embedded operation (automatic Chip Erase, Sector Erase, or Program) successfully, it will automatically return to Read mode and data can be read from any address in the array. If the embedded operation fails to complete, as indicated by status register bit Q5 (exceeds time limit flag) going HIGH during the operations, the system must perform a reset operation to return the device to Read mode. There are several states that require a reset operation to return to Read mode: 1. A program or erase failure--indicated by status register bit Q5 going HIGH during the operation. Failures during either of these states will prevent the device from automatically returning to Read mode. 2. The device is in Auto Select mode or CFI mode. These two states remain active until they are terminated by a reset operation. In the two situations above, if a reset operation (either hardware reset or software reset command) is not performed, the device will not return to Read mode and the system will not be able to read array data. AUTOMATIC PROGRAMMING OF THE MEMORY ARRAY The device provides the user the ability to program the memory array in Byte mode or Word mode. As long as the users enters the correct cycle defined in the Table 3 (including 2 unlock cycles and the A0H program command), any byte or word data provided on the data lines by the system will automatically be programmed into the array at the specified location. After the program command sequence has been executed, the internal write state machine (WSM) automatically executes the algorithms and timings necessary for programming and verification, which includes generating suitable program pulses, checking cell threshold voltage margins, and repeating the program pulse if any cells do not pass verification or have low margins. The internal controller protects cells that do pass verification and margin tests from being over-programmed by inhibiting further program pulses to these passing cells as weaker cells continue to be programmed. With the internal WSM automatically controlling the programming process, the user only needs to enter the program command and data once. P/N:PM1494 REV. 1.6, OCT. 30, 2013 29 MX29GL640E T/B MX29GL640E H/L COMMAND OPERATIONS (cont'd) AUTOMATIC PROGRAMMING OF THE MEMORY ARRAY (cont'd) Programming will only change the bit status from "1" to "0". It is not possible to change the bit status from "0" to "1" by programming. This can only be done by an erase operation. Furthermore, the internal write verification only checks and detects errors in cases where a "1" is not successfully programmed to "0". Any commands written to the device during programming will be ignored except hardware reset or program suspend. Hard ware reset will terminate the program operation after a period of time no more than 10us. When the embedded program algorithm is complete or the program operation is terminated by a hardware reset, the device will return to Read mode. Program suspend ready, the device will enter program suspend read mode. After the embedded program operation has begun, the user can check for completion by reading the following bits in the status register: Status In progress Exceed time limit Q7*1 Q7# Q7# Q6*1 Toggling Toggling Q5 0 1 Q1 0 N/A RY/BY# (Note) 0 0 Note: RY/BY# is an open drain output pin and should be connected to VCC through a high value pull-up resistor. ERASING THE MEMORY ARRAY There are two types of erase operations performed on the memory array -- Sector Erase and Chip Erase. In the Sector Erase operation, one or more selected sectors may be erased simultaneously. In the Chip Erase operation, the complete memory array is erased except for any protected sectors. More details of the protected sectors are explained in section Advanced Sector Protection/Un-protection. SECTOR ERASE The sector erase operation is used to clear data within a sector by returning all of its memory locations to the "1" state. It requires six command cycles to initiate the erase operation. The first two cycles are "unlock cycles", the third is a configuration cycle, the fourth and fifth are also "unlock cycles", and the sixth cycle is the Sector Erase command. After the sector erase command sequence has been issued, an internal 50us time-out counter is started. Until this counter reaches zero, additional sector addresses and Sector Erase commands may be issued thus allowing multiple sectors to be selected and erased simultaneously. After the 50us time-out counter has expired, no new commands will be accepted and the embedded sector erase operation will begin. Note that the 50us timer-out counter is restarted after every erase command sequence. If the user enters any command other than Sector Erase or Erase Suspend during the time-out period, the erase operation will abort and the device will return to Read mode. After the embedded sector erase operation begins, all commands except Erase Suspend will be ignored. The only way to interrupt the operation is with an Erase Suspend command or with a hardware reset. The hardware reset will completely abort the operation and return the device to Read mode. P/N:PM1494 REV. 1.6, OCT. 30, 2013 30 MX29GL640E T/B MX29GL640E H/L COMMAND OPERATIONS (cont'd) SECTOR ERASE (cont'd) The system can determine the status of the embedded sector erase operation by the following methods: Status Time-out period In progress Exceeded time limit Q7 0 0 0 Q6 Toggling Toggling Toggling Q3*1 0 1 1 Q5 0 0 1 Q2 Toggling Toggling Toggling RY/BY#*2 0 0 0 Notes: 1. The Q3 status bit is the 50us time-out indicator. When Q3=0, the 50us time-out counter has not yet reached zero and a new Sector Erase command may be issued to specify the address of another sector to be erased. When Q3=1, the 50us time-out counter has expired and the Sector Erase operation has already begun. Erase Suspend is the only valid command that may be issued once the embedded erase operation is underway. 2. RY/BY# is open drain output pin and should be connected to VCC through a high value pull-up resistor. 3. When an attempt is made to erase only protected sector(s), the erase operation will abort thus preventing any data changes in the protected sector(s). Q7 will output "0" and Q6 will toggle briefly (100us or less) before aborting and returning the device to Read mode. If unprotected sectors are also specified, however, they will be erased normally and the protected sector(s) will remain unchanged. 4. Q2 is a localized indicator showing a specified sector is undergoing erase operation or not. Q2 toggles when user reads at addresses where the sectors are actively being erased (in erase mode) or to be erased (in erase suspend mode). CHIP ERASE The Chip Erase operation is used erase all the data within the memory array. All memory cells containing a "0" will be returned to the erased state of "1". This operation requires 6 write cycles to initiate the action. The first two cycles are "unlock" cycles, the third is a configuration cycle, the fourth and fifth are also "unlock" cycles, and the sixth cycle initiates the chip erase operation. During the chip erase operation, no other software commands will be accepted, but if a hardware reset is received or the working voltage is too low, that chip erase will be terminated. After Chip Erase, the chip will automatically return to Read mode. The system can determine the status of the embedded chip erase operation by the following methods: Status In progress Exceed time limit Q7 0 0 Q6 Toggling Toggling Q5 0 1 Q2 Toggling Toggling RY/BY#*1 0 0 *1: RY/BY# is open drain output pin and should be connected to VCC through a high value pull-up resistor. P/N:PM1494 REV. 1.6, OCT. 30, 2013 31 MX29GL640E T/B MX29GL640E H/L COMMAND OPERATIONS (cont'd) ERASE SUSPEND/RESUME After beginning a sector erase operation, Erase Suspend is the only valid command that may be issued. If system issues an Erase Suspend command during the 50us time-out period following a Sector Erase command, the time-out period will terminate immediately and the device will enter Erase-Suspended Read mode. If the system issues an Erase Suspend command after the sector erase operation has already begun, the device will not enter Erase-Suspended Read mode until 20us time has elapsed. The system can determine if the device has entered the Erase-Suspended Read mode through Q6, Q7, and RY/BY#. After the device has entered Erase-Suspended Read mode, the system can read or program any sector(s) except those being erased by the suspended erase operation. Reading any sector being erased or programmed will return the contents of the status register. Whenever a suspend command is issued, user must issue a resume command and check Q6 toggle bit status, before issue another erase command. The system can use the status register bits shown in the following table to determine the current state of the device: Status Erase suspend read in erase suspended sector Erase suspend read in non-erase suspended sector Q7 Q6 Q5 Q3 Q2 Q1 RY/BY# 1 No toggle 0 N/A toggle N/A 1 Data Data 1 N/A N/A 0 Data Erase suspend program in non-erase suspended sector Q7# Data Toggle Data Data 0 N/A When the device has suspended erasing, user can execute the command sets except sector erase and chip erase, such as read silicon ID, sector protect verify, program, CFI query and erase resume. SECTOR ERASE RESUME The sector Erase Resume command is valid only when the device is in Erase-Suspended Read mode. After erase resumes, the user can issue another Ease Suspend command, but there should be a 400us interval between Ease Resume and the next Erase Suspend command. P/N:PM1494 REV. 1.6, OCT. 30, 2013 32 MX29GL640E T/B MX29GL640E H/L COMMAND OPERATIONS (cont'd) PROGRAM SUSPEND/RESUME After beginning a program operation, Program Suspend is the only valid command that may be issued. The system can determine if the device has entered the Program-Suspended Read mode through Q6 and RY/BY#. After the device has entered Program-Suspended mode, the system can read any sector(s) except those being programmed by the suspended program operation. Reading the sector being program suspended is invalid. Whenever a suspend command is issued, user must issue a resume command and check Q6 toggle bit status, before issue another program command. The system can use the status register bits shown in the following table to determine the current state of the device: Status Q7 Q6 Q5 Program suspend read in program suspended sector Q3 Q2 Q1 Invalid Program suspend read in non-program suspended Data sector Data Data RY/BY# 1 Data Data Data 1 When the device has Program/Erase suspended, user can execute read array, auto-select, read CFI, read security silicon. PROGRAM RESUME The Program Resume command is valid only when the device is in Program-Suspended mode. After program resumes, the user can issue another Program Suspend command, but there should be a 5us interval between Program Resume and the next Program Suspend command. BUFFER WRITE ABORT Q1 is the indicator of Buffer Write Abort. When Q1=1, the device will abort from buffer write and go back to read status register shown as following table: Status Q7 Q6 Q5 Q3 Q2 Q1 RY/BY# Buffer Write Busy Q7# Toggle 0 N/A N/A 0 0 Buffer Write Abort Q7# Toggle 0 N/A N/A 1 0 Buffer Write Exceeded Time Limit Q7# Toggle 1 N/A N/A 0 0 P/N:PM1494 REV. 1.6, OCT. 30, 2013 33 MX29GL640E T/B MX29GL640E H/L COMMAND OPERATIONS (cont'd) AUTOMATIC SELECT OPERATIONS When the device is in Read mode, Program Suspended mode, Erase-Suspended Read mode, or CFI mode, the user can issue the Automatic Select command shown in Table 3 (two unlock cycles followed by the Automatic Select command 90h) to enter Automatic Select mode. After entering Automatic Select mode, the user can query the Manufacturer ID, Device ID, Security Sector locked status, or Sector protected status multiple times without issuing a new Automatic Select command. While In Automatic Select mode, issuing a Reset command (F0h) will return the device to Read mode (or EaseSuspended Read mode if Erase-Suspend was active) or Program Suspended Read mode if Program Suspend was active. Another way to enter Automatic Select mode is to use one of the bus operations shown in Table 2-2. BUS OPERATION. After the high voltage (Vhv) is removed from the A9 pin, the device will automatically return to Read mode or Erase-Suspended Read mode. AUTOMATIC SELECT COMMAND SEQUENCE Automatic Select mode is used to access the manufacturer ID, device ID and to verify whether or not secured silicon is locked and whether or not a sector is protected. The automatic select mode has four command cycles. The first two are unlock cycles, and followed by a specific command. The fourth cycle is a normal read cycle, and user can read at any address any number of times without entering another command sequence. The Reset command is necessary to exit the Automatic Select mode and back to read array. The following table shows the identification code with corresponding address. Manufacturer ID MX29GL640E T/B Device ID MX29GL640E H/L Address Word X00 Byte X00 Word X01/0E/0F Byte X02/1C/1E Word X01/0E/0F Data (Hex) C2 C2 227E/2210/2201 (Top) 227E/2210/2200 (Bottom) 7E/10/01 (Top) 7E/10/00 (Bottom) 227E/220C/2201 Byte X02/1C/1E 7E/0C/01 Word X03 Byte X06 9A/1A (H) 8A/0A (L) 9A/1A (H) 8A/0A (L) Secured Silicon Word Sector Protect Verify Byte (Sector address) X 02 (Sector address) X 04 Representation Factory locked/ unlocked Factory locked/ unlocked 00/01 Unprotected/protected 00/01 Unprotected/protected After entering automatic select mode, no other commands are allowed except the reset command. P/N:PM1494 REV. 1.6, OCT. 30, 2013 34 MX29GL640E T/B MX29GL640E H/L COMMAND OPERATIONS (cont'd) READ MANUFACTURER ID OR DEVICE ID The Manufacturer ID (identification) is a unique hexadecimal number assigned to each manufacturer by the JEDEC committee. Each company has its own manufacturer ID, which is different from the ID of all other companies. The number assigned to Macronix is C2h. After entering Automatic Select mode, performing a read operation with A1 & A0 held LOW will cause the device to output the Manufacturer ID on the Data I/O (Q7 to Q0) pins. RESET In the following situations, executing reset command will reset device back to Read mode: • • • • Among erase command sequence (before the full command set is completed) Sector erase time-out period Erase fail (while Q5 is high) Among program command sequence (before the full command set is completed, erase-suspended program included) • Program fail (while Q5 is high, and erase-suspended program fail is included) • Auto-select mode • CFI mode While device is at the status of program fail or erase fail (Q5 is high), user must issue reset command to reset device back to read array mode. While the device is in Auto-Select mode or CFI mode, user must issue reset command to reset device back to read array mode. When the device is in the progress of programming (not program fail) or erasing (not erase fail), device will ignore reset command. P/N:PM1494 REV. 1.6, OCT. 30, 2013 35 MX29GL640E T/B MX29GL640E H/L ADVANCED SECTOR PROTECTION/UN-PROTECTION There are two ways to implement software Advanced Sector Protection on this device: Password method or Solid methods. Through these two protection methods, user can disable or enable the programming or erasing operation to any individual sector or the whole chip. The figure below helps to describe an overview of these methods. The device is default to the Solid mode. All sectors are default as unprotected when shipped from factory. The detailed algorithm of advance sector protection is shown as follows: Figure 1. Advance Sector Protection/Unprotection SPB Program Algorithm Start To choose protection mode set lock register bit (Q1/Q2) Q1=0 Solid Protection Mode Q2=0 Password Protection Mode Set 64 bit Password Set SPB Lock Bit SPBLK = 0 SPB Lock bit locked All SPBs can not changeable SPBLK = 1 SPB Lock bit Unlocked All SPBs are changeable Dynamic write Protect bit (DPB) DPB=0 sector protect Sector Array DPB=1 sector unprotect Solid write Protect bit (SPB) Temporary Unprotect SPB bit (USPB) SPB=0 sector protect USPB=0 SPB bit is disabled SPB=1 sector unprotect USPB=1 SPB bit is enabled DPB 0 SA 0 SPB 0 USPB 0 DPB 1 SA 1 SPB 1 USPB 1 DPB 2 SA 2 SPB 2 USPB 2 : : : : : : : : DPB N-1 SA N-1 SPB N-1 USPB N-1 DPB N SA N SPB N USPB N P/N:PM1494 REV. 1.6, OCT. 30, 2013 36 MX29GL640E T/B MX29GL640E H/L 1. Lock Register User can choose the sector protecting method via setting Lock Register bits as Q1 and Q2. Lock Register is a 16-bit one-time programmable register. Once programming either Q1 or Q2, they will be locked in that mode and the others will be disabled permanently. Q1 and Q2 can not be programmed at the same time, otherwise the device will abort the operation. If users select Password Protection mode, the password setting is required. Users can set password by issuing password program command. Lock Register bits Q15-Q3 Q2 Q1 Q0 Password Protection Mode Solid Protection Mode Secured Silicon Sector Don't care Lock Bit Lock Bit Protection Bit Please refer to the command for Lock Register command set about how to read and program the Lock Register bits. Figure 2. Lock Register Program Algorithm START Write Data AAH, Address 555H Lock register command set Entry Write Data 55H, Address 2AAH Write Data 40H, Address 555H Write Data A0H, Address don’t care Lock register data program Write Program Data, Address don’t care Data # Polling Algorithm Done YES NO NO Pass Q5 = 1 YES Exit Lock Register command Fail Reset command P/N:PM1494 REV. 1.6, OCT. 30, 2013 37 MX29GL640E T/B MX29GL640E H/L 2. Solid Protection Mode 2.1 Solid write Protection Bits (SPB) The Solid write Protection bits (SPB) are nonvolatile bit with the same endurances as the Flash memory. Each SPB is assigned to each sector individually. The SPB is preprogrammed, and verified prior to erasure are managed by the device, so system monitoring is not necessary. When SPB is set to “0”, the associated sector may be protected, preventing any program or erase operation on this sector. Whether the sector is protected depends also upon the value of the USPB, as described elsewhere. The SPB bits are set individually by SPB program command. However, it cannot be cleared individually. Issuing the All SPB Erase command will erase all SPB in the same time. During SPB programming period, the read and write operations are disabled for normal sector until exiting this mode. To unprotect a protected sector, the SPB lock bit must be cleared first by using a hardware reset or a power-up cycle. After the SPB lock bit is cleared, the SPB status can be changed to the desired settings. To lock the Solid Protection Bits after the modification has finished, the SPB Lock Bit must be set once again. To verify the state of the SPB for a given sector, issuing a SPB Status Read Command to the device is required. Refer to the flow chart for details in Figure 3. 2.2 Dynamic write Protection Bits (DPB) The Dynamic Protection features a volatile type protection to each individual sector. It can protect sectors from being unintentionally changed, and is easy to disable. All Dynamic write Protection bit (DPB) can be modified individually. DPBs protect the unprotected sectors with their SPBs cleared. To modify the DPB status by issuing the DPB Set (programmed to “0”) or DPB Clear (erased to “1”) commands, and place each sector in the protected or unprotected state seperately. After the DPB Clear command is issued (erased to “1”), the sector may be modified depending on the SPB state of that sector. The DPBs are default to be erased to “1” when first shipped from factory. P/N:PM1494 REV. 1.6, OCT. 30, 2013 38 MX29GL640E T/B MX29GL640E H/L 2.3 Temporary Un-protect Solid write Protect Bits (USPB) Temporary Un-protect Solid write Protect Bits are volatile. They are unique for each sector and can be individually modified. Software can temporarily unprotect write protect sectors despite of SPB's property when DPBs are cleared. While the USPB is set (to “0”), the corresponding sector's SPB property is masked. Notes: 1. Upon power up, the USPBs are cleared (all “1”). The USPBs can be set (to “0”) or cleared (to “1”) as often as needed. The hardware reset will reset USPB/DPB to their default values. 2. To change the protected sector status of solid write protect bit, users don't need to clear all SPBs. The users can just implement software to set corresponding USPB to "0", in which the corresponding DPB status is cleared too. Consequently, the original solid write protect status of protected sectors can be temporarily changed. Figure 3. SPB Program Algorithm SPB command set entry Program SPB Read Q7~Q0 Twice NO Q6 Toggle ? YES Q5 = 1 ? NO Wait 500 µs YES Read Q7~Q0 Twice Read Q7~Q0 Twice NO Q6 Toggle ? YES Q0= '1' (Erase) '0' (Program) NO YES Program Fail Write Reset CMD Pass SPB command set Exit Note: SPB program/erase status polling flowchart: check Q6 toggle, when Q6 stop toggle, the read status is 00H /01H (00H for program/ 01H for erase), otherwise, the status is “fail” and “exit”. P/N:PM1494 REV. 1.6, OCT. 30, 2013 39 MX29GL640E T/B MX29GL640E H/L 3. Solid Protection Bit Lock Bit The Solid Protection Bit Lock Bit (SPBLK) is assigned to control all SPB status. It is an unique and volatile. When SPBLK=0 (set), all SPBs are locked and can not be changed. When SPBLK=1 (cleared), all SPBs are allowed to be changed. There is no software command sequence requested to unlock this bit, unless the device is in the password protection mode. To clear the SPB Lock Bit, just execute a hardware reset or a power-up cycle. In order to prevent modification, the SPB Lock Bit must be set (SPBLK=0) after all SPBs are set to desired status. 4. Password Protection Method The security level of Password Protection Method is higher than the Solid protection mode. The 64 bit password is requested before modifying SPB lock bit status. When device is under password protection mode, the SPB lock bit is set as “0”, after a power-up cycle or Reset Command. A correct password is required for password Unlock command to unlock the SPB lock bit. Await 2us is necessary to unlock the device after a valid password is given. After that, the SPB bits are allowed to be changed. The Password Unlock command is issued slower than 2 μs every time, to prevent hacker from trying all the 64-bit password combinations. There are a few steps to start password protection mode: (1). Set a 64-bit password for verification before entering the password protection mode. This verification is only allowed in password programming. (2). Set the Password Protection Mode Lock Bit to”0” to activate the password protection mode. Once the password protection mode lock bit is programmed, the programmed Q2 bit can not be erased any more and the device will remain permanently in password protection mode. The previous set 64-bit password can not be retrieved or programmed. All the commands to the password-protected address will also be disabled. All the combinations of the 64-bit password can be used as a password, and programming the password does not require special address. The password is defaulted to be all “1” when shipped from the factory. Under password program command, only "0" can be programmed. In order to prevent access, the Password Mode Locking Bit must be set after the Password is programmed and verified. To set the Password Mode Lock Bit will prevent this 64-bits password to be read on the data bus. Any modification is impossible then, and the password can not be checked anymore after the Password Mode Lock Bit is set. P/N:PM1494 REV. 1.6, OCT. 30, 2013 40 MX29GL640E T/B MX29GL640E H/L Sector Protection Status Table DPB clear clear clear clear set set set set Protection Bit Status SPB clear clear set set clear clear set set USPB clear set clear set clear set clear set Sector Status Unprotect Unprotect Protect Unprotect Protect Protect Protect Protect Notes: If SPBLK is set, SPB will be unchangeable. If SPBLK is cleared, SPB will be changeable. P/N:PM1494 REV. 1.6, OCT. 30, 2013 41 MX29GL640E T/B MX29GL640E H/L SECURITY SECTOR FLASH MEMORY REGION The Security Sector region is an extra OTP memory space of 128 words in length. The security sector can be locked upon shipping from factory, or it can be locked by customer after shipping. Customer can issue Security Sector Factory Protect Verify and/or Security Sector Protect Verify to query the lock status of the device. In factory-locked device, security sector region is protected when shipped from factory and the security silicon sector indicator bit, Q7 (at Autoslect address 03h) is set to "1". In customer lockable device, security sector region is unprotected when shipped from factory and the security silicon indicator bit is set to "0". Factory Locked: Security Sector Programmed and Protected at the Factory In a factory locked device, the Security Sector is permanently locked before shipping from the factory. The device will have a 16-byte (8-word) ESN in the security region. Security Sector Address for MX29GL640ET device Secured Silicon Sector Address Range Standard Factory Locked 3FFF80h-3FFF87h ESN 3FFF88h-3FFFFFh Unavailable Express Flash Factory Locked ESN or Determined by Customer Determined by Customer Customer Lockable Determined by Customer Security Sector Address for MX29GL640EB device Secured Silicon Sector Address Range Standard Factory Locked 000000h-000007h ESN 000008h-00007Fh Unavailable Express Flash Factory Locked ESN or Determined by Customer Determined by Customer Customer Lockable Determined by Customer Security Sector Address for MX29GL640E H/L device Secured Silicon Sector Address Range Standard Factory Locked 000000h-000007h ESN 000008h-00007Fh Unavailable Express Flash Factory Locked ESN or Determined by Customer Determined by Customer Customer Lockable Determined by Customer Customer Lockable: Security Sector NOT Programmed or Protected at the Factory When the security feature is not required, the security region can act as an extra memory space. Security silicon sector can also be protected by two methods. Note that once the security silicon sector is protected, there is no way to unprotect the security silicon sector and the content of it can no longer be altered. After the security silicon is locked and verified, system must write Exit Security Sector Region, go through a power cycle, or issue a hardware reset to return the device to read normal array mode. P/N:PM1494 REV. 1.6, OCT. 30, 2013 42 MX29GL640E T/B MX29GL640E H/L TABLE 3. COMMAND DEFINITIONS Command 1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle 4th Bus Cycle 5th Bus Cycle 6th Bus Cycle Read Reset Mode Mode Addr Addr Data Data Addr Data Addr Data Addr Data Addr Data Addr Data XXX F0 Automatic Select Factory Protect Sector Protect Verify Silicon ID Device ID Verify Word Byte Word Byte Word Byte Word Byte 555 AAA 555 AAA 555 AAA 555 AAA AA AA AA AA AA AA AA AA 2AA 555 2AA 555 2AA 555 2AA 555 55 55 55 55 55 55 55 55 555 AAA 555 AAA 555 AAA 555 AAA 90 90 90 90 90 90 90 90 (Sector) (Sector) X00 X00 X01 X02 X03 X06 X02 X04 9A/1A(H) C2h C2h ID1 ID1 00/01 00/01 8A/0A(L) X0E X1C ID2 ID2 X0F X1E ID3 ID3 Security Sector Region Word Byte 555 AAA AA AA 2AA 555 55 55 555 AAA 88 88 Exit Security Sector Word 555 AA 2AA 55 555 90 Byte AAA AA 555 55 AAA 90 XXX XXX 00 00 Write to Write to Program/ Program/ Buffer Buffer Sector Program Chip Erase CFI Read Erase Erase Program Program Erase Suspend Resume Abort Reset confirm Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Write to Buffer Program Command 1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle 4th Bus Cycle 5th Bus Cycle Addr Data Addr Data Addr Data Addr Data Addr Data 555 AA 2AA 55 555 A0 Addr Data AAA 555 AAA 555 AAA AA AA AA AA AA 555 2AA 555 2AA 555 55 55 55 55 55 AAA SA SA 555 AAA A0 25 25 F0 F0 Addr SA SA Data N-1 N-1 WA WA WD WD 6th Bus Cycle Addr WBL WBL Data WD WD SA 29 SA 29 555 AA 2AA 55 555 80 555 AA 2AA 55 AAA AA 555 55 AAA 80 AAA AA 555 55 555 AA 2AA 55 555 80 555 AA 2AA 55 Sec555 AAA tor 10 10 30 AAA AA 555 55 AAA 80 AAA AA 555 55 Sector 30 55 98 AA 98 xxx B0 xxx B0 xxx 30 xxx 30 WA= Write Address WD= Write Data SA= Sector Address N= Word Count WBL= Write Buffer Location PWD= Password PWDn=Password word 0, word 1, word n ID1/ID2/ID3: Refer to Table 2-2 for detail ID of each device. P/N:PM1494 REV. 1.6, OCT. 30, 2013 43 MX29GL640E T/B MX29GL640E H/L Deep Power Down Command 4th Bus Cycle Addr Data Addr Data Addr Data Addr Data 5th Bus Cycle 6th Bus Cycle 7th Bus Cycle 8th Bus Cycle 9th Bus Cycle 10th Bus Cycle 11th Bus Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data 1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle Enter Word 555 AA 2AA 55 XXX B9 Byte AAA AA 555 55 XXX B9 Password Protection Password Command Set Entry Byte Word Byte XXX 555 AAA AB AA AA 2AA 555 55 55 555 AAA 60 60 Exit Word XXX AB Password Program Word XXX A0 PWA PWD Byte XXX A0 PWA PWD Password Command Set Exit Word Byte Word Byte Word Byte X00 X00 00 00 XXX XXX PWD0 PWD0 25 25 90 90 X01 X01 00 00 XXX XXX PWD1 PWD1 03 03 00 00 X02 X02 X00 X00 PWD2 PWD2 PWD0 PWD0 X03 X03 X01 X01 PWD3 PWD3 PWD1 PWD1 Password Read Password Unlock X04 X02 X02 PWD4 PWD2 PWD2 X05 X03 X03 PWD5 PWD3 PWD3 X06 00 X04 PWD6 29 PWD4 X07 X05 PWD7 PWD5 X06 PWD6 X07 PWD7 00 29 P/N:PM1494 REV. 1.6, OCT. 30, 2013 44 MX29GL640E T/B MX29GL640E H/L Lock Register Command 4th Bus Cycle Addr Data Addr Data Addr Data Addr Data 5th Bus Cycle Addr Data 1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle Command 4th Bus Cycle Addr Data Addr Data Addr Data Addr Data 5th Bus Cycle Addr Data 1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle Lock register Command Set Entry Word Byte 555 AAA AA AA 2AA 555 55 55 555 AAA 40 40 Global Non-Volatile Lock register Command Set Exit Word Byte Word Byte Word Byte XXX XXX XXX XXX XXX XXX A0 A0 DATA DATA 90 90 XXX XXX XXX XXX Data Data 00 00 Program Read SPB SPB All SPB SPB Status Command Program Erase Read Set Entry Word Byte Word Byte Word Byte Word Byte 555 AAA XXX XXX XXX XXX SA SA AA AA A0 A0 80 80 00/01 00/01 2AA 555 SA SA 00 00 55 55 00 00 30 30 555 AAA C0 C0 Global NonGlobal Volatile Freeze Volatile Volatile SPB SPB Lock SPB Lock DPB SPB Lock SPB Lock Command Command Command Command DPB Set DPB Clear Set Status Read Set Exit Set Entry Set Exit Set Entry Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte XXX XXX 555 AAA XXX XXX XXX XXX XXX XXX 555 AAA XXX XXX XXX XXX 90 90 AA AA A0 A0 00/01 00/01 90 90 AA AA A0 A0 A0 A0 XXX XXX 2AA 555 XXX XXX XXX XXX 2AA 555 SA SA SA SA 00 00 55 55 00 00 00 00 55 55 00 00 01 01 555 AAA 555 AAA 50 50 E0 E0 Volatile Command Addr Data 2nd Bus Addr Cycle Data 3rd Bus Addr Cycle Data 4th Bus Addr Cycle Data 1st Bus Cycle 5th Bus Cycle DPB Status DPB Command Read Set Exit Word Byte Word Byte SA SA XXX XXX 00/01 00/01 90 90 XXX XXX 00 00 Addr Data Notes: * It is not recommended to adopt any other code not in the command definition table which will potentially enter the hidden mode. * For the SPB Lock and DPB Status Read "00" means lock (protect), "01" means unlock (unprotect). P/N:PM1494 REV. 1.6, OCT. 30, 2013 45 MX29GL640E T/B MX29GL640E H/L COMMON FLASH MEMORY INTERFACE (CFI) MODE QUERY COMMAND AND COMMAND FLASH MEMORY INTERFACE (CFI) MODE The device features CFI mode. Host system can retrieve the operating characteristics, structure and vendorspecified information such as identifying information, memory size, byte/word configuration, operating voltages and timing information of this device by CFI mode. If the system writes the CFI Query command "98h", to address "55h"/"AAh" (depending on Word/Byte mode), the device will enter the CFI Query Mode, any time the device is ready to read array data. The system can read CFI information at the addresses given in Table 4. Once user enters CFI query mode, user can issue reset command to exit CFI mode and return to read array mode. The unused CFI area is reserved by Macronix. Table 4-1. CFI mode: Identification Data Values (Note 1) (All values in these tables are in hexadecimal) Address (h) Address (h) (Word Mode) (Byte Mode) 10 20 Query-unique ASCII string "QRY" 11 22 12 24 13 26 Primary vendor command set and control interface ID code 14 28 15 2A Address for primary algorithm extended query table 16 2C 17 2E Alternate vendor command set and control interface ID code 18 30 19 32 Address for alternate algorithm extended query table 1A 34 Note 1. Query data are always presented on the lowest data output Q7~Q0 only, Q8~Q15 are "0". Description Data (h) 0051 0052 0059 0002 0000 0040 0000 0000 0000 0000 0000 Table 4-2. CFI mode: System Interface Data Values Description Vcc supply minimum program/erase voltage Vcc supply maximum program/erase voltage VPP supply minimum program/erase voltage VPP supply maximum program/erase voltage Typical timeout per single word/byte write, 2n us Typical timeout for maximum-size buffer write, 2n us (00h, not support) Typical timeout per individual block erase, 2n ms Typical timeout for full chip erase, 2n ms (00h, not support) Maximum timeout for word/byte write, 2n times typical Maximum timeout for buffer write, 2n times typical Maximum timeout per individual block erase, 2n times typical Maximum timeout for chip erase, 2n times typical (00h, not support) P/N:PM1494 Address (h) (Word Mode) 1B 1C 1D 1E 1F Address (h) (Byte Mode) 36 38 3A 3C 3E 20 40 0006 21 22 23 24 25 42 44 46 48 4A 0009 0013 0003 0005 0003 26 4C 0002 Data (h) 0027 0036 0000 0000 0003 REV. 1.6, OCT. 30, 2013 46 MX29GL640E T/B MX29GL640E H/L Table 4-3. CFI mode: Device Geometry Data Values Description Device size = 2n in number of bytes (17=64Mb) Flash device interface description (02=asynchronous x8/x16) Maximum number of bytes in buffer write = 2n (00h, not support) Number of erase regions within device 29GL640E T/B=02 (boot device) 29GL640E H/L=01 (uniform device) Index for Erase Bank Area 1: [2E,2D] = # of same-size sectors in region 1-1 [30, 2F] = sector size in multiples of 256-bytes 29GL640E T/B=0007, 0000, 0020, 0000 29GL640E H/L=007F, 0000, 0000, 0001 Address (h) (Word Mode) Address (h) (Byte Mode) Data (h) 27 4E 0017 28 29 2A 2B 50 52 54 56 0002 0000 0005 0000 2C 58 00XX 2D 5A 2E 5C 00XX 0000 2F 5E 00XX 30 60 62 64 66 68 6A 6C 6E 70 72 74 76 78 00XX 00XX 0000 0000 00XX 0000 0000 0000 0000 0000 0000 0000 0000 31 32 33 34 35 36 37 38 39 3A 3B 3C Index for Erase Bank Area 2 29GL640E T/B=007E, 0000, 0000, 0001 29GL640E H/L=0000, 0000, 0000, 0000 Index for Erase Bank Area 3 Index for Erase Bank Area 4 P/N:PM1494 REV. 1.6, OCT. 30, 2013 47 MX29GL640E T/B MX29GL640E H/L Table 4-4. CFI mode: Primary Vendor-Specific Extended Query Data Values Address (h) (Word Mode) 40 41 42 43 44 Address (h) (Byte Mode) 80 82 84 86 88 Unlock recognizes address (Bits 1-0) 0= recognize, 1= don't recognize Process Technology (Bits 7-2) 0101b=110nm 45 8A 0014 Erase suspend (2= to both read and program) Sector protect (N= # of sectors/group) Temporary sector unprotect (1=supported) Sector protect/Chip unprotect scheme Simultaneous R/W operation (0=not supported) Burst mode (0=not supported) 46 47 48 49 4A 4B 8C 8E 90 92 94 96 0002 0001 0000 0008 0000 0000 Page mode (0=not supported, 01 = 4 word page, 02 = 8 word page) 4C 98 0002 4D 9A 0095 4E 9C 00A5 WP# Protection Flag 29GL640EB=02 (Bottom Boot Sectors WP# Protect) 29GL640ET=03 (Top Boot Sectors WP# Protect) 29GL640EL=04 (Uniform Sectors Bottom WP# Protect) 29GL640EH=05 (Uniform Sectors Top WP# Protect) 4F 9E 00XX Program Suspend (0=not supported, 1=supported) 50 A0 0001 Description Query - Primary extended table, unique ASCII string, PRI Major version number, ASCII Minor version number, ASCII Minimum ACC(acceleration) supply (0= not supported), [D7:D4] for volt, [D3:D0] for 100mV Maximum ACC(acceleration) supply (0= not supported), [D7:D4] for volt, [D3:D0] for 100mV P/N:PM1494 Data (h) 0050 0052 0049 0031 0033 REV. 1.6, OCT. 30, 2013 48 MX29GL640E T/B MX29GL640E H/L ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM STRESS RATINGS Storage Temperature Voltage Range VCC -65°C to +150°C -0.5V to +4.0 V VI/O -0.5V to +4.0 V A9 , WP#/ACC The other pins. -0.5V to +10.5 V -0.5V to Vcc +0.5V Output Short Circuit Current (less than one second) 200 mA OPERATING TEMPERATURE AND VOLTAGE Industrial (I) Grade Surrounding Temperature (TA ) -40°C to +85°C VCC Supply Voltages Full VCC range VI/O range +2.7 V to 3.6 V +2.7 V to 3.6 V NOTICE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. 2. Specifications contained within the following tables are subject to change. 3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see below Figure. Maximum Positive Overshoot Waveform Maximum Negative Overshoot Waveform 20ns 20ns 20ns Vss Vcc + 2.0V Vss - 2.0V Vcc 20ns 20ns P/N:PM1494 20ns REV. 1.6, OCT. 30, 2013 49 MX29GL640E T/B MX29GL640E H/L DC CHARACTERISTICS Symbol Description Iilk Input Leak Iilk9 A9 Leak Iolk Output Leak Icr1 Icr2 Min. Typ. Max. Remark ±2.0uA 35uA A9=10.5V ±1.0uA Read Current 5mA 15mA 10mA 20mA 15mA 30mA 2mA 10mA 5mA 20mA VCC Page Read Current CE#=Vil, OE#=Vih, Vcc=Vccmax; f=1MHz, Byte Mode CE#=Vil, OE#=Vih, Vcc=Vccmax; f=5MHz, Byte Mode CE#=Vil, OE#=Vih, Vcc=Vccmax; f=10MHz CE#=Vil, OE#=Vih, Vcc=Vccmax; f=10MHz CE#=Vil, OE#=Vih, Vcc=Vccmax; f=33MHz Iio VIO non-active current 0.2mA 10mA Icw Write Current 14mA 30mA Isb Standby Current 20uA 100uA Isbr Reset Current 20uA 100uA Isbs Sleep Mode Current 20uA 100uA Vcc deep power down current 1uA 15uA 1mA 3mA CE#=Vil, OE#=Vih 7mA 14mA CE#=Vil, OE#=Vih Idpd Icp1 Icp2 Vil Vih Vhv Vol Accelerated Pgm Current, WP#/ACC pin(Word/Byte) Accelerated Pgm Current, Vcc pin, (Word/ Byte) Input Low Voltage -0.1V Input High Voltage 0.7xVI/O Very High Voltage for Auto Select/ 9.5V Accelerated Program Output Low Voltage Voh1 Ouput High Voltage Vlko Low Vcc Lock-out voltage Vcc=Vcc max, other pin disable Vcc=Vccmax, RESET# enable, other pin disable 0.3xVI/O VI/O+0.3V 10.5V 0.45V 0.85xVI/O 2.3V CE#=Vil, OE#=Vih Iol=100uA Ioh=-100uA 2.5V Note: Sleep mode enables the lower power when address remain stable for taa+30ns. P/N:PM1494 REV. 1.6, OCT. 30, 2013 50 MX29GL640E T/B MX29GL640E H/L SWITCHING TEST CIRCUITS 3.3V 2.7KΩ DEVICE UNDER TEST CL 6.2KΩ Test Condition Output Load Capacitance, CL : 1TTL gate, 30pF Rise/Fall Times : 5ns Input Pulse levels :0.0 ~ VI/O In/Out reference levels :0.5VI/O SWITCHING TEST WAVEFORMS VI/O VI/O / 2 0.0V VI/O / 2 Test Points INPUT OUTPUT P/N:PM1494 REV. 1.6, OCT. 30, 2013 51 MX29GL640E T/B MX29GL640E H/L AC CHARACTERISTICS Symbol Description Taa Tpa Tce Toe Tdf Tsrw Valid data output after address Page access time Valid data output after CE# low Valid data output after OE# low Data output floating after OE# high Latency between read and write operation (Note) Toh Output hold time from the earliest rising edge of address,CE#, OE# Trc Twc Tcwc Tas Tah Tds Tdh Tvcs Tcs Tch Toes Read period time Write period time Command write period time Address setup time Address hold time Data setup time Data hold time Vcc setup time Chip enable Setup time Chip enable hold time Output enable setup time Toeh Output enable hold time Tws Twh Tcepw Tcepwh Twp Twph ns ns ns ns ns ns ns 70 70 70 0 45 30 0 500 0 0 0 ns ns ns ns ns ns ns us ns ns ns Read 0 ns Toggle & Data# Polling 10 0 0 35 30 35 30 ns ns ns ns ns ns ns Tbusy Program/Erase active time by RY/BY# Tghwl Read recover time before write Tghel Read recover time before write Twhwh1 Twhwh2 Tbal Trdp Unit 0 WE# setup time WE# hold time CE# pulse width CE# pulse width high WE# pulse width WE# pulse width high Twhwh1 Program operation 29GL640E (VCC=2.7V~3.6V) Min. Typ. Max. 70 25 70 25 20 35 70 0 0 Byte Word Acc program operation (Word/Byte) Sector erase operation Sector add hold time Release from deep power down mode 10 10 10 0.5 3.5 50 200 ns ns ns us us us sec us us Note : Not 100% tested. P/N:PM1494 REV. 1.6, OCT. 30, 2013 52 MX29GL640E T/B MX29GL640E H/L Figure 4. COMMAND WRITE OPERATION Tcwc CE# Vih Vil Tch Tcs WE# Vih Vil Toes OE# Twph Twp Vih Vil Addresses Vih VA Vil Tah Tas Tdh Tds Vih Data Vil DIN VA: Valid Address P/N:PM1494 REV. 1.6, OCT. 30, 2013 53 MX29GL640E T/B MX29GL640E H/L READ/RESET OPERATION Figure 5. READ TIMING WAVEFORMS Tce CE# Vih Vil Vih WE# Vil Toeh Tdf Toe Vih OE# Vil Toh Taa Trc Vih ADD Valid Addresses Vil Outputs Voh HIGH Z DATA Valid HIGH Z Vol P/N:PM1494 REV. 1.6, OCT. 30, 2013 54 MX29GL640E T/B MX29GL640E H/L AC CHARACTERISTICS Item Description Setup Speed Unit Trp1 RESET# Pulse Width (During Automatic Algorithms) MIN 10 us Trp2 RESET# Pulse Width (NOT During Automatic Algorithms) MIN 500 ns Trh RESET# High Time Before Read MIN 200 ns Trb1 RY/BY# Recovery Time (to CE#, OE# go low) MIN 0 ns Trb2 RY/BY# Recovery Time (to WE# go low) MIN 50 ns Tready1 RESET# PIN Low (During Automatic Algorithms) to Read or Write MAX 20 us Tready2 RESET# PIN Low (NOT During Automatic Algorithms) to Read or Write MAX 500 ns Figure 6. RESET# TIMING WAVEFORM Trb1 CE#, OE# Trb2 WE# Tready1 RY/BY# RESET# Trp1 Reset Timing during Automatic Algorithms CE#, OE# Trh RY/BY# RESET# Trp2 Tready2 Reset Timing NOT during Automatic Algorithms P/N:PM1494 REV. 1.6, OCT. 30, 2013 55 MX29GL640E T/B MX29GL640E H/L ERASE/PROGRAM OPERATION Figure 7. AUTOMATIC CHIP ERASE TIMING WAVEFORM CE# Tch Twhwh2 Twp WE# Twph Tcs Tghwl OE# Last 2 Erase Command Cycle Twc Address 2AAh VA 555h Tds Data Read Status Tah Tas Tdh 55h VA In Progress Complete 10h Tbusy Trb RY/BY# P/N:PM1494 REV. 1.6, OCT. 30, 2013 56 MX29GL640E T/B MX29GL640E H/L Figure 8. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 10H Address 555H Data# Polling Algorithm or Toggle Bit Algorithm NO Data=FFh ? YES Auto Chip Erase Completed P/N:PM1494 REV. 1.6, OCT. 30, 2013 57 MX29GL640E T/B MX29GL640E H/L Figure 9. AUTOMATIC SECTOR ERASE TIMING WAVEFORM Read Status CE# Tch Twhwh2 Twp WE# Twph Tcs Tghwl OE# Tbal Last 2 Erase Command Cycle Twc Address Tas Sector Address 0 2AAh Tds Tdh 55h Sector Address 1 Sector Address n Tah VA VA In Progress Complete 30h 30h 30h Data Tbusy Trb RY/BY# P/N:PM1494 REV. 1.6, OCT. 30, 2013 58 MX29GL640E T/B MX29GL640E H/L Figure 10. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 30H Sector Address Last Sector NO to Erase YES Data# Polling Algorithm or Toggle Bit Algorithm Data=FFh NO YES Auto Sector Erase Completed P/N:PM1494 REV. 1.6, OCT. 30, 2013 59 MX29GL640E T/B MX29GL640E H/L Figure 11. ERASE SUSPEND/RESUME FLOWCHART START Write Data B0H Toggle Bit checking Q6 NO ERASE SUSPEND not toggled YES Read Array or Program Reading or Programming End NO YES Write Data 30H ERASE RESUME Continue Erase Another Erase Suspend ? NO YES P/N:PM1494 REV. 1.6, OCT. 30, 2013 60 MX29GL640E T/B MX29GL640E H/L Figure 12. AUTOMATIC PROGRAM TIMING WAVEFORMS CE# Tch Twhwh1 Twp WE# Tcs Twph Tghwl OE# Last 2 Program Command Cycle 555h Address Last 2 Read Status Cycle Tah Tas VA PA Tds VA Tdh A0h Status PD DOUT Data Tbusy Trb RY/BY# Figure 13. ACCELERATED PROGRAM TIMING DIAGRAM Vcc (min) Vcc GND Tvcs Vhv (9.5V ~ 10.5V) WP#/ACC Vil or Vih Vil or Vih 250ns 250ns P/N:PM1494 REV. 1.6, OCT. 30, 2013 61 MX29GL640E T/B MX29GL640E H/L Figure 14. CE# CONTROLLED WRITE TIMING WAVEFORM WE# Tws Tcepw Twhwh1 or Twhwh2 Twh CE# Tcepwh Tghwl OE# Tah Tas Address 555h Tds Data VA PA VA Tdh A0h Status PD DOUT Tbusy RY/BY# P/N:PM1494 REV. 1.6, OCT. 30, 2013 62 MX29GL640E T/B MX29GL640E H/L Figure 15. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data A0H Address 555H Write Program Data/Address Data# Polling Algorithm or Toggle Bit Algorithm next address Read Again Data: Program Data? No YES No Last Word to be Programed YES Auto Program Completed P/N:PM1494 REV. 1.6, OCT. 30, 2013 63 MX29GL640E T/B MX29GL640E H/L Figure 16. SILICON ID READ TIMING WAVEFORM VCC 3V Vhv ADD Vih A9 ADD A0 Vil Vih Vil Taa A1 Taa Taa Taa Vih Vil A2 Vih Vil ADD CE# WE# Vih Vil Disable Enable Tce Vih Vil OE# Vih Toe Tdf Vil Toh DATA Q15~Q0 Toh Toh Toh Vih Vil DATA OUT DATA OUT DATA OUT DATA OUT Manufacturer ID Device ID Cycle 1 Device ID Cycle 2 Device ID Cycle 3 P/N:PM1494 REV. 1.6, OCT. 30, 2013 64 MX29GL640E T/B MX29GL640E H/L WRITE OPERATION STATUS Figure 17. DATA# POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS) Tce CE# Tch WE# Toe OE# Toeh Tdf Trc Address VA VA Taa Toh Q7 Complement Complement True Valid Data Q6~Q0 Status Data Status Data True Valid Data High Z High Z Tbusy RY/BY# P/N:PM1494 REV. 1.6, OCT. 30, 2013 65 MX29GL640E T/B MX29GL640E H/L Figure 18. STATUS POLLING FOR WORD PROGRAM/ERASE Start Read Data at valid address (Note 1) No Q7 = Data# ? Yes Q5 = 1 ? No Yes Read Data at valid address (Note 1) No Q7 = Data# ? (Note 2) Yes Pass Fail Notes: 1. For programming, valid address means program address. For erasing, valid address means erase sectors address. 2. Q7 may change simultaneously with Q5, so even Q5=1, Q7 should be reverify. P/N:PM1494 REV. 1.6, OCT. 30, 2013 66 MX29GL640E T/B MX29GL640E H/L Figure 19. STATUS POLLING FOR WRITE BUFFER PROGRAM Start Read Data at last write address (Note 1) Q7 = Data# ? No Yes Q1=1 ? Only for write buffer program Yes No No Q5=1 ? Read Data at last write address (Note 1) Yes Read Data at last write address (Note 1) Q7 = Data# ? (Note 2) No Q7 = Data# ? (Note 2) No Yes Write Buffer Abort Yes Fail Pass Notes: 1. For programming, valid address means program address. For erasing, valid address means erase sectors address. 2. Q7 may change simultaneously with Q5, so even Q5=1, Q7 should be reverify. P/N:PM1494 REV. 1.6, OCT. 30, 2013 67 MX29GL640E T/B MX29GL640E H/L Figure 20. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS) Tce CE# Tch WE# Toe OE# Toeh Tdf Trc Address VA VA VA VA Taa Toh Q6/Q2 Valid Status (first read) Valid Status Valid Data (second read) (stops toggling) Valid Data Tbusy RY/BY# VA : Valid Address P/N:PM1494 REV. 1.6, OCT. 30, 2013 68 MX29GL640E T/B MX29GL640E H/L Figure 21. TOGGLE BIT ALGORITHM Start Read Data Twice (Note 1) No Q6 Toggle ? Yes Q5 = 1 ? No Yes Read Data Twice (Note 1, 2) No Q6 Toggle ? Yes Pass Fail Notes: 1. Toggle bit Q7-Q0 should be read twice to check if it is toggling. 2. While Q5=1, the toggle bit (Q6) may stop toggling. Therefore, the system should be read again. P/N:PM1494 REV. 1.6, OCT. 30, 2013 69 MX29GL640E T/B MX29GL640E H/L AC CHARACTERISTICS WORD/BYTE CONFIGURATION (BYTE#) Test Setup Max. Max. Min. Parameter Description Telfl/Telfh Tflqz Tfhqv CE# to BYTE# from L/H BYTE# from L to Output Hiz BYTE# from H to Output Active All Speed Options Unit 5 30 70 ns ns ns Figure 22. BYTE# TIMING WAVEFORM FOR READ OPERATIONS (BYTE# switching from byte mode to word mode) CE# OE# Telfh BYTE# Q14~Q0 DOUT (Q0-Q7) Q15/A-1 VA DOUT (Q0-Q14) DOUT (Q15) Tfhqv Figure 23. PAGE READ TIMING WAVEFORM VALID ADD Amax:A3 (A-1),A0,A1,A2 1'st ADD Taa DATA 2'nd ADD 3'rd ADD Tpa Tpa Data 1 Data 2 Data 3 Toe OE# Tce CE# Note: CE#, OE# are enable. Page size is 8 words in Word mode, 16 bytes in Byte mode. Address are A2~A0 for Word mode, A2~A-1 for Byte mode. P/N:PM1494 REV. 1.6, OCT. 30, 2013 70 MX29GL640E T/B MX29GL640E H/L AC CHARACTERISTICS ITEM WEB high to release from deep power down mode WEB high to deep power down mode TYP. MAX. tRDP 100us 200us tDP 10us 20us Figure 24. DEEP POWER DOWN MODE WAVEFORM CEB WEB ADD DATA tDP 55 XX 2AA AA 55 tRDP XX (don't care) AB B9 Standby mode P/N:PM1494 Deep power down mode Standby mode REV. 1.6, OCT. 30, 2013 71 MX29GL640E T/B MX29GL640E H/L Figure 25. WRITE BUFFER PROGRAM FLOWCHART Write CMD: Data=AAh, Addr=555h Write CMD: Data=55h, Addr=2AAh Write CMD: Data=29h, Addr=SA Write CMD: Data=25h, Addr=SA Polling Status Write CMD: Data=N-1, Addr=SA Yes Write CMD: Data=PGM_data, Addr=PGM_addr PWC=PWC-1 Want to Abort ? PWC =0? No Return to read Mode No Fail Yes Write a different sector address to cause Abort Yes No No Pass Yes Yes Write Buffer Abort No SA: Sector Address of to be Programmed page N: Word Count Write Abort reset CMD to return to read Mode P/N:PM1494 Write reset CMD to return to read Mode REV. 1.6, OCT. 30, 2013 72 MX29GL640E T/B MX29GL640E H/L RECOMMENDED OPERATING CONDITIONS At Device Power-Up AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device powerup (e.g. Vcc and CE# ramp up simultaneously). If the timing in the figure is ignored, the device may not operate correctly. Vcc(min) Vcc GND Tvr Tvcs Tf Tce Tr Vih CE# Vil Vih WE# Vil Tf Toe Tr Vih OE# Vil Tr or Tf Vih ADDRESS Tr or Tf Valid Address Vil Voh DATA Taa High Z Valid Ouput Vol Vih WP#/ACC Vil Figure A. AC Timing at Device Power-Up Symbol Tvr Tr Tf Tvcs Parameter Vcc Rise Time Input Signal Rise Time Input Signal Fall Time Vcc Setup Time Min. 20 500 Max. 500000 20 20 Unit us/V us/V us/V us Notes: 1. Not test 100%. P/N:PM1494 REV. 1.6, OCT. 30, 2013 73 MX29GL640E T/B MX29GL640E H/L ERASE AND PROGRAMMING PERFORMANCE Limits Typ. (1) 60 Max. (2) 150 Sector Erase Time 0.5 3.5 Chip Programming Time (Page Mode) 20 Word Program Time 10 180 us Total Write Buffer Time 80 400 us ACC Total Write Buffer Time 75 us 100,000 Cycles Parameter Min. Chip Erase Time Erase/Program Cycles Units sec sec sec Notes: 1. Typical program and erase times assume the following conditions: 25°C, 3.0V VCC. Programming specifications assume checkboard data pattern. 2. Maximum values are measured at VCC = 3.0 V, worst case temperature. Maximum values are valid up to and including 100,000 program/erase cycles. 3. Erase/Program cycles comply with JEDEC JESD-47 & JESD 22-A117 standard. 4. Exclude 00h program before erase operation. DATA RETENTION Parameter Condition Min. Data retention 55˚C 20 Max. Unit years LATCH-UP CHARACTERISTICS Min. -1.0V -1.0V -100mA Input Voltage voltage difference with GND on WP#/ACC and A9 pins Input Voltage voltage difference with GND on all normal pins input Vcc Current All pins included except Vcc. Test conditions: Vcc = 3.0V, one pin per testing Max. 10.5V 1.5Vcc +100mA PIN CAPACITANCE Parameter Symbol CIN2 COUT CIN Parameter Description Control Pin Capacitance Output Capacitance Input Capacitance Test Set VIN=0 VOUT=0 VIN=0 P/N:PM1494 Typ. 7.5 8.5 6 Max. 9 12 7.5 Unit pF pF pF REV. 1.6, OCT. 30, 2013 74 MX29GL640E T/B MX29GL640E H/L ORDERING INFORMATION MX29GL640E T/B PART NO. ACCESS TIME (ns) PACKAGE MX29GL640ETTI-70G 70ns 48 Pin TSOP MX29GL640EBTI-70G 70ns 48 Pin TSOP MX29GL640ETXEI-70G 70ns 48 Ball LFBGA MX29GL640EBXEI-70G 70ns 48 Ball LFBGA MX29GL640ETTI-90G 90ns 48 Pin TSOP MX29GL640EBTI-90G 90ns 48 Pin TSOP MX29GL640ETXEI-90G 90ns 48 Ball LFBGA MX29GL640EBXEI-90G 90ns 48 Ball LFBGA ACCESS TIME (ns) PACKAGE MX29GL640EHT2I-70G 70ns 56 Pin TSOP MX29GL640ELT2I-70G 70ns 56 Pin TSOP MX29GL640EHXFI-70G 70ns 64 LFBGA MX29GL640ELXFI-70G 70ns 64 LFBGA MX29GL640EHT2I-90G 90ns 56 Pin TSOP MX29GL640ELT2I-90G 90ns 56 Pin TSOP MX29GL640EHXFI-90G 90ns 64 LFBGA MX29GL640ELXFI-90G 90ns 64 LFBGA Remark MX29GL640E H/L PART NO. P/N:PM1494 Remark REV. 1.6, OCT. 30, 2013 75 MX29GL640E T/B MX29GL640E H/L PART NAME DESCRIPTION MX 29 GL 640 E H T2 I 70 G OPTION: G: RoHS Compliant & Halogen-free SPEED: 70: 70ns 90: 90ns TEMPERATURE RANGE: I: Industrial (-40° C to 85° C) PACKAGE: T: 48-TSOP T2: 56-TSOP XE: LFBGA (6mm x 8mm) XF: LFBGA (11mm x 13mm) BOOT BLOCK TYPE: T: Top Boot B: Bottom Boot H: Highest Address Sector Protected L: Lowest Address Sector Protected REVISION: E DENSITY & MODE: 640: 64Mb with x8/x16 Architecture TYPE: GL: 3V Page Mode DEVICE: 29:Flash P/N:PM1494 REV. 1.6, OCT. 30, 2013 76 MX29GL640E T/B MX29GL640E H/L PACKAGE INFORMATION P/N:PM1494 REV. 1.6, OCT. 30, 2013 77 MX29GL640E T/B MX29GL640E H/L P/N:PM1494 REV. 1.6, OCT. 30, 2013 78 MX29GL640E T/B MX29GL640E H/L P/N:PM1494 REV. 1.6, OCT. 30, 2013 79 MX29GL640E T/B MX29GL640E H/L P/N:PM1494 REV. 1.6, OCT. 30, 2013 80 MX29GL640E T/B MX29GL640E H/L REVISION HISTORY Revision No. Description 1.0 1. Modified CFI descriptions 2. Removed "Preliminary" title Page P44~45 P2 Date AUG/28/2009 1.1 P2,19,22 SEP/10/2009 P2,49,67, P72,73 P70 NOV/10/2009 1. Added WP# protected area description 1.2 1. Added 70ns grade spec. and part numbers 2. Added (e.g. Vcc and CE# ramp up simultaneously) wording 1.3 1. Modified Figure 10. Accelerated Program Timing Diagram P58 2. Modified "Query Command And Command Flash Memory P43 Interface (CFI) Mode" description OCT/12/2010 1.4 1. Modified sector erase time (typ.) from 0.6s to 0.5s 2. Modified Figure 11. CE# Controlled Write Timing Waveform 3. Modified Figure 16. Status Polling For Write Buffer Program 4. Modified description for RoHS compliance DEC/27/2011 P5,74 P62 P26,67 P75,76 1.5 1. Added MAX. Total Write Buffer Time P74 AUG/16/2013 2. Modified Figure 23. PAGE READ TIMING WAVEFORM P70 3. Advanced Sector Protection/Un-Protection description update P36~41 4. Added Note 1. Query data are always presented on the lowest P46 data output Q7~Q0 only, Q8~Q15 are "0". 1.6 1. Updated parameters for DC Characteristics. 2. Updated Erase and Programming Performance. 3. Content correction P5,50 P5,52,74 P36~41 OCT/30/2013 P/N:PM1494 REV. 1.6, OCT. 30, 2013 81 MX29GL640E T/B MX29GL640E H/L Except for customized products which has been expressly identified in the applicable agreement, Macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. In the event Macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or distributors shall be released from any and all liability arisen therefrom. Copyright© Macronix International Co., Ltd. 2009~2013. All rights reserved, including the trademarks and tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit, NBiit, Macronix NBit, eLiteFlash, HybridNVM, HybridFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC, Kingtech, MXSMIO, Macronix vEE, Macronix MAP, Rich Au­dio, Rich Book, Rich TV, and FitCAM. The names and brands of third party referred thereto (if any) are for identification purposes only. For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 82