MX29LV040CQI-90G

MX29LV040C 4M-BIT [512K x 8] CMOS SINGLE VOLTAGE 3V ONLY EQUAL SECTOR FLASH MEMORY FEATURES • • • • • • • • • • • • • • • Extended single - supply voltage range 2.7V to 3.6V 524,288 x 8 only Single power supply operation - 3.0V only operation for read, erase and program operation Fully compatible with MX29LV040 device Fast access time: 55Q/70/90ns Low power consumption - 30mA maximum active current - 0.2uA typical standby current Command register architecture - 8 equal sector of 64K-Byte each - Byte Programming (9us typical) - Sector Erase (Sector structure 64K-Byte x8) Auto Erase (chip & sector) and Auto Program - Automatically erase any combination of sectors with Erase Suspend capability - Automatically program and verify data at specified address Erase suspend/Erase Resume - Suspends sector erase operation to read data from, or program data to, any sector that is not being erased, then resumes the erase Status Reply - Data# Polling & Toggle bit for detection of program and erase operation completion Sector protection - Hardware method to disable any combination of sectors from program or erase operations - Any combination of sectors can be erased with erase suspend/resume function CFI (Common Flash Interface) compliant - Flash device parameters stored on the device and provide the host system to access 100,000 minimum erase/program cycles Latch-up protected to 100mA from -1V to VCC+1V Package type: - 32-pin PLCC - 32-pin TSOP (8mmx20mm, 8mmx14mm) - All devices are RoHS Compliant P/N:PM1149 REV. 2.5, DEC. 15, 2011 1 MX29LV040C PIN CONFIGURATIONS 32 TSOP (Standard Type) (8mm x 20mm) A11 A9 A8 A13 A14 A17 WE# VCC A18 A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A11 A9 A8 A13 A14 A17 WE# VCC A18 A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MX29LV040C 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE# A10 CE# Q7 Q6 Q5 Q4 Q3 GND Q2 Q1 Q0 A0 A1 A2 A3 MX29LV040C 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE# A10 CE# Q7 Q6 Q5 Q4 Q3 GND Q2 Q1 Q0 A0 A1 A2 A3 1 32 PIN DESCRIPTION A17 A16 4 VCC 5 A18 A7 A15 A12 32 PLCC WE# 32 TSOP (8mm x 14mm) 30 29 A6 A13 A5 A8 A4 A3 A9 9 MX29LV040C 25 A11 A2 OE# A1 A10 A0 CE# 21 20 Q5 Q4 Q3 GND Q2 17 PIN NAME Address Input Data Input/Output Chip Enable Input Write Enable Input Output Enable Input Ground Pin +3.0V single power supply Q7 Q6 13 14 Q1 Q0 SYMBOL A0~A18 Q0~Q7 CE# WE# OE# GND VCC A14 P/N:PM1149 REV. 2.5, DEC. 15, 2011 2 MX29LV040C BLOCK DIAGRAM CE# OE# WE# CONTROL INPUT LOGIC A0-A18 LATCH BUFFER Y-DECODER AND HIGH VOLTAGE X-DECODER ADDRESS PROGRAM/ERASE WRITE STATE MACHINE (WSM) STATE FLASH ARRAY Y-PASS GATE SENSE AMPLIFIER PGM DATA HV REGISTER ARRAY SOURCE HV COMMAND DATA DECODER COMMAND DATA LATCH PROGRAM DATA LATCH Q0-Q7 I/O BUFFER P/N:PM1149 REV. 2.5, DEC. 15, 2011 3 MX29LV040C Table 1. SECTOR (GROUP) STRUCTURE Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 A18 0 0 0 0 1 1 1 1 A17 0 0 1 1 0 0 1 1 A16 0 1 0 1 0 1 0 1 Address Range 00000h-0FFFFh 10000h-1FFFFh 20000h-2FFFFh 30000h-3FFFFh 40000h-4FFFFh 50000h-5FFFFh 60000h-6FFFFh 70000h-7FFFFh Note:All sectors are 64 Kbytes in size. P/N:PM1149 REV. 2.5, DEC. 15, 2011 4 MX29LV040C Table 2-1. BUS OPERATION Operation Read Mode Write Standby Mode Output Disable CE# L L Vcc±0.3V L OE# L H X H WE# H L X H Address AIN AIN X X Q7~Q0 DOUT DIN High-Z High-Z Table 2-2. BUS OPERATION Operation Read Silicon ID Manufactures Code Read Silicon ID Device Code Sector Protect Chip Unprotected Sector Protect Verify CE# OE# WE# A0 A1 A6 A9 Q7~Q0 L L H L L X Vhv C2H L L H H L X Vhv 4FH L L L Vhv Vhv L L L H X X X X X H L H X Vhv Vhv Vhv X X Code(1) Notes: 1. Sector unprotected code:00h. Sector protected code:01h. 2. AM: MSB of address. 3. Sector addresses: A18~A16. 4. Vhv is 11.5V to 12.5V. 5. X means don't care. P/N:PM1149 REV. 2.5, DEC. 15, 2011 5 MX29LV040C WRITE COMMANDS/COMMAND SEQUENCES To write a command to the device, system must drive WE# and CE# to Vil, and OE# to Vih. In a command cycle, all address are latched at the later falling edge of CE# and WE#, and all data are latched at the earlier rising edge of CE# and WE#. Figure 1 illustrates the AC timing waveform of a write command, and Table 3 defines all the valid command sets of the device. System is not allowed to write invalid commands not defined in this datasheet. Writing an invalid command will bring the device to an undefined state. REQUIREMENTS FOR READING ARRAY DATA Read array action is to read the data stored in the array. While the memory device is in powered up or has been reset, it will automatically enter the status of read array. If the microprocessor wants to read the data stored in the array, it has to drive CE# (device enable control pin) and OE# (Output control pin) as Vil, and input the address of the data to be read into address pin at the same time. After a period of read cycle (Tce or Taa), the data being read out will be displayed on output pin for microprocessor to access. If CE# or OE# is Vih, the output will be in tri-state, and there will be no data displayed on output pin at all. After the memory device completes embedded operation (automatic Erase or Program), it will automatically return to the status of read array, and the device can read the data in any address in the array. In the process of erasing, if the device receives the Erase suspend command, erase operation will be stopped temporarily after a period of time no more than Tready1 and the device will return to the status of read array. At this time, the device can read the data stored in any address except the sector being erased in the array. In the status of erase suspend, if user wants to read the data in the sectors being erased, the device will output status data onto the output. Similarly, if program command is issued after erase suspend, after program operation is completed, system can still read array data in any address except the sectors to be erased. The device needs to issue reset command to enable read array operation again in order to arbitrarily read the data in the array in the following two situations: 1. In program or erase operation, the programming or erasing failure causes Q5 to go high. 2. The device is in auto select mode or CFI mode. In the two situations above, if reset command is not issued, the device is not in read array mode and system must issue reset command before reading array data. P/N:PM1149 REV. 2.5, DEC. 15, 2011 6 MX29LV040C SECTOR PROTECT OPERATION When a sector is protected, program or erase operation will be disabled on that protected sector. MX29LV040C provides a methods for sector protection. The method is asserting Vhv on A9 and OE# pins, with A6 and CE# at Vil. The protection operation begins at the falling edge of WE# and terminates at the rising edge. Contact Macronix for details. CHIP UNPROTECT OPERATION MX29LV040C provides one methods for chip unprotect. The chip unprotect operation unprotects all sectors within the device. It is recommended to protect all sectors before activating chip unprotect mode. All sector groups are unprotected when shipped from the factory. The method is asserting Vhv on A9 and OE# pins, with A6 at Vih and CE# at Vil (see Table 2). The unprotect operation begins at the falling edge of WE# and terminates at the rising edge. Contact Macronix for details. AUTOMATIC SELECT OPERATION When the device is in Read array mode, erase-suspended read array mode or CFI mode, user can issue read silicon ID command to enter read silicon ID mode. After entering read silicon ID mode, user can query several silicon IDs continuously and does not need to issue read silicon ID mode again. When A0 is Low, device will output Macronix Manufacture ID C2. When A0 is high, device will output Device ID. In read silicon ID mode, issuing reset command will reset device back to read array mode or erase-suspended read array mode. Another way to enter read silicon ID is to apply high voltage on A9 pin with CE#, OE#, A6 and A1 at Vil. While the high voltage of A9 pin is discharged, device will automatically leave read silicon ID mode and go back to read array mode or erase-suspended read array mode. When A0 is Low, device will output Macronix Manufacture ID C2. When A0 is high, device will output Device ID. VERIFY SECTOR PROTECT STATUS OPERATION MX29LV040C provides hardware sector protection against Program and Erase operation for protected sectors. The sector protect status can be read through Sector Protect Verify command. This method requires Vhv on A9 pin, Vih on WE# and A1 pins, Vil on CE#, OE#, A6 and A0 pins, and sector address on A16 to A18 pins. If the read out data is 01H, the designated sector is protected. Oppositely, if the read out data is 00H, the designated sector is not protected. DATA PROTECTION To avoid accidental erasure or programming of the device, the device is automatically reset to read array mode during power up. Besides, only after successful completion of the specified command sets will the device begin its erase or program operation. Other features to protect the data from accidental alternation are described as followed. P/N:PM1149 REV. 2.5, DEC. 15, 2011 7 MX29LV040C LOW VCC WRITE INHIBIT The device refuses to accept any write command when Vcc is less than 1.4V. This prevents data from spuriously altered. The device automatically resets itself when Vcc is lower than 1.4V and write cycles are ignored until Vcc is greater than 1.4V. System must provide proper signals on control pins after Vcc is larger than 1.4V to avoid unintentional program or erase operation WRITE PULSE "GLITCH" PROTECTION CE#, WE#, OE# pulses shorter than 5ns are treated as glitches and will not be regarded as an effective write cycle. LOGICAL INHIBIT A valid write cycle requires both CE# and WE# at Vil with OE# at Vih. Write cycle is ignored when either CE# at Vih, WE# a Vih, or OE# at Vil. POWER-UP SEQUENCE Upon power up, MX29LV040C is placed in read array mode. Furthermore, program or erase operation will begin only after successful completion of specified command sequences. POWER-UP WRITE INHIBIT When WE#, CE# is held at Vil and OE# is held at Vih during power up, the device ignores the first command on the rising edge of WE#. POWER SUPPLY DECOUPLING A 0.1uF capacitor should be connected between the Vcc and GND to reduce the noise effect. P/N:PM1149 REV. 2.5, DEC. 15, 2011 8 MX29LV040C TABLE 3. MX29LV040C COMMAND DEFINITIONS Command 1st Bus Cyc 2nd Bus Cyc 3rd Bus Cyc Addr Data Addr Data Addr Data 4th Bus Addr Cyc Data 5th Bus Addr Cyc Data 6th Bus Addr Cyc Data Read Mode Reset Mode Addr Data XXX F0 Automatic Select Sector Program Silicon Device Protect ID ID Verify 555 555 555 555 AA AA AA AA 2AA 2AA 2AA 2AA 55 55 55 55 555 555 555 555 90 90 90 A0 (Sector) X00 X01 Addr X02 C2 4F 00/01 Data Chip Erase Sector Erase Erase CFI Read Erase Suspend Resume 555 AA 2AA 55 555 80 555 AA 2AA 55 555 80 555 555 AA 2AA 55 555 10 AA 2AA 55 Sector 30 AA 98 XXX B0 XXX 30 Notes: 1. It is not allowed to adopt any other code which is not in the above command definition table. P/N:PM1149 REV. 2.5, DEC. 15, 2011 9 MX29LV040C RESET In the following situations, executing reset command will reset device back to read array mode: • Among erase command sequence (before the full command set is completed) • Sector erase time-out period • Erase fail (while Q5 is high) • Among program command sequence (before the full command set is completed, erase-suspended program included) • Program fail (while Q5 is high, and erase-suspended program fail is included) • Read silicon ID mode • Sector protect verify • CFI mode While device is at the status of program fail or erase fail (Q5 is high), user must issue reset command to reset device back to read array mode. While the device is in read silicon ID mode, sector protect verify or CFI mode, user must issue reset command to reset device back to read array mode. When the device is in the progress of programming (not program fail) or erasing (not erase fail), device will ignore reset command. P/N:PM1149 REV. 2.5, DEC. 15, 2011 10 MX29LV040C AUTOMATIC PROGRAMMING The MX29LV040C can provide the user program function by the form of Byte-Mode. As long as the users enter the right cycle defined in the Table.3 (including 2 unlock cycles and A0H), any data user inputs will automatically be programmed into the array. Once the program function is executed, the internal write state controller will automatically execute the algorithms and timings necessary for program and verification, which includes generating suitable program pulse, verifying whether the threshold voltage of the programmed cell is high enough and repeating the program pulse if any of the cells does not pass verification. Meanwhile, the internal control will prohibit the programming to cells that pass verification while the other cells fail in verification in order to avoid over-programming. With the internal write state controller, the device requires the user to write the program command and data only. Programming will only change the bit status from "1" to "0". That is to say, it is impossible to convert the bit status from "0" to "1" by programming. Meanwhile, the internal write verification only detects the errors of the "1" that is not successfully programmed to "0". Any command written to the device during programming will be ignored except hardware reset, which will terminate the program operation after a period of time no more than Tready1. When the embedded program algorithm is complete or the program operation is terminated by hardware reset, the device will return to the reading array data mode. The typical chip program time at room temperature of the MX29LV040C is less than 4.5 seconds. When the embedded program operation is on going, user can confirm if the embedded operation is finished or not by the following methods: Status In progress*1 Finished Exceed time limit Q7 Q7# Q7 Q7# Q6 Toggling Stop toggling Toggling Q5 0 0 1 *1: The status "in progress" means both program mode and erase-suspended program mode. *2: When an attempt is made to program a protected sector, Q7 will output its complement data or Q6 continues to toggle for about 1us or less and the device returns to read array state without programing the data in the protected sector. P/N:PM1149 REV. 2.5, DEC. 15, 2011 11 MX29LV040C CHIP ERASE Chip Erase is to erase all the data with "1" and "0" as all "1". It needs 6 cycles to write the action in, and the first two cycles are "unlock" cycles, the third one is a configuration cycle, the fourth and fifth are also "unlock" cycles, and the sixth cycle is the chip erase operation. During chip erasing, all the commands will not be accepted except hardware reset or the working voltage is too low that chip erase will be interrupted. After Chip Erase, the chip will return to the state of Read Array. When the embedded chip erase operation is on going, user can confirm if the embedded operation is finished or not by the following methods: Status In progress Finished Exceed time limit Q7 0 1 0 Q6 Toggling Stop toggling Toggling Q5 0 0 1 Q2 Toggling 1 Toggling SECTOR ERASE Sector Erase is to erase all the data in a sector with "1" and "0" as all "1". It requires six command cycles to issue. The first two cycles are "unlock cycles", the third one is a configuration cycle, the fourth and fifth are also "unlock cycles" and the sixth cycle is the sector erase command. After the sector erase command sequence is issued, there is a time-out period of 50us counted internally. During the time-out period, additional sector address and sector erase command can be written multiply. Once user enters another sector erase command, the time-out period of 50us is recounted. If user enters any command other than sector erase or erase suspend during time-out period, the erase command would be aborted and the device is reset to read array condition. The number of sectors could be from one sector to all sectors. After time-out period passing by, additional erase command is not accepted and erase embedded operation begins. During sector erasing, all commands will not be accepted except hardware reset and erase suspend and user can check the status as chip erase. When the embedded erase operation is on going, user can confirm if the embedded operation is finished or not by the following methods: Status Time-out period In progress Finished Exceed time limit Q7 0 0 1 0 Q6 Toggling Toggling Stop toggling Toggling Q5 0 0 0 1 Q3 0 1 1 1 Q2 Toggling Toggling 1 Toggling *1: The status Q3 is the time-out period indicator. When Q3=0, the device is in time-out period and is acceptible to another sector address to be erased. When Q3=1, the device is in erase operation and only erase suspend is valid. *2: When an attempt is made to erase a protected sector, Q7 will output its complement data or Q6 continues to toggle for 100us or less and the device returned to read array status without erasing the data in the protected sector. P/N:PM1149 REV. 2.5, DEC. 15, 2011 12 MX29LV040C SECTOR ERASE SUSPEND During sector erasure, sector erase suspend is the only valid command. If user issue erase suspend command in the time-out period of sector erasure, device time-out period will be over immediately and the device will go back to erase-suspended read array mode. If user issue erase suspend command during the sector erase is being operated, device will suspend the ongoing erase operation, and after the Tready1 (