MX29LV320AT/B
32M-BIT [4M x 8 / 2M x 16] SINGLE VOLTAGE 3V ONLY FLASH MEMORY
FEATURES
GENERAL FEATURES • 4,194,304 x 8 / 2,097,152 x 16 switchable • Sector Structure - 8K-Byte x 8 and 64K-Byte x 63 • Extra 64K-Byte sector for security - Features factory locked and identifiable, and customer lockable • Twenty-Four Sector Groups - Provides sector group protect function to prevent program or erase operation in the protected sector group - Provides chip unprotect function to allow code changing - Provides temporary sector group unprotect function for code changing in previously protected sector groups • Single Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations • Latch-up protected to 250mA from -1V to Vcc + 1V • Low Vcc write inhibit is equal to or less than 1.4V • Compatible with JEDEC standard - Pinout and software compatible to single power supply Flash • 2nd generation of 3V/32M Flash product - Fully compatible with MX29LV320T/B device PERFORMANCE • High Performance - Fast access time: 70/90ns - Fast program time: 7us/word typical utilizing accelerate function - Fast erase time: 0.9s/sector, 35s/chip (typical) • Low Power Consumption - Low active read current: 10mA (typical) at 5MHz - Low standby current: 200nA (typical) • Minimum 100,000 erase/program cycle • 10 years data retention SOFTWARE FEATURES • Erase Suspend/ Erase Resume - Suspends sector erase operation to read data from or program data to another sector which is not being erased • Status Reply - Data polling & Toggle bits provide detection of program and erase operation completion • Support Common Flash Interface (CFI) HARDWARE FEATURES • Ready/Busy (RY/BY) Output - Provides a hardware method of detecting program and erase operation completion • Hardware Reset (RESET) Input - Provides a hardware method to reset the internal state machine to read mode • WP/ACC input pin - Provides accelerated program capability PACKAGE • 48-Pin TSOP • 48-Ball CSP
GENERAL DESCRIPTION
The MX29LV320AT/B is a 32-mega bit Flash memory organized as 4M bytes of 8 bits and 2M words of 16 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX29LV320AT/B is packaged in 48-pin TSOP and 48-ball CSP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers. The standard MX29LV320AT/B offers access time as fast as 70ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX29LV320AT/B has separate chip enable (CE) and output enable (OE) controls.
P/N:PM1008
MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29LV320AT/B uses a command register to manage this functionality. MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and program mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling.
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The MX29LV320AT/B uses a 2.7V to 3.6V VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamperes on address and data pin from -1V to VCC + 1V.
modes allow sectors of the array to be erased in one erase cycle. The Automatic Sector Erase algorithm automatically programs the specified sector(s) prior to electrical erase. The timing and verification of electrical erase are controlled internally within the device.
AUTOMATIC ERASE ALGORITHM MXIC's Automatic Erase algorithm requires the user to write commands to the command register using standard microprocessor write timings. The device will automatically pre-program and verify the entire array. Then the device automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. A status bit toggling between consecutive read cycles provides feedback to the user as to the status of the programming operation. Register contents serve as inputs to an internal statemachine which controls the erase and programming circuitry. During write cycles, the command register internally latches address and data needed for the programming and erase operations. During a system write cycle, addresses are latched on the falling edge, and data are latched on the rising edge of WE . MXIC's Flash technology combines years of EPROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The MX29LV320AT/B electrically erases all bits simultaneously using Fowler-Nordheim tunneling. The bytes/words are programmed by using the EPROM programming mechanism of hot electron injection. During a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. During a Sector Erase cycle, the command register will only respond to Erase Suspend command. After Erase Suspend is completed, the device stays in read mode. After the state machine has completed its task, it will allow the command register to respond to its full command set.
AUTOMATIC PROGRAMMING The MX29LV320AT/B is byte/word programmable using the Automatic Programming algorithm. The Automatic Programming algorithm makes the external system do not need to have time out sequence nor to verify the data programmed. The typical chip programming time at room temperature of the MX29LV320AT/B is less than 36 seconds.
AUTOMATIC PROGRAMMING ALGORITHM MXIC's Automatic Programming algorithm require the user to only write program set-up commands (including 2 unlock write cycle and A0H) and a program command (program data and address). The device automatically times the programming pulse width, provides the program verification, and counts the number of sequences. A status bit similar to DATA polling and a status bit toggling between consecutive read cycles, provide feedback to the user as to the status of the programming operation.
AUTOMATIC CHIP ERASE The entire chip is bulk erased using 50 ms erase pulses according to MXIC's Automatic Chip Erase algorithm. Typical erasure at room temperature is accomplished in less than 35 seconds. The Automatic Erase algorithm automatically programs the entire array prior to electrical erase. The timing and verification of electrical erase are controlled internally within the device.
AUTOMATIC SECTOR ERASE The MX29LV320AT/B is sector(s) erasable using MXIC's Auto Sector Erase algorithm. Sector erase
P/N:PM1008
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PIN CONFIGURATION
48 TSOP
A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE RESET NC WP/ACC RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC Q11 Q3 Q10 Q2 Q9 Q1 Q8 Q0 OE GND CE A0
MX29LV320AT/B
48-Ball CSP 6mm x 8mm (Ball Pitch = 0.8 mm), Top View, Balls Facing Down A B C D E F G H 6 5 4 3 2 1 A13 A9 WE A12 A8 RESET A14 A10 NC A18 A6 A2 A15 A11 A19 A20 A5 A1 A16 Q7 Q5 Q2 Q0 A0 BYTE Q14 Q12 Q10 Q8 CE Q15/A-1 GND Q13 Vcc Q11 Q9 OE Q6 Q4 Q3 Q1 GND
RY/BY WP/ACC A7 A3 A17 A4
PIN DESCRIPTION
SYMBOL A0~A20 Q0~Q14 Q15/A-1 CE WE OE BYTE RESET RY/BY VCC WP/ACC GND NC
P/N:PM1008
LOGIC SYMBOL
21 A0-A20 Q0-Q15 (A-1) 16 or 8
PIN NAME Address Input 15 Data Inputs/Outputs Q15(Data Input/Output, word mode) A-1(LSB Address Input, byte mode) Chip Enable Input Write Enable Input Output Enable Input Word/Byte Selection Input Hardware Reset Pin, Active Low Read/Busy Output 3.0 volt-only single power supply Hardware Write Protect/Acceleration Pin Device Ground Pin Not Connected Internally
CE OE WE RESET BYTE WP/ACC RY/BY
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BLOCK DIAGRAM
CE OE WE RESET BYTE
WRITE CONTROL INPUT LOGIC HIGH VOLTAGE MACHINE (WSM) PROGRAM/ERASE STATE
X-DECODER
MX29LV320AT/B FLASH ARRAY ARRAY
STATE REGISTER
ADDRESS LATCH A0-A20 AND BUFFER
SENSE AMPLIFIER
Y-DECODER
Y-PASS GATE
SOURCE HV COMMAND DATA DECODER
PGM DATA HV COMMAND DATA LATCH
PROGRAM DATA LATCH
Q0-Q15/A-1
I/O BUFFER
P/N:PM1008
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Table 1.a: MX29LV320AT SECTOR GROUP ARCHITECTURE
Sector Group 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6 7 7 7 7 8 8 8 8 9 9 9 9 10 10 10 10
P/N:PM1008
Sector Sector Address A20-A12 SA0 000000xxx SA1 000001xxx SA2 000010xxx SA3 000011xxx SA4 000100xxx SA5 000101xxx SA6 000110xxx SA7 000111xxx SA8 001000xxx SA9 001001xxx SA10 001010xxx SA11 001011xxx SA12 001100xxx SA13 001101xxx SA14 001110xxx SA15 001111xxx SA16 010000xxx SA17 010001xxx SA18 010010xxx SA19 010011xxx SA20 010100xxx SA21 010101xxx SA22 010110xxx SA23 010111xxx SA24 011000xxx SA25 011001xxx SA26 011010xxx SA27 011011xxx SA28 011100xxx SA29 011101xxx SA30 011110xxx SA31 011111xxx SA32 100000xxx SA33 100001xxx SA34 100010xxx SA35 100011xxx SA36 100100xxx SA37 100101xxx SA38 100110xxx SA39 100111xxx
Sector Size (Kbytes/Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32
(x8) Address Range 000000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 200000h-20FFFFh 210000h-21FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 260000h-26FFFFh 270000h-27FFFFh
(x16) Address Range 000000h-07FFFh 008000h-0FFFFh 010000h-17FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh
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Sector Group 11 11 11 11 12 12 12 12 13 13 13 13 14 14 14 14 15 15 15 15 16 16 16 17 18 19 20 21 22 23 24 Sector Sector Address A20-A12 SA40 101000xxx SA41 101001xxx SA42 101010xxx SA43 101011xxx SA44 101100xxx SA45 101101xxx SA46 101110xxx SA47 101111xxx SA48 110000xxx SA49 110001xxx SA50 110010xxx SA51 110011xxx SA52 110100xxx SA53 110101xxx SA54 110110xxx SA55 110111xxx SA56 111000xxx SA57 111001xxx SA58 111010xxx SA59 111011xxx SA60 111100xxx SA61 111101xxx SA62 111110xxx SA63 111111000 SA64 111111001 SA65 111111010 SA66 111111011 SA67 111111100 SA68 111111101 SA69 111111110 SA70 111111111 Sector Size (Kbytes/Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 (x8) Address Range 280000h-28FFFFh 290000h-29FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3F1FFFh 3F2000h-3F3FFFh 3F4000h-3F5FFFh 3F6000h-3F7FFFh 3F8000h-3F9FFFh 3FA000h-3FBFFFh 3FC000h-3FDFFFh 3FE000h-3FFFFFh (x16) Address Range 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-147FFFh 168000h-14FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1F8FFFh 1F9000h-1F9FFFh 1FA000h-1FAFFFh 1FB000h-1FBFFFh 1FC000h-1FCFFFh 1FD000h-1FDFFFh 1FE000h-1FEFFFh 1FF000h-1FFFFFh
Note:The address range is A20:A-1 in byte mode (BYTE=VIL) or A20:A0 in word mode (BYTE=VIH)
Top Boot Security Sector Addresses
Sector Address A20~A12 111111xxx Sector Size (Kbytes/Kwords) 64/32 (x8) Address Range 3F0000h-3FFFFFh (x16) Address Range 1F8000h-1FFFFFh
P/N:PM1008
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Table 1.b: MX29LV320AB SECTOR GROUP ARCHITECTURE
Sector Group 1 2 3 4 5 6 7 8 9 9 9 10 10 10 10 11 11 11 11 12 12 12 12 13 13 13 13 14 14 14 14 15 15 15 15 16 16 16 16 Sector Sector Address A20-A12 SA0 000000000 SA1 000000001 SA2 000000010 SA3 000000011 SA4 000000100 SA5 000000101 SA6 000000110 SA7 000000111 SA8 000001xxx SA9 000010xxx SA10 000011xxx SA11 000100xxx SA12 000101xxx SA13 000110xxx SA14 000111xxx SA15 001000xxx SA16 001001xxx SA17 001010xxx SA18 001011xxx SA19 001100xxx SA20 001101xxx SA21 001110xxx SA22 001111xxx SA23 010000xxx SA24 010001xxx SA25 010010xxx SA26 010011xxx SA27 010100xxx SA28 010101xxx SA29 010110xxx SA30 010111xxx SA31 011000xxx SA32 011001xxx SA33 011010xxx SA34 011011xxx SA35 011100xxx SA36 011101xxx SA37 011110xxx SA38 011111xxx Sector Size (Kbytes/Kwords) 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x8) Address Range 000000h-001FFFh 002000h-003FFFh 004000h-005FFFh 006000h-007FFFh 008000h-009FFFh 00A000h-00BFFFh 00C000h-00DFFFh 00E000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh (x16) Address Range 000000h-000FFFh 001000h-001FFFh 002000h-002FFFh 003000h-003FFFh 004000h-004FFFh 005000h-005FFFh 006000h-006FFFh 007000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh
P/N:PM1008
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MX29LV320AT/B
Sector Group 17 17 17 17 18 18 18 18 19 19 19 19 20 20 20 20 21 21 21 21 22 22 22 22 23 23 23 23 24 24 24 24 Sector Sector Address A20-A12 SA39 100000xxx SA40 100001xxx SA41 100010xxx SA42 100011xxx SA43 100100xxx SA44 100101xxx SA45 100110xxx SA46 100111xxx SA47 101000xxx SA48 101001xxx SA49 101010xxx SA50 101011xxx SA51 101100xxx SA52 101101xxx SA53 101110xxx SA54 101111xxx SA55 110000xxx SA56 110001xxx SA57 110010xxx SA58 110011xxx SA59 110100xxx SA60 110101xxx SA61 110110xxx SA62 110111xxx SA63 111000xxx SA64 111001xxx SA65 111010xxx SA66 111011xxx SA67 111100xxx SA68 111101xxx SA69 111110xxx SA70 111111xxx Sector Size (Kbytes/Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x8) Address Range 200000h-20FFFFh 210000h-21FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3FFFFFh (x16) Address Range 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh
Note:The address range is A20:A-1 in byte mode (BYTE=VIL) or A20:A0 in word mode (BYTE=VIH)
Bottom Boot Security Sector Addresses
Sector Address A20~A12 111111xxx Sector Size (Kbytes/Kwords) 64/32 (x8) Address Range 000000h-00FFFFh (x16) Address Range 00000h-07FFFh
P/N:PM1008
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Table 2. BUS OPERATION--1
Operation Read Write (Note 1) Accelerate Program Standby Output Disable Reset Sector Group Protect (Note 2) Chip Unprotect (Note 2) Temporary Sector Group Unprotect Legend: L=Logic LOW=VIL, H=Logic High=VIH, VID=12.0±0.5V, VHH=11.5-12.5V, X=Don't Care, AIN=Address IN, DIN=Data IN, DOUT=Data OUT Notes: 1. When the WP/ACC pin is at VHH, the device enters the accelerated program mode. See "Accelerated Program Operations" for more information. 2.The sector group protect and chip unprotect functions may also be implemented via programming equipment. See the "Sector Group Protection and Chip Unprotection" section. 3.If WP/ACC=VIL, the two outermost boot sectors remain protected. If WP/ACC=VIH, the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in "Sector/ Sector Block Protection and Unprotection". If WP/ACC=VHH, all sectors will be unprotected. 4.DIN or Dout as required by command sequence, data polling, or sector protection algorithm. 5.Address are A20:A0 in word mode (BYTE=VIH), A20:A-1 in byte mode (BYTE=VIL). X X X VID Note 3 L H L VID Note 3 VCC ± X 0.3V L X L H X H H X L X VCC ± 0.3V H L VID L/H L/H L/H X X A6=L, A1=H, A0=L Sector Addresses, DIN, DOUT A6=H, A1=H, A0=L AIN DIN DIN High-Z X X High-Z High-Z High-Z High-Z X High-Z High-Z X H X High-Z High-Z High-Z CE L L L OE L H H WE RESET WP/ACC H L L H H H L/H Note 3 V HH Addresses (Note 2) AIN AIN AIN DOUT DIN DIN Q0~Q7 DOUT DIN DIN Q8 ~ Q15 Byte=VIH Byte=VIL Q8-A14 =High-Z Q15=A-1
Sector Addresses, DIN, DOUT
P/N:PM1008
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BUS OPERATION--2
A20 to A12 X X X SA X A11 to A10 X X X X X A9 A8 to A7 X X X X X A6 A5 to A2 X X X X X
Operation Read Silicon ID Manufacturer Code Read Silicon ID MX29LV320AT Read Silicon ID MX29LV320AB Sector Protect Verification Security Sector Indicater Bit (Q7)
CE L L L L L
OE L L L L L
WE H H H H H
A1 L L L H H
A0 L H H L H
Q0-Q7 C2H A7H A8H 01h(1), or 00h 99h(2), or 19h
Q8-Q15 X 22h(word) X (byte) 22h(word) X (byte) X X
VID VID VID VID VID
L L L L L
Notes: 1.Code=00h means unprotected, or code=01h protected. 2.Code=99 means factory locked, or code=19h not factory locked.
P/N:PM1008
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MX29LV320AT/B
REQUIREMENTS FOR READING ARRAY DATA
To read array data from the outputs, the system must drive the CE and OE pins to VIL. CE is the power control and selects the device. OE is the output control and gates array data to the output pins. WE should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid address on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered.
ACCELERATED PROGRAM OPERATION
The device offers accelerated program operations through the WP/ACC function. If the system asserts VHH on ACC pin, the device will provide the fast programming time to user. This function is primarily intended to allow faster manufacturing throughput during production. Removing VHH from the WP/ACC pin returns the device to normal operation. Note that the WP/ACC pin must not be at VHH for operations other than accelerated programming, or device damage may result.
STANDBY MODE
MX29LV320AT/B can be set into Standby mode with two different approaches. One is using both CE and RESET pins and the other one is using RESET pin only. When using both pins of CE and RESET, a CMOS Standby mode is achieved with both pins held at Vcc ± 0.3V. Under this condition, the current consumed is less than 0.2uA (typ.). If both of the CE and RESET are held at VIH, but not within the range of VCC ± 0.3V, the device will still be in the standby mode, but the standby current will be larger. During Auto Algorithm operation, Vcc active current (ICC2) is required even CE = "H" until the operation is completed. The device can be read with standard access time (tCE) from either of these standby modes. When using only RESET, a CMOS standby mode is achieved with RESET input held at Vss ± 0.3V, Under this condition the current is consumed less than 1uA (typ.). Once the RESET pin is taken high, the device is back to active without recovery delay. In the standby mode the outputs are in the high impedance state, independent of the OE input. MX29LV320AT/B is capable to provide the Automatic Standby Mode to restrain power consumption during readout of data. This mode can be used effectively with an application requested low power consumption such as handy terminals. To active this mode, MX29LV320AT/B automatically switch themselves to low power mode when MX29LV320AT/B addresses remain stable during access time of tACC+30ns. It is not necessary to control CE, WE, and OE on the mode. Under the mode, the current consumed is typically 0.2uA (CMOS level).
WRITE COMMANDS/COMMAND SEQUENCES
To program data to the device or erase sectors of memory , the system must drive WE and CE to VIL, and OE to VIH. An erase operation can erase one sector, multiple sectors , or the entire device. Table 1 indicates the address space that each sector occupies. A "sector address" consists of the address bits required to uniquely select a sector. Writing specific address and data commands or sequences into the command register initiates device operations. Table 3 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. Section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the Automatic Select command sequence, the device enters the Automatic Select mode. The system can then read Automatic Select codes from the internal register (which is separate from the memory array) on Q7-Q0. Standard read cycle timings apply in this mode. Refer to the Automatic Select Mode and Automatic Select Command Sequence section for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC Characteristics" section contains timing specification table and timing diagrams for write operations.
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OUTPUT DISABLE
With the OE input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins to be in a high impedance state. The primary method requires VID on the RESET only. This method can be implemented either in-system or via programming equipment. This method uses standard microprocessor bus cycle timing. Refer to Figure 13 for timing diagram and Figure 14 illustrates the algorithm for the sector group protection operation. The alternate method intended only for programming equipment, must force VID on address pin A9 and control pin OE, (suggest VID = 12V) A6 = VIL and CE = VIL(see Table 2). Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated on the rising edge. Contact MXIC for details. To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9 ( with CE and OE at VIL and WE at VIH). When A1=1, it will produce a logical "1" code at device output Q0 for a protected sector. Otherwise the device will produce 00H for the unprotected sector. In this mode, the addresses, except for A1, are don't care. Address locations with A1= VIL are reserved to read manufacturer and device codes.(Read Silicon ID) It is also possible to determine if the group is protected in the system by writing a Read Silicon ID command. Performing a read operation with A1=VIH, it will produce a logical "1" at Q0 for the protected sector.
RESET OPERATION
The RESET pin provides a hardware method of resetting the device to reading array data. When the RESET pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity Current is reduced for the duration of the RESET pulse. When RESET is held at VSS±0.3V, the device draws CMOS standby current (ICC4). If RESET is held at VIL but not within VSS±0.3V, the standby current will be greater. The RESET pin may be tied to system reset circuitry. A system reset would that also reset the Flash memory, enabling the system to read the boot-up firm-ware from the Flash memory. If RESET is asserted during a program or erase operation, the RY/BY pin remains a "0" (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY to determine whether the reset operation is complete. If RESET is asserted when a program or erase operation is not executing (RY/BY pin is "1"), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET pin returns to VIH. Refer to the AC Characteristics tables for RESET parameters and to Figure 14 for the timing diagram.
CHIP UNPROTECT OPERATION
The MX29LV320AT/B also features the chip unprotect mode, so that all sectors are unprotected after chip unprotect is completed to incorporate any changes in the code. It is recommended to protect all sectors before activating chip unprotect mode. The primary method requires VID on the RESET only. This method can be implemented either in-system or via programming equipment. This method uses standard microprocessor bus cycle timing. Refer to Figure 13 for timing diagram and Figure 14 illustrates the algorithm for the sector group protection operation. The alternate method intended only for programming equipment, must force VID on address pin A9 and control pin OE, (suggest VID = 12V) A6 = VIL and CE = VIL(see Table 2). Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated on the rising edge. Contact MXIC for details.
SECTOR GROUP PROTECT OPERATION
The MX29LV320AT/B features hardware sector group protection. This feature will disable both program and erase operations for these sector group protected. Sector protection can be implemented via two methods.
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It is also possible to determine if the chip is unprotected in the system by writing the Read Silicon ID command. Performing a read operation with A1=VIH, it will produce 00H at data outputs(Q0-Q7) for an unprotected sector. It is noted that all sectors are unprotected after the chip unprotect algorithm is completed.
AUTOMATIC SELECT OPERATION
Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacturer and device codes must be accessible while the device resides in the target system. PROM programmers typically access signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto address lines is not generally desired system design practice. MX29LV320AT/B provides hardware method to access the Automatic Select operation. This method requires VID on A9 pin, VIL on CE, OE, A6, and A1 pins. When applying VIL on A0 pin, the device will output MXIC's manufacture code of C2H. When applying VIH on A0 pin, the device will output MX29LV320AT/B device code of 22A7h and 22A8h.
TEMPORARY SECTOR GROUP UNPROTECT OPERATION
This feature allows temporary unprotection of previously protected sector to change data in-system. The Temporary Sector Unprotect mode is activated by setting the RESET pin to VID(11.5V-12.5V). During this mode, formerly protected sectors can be programmed or erased as un-protected sector. Once VID is remove from the RESET pin, all the previously protected sectors are protected again.
WRITE PROTECT (WP)
The write protect function provides a hardware method to protect boot sectors without using VID. If the system asserts VIL on the WP/ACC pin, the device disables program and erase functions in the two "outermost" 8 Kbyte boot sectors independently of whether those sectors were protected or unprotected using the method described in Sector/Sector Group Protection and Chip Unprotection". The two outermost 8 Kbyte boot sectors are the two sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-configured device. If the system asserts VIH on the WP/ACC pin, the device reverts to whether the two outermost 8K Byte boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in "Sector/Sector Group Protection and Chip Unprotection". Note that the WP/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result.
VERIFY SECTOR GROUP PROTECT STATUS OPERATION
MX29LV320AT/B provides hardware method for sector group protect status verify. This method requires VID on A9 pin, VIH on WE and A1 pins, VIL on CE, OE, A6, and A0 pins, and sector address on A12 to A20 pins. When the identified sector is protected, the device will output 01H. When the identified sector is not protect, the device will output 00H.
SECURITY SECTOR FLASH MEMORY REGION
The Security Sector (Security Sector) feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The Security Sector is 64 Kbytes (32 Kwords) in length, and uses a Security Sector Indicator Bit (Q7) to indicate whether or not the Security Sector is locked when shipped from the factory. This bit is per-manently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field. MXIC offers the device with the Security Sector either factory locked or customer lockable. The factory-locked version is always protected when shipped from the factory, and has the Security on Silicon Sector (Security Sector) Indicator Bit permanently set to a "1". The customer-lockable version is shipped with the unprotected, allowing customers to utilize the that sector in any man-
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ner they choose. The customer-lockable version has the Security on Silicon Sector (Security Sector) Indicator Bit permanently set to a "0". Thus, the Security Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory locked. The system accesses the Security Sector through a command sequence (see "Enter Security Sector/Exit Security Sector Command Sequence"). After the system has written the Enter Security Sector command sequence, it may read the Security Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit Security Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the boot sectors. Write the three-cycle Enter Security Region command sequence, and then follow the in-system sector group protect algorithm as shown in Figure 14, except that RESET may be at either VIH or VID. This allows in-system protection of the without raising any device pin to a high voltage. Note that this method is only applicable to the Security Sector. Write the three-cycle Enter Security Region command sequence, and then use the alternate method of sector protection described in the "Sector/Sector Block Protection and Unprotection section. Once the Security Sector is locked and verified, the system must write the Exit Security Sector Region command sequence to return to reading and writing the remainder of the array. The Security Sector protection must be used with caution since, once protected, there is no procedure available for unprotecting the Security Sector area and none of the bits in the Security Sector memory space can be modified in any way.
Factory Locked: Security Sector Programmed and Protected at the Factory
In a factory locked device, the Security Sector is protected when the device is shipped from the factory. The Security Sector cannot be modified in any way. The device is available preprogrammed with one of the following: A random, secure ESN only. Customer code through the Express Flash service. Both a random, secure ESN and customer code through the Express Flash service. In devices that have an ESN, a Bottom Boot device will have the 16-byte (8-word) ESN in the lowest addressable memory area starting at 00000h and ending at 0000Fh (00007h). In the Top Boot device the starting address of the ESN will be at the bottom of the lowest 8 Kbyte (4 Kword) boot sector starting at 3F0000h (1F8000h) and ending at 3F000Fh (1F8007h).
DATA PROTECTION
The MX29LV320AT/B is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise.
LOW VCC WRITE INHIBIT Customer Lockable: Security Sector NOT Programmed or Protected at the Factory
If the security feature is not required, the Security Sector can be treated as an additional Flash memory space, expanding the size of the available Flash array by 64 Kbytes (32 Kwords). The Security Sector can be read, programmed, and erased as often as required. The Security Sector area can be protected using one of the following procedures:
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When VCC is less than VLKO the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional write when VCC is greater than VLKO.
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WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 5ns (typical) on OE, CE or WE will not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE = VIL, CE = VIH or WE = VIH. To initiate a write cycle CE and WE must be a logical zero while OE is a logical one.
POWER-UP SEQUENCE
The MX29LV320AT/B powers up in the Read only mode. In addition, the memory contents may only be altered after successful completion of the predefined command sequences.
POWER-UP WRITE INHIBIT
If WE=CE=VIL and OE=VIH during power up, the device does not accept commands on the rising edge of WE. The internal state machine is automatically reset to the read mode on power-up.
POWER SUPPLY DECOUPLING
In order to reduce power switching effect, each device should have a 0.1uF ceramic capacitor connected between its VCC and GND.
SOFTWARE COMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. Table 3 defines the valid register command sequences. Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Either of the two reset command sequences will reset the device (when applicable). All addresses are latched on the falling edge of WE or CE, whichever happens later. All data are latched on rising edge of WE or CE, whichever happens first.
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TABLE 3. MX29LV320AT/B COMMAND DEFINITIONS
First Bus Command Read(Note 5) Reset(Note 4) Automatic Select(Note 5) Manufacturer ID Device ID Word Byte Word Byte Security Sector Factory Word Protect Verify (Note 6) Byte Sector Protect Verify (Note 7) Enter Security Sector Region Exit Security Sector Program Chip Erase Sector Erase CFI Query (Note 8) Erase Suspend(Note 9) Erase Resume(Note 10) Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte 4 4 4 4 4 4 4 4 3 3 4 4 4 4 6 6 6 6 1 1 1 1 555 AAA 555 AAA 555 AAA 555 AAA 555 AAA 555 AAA 555 AAA 555 AAA 555 AAA 55 AA SA SA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA 98 98 B0 30 PD=Data to be programmed at location PA. Data is latched on the rising edge of WE or CE pulse. SA=Address of the sector to be erased or verified. Address bits A20-A12 uniquely select any sector. ID=22A7h(Top), 22A8h(Bottom) 2AA 555 2AA 555 2AA 555 2AA 555 2AA 555 2AA 555 2AA 555 2AA 555 2AA 555 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 555 AAA 555 AAA 555 AAA 555 AAA 555 AAA 555 AAA 555 AAA 555 AAA 555 AAA 90 90 90 90 90 90 90 90 88 88 90 90 A0 A0 80 80 80 80 XXX XXX PA PA 555 AAA 555 AAA 00 00 PD PD AA AA AA AA 2AA 55 555 555 55 55 2AA 55 555 SA SA 10 30 30 AAA 10 X00 X00 X01 X02 X03 X06 (SA)X02 00/01 (SA)X04 99/19 C2H C2H ID Bus 1 1 Cycle RA XXX RD F0 Second Bus Third Bus Cycle Cycle Fourth Bus Cycle Data Fifth Bus Cycle Sixth Bus Cycle
Cycles Addr Data Addr Data Addr Data Addr
Addr Data Addr Data
Legend:
X=Don't care RA=Address of the memory location to be read. RD=Data read from location RA during read operation. PA=Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE or CE pulse.
Notes:
1. 2. 3. 4. See Table 1 for descriptions of bus operations. All values are in hexadecimal. Except when reading array or Automatic Select data, all bus cycles are write operation. The Reset command is required to return to the read mode when the device is in the Automatic Select mode or if Q5 goes high. 5. The fourth cycle of the Automatic Select command sequence is a read cycle. 6. The data is 99h for factory locked and 19h for not factory locked. 7. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. In the third cycle of the command sequence, address bit A20=0 to verify sectors 0~31, A20=1 to verify sectors 32~70 for Top Boot device. 8. Command is valid when device is ready to read array data or when device is in Automatic Select mode. 9. The system may read and program functions in non-erasing sectors, or enter the Automatic Select mode, when in the erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 10. The Erase Resume command is valid only during the Erase Suspend mode.
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READING ARRAY DATA
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Automatic Program or Automatic Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erasesuspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See Erase Suspend/Erase Resume Commands” for more information on this mode. The system must issue the reset command to re-enable the device for reading array data if Q5 goes high during an active program or erase operation, or while in the Automatic Select mode. See the "Reset Command" section, next.
AUTOMATIC SELECT COMMAND SEQUENCE
The Automatic Select command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Table 2 shows the address and data requirements. This method is an alternative to that shown in Table 3, which is intended for EPROM programmers and requires VID on address bit A9. The Automatic Select command sequence is initiated by writ-ing two unlock cycles, followed by the Automatic Select command. The device then enters the Automatic Select mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h in word mode (or xx02h in byte mode) returns the device code. A read cycle containing a sector address (SA) and the address 02h on A7-A0 in word mode (or the address 04h on A6-A-1 in byte mode) returns 01h if that sector is protected, or 00h if it is unprotected. Refer to Table 1 for valid sector addresses. The system must write the reset command to exit the Automatic Select mode and return to reading array data.
RESET COMMAND
Writing the reset command to the device resets the device to reading array data. Address bits are don't care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an Automatic Select command sequence. Once in the Automatic Select mode, the reset command must be written to return to reading array data (also applies to Automatic Select during Erase Suspend). If Q5 goes high during a program or erase operation, writing the reset command returns the device to read-ing array data (also applies during Erase Suspend).
ENTER SECURITY SECTOR & EXIT SECURITY SECTOR COMMAND SEQUENCE
The Security Sector provides a secured area which contains a random, sixteen-byte electronic serial number.(ESN) The system can access the Security Sector area by issuing the three-cycle "Enter Security Sector command sequence. The device continues to access the security section area until the system issues the four-cycle Exit Security Sector command sequence. The Exit Security Sector command sequence returns the device to normal operation.
BYTE/WORD PROGRAM COMMAND SEQUENCE
The device programs one byte/word of data for each program operation. The command sequence requires four bus cycles, and is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically generates the program pulses and
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verifies the programmed cell margin. Table 3 shows the address and data requirements for the byte/word program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using Q7, Q6, or RY/ BY. See "Write Operation Status" for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming operation. The Byte/Word Program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a "0" back to a "1". Attempting to do so may cause the device to set Q5 to "1" ,” or cause the Data Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still "0". Only erase operations can convert a "0" to a "1".
SETUP AUTOMATIC CHIP/SECTOR ERASE
Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command 80H. Two more "unlock" write cycles are then followed by the chip erase command 10H, or the sector erase command 30H. The MX29LV320AT/B contains a Silicon-ID-Read operation to supplement traditional PROM programming methodology. The operation is initiated by writing the read silicon ID command sequence into the command register. Following the command write, a read cycle with A1=VIL,A0=VIL retrieves the manufacturer code of C2H. A read cycle with A1=VIL, A0=VIH returns the device code of A7H/A8H for MX29LV320AT/B.
TABLE 4. SILICON ID CODE
Pins Manufacture code Device code for MX29LV320AT Device code for MX29LV320AB A0 VIL A1 VIL Q7 1 1 1 Q6 1 0 0 Q5 0 1 1 Q4 0 0 0 Q3 0 0 1 Q2 0 1 0 Q1 1 1 0 Q0 0 1 0 Code (Hex) C2H 22A7H 22A8H
VIH VIL VIH VIL
AUTOMATIC CHIP/SECTOR ERASE COMMAND The device does not require the system to preprogram prior to erase. The Automatic Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 3 shows the address and data requirements for the chip erase command sequence. Any commands written to the chip during the Automatic Erase algorithm are ignored. Note that a hard-ware reset during the chip erase operation immediately terminates the operation. The Chip Erase command sequence should
be reinitiated once the device has returned to reading array data, to ensure data integrity. The system can determine the status of the erase operation by using Q7, Q6, Q2, or RY/BY. See "Write Operation Status" for information on these status bits. When the Automatic Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Figure 5 illustrates the algorithm for the erase opera-tion. See the Erase/Program Operations tables in "AC Characteristics" for parameters, and to Figure 4 for timing diagrams.
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SECTOR ERASE COMMANDS
The device does not require the system to entirely pre-program prior to executing the Automatic Set-up Sector Erase command and Automatic Sector Erase command. Upon executing the Automatic Sector Erase command, the device will automatically program and verify the sector(s) memory for an allzero data pattern. The system is not required to provide any control or timing during these operations. When the sector(s) is automatically verified to contain an all-zero pattern, a self-timed sector erase and verify begin. The erase and verify operations are complete when the data on Q7 is "1" and the data on Q6 stops toggling for two consecutive read cycles, at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations. When using the Automatic Sector Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required). Sector erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the set-up command 80H. Two more "unlock" write cycles are then followed by the sector erase command 30H. The sector address is latched on the falling edge of WE or CE, whichever happens later , while the command(data) is latched on the rising edge of WE or CE, whichever happens first. Sector addresses selected are loaded into internal register on the sixth falling edge of WE or CE, whichever happens later. Each successive sector load cycle started by the falling edge of WE or CE, whichever happens later must begin within 50us from the rising edge of the preceding WE or CE, whichever happens first. Otherwise, the loading period ends and internal auto sector erase cycle starts. (Monitor Q3 to determine if the sector erase timer window is still open, see section Q3, Sector Erase Timer.) Any command other than Sector Erase(30H) or Erase Suspend(B0H) during the time-out period resets the device to read mode. Sector Erase operation. When the Erase Suspend command is issued during the sector erase operation, the device requires a maximum 20us to suspend the sector erase operation. However, When the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After this command has been executed, the command register will initiate erase suspend mode. The state machine will return to read mode automatically after suspend is ready. At this time, state machine only allows the command register to respond to the Erase Resume, program data to, or read data from any sector not selected for erasure. The system can use Q7, or Q6 and Q2 together, to determine if a sector is actively erasing or is erase-suspended. The system can determine the status of the program operation using the Q7 or Q6 status bits, just as in the standard program operation. After an erase-suspend program operation is complete, the system can once again read array data within non-suspended blocks.
ERASE RESUME This command will cause the command register to clear the suspend state and return back to Sector Erase mode but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect in all other conditions. Another Erase Suspend command can be written after the chip has resumed erasing.
ERASE SUSPEND This command only has meaning while the state machine is executing Automatic Sector Erase operation, and therefore will only be responded during Automatic
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WRITE OPERATION STATUS
The device provides several bits to determine the status of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/BY. Table 5 and the following subsections describe the functions of these bits. Q7, RY/BY, and Q6 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first.
Table 5. Write Operation Status
Status Byte/Word Program in Auto Program Algorithm Auto Erase Algorithm Erase Suspend Read (Erase Suspended Sector) In Progress Erase Suspended Mode Erase Suspend Read Data (Non-Erase Suspended Sector) Erase Suspend Program Byte/Word Program in Auto Program Algorithm Exceeded Time Limits Auto Erase Algorithm Erase Suspend Program Q7 Q7 0 Q7 Data Toggle Toggle Toggle Toggle Data 0 1 1 1 Data Data N/A N/A 1 N/A N/A No Toggle Toggle N/A 1 0 0 0 0 Q7 Note1 Q7 0 1 Q6 Toggle Toggle No Toggle Q5 Note2 0 0 0 Q3 N/A 1 Q2 No Toggle Toggle RY/BY 0 0 1
N/A Toggle
Notes: 1. Performing successive read operations from the erase-suspended sector will cause Q2 to toggle. 2. Performing successive read operations from any address will cause Q6 to toggle. 3. Reading the byte/word address being programmed while in the erase-suspend program mode will indicate logic "1" at the Q2 bit. However, successive reads from the erase-suspended sector will cause Q2 to toggle.
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Q7: Data Polling
The Data Polling bit, Q7, indicates to the host system whether an Automatic Algorithm is in progress or completed, or whether the device is in Erase Suspend. Data Polling is valid after the rising edge of the final WE pulse in the program or erase command sequence. During the Automatic Program algorithm, the device outputs on Q7 the complement of the datum programmed to Q7. This Q7 status also applies to programming during Erase Suspend. When the Automatic Program algorithm is complete, the device outputs the datum programmed to Q7. The system must provide the program address to read valid status information on Q7. If a program address falls within a protected sector, Data Polling on Q7 is active for approximately 1 us, then the device returns to reading array data. During the Automatic Erase algorithm, Data Polling produces a "0" on Q7. When the Automatic Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data Polling produces a "1" on Q7. This is analogous to the complement/true datum out-put described for the Automatic Program algorithm: the erase function changes all the bits in a sector to "1" prior to this, the device outputs the "complement,” or "0". ” The system must provide an address within any of the sectors selected for erasure to read valid status information on Q7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data Polling on Q7 is active for approximately 100 us, then the device returns to reading array data. If not all selected sectors are protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. When the system detects Q7 has changed from the complement to true data, it can read valid data at Q7-Q0 on the following read cycles. This is because Q7 may change asynchronously with Q0-Q6 while Output Enable (OE) is asserted low. after the rising edge of the final WE or CE, whichever happens first pulse in the command sequence (prior to the program or erase operation), and during the sector time-out. During an Automatic Program or Erase algorithm operation, successive read cycles to any address cause Q6 to toggle. The system may use either OE or CE to control the read cycles. When the operation is complete, Q6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, Q6 toggles for 100us and returns to reading array data. If not all selected sectors are protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use Q6 and Q2 together to determine whether a sector is actively erasing or is erase suspended. When the device is actively erasing (that is, the Automatic Erase algorithm is in progress), Q6 toggling. When the device enters the Erase Suspend mode, Q6 stops toggling. However, the system must also use Q2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use Q7. If a program address falls within a protected sector, Q6 toggles for approximately 2us after the program command sequence is written, then returns to reading array data. Q6 also toggles during the erase-suspend-program mode, and stops toggling once the Automatic Program algorithm is complete. Table 5 shows the outputs for Toggle Bit I on Q6.
Q2:Toggle Bit II
The "Toggle Bit II" on Q2, when used with Q6, indicates whether a particular sector is actively erasing (that is, the Automatic Erase algorithm is in process), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE or CE, whichever happens first pulse in the command sequence. Q2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE or CE to control the read
Q6:Toggle BIT I
Toggle Bit I on Q6 indicates whether an Automatic Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid
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cycles.) But Q2 cannot distinguish whether the sector is actively erasing or is erase-suspended. Q6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sectors and mode information. Refer to Table 5 to compare outputs for Q2 and Q6. only operating functions of the device under this condition. If this time-out condition occurs during sector erase operation, it specifies that a particular sector is bad and it may not be reused. However, other sectors are still functional and may be used for the program or erase operation. The device must be reset to use other sectors. Write the Reset command sequence to the device, and then execute program or erase command sequence. This allows the system to continue to use the other active sectors in the device. If this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad or combination of sectors are bad. If this time-out condition occurs during the byte/word programming operation, it specifies that the entire sector containing that byte/word is bad and this sector maynot be reused, (other sectors are still functional and can be reused). The time-out condition may also appear if a user tries to program a non blank location without erasing. In this case the device locks out and never completes the Automatic Algorithm operation. Hence, the system never reads a valid data on Q7 bit and Q6 never stops toggling. Once the Device has exceeded timing limits, the Q5 bit will indicate a "1". Please note that this is not a device failure condition since the device was incorrectly used. The Q5 failure condition may appear if the system tries to program a "1" to a location that is previously programmed to "0". Only an erase operation can change a "0" back to a "1".” Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, Q5 produces a "1".
Reading Toggle Bits Q6/ Q2
Whenever the system initially begins reading toggle bit status, it must read Q7-Q0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on Q7-Q0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of Q5 is high (see the section on Q5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as Q5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that system initially determines that the toggle bit is toggling and Q5 has not gone high. The system may continue to monitor the toggle bit and Q5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation.
Q3:Sector Erase Timer
After the completion of the initial sector erase command sequence, the sector erase time-out will begin. Q3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, Q3 may be used to determine if the sector erase timer window is
Q5:Program/Erase Timing
Q5 will indicate if the program or erase time has exceeded the specified limits(internal pulse count). Under these conditions Q5 will produce a "1". This time-out condition indicates that the program or erase cycle was not successfully completed. Data Polling and Toggle Bit are the
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still open. If Q3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit. If Q3 is low ("0"), the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of Q3 prior to and following each subsequent sector erase command. If Q3 were high on the second status check, the command may not have been accepted. If the time between additional erase commands from the system can be less than 50us, the system need not to monitor Q3. lect mode. The command is valid only when the device is in the CFI mode.
RY/BY:READY/BUSY OUTPUT
The RY/BY is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY status is valid after the rising edge of the final WE pulse in the command sequence. Since RY/BY is an open-drain output, several RY/BY pins can be tied together in parallel with a pull-up resistor to VCC . If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (includ-ing during the Erase Suspend mode), or is in the standby mode.
QUERY COMMAND AND COMMON FLASH INTERFACE (CFI) MODE
MX29LV320AT/B is capable of operating in the CFI mode. This mode all the host system to determine the manufacturer of the device such as operating parameters and configuration. Two commands are required in CFI mode. Query command of CFI mode is placed first, then the Reset command exits CFI mode. These are described in Table 3. The single cycle Query command is valid only when the device is in the Read mode, including Erase Suspend, Standby mode, and Automatic Select mode; however, it is ignored otherwise. The Reset command exits from the CFI mode to the Read mode, or Erase Suspend mode, or Automatic SeP/N:PM1008 REV. 1.1, MAY 28, 2004
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Table 6-1. CFI mode: Identification Data Values
(All values in these tables are in hexadecimal) Description Query-unique ASCII string "QRY" Address (h) (Word Mode) 10 11 12 Primary vendor command set and control interface ID code Address for primary algorithm extended query table Alternate vendor command set and control interface ID code (none) Address for secondary algorithm extended query table (none) 13 14 15 16 17 18 19 1A Address (h) (Byte Mode) 20 22 24 26 28 2A 2C 2E 30 32 34 0051 0052 0059 0002 0000 0040 0000 0000 0000 0000 0000 Data (h)
Table 6-2. CFI Mode: System Interface Data Values
Description VCC supply, minimum (2.7V) VCC supply, maximum (3.6V) VPP supply, minimum (none) VPP supply, maximum (none) Typical timeout for single word/byte write (2 us) Typical timeout for maximum size buffer write (2 us) (not supported) Typical timeout for individual sector erase (2 ms) Typical timeout for full chip erase (2 ms) Maximum timeout for single word/byte write times (2 X Typ) Maximum timeout for maximum size buffer write times (2 X Typ) Maximum timeout for individual sector erase times (2 X Typ) Maximum timeout for full chip erase times (not supported)
N N N N N N N
Address (h) (Word Mode) 1B 1C 1D 1E 1F 20 21 22 23 24 25 26
Address (h) (Byte Mode) 36 38 3A 3C 3E 40 42 44 46 48 4A 4C
Data (h) 0027 0036 0000 0000 0004 0000 000A 0000 0005 0000 0004 0000
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Table 6-3. CFI Mode: Device Geometry Data Values
Description Device size (2 bytes) Flash device interface code (02=asynchronous x8/x16) Maximum number of bytes in multi-byte write (not supported) Number of erase sector regions Erase Sector Region 1 Information [2E,2D] = # of same-size sectors in region 1-1 [30, 2F] = sector size in multiples of 256-bytes Erase Sector Region 2 Information
N
Address (h) (Word Mode) 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34
Address (h) (Byte Mode) 4E 50 52 54 56 58 5A 5C 5E 60 62 64 66 68 6A 6C 6E 70 72 74 76 78
Data (h) 0016 0002 0000 0000 0000 0002 0007 0000 0020 0000 003E 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000
Erase Sector Region 3 Information
35 36 37 38
Erase Sector Region 4 Information
39 3A 3B 3C
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Table 6-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values
Description Query-unique ASCII string "PRI" Address (h) (Word Mode) 40 41 42 Major version number, ASCII Minor version number, ASCII Address sensitive unlock (0=required, 1= not required) Erase suspend (2= to read and write) Sector protect (N= # of sectors/group) Temporary sector unprotect (1=supported) Sector protect/Chip unprotect scheme Simultaneous R/W operation (0=not supported) Burst mode type (0=not supported) Page mode type (0=not supported) ACC (Acceleration) Supply Minimum (0=not supported, D7-D4:Volt, D3-D0:100mV ACC (Acceleration) Supply Maximum (0=not supported, D7-D4:Volt, D3-D0:100mV Top/Bottom Boot Sector Flag 02h=Bottom Boot Device, 03h=Top Boot Device 4F 9E 000X 4E 9C 00C5 43 44 45 46 47 48 49 4A 4B 4C 4D Address (h) (Byte Mode) 80 82 84 86 88 8A 8C 8E 90 92 94 96 98 9A 0050 0052 0049 0031 0031 0000 0002 0004 0001 0004 0000 0000 0000 00B5 Data (h)
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ABSOLUTE MAXIMUM RATINGS
Storage Temperature Plastic Packages . . . . . . . . . . . . . ..... -65oC to +150oC Ambient Temperature with Power Applied. . . . . . . . . . . . . .... -65oC to +125oC Voltage with Respect to Ground VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V A9, OE, and RESET (Note 2) . . . . . . . . . . . ....-0.5 V to +12.5 V All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V Output Short Circuit Current (Note 3) . . . . . . 200 mA Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to -2.0 V for periods of up to 20ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. 2. Minimum DC input voltage on pins A9, OE, and RESET is -0.5 V. During voltage transitions, A9, OE, and RESET may overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
OPERATING RATINGS
Commercial (C) Devices Ambient Temperature (TA ). . . . . . . . . . . . 0° C to +70° C Industrial (I) Devices Ambient Temperature (TA ). . . . . . . . . . -40° C to +85° C VCC Supply Voltages VCC for full voltage range. . . . . . . . . . . +2.7 V to 3.6 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
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DC CHARACTERISTICS
Para- Description meter ILI Input Load Current (Note 1) ILIT A9 Input Load Current ILO ICC1 ICC2 ICC3 ICC4 ICC5
VCC=2.7V~3.6V
Test Conditions TA=0° C to 70° C Min Typ Max ±1.0 35 ±1.0 10 2 15 0.2 0.2 0.2 16 4 30 15 15 15 10 2 15 0.2 0.2 0.2 TA=-40° C to 85° C Min Typ Max Unit ±1.0 uA 45 ±1.0 16 4 30 15 15 15 uA uA mA mA mA uA uA uA
IACC VIL VIH VHH
VID
VOL VOH1 VOH2 VLKO
VIN = VSS to VCC, VCC = VCC max VCC = VCC max, A9=12.5V Output Leakage Current VOUT = VSS to VCC , VCC = VCC max VCC Active Read Current CE= VIL, 5 MHz (Notes 2, 3) OE = VIH 1 MHz VCC Active Write Current CE= VIL , OE = VIH, (Notes 2, 4, 6) WE=VIL VCC Standby Current CE, RESET, (Note 2) WP/ACC = VCC±0.3V VCC Reset Current (Note 2) RESET = VSS ± 0.3V, WP/ACC= VCC ± 0.3V Automatic Sleep Mode VIH = VCC ± 0.3V; (Notes 2,5) VIL = VSS ± 0.3V, WP/ACC=VCC±0.3V WP/ACC Accelerated Program CE=VIL, WP/ACC pin Current, Word or Byte OE=VIH VCC pin Input Low Voltage -0.5 Input High Voltage 0.7xVcc Voltage for WP/ACC Sector VCC = 3.0 V ± 10% 11.5 Protect/Unprotect and Program Acceleration Voltage for Automatic Select VCC = 3.0 V ± 10% 11.5 and Temporary Sector Unprotect Output Low Voltage IOL=4.0mA, VCC=VCC min Output High Voltage IOH=-2.0mA, 0.85Vcc VCC=VCC min IOH=-100uA, Vcc-0.4 VCC = VCC min Low VCC Lock-Out Voltage 1.4 (Note 6)
5 15
10 5 10 mA 30 15 30 mA 0.8 -0.5 0.8 V Vcc+0.3 0.7xVcc Vcc+0.3 V 12.5 11.5 12.5 V
12.5
11.5
12.5
V
0.45 0.85Vcc Vcc-0.4 2.1 1.4
0.45
V V V
2.1
V
Notes: 1. On the WP/ACC pin only, the maximum input load current when WP/ACC = VIL is ± 5.0uA / VIH is ± 3.0uA. 2. Maximum ICC specifications are tested with VCC = VCC max. 3. The ICC current listed is typically is less than 2 mA/MHz, with OE at VIH. Typical specifications are for VCC = 3.0V. 4. ICC active while Embedded Erase or Embedded Program is in progress. 5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 6. Not 100% tested.
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SWITCHING TEST CIRCUITS TEST SPECIFICATIONS Test Condition Output Load Output Load Capacitance,CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels 70 90 Unit 1 TTL gate 30 100 pF 5 0.0-3.0 1.5 1.5 ns V V V
DEVICE UNDER TEST
1.6K ohm +3.3V
CL
6.2K ohm
DIODES=IN3064 OR EQUIVALENT
KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS Steady Changing from H to L Changing from L to H Don't Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State(High Z) OUTPUTS
SWITCHING TEST WAVEFORMS
3.0V
1.5V
Measurement Level
1.5V
0.0V INPUT
OUTPUT
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AC CHARACTERISTICS TA=-40° C to 85° C, VCC=2.7V~3.6V
Symbol tACC tCE tOE tDF tOH DESCRIPTION Address to output delay CONDITION CE=VIL MAX OE=VIL OE=VIL MAX MAX MAX MIN MIN MIN MIN MIN MIN MIN MIN MIN MIN MIN MIN MIN MIN MIN MIN MIN MIN MIN MIN MAX MIN MIN TYP TYP TYP TYP MAX 70 70 70 40 30 0 70 70 70 0 45 45 0 50 0 0 0 0 10 0 0 45 30 45 30 90 0 0 9 11 7 0.9 50 90 90 90 40 30 0 90 90 90 0 45 45 0 50 0 0 0 0 10 0 0 45 30 45 30 90 0 0 9 11 7 0.9 50 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns us us us sec us
Chip enable to output delay Output enable to output delay OE High to output float(Note1) Output hold time of from the rising edge of Address, CE or OE whichever happens first tRC Read cycle time (Note 1) tWC Write cycle time (Note 1) tCWC Command write cycle time(Note 1) tAS Address setup time tAH Address hold time tDS Data setup time tDH Data hold time tVCS Vcc setup time(Note 1) tCS Chip enable setup time tCH Chip enable hold time tOES Output enable setup time (Note 1) tOEH Output enable hold time (Note 1) Read Toggle & Data Polling tWES WE setup time tWEH WE hold time tCEP CE pulse width tCEPH CE pulse width high tWP WE pulse width tWPH WE pulse width high tBUSY Program/Erase valid to RY/BY delay tGHWL Read recovery time before write tGHEL Read recovery time before write tWHWH1 Programming operation BYTE WORD Accelerated programming operation word or byte tWHWH2 Sector erase operation tBAL Sector address hold time Note: 1.Not 100% Tested 2.tr = tf = 5ns
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Fig 1. COMMAND WRITE OPERATION
VCC
3V
Addresses
VIH
ADD Valid
VIL tAS tAH
WE
VIH VIL tOES tWPH tCWC
tWP
CE
VIH VIL tCS tCH
OE
VIH VIL VIH tDS tDH
Data
VIL
DIN
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READ/RESET OPERATION Fig 2. READ TIMING WAVEFORMS
tRC VIH
Addresses
VIL
ADD Valid
tCE VIH
CE
VIL
VIH
WE
VIL VIH VIL tOH tOEH tOE tDF
OE
tACC
Outputs
VOH VOL
HIGH Z
DATA Valid
HIGH Z
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AC CHARACTERISTICS
Parameter tREADY1 tREADY2 tRP1 tRP2 tRH tRB1 tRB2 Description RESET PIN Low (During Automatic Algorithms) to Read or Write (See Note) RESET PIN Low (NOT During Automatic Algorithms) to Read or Write (See Note) RESET Pulse Width (During Automatic Algorithms) RESET Pulse Width (NOT During Automatic Algorithms) RESET High Time Before Read(See Note) RY/BY Recovery Time(to CE, OE go low) RY/BY Recovery Time(to WE go low) MIN MIN MIN MIN MIN 10 500 70 0 50 us ns ns ns ns MAX 500 ns Test Setup All Speed Options Unit MAX 20 us
Note:Not 100% tested
Fig 3. RESET TIMING WAVEFORM
RY/BY
CE, OE
tRH
RESET
tRP2 tReady2
Reset Timing NOT during Automatic Algorithms
tReady1
RY/BY
tRB1
CE, OE
WE
tRB2
RESET
tRP1
Reset Timing during Automatic Algorithms
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ERASE/PROGRAM OPERATION Fig 4. AUTOMATIC CHIP ERASE TIMING WAVEFORM
Erase Command Sequence(last two cycle)
tWC tAS
Read Status Data
Address
2AAh
SA
555h for chip erase tAH
VA
VA
CE
tCH tGHWL
OE
tWP
tWHWH2
WE
tCS tDS tDH
tWPH
55h Data
10h
In Progress Complete
tBUSY
tRB
RY/BY
tVCS
VCC
NOTES: SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").
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Fig 5. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 10H Address 555H
Data Poll from system YES
No
DATA = FFh ?
YES
Auto Erase Completed
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Fig 6. AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Erase Command Sequence(last two cycle)
tWC tAS
Read Status Data
Address
2AAh
Sector Address 0
tAH
Sector Address 1
Sector Address n
VA
VA
CE
tCH tGHWL
OE
tBAL tWHWH2
tWP
WE
tCS tDS tDH
tWPH
55h Data
30h
30h
30h
In Progress Complete
tBUSY
tRB
RY/BY
tVCS
VCC
NOTES: SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").
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Fig 7. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 30H Sector Address
Last Sector to Erase ?
NO
YES Data Poll from System
NO Data=FFh? YES
Auto Sector Erase Completed
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Fig 8. ERASE SUSPEND/RESUME FLOWCHART
START
Write Data B0H
NO Toggle Bit checking Q6 not toggled YES Read Array or Program
ERASE SUSPEND
Reading or Programming End YES Write Data 30H
NO
ERASE RESUME Continue Erase
Another Erase Suspend ? YES
NO
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Fig 9. AUTOMATIC PROGRAM TIMING WAVEFORMS
Program Command Sequence(last two cycle)
tWC tAS
Read Status Data (last two cycle)
Address
555h
PA
tAH
PA
PA
CE
tCH tGHWL
OE
tWP
tWHWH1
WE
tCS tDS tDH
tWPH
A0h Data
PD
Status
DOUT
tBUSY
tRB
RY/BY
tVCS
VCC
NOTES: 1.PA=Program Address, PD=Program Data, DOUT is the true data the program address
Fig 10. Accelerated Program Timing Diagram
(11.5V ~ 12.5V) VHH
WP/ACC
VIL or VIH VIL or VIH
tVHH
tVHH
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Fig 11. CE CONTROLLED WRITE TIMING WAVEFORM
PA for program SA for sector erase 555 for chip erase
555 for program 2AA for erase
Data Polling Address
tWC tWH tAS tAH
PA
WE
tGHEL
OE
tCP tWHWH1 or 2
CE
tWS tDS tDH
tCPH tBUSY
Q7 Data
tRH A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase
DOUT
RESET
RY/BY
NOTES: 1. PA=Program Address, PD=Program Data, DOUT=Data Out, Q7=complement of data written to device. 2. Figure indicates the last two bus cycles of the command sequence.
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Fig 12. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data A0H Address 555H
Write Program Data/Address
Increment Address
Data Poll from system
No Verify Data OK ?
YES
No Last Address ?
YES
Auto Program Completed
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SECTOR GROUP PROTECT/CHIP UNPROTECT Fig 13. Sector Group Protect/Chip Unprotect Waveform (RESET Control)
VID VIH
RESET
SA, A6 A1, A0
Valid (note2)
Valid (note2)
Valid (note2)
Sector Group Protect or Chip Unprotect Data
1us
Verify 40h Status
60h
60h
Sector Group Protect: 150us Chip Unprotect: 15ms
CE
WE
OE
Note: 1. For sector group protect A6=0, A1=1, A0=0 ; for chip unprotect A6=1, A1=1, A0=0
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Fig 14. IN-SYSTEM SECTOR GROUP PROTECT/CHIP UNPROTECT ALGORITHMS WITH RESET=VID
START START PLSCNT=1 Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address
PLSCNT=1
RESET=VID
RESET=VID
Wait 1us
Wait 1us
Temporary Sector Unprotect Mode
No
First Write Cycle=60h? Yes Set up sector address No Sector Protect: Write 60h to sector address with A6=0, A1=1, A0=0 Yes First Write Cycle=60h? No Temporary Sector Unprotect Mode
All sectors protected? Yes Set up first sector address
Wait 150us
Verify Sector Protect: Write 40h to sector address with A6=0, A1=1, A0=0 Increment PLSCNT Read from sector address with A6=0, A1=1, A0=0 No
Reset PLSCNT=1
Chip Unprotect: Write 60h to sector address with A6=1, A1=1, A0=0
Wait 15ms
Increment PLSCNT No PLSCNT=25? Data=01h?
Verify Sector Unprotect: Write 40h to sector address with A6=1, A1=1, A0=0 Read from sector address with A6=1, A1=1, A0=0
Yes Device failed
Yes No Protect another sector? Yes No PLSCNT=1000?
Reset PLSCNT=1 Data=00h?
Sector Protect Algorithm
No Remove VID from RESET Yes Device failed Write reset command Last sector verified? No Yes
Sector Protect complete
Chip Unprotect Algorithm
Yes Remove VID from RESET
Write reset command
Chip Unprotect complete
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Table 7. TEMPORARY SECTOR GROUP UNPROTECT
Parameter Std. Description tVIDR tRSP Note: Not 100% tested VID Rise and Fall Time (See Note) RESET Setup Time for Temporary Sector Unprotect Test Setup All Speed Options Unit Min Min 500 4 ns us
Fig 15. TEMPORARY SECTOR GROUP UNPROTECT WAVEFORMS
12V
RESET
0 or 3V VIL or VIH
tVIDR
tVIDR
Program or Erase Command Sequence
CE
WE
tRSP
RY/BY
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Fig 16. TEMPORARY SECTOR GROUP UNPROTECT FLOWCHART
Start
RESET = VID (Note 1) Perform Erase or Program Operation Operation Completed RESET = VIH Temporary Sector Unprotect Completed(Note 2)
Note : 1. All protected sectors are temporary unprotected. VID=11.5V~12.5V. (if WP/ACC=VIL, outermost boot sectors will remain protected) 2. All previously protected sectors are protected again.
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Fig 17. SILICON ID READ TIMING WAVEFORM
VCC
3V VID VIH VIL
VIH VIL tACC tACC
ADD A9
ADD A0 A1
VIH VIL
VIH
ADD
VIL
CE
VIH VIL
WE
VIH VIL
tCE
OE
VIH VIL
tOE tDF tOH tOH
VIH
DATA Q0-Q7
DATA OUT
VIL
DATA OUT A7H (TOP boot) A8H (Bottom boot)
C2H
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WRITE OPERATION STATUS Fig 18. DATA POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)
tRC
Address
tACC tCE
VA
VA
CE
tCH tOE
OE
tOEH tDF
WE
tOH
Q7 Q0-Q6
tBUSY
Status Data
Complement
True
Valid Data
High Z
Status Data
Status Data
True
Valid Data
High Z
RY/BY
NOTES: VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data read cycle.
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Fig 19. Data Polling Algorithm
START
Read Q7~Q0 Add. = VA (1)
Q7 = Data ?
Yes
No
No
Q5 = 1 ?
Yes Read Q7~Q0 Add. = VA
Yes Q7 = Data ? (2) No
FAIL
PASS
Notes: 1. VA=valid address for programming or erasure. 2. Q7 should be rechecked even Q5="1" because Q7 may change simultaneously with Q5.
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Fig 20. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)
tRC
Address
VA
tACC tCE
VA
VA
VA
CE
tCH tOE
OE
tOEH tDF
WE
tOH
Q6/Q2
tBUSY
Valid Status (first read)
Valid Status (second read)
Valid Data (stops toggling)
Valid Data
RY/BY
NOTES: VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read cycle, and array data read cycle.
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Fig 21. Toggle Bit Algorithm
START
Read Q7~Q0
Read Q7~Q0
(Note 1)
Toggle Bit Q6 =Toggle? YES
NO
NO Q5=1?
YES Read Q7~Q0 Twice (Note 1,2)
Toggle Bit Q6= Toggle? YES Program/Erase Operation Not Complete, Write Reset Command
Program/Erase Operation Complete
Note: 1. Read toggle bit twice to determine whether or not it is toggling. 2. Recheck toggle bit because it may stop toggling as Q5 changes to "1".
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Fig 22. Q6 versus Q2
Enter Embedded Erasing Erase Suspend Erase Erase Suspend Read Enter Erase Suspend Program Erase Suspend Program Erase Suspend Read Erase Resume Erase Erase Complete
WE
Q6
Q2
NOTES: The system can use OE or CE to toggle Q2/Q6, Q2 toggles only when read at an address within an erase-suspended
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AC CHARACTERISTICS WORD/BYTE CONFIGURATION (BYTE)
Parameter JEDEC Std tELFL/tELFH tFLQZ tFHQV CE to BYTE Switching Low or High BYTE Switching Low to Output HIGH Z BYTE Switching High to Output Active Max Max Min 25 70 Description Speed Options -70 5 30 90 -90 ns ns ns Unit
Figure 23. BYTE TIMING WAVEFORM FOR READ OPERATIONS (BYTE switching from byte mode to word mode)
CE
OE
tELFH
BYTE
Q0~Q14
DOUT (Q0-Q7)
DOUT (Q0-Q14)
Q15/A-1
VA tFHQV
DOUT (Q15)
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ERASE AND PROGRAMMING PERFORMANCE(1)
LIMITS PARAMETER Sector Erase Time Chip Erase Time Byte Programming Time Word Program Time Chip Programming Time Byte Mode Word Mode Accelerated Byte/Word Program Time Erase/Program Cycles Note: 100,000 MIN. TYP.(2) 0.9 35 9 11 36 24 7 MAX. 15 50 300 360 108 72 210 UNITS sec sec us us sec sec us Cycles
1.Not 100% Tested, Excludes external system level over head. 2.Typical values measured at 25° C,3.3V.
LATCH-UP CHARACTERISTICS
MIN. Input Voltage with respect to GND on all pins except I/O pins Input Voltage with respect to GND on all I/O pins VCC Current Includes all pins except Vcc. Test conditions: Vcc = 3.0V, one pin at a time. -1.0V -1.0V -100mA MAX. 12.5V Vcc + 1.0V +100mA
TSOP PIN CAPACITANCE
Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Set VIN=0 VOUT=0 VIN=0 TYP 6 8.5 7.5 MAX 7.5 12 9 UNIT pF pF pF
Notes: 1. Sampled, not 100% tested. 2. Test conditions TA=25° C, f=1.0MHz
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ORDERING INFORMATION PLASTIC PACKAGE
PART NO. MX29LV320ATTC-70 MX29LV320ABTC-70 MX29LV320ATTI-70 MX29LV320ABTI-70 MX29LV320ATTC-90 MX29LV320ABTC-90 MX29LV320ATTI-90 MX29LV320ABTI-90 MX29LV320ATXBC-70 MX29LV320ABXBC-70 MX29LV320ATXEC-70 MX29LV320ABXEC-70 MX29LV320ATXBI-70 MX29LV320ABXBI-70 MX29LV320ATXEI-70 MX29LV320ABXEI-70 MX29LV320ATXBC-90 MX29LV320ABXBC-90 MX29LV320ATXEC-90 MX29LV320ABXEC-90 MX29LV320ATXBI-90 MX29LV320ABXBI-90 MX29LV320ATXEI-90 MX29LV320ABXEI-90 ACCESS TIME (ns) 70 70 70 70 90 90 90 90 70 70 70 70 70 70 70 70 90 90 90 90 90 90 90 90 Ball Pitch/ Ball Size 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.4mm 0.8mm/0.4mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.4mm 0.8mm/0.4mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.4mm 0.8mm/0.4mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.4mm 0.8mm/0.4mm 48 Pin TSOP 48 Pin TSOP 48 Pin TSOP 48 Pin TSOP 48 Pin TSOP 48 Pin TSOP 48 Pin TSOP 48 Pin TSOP 48-Ball CSP 48-Ball CSP 48-Ball CSP 48-Ball CSP 48-Ball CSP 48-Ball CSP 48-Ball CSP 48-Ball CSP 48-Ball CSP 48-Ball CSP 48-Ball CSP 48-Ball CSP 48-Ball CSP 48-Ball CSP 48-Ball CSP 48-Ball CSP PACKAGE Remark
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PART NO. MX29LV320ATTC-70G MX29LV320ABTC-70G MX29LV320ATTI-70G MX29LV320ABTI-70G MX29LV320ATTC-90G MX29LV320ABTC-90G MX29LV320ATTI-90G MX29LV320ABTI-90G MX29LV320ATXBC-70G MX29LV320ABXBC-70G MX29LV320ATXEC-70G MX29LV320ABXEC-70G MX29LV320ATXBI-70G MX29LV320ABXBI-70G MX29LV320ATXEI-70G MX29LV320ABXEI-70G MX29LV320ATXBC-90G MX29LV320ABXBC-90G MX29LV320ATXEC-90G MX29LV320ABXEC-90G MX29LV320ATXBI-90G MX29LV320ABXBI-90G MX29LV320ATXEI-90G MX29LV320ABXEI-90G ACCESS TIME (ns) 70 70 70 70 90 90 90 90 70 70 70 70 70 70 70 70 90 90 90 90 90 90 90 90 Ball Pitch/ Ball Size 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.4mm 0.8mm/0.4mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.4mm 0.8mm/0.4mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.4mm 0.8mm/0.4mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.4mm 0.8mm/0.4mm 48 Pin TSOP 48 Pin TSOP 48 Pin TSOP 48 Pin TSOP 48 Pin TSOP 48 Pin TSOP 48 Pin TSOP 48 Pin TSOP 48-Ball CSP 48-Ball CSP 48-Ball CSP 48-Ball CSP 48-Ball CSP 48-Ball CSP 48-Ball CSP 48-Ball CSP 48-Ball CSP 48-Ball CSP 48-Ball CSP 48-Ball CSP 48-Ball CSP 48-Ball CSP 48-Ball CSP 48-Ball CSP Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free PACKAGE Remark
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PACKAGE INFORMATION
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REVISION HISTORY
Revision No. Description 1.0 1. Removed "Advanced Information" on page 1 1.1 1. To removed data retention information Page P1 P53 Date JAN/30/2004 MAY/28/2004
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MACRONIX INTERNATIONAL CO., LTD.
Headquarters:
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