MX30LF2G18AC-XKI

MX30LF2G18AC MX30LF4G18AC 3V, 2G/4G-bit NAND Flash Memory MX30LFxG18AC P/N: PM2129 REV. 1.4, January. 20, 2017 1 MX30LF2G18AC MX30LF4G18AC Contents 1. FEATURES........................................................................................................................................6 2. GENERAL DESCRIPTIONS..............................................................................................................7 Figure 1. Logic Diagram.......................................................................................................................... 7 2-1. ORDERING INFORMATION....................................................................................................8 3. PIN CONFIGURATIONS....................................................................................................................9 3-1. PIN DESCRIPTIONS..............................................................................................................11 4. BLOCK DIAGRAM...........................................................................................................................13 5. SCHEMATIC CELL LAYOUT AND ADDRESS ASSIGNMENT.......................................................14 Table 1. Address Allocation................................................................................................................... 14 6. DEVICE OPERATIONS....................................................................................................................15 6-1. Address Input/Command Input/Data Input.........................................................................15 Figure 2. AC Waveforms for Command / Address / Data Latch Timing................................................ 15 Figure 3. AC Waveforms for Address Input Cycle................................................................................. 15 Figure 4. AC Waveforms for Command Input Cycle............................................................................. 16 Figure 5. AC Waveforms for Data Input Cycle...................................................................................... 16 6-2. Page Read.............................................................................................................................17 Figure 6. AC Waveforms for Read Cycle.............................................................................................. 17 Figure 7. AC Waveforms for Read Operation (Intercepted by CE#)..................................................... 18 Figure 8. AC Waveforms for Read Operation (with CE# Don't Care).................................................... 19 Figure 9-1. AC Waveforms for Sequential Data Out Cycle (After Read)............................................... 19 Figure 9-2. AC Waveforms for Sequential Data Out Cycle (After Read) - EDO Mode.......................... 20 Figure 10. AC Waveforms for Random Data Output............................................................................. 21 6-3. Cache Read Sequential........................................................................................................22 Figure 11-1. AC Waveforms for Cache Read Sequential...................................................................... 23 6-4. Cache Read Random............................................................................................................24 Figure 11-2. AC Waveforms for Cache Read Random......................................................................... 25 6-5. Page Program.......................................................................................................................26 Figure 12. AC Waveforms for Program Operation after Command 80H............................................... 26 Figure 13. AC Waveforms for Random Data In (For Page Program).................................................... 27 Figure 14. AC Waveforms for Program Operation with CE# Don't Care............................................... 28 P/N: PM2129 REV. 1.4, January. 20, 2017 2 MX30LF2G18AC MX30LF4G18AC 6-6. Cache Program.....................................................................................................................29 Figure 15-1. AC Waveforms for Cache Program ................................................................................. 30 Figure 15-2. AC Waveforms for Sequence of Cache Program ............................................................ 31 6-7. Block Erase...........................................................................................................................32 Figure 16. AC Waveforms for Erase Operation..................................................................................... 32 6-8. ID Read..................................................................................................................................33 Table 2. ID Codes Read Out by ID Read Command 90H..................................................................... 33 Table 3. The Definition of Byte2~Byte4 of ID Table............................................................................... 34 Figure 17-1. AC Waveforms for ID Read Operation.............................................................................. 35 Figure 17-2. AC Waveforms for ID Read (ONFI Identifier) Operation................................................... 35 6-9. Status Read...........................................................................................................................36 Table 4. Status Output........................................................................................................................... 36 Figure 18. Bit Assignment (HEX Data).................................................................................................. 37 Figure 19. AC Waveforms for Status Read Operation.......................................................................... 37 6-10. Status Enhance Read...........................................................................................................38 6-11. Block Protection Status Read.............................................................................................38 Figure 20. AC Waveforms for Status Enhance Operation..................................................................... 38 Table 5. Block-Protection Status Output............................................................................................... 39 Table 6. Address Cycle Definition of Block............................................................................................ 39 Figure 21. AC Waveforms for Block Protection Status Read................................................................ 39 6-12. Reset......................................................................................................................................40 Figure 22. AC waveforms for Reset Operation..................................................................................... 40 6-13. Parameter Page Read (ONFI)...............................................................................................41 Figure 23. AC waveforms for Parameter Page Read (ONFI) Operation .............................................. 41 Figure 24. AC Waveforms for Parameter Page Read (ONFI) Random Operation (For 05h-E0h)........ 42 Table 7. Parameter Page (ONFI).......................................................................................................... 43 6-14. Unique ID Read (ONFI).........................................................................................................45 Figure 25. AC waveforms for Unique ID Read Operation..................................................................... 45 Figure 26. AC waveforms for Unique ID Read Operation (For 05h-E0h).............................................. 46 6-15. Feature Set Operation (ONFI)..............................................................................................47 Table 8-1. Definition of Feature Address............................................................................................... 47 Table 8-2. Sub-Feature Parameter Table of Feature Address - 90h (Array Operation Mode)............... 47 Table 8-3. Sub-Feature Parameter Table of Feature Address - A0h (Block Protection Operation) (note 1)..........47 6-15-1. Set Feature (ONFI).................................................................................................................. 48 Figure 27. AC Waveforms for Set Feature (ONFI) Operation .............................................................. 48 P/N: PM2129 REV. 1.4, January. 20, 2017 3 MX30LF2G18AC MX30LF4G18AC 6-15-2. Get Feature (ONFI).................................................................................................................. 49 Figure 28. AC Waveforms for Get Feature (ONFI) Operation............................................................... 49 6-15-3. Secure OTP (One-Time-Programmable) Feature................................................................. 50 Figure 29. AC Waveforms for OTP Data Read..................................................................................... 50 Figure 30. AC Waveforms for OTP Data Read with Random Data Output........................................... 51 Figure 31. AC Waveforms for OTP Data Program................................................................................ 52 Figure 32. AC Waveforms for OTP Data Program with Random Data Input......................................... 53 Figure 33. AC Waveforms for OTP Protection Operation ..................................................................... 54 6-15-4. Block Protection..................................................................................................................... 55 Table 9. Definition of Protection Bits..................................................................................................... 55 Figure 34. PT Pin and Block Protection Mode Operation..................................................................... 56 6-16. Two-Plane Operations..........................................................................................................57 6-17. Two-plane Program (ONFI & Traditional)and Two-plane Cache Program (ONFI & Traditional).......................................................................................................................................57 6-18. Two-plane Block Erase (ONFI & Traditional)......................................................................57 Figure 35-1. AC Waveforms for Two-plane Program (ONFI)................................................................ 58 Figure 35-2. AC Waveforms for Page Program Random Data Two-plane (ONFI)................................ 59 Figure 36. AC Waveforms for Two-plane Cache Program (ONFI)........................................................ 60 Figure 37. AC Waveforms for Two-plane Erase (ONFI)........................................................................ 61 Figure 38. AC waveforms for Two-plane Program (Traditional)............................................................ 61 Figure 39. AC waveforms for Two-plane Cache Program (Traditional)................................................. 61 Figure 40. AC waveforms for Two-plane Erase (Traditional)................................................................. 62 Figure 41. Maximum Negative Overshoot Waveform........................................................................... 63 7. PARAMETERS.................................................................................................................................63 7-1. ABSOLUTE MAXIMUM RATINGS........................................................................................63 Figure 42. Maximum Positive Overshoot Waveform............................................................................. 63 Table 10. Operating Range................................................................................................................... 64 Table 11. DC Characteristics................................................................................................................. 64 Table 12. Capacitance........................................................................................................................... 65 Table 13. AC Testing Conditions........................................................................................................... 65 Table 14. Program and Erase Characteristics....................................................................................... 65 Table 15. AC Characteristics................................................................................................................. 66 8. OPERATION MODES: LOGIC AND COMMAND TABLES.............................................................67 Table 16. Logic Table............................................................................................................................ 67 P/N: PM2129 REV. 1.4, January. 20, 2017 4 MX30LF2G18AC MX30LF4G18AC Table 17-1. HEX Command Table......................................................................................................... 68 Table 17-2. Two-plane Command Set................................................................................................... 68 8-1. R/B#: Termination for The Ready/Busy# Pin (R/B#).........................................................69 Figure 43. R/B# Pin Timing Information................................................................................................ 70 8-2. Power On/Off Sequence.......................................................................................................71 Figure 44. Power On/Off Sequence ..................................................................................................... 71 8-2-1. WP# Signal .............................................................................................................................. 72 Figure 45-1. Enable Programming of WP# Signal................................................................................ 72 Figure 45-2. Disable Programming of WP# Signal .................................................................................. 72 Figure 45-3. Enable Erasing of WP# Signal.......................................................................................... 72 Figure 45-4. Disable Erasing of WP# Signal......................................................................................... 72 9. SOFTWARE ALGORITHM...............................................................................................................73 9-1. Invalid Blocks (Bad Blocks) ................................................................................................73 Figure 46. Bad Blocks........................................................................................................................... 73 Table 18. Valid Blocks........................................................................................................................... 73 9-2. Bad Block Test Flow.............................................................................................................74 Figure 47. Bad Block Test Flow............................................................................................................. 74 9-3. Failure Phenomena for Read/Program/Erase Operations................................................74 Table 19. Failure Modes........................................................................................................................ 74 9-4. Program.................................................................................................................................75 Figure 48. Failure Modes...................................................................................................................... 75 Figure 49. Program Flow Chart............................................................................................................. 75 9-5. Erase......................................................................................................................................75 Figure 50. Erase Flow Chart................................................................................................................. 76 Figure 51. Read Flow Chart.................................................................................................................. 76 10. PACKAGE INFORMATION..............................................................................................................77 11. REVISION HISTORY .......................................................................................................................79 P/N: PM2129 REV. 1.4, January. 20, 2017 5 MX30LF2G18AC MX30LF4G18AC 3V, 2Gb/4Gb NAND Flash Memory 1. FEATURES • 2G/4G-bit • Hardware Data Protection: WP# pin SLC NAND Flash - Bus: x8 • Block Protection - Page size: (2048+64) byte, - Block size: (128K+4K) byte, - Plane size: 1024-block/plane x 2 for 2Gb - PT (Protection) pin: active high at power-on, which protects the entire chip. The pin has an internal weak pull down. - Temporary protection/un-protection function (enabling by PT pin) 2048-block/plane x 2 for 4Gb • ONFI 1.0 compliant - Solid protection (enabling by PT pin) • Multiplexed Command/Address/Data • User Redundancy • Device Status Indicators - 64-byte attached to each page - Ready/Busy (R/B#) pin • Fast Read Access - Status Register - Latency of array to register: 25us • Chip Enable Don't Care - Sequential read: 20ns - Simplify System Interface • Cache Read Support • Unique ID Read support (ONFI) • Page Program Operation • Secure OTP support - Page program time: 300us( typ.) • High Reliability • Cache Program Support - Endurance: typical 100K cycles (with 4-bit ECC per (512+16) Byte) • Block Erase Operation - Block erase time: 1ms (typ.) - Data Retention: 10 years • Single Voltage Operation: • Wide Temperature Operating Range - VCC: 2.7 ~ 3.6V -40°C to +85°C • Low Power Dissipation • Package: - Max. 30mA Active current (Read/Program/Erase) 1) 48-TSOP(I) (12mm x 20mm) 2) 63-ball 9mmx11mm VFBGA • Sleep Mode All packaged devices are RoHS Compliant and Halogen-free. - 50uA (Max) standby current P/N: PM2129 REV. 1.4, January. 20, 2017 6 MX30LF2G18AC MX30LF4G18AC 2. GENERAL DESCRIPTIONS The MX30LFxG18AC are 2Gb/4Gb SLC NAND Flash memory device. Its standard NAND Flash features and reliable quality of typical P/E cycles 100K (with host ECC), which makes it most suitable for embedded system code and data storage. The product family requires 4-bit ECC per (512+16)B. The MX30LFxG18AC is typically accessed in pages of 2,112 bytes for read and program operations. The MX30LFxG18AC array is organized as thousands of blocks, which is composed by 64 pages of (2,048+64) byte in two NAND strings structure with 32 serial connected cells in each string. Each page has an additional 64 bytes for ECC and other purposes. The device has an on-chip buffer of 2,112 bytes for data load and access. The Cache Read Operation of the MX30LFxG18AC enables first-byte read-access latency of 25us and sequential read of 20ns and the latency time of next sequential page will be shorten from tR to tRCBSY. The MX30LFxG18AC power consumption is 30mA during all modes of operations (Read/Program/Erase), and 50uA in standby mode. Figure 1. Logic Diagram ALE CLE IO7 - IO0 CE# RE# WE# 2Gb 4Gb WP# R/B# PT P/N: PM2129 REV. 1.4, January. 20, 2017 7 MX30LF2G18AC MX30LF4G18AC 2-1. ORDERING INFORMATION Part Name Description MX 30 L F 2G 18A C - T I xx RESERVE OPERATING TEMPERATURE: I: Industrial (-40°C to 85°C) PACKAGE TYPE: T: 48TSOP XK: 0.8mm Ball Pitch, 0.45mm Ball Size and 1.0mm height of VFBGA Package: RoHS Compliant & Halogen-free GENERATION: C OPTION CODE: 18A=4-bit ECC Requirement with standard feature, x8, mode A Mode A: Number of die Number of CE# = 1, Number of R/B# = 1 DENSITY: 2G=2G-bit 4G=4G-bit CLASSIFICATION: F = SLC + Large Block VOLTAGE: L = 2.7V to 3.6V TYPE: 30 = NAND Flash BRAND: MX Please contact our regional sales for the latest product selection and available form factors. Part Number Density Organization VCC Range Package Temperature Grade MX30LF2G18AC-TI 2Gb x8 3V 48-TSOP Industrial MX30LF2G18AC-XKI 2Gb x8 3V 63-VFBGA Industrial MX30LF4G18AC-TI 4Gb x8 3V 48-TSOP Industrial MX30LF4G18AC-XKI 4Gb x8 3V 63-VFBGA Industrial P/N: PM2129 REV. 1.4, January. 20, 2017 8 MX30LF2G18AC MX30LF4G18AC 3. PIN CONFIGURATIONS 48-TSOP NC NC NC NC NC NC R/B# RE# CE# NC NC VCC VSS NC NC CLE ALE WE# WP# NC NC NC NC NC 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 VSS1 NC NC NC IO7 IO6 IO5 IO4 NC VCC1 PT VCC VSS NC VCC1 NC IO3 IO2 IO1 IO0 NC NC NC VSS1 Note 1. These pins might not be connected internally. However, it is recommended to connect these pins to power(or ground) as designated for ONFI compatibility. P/N: PM2129 REV. 1.4, January. 20, 2017 9 MX30LF2G18AC MX30LF4G18AC 63-ball 9mmx11mm VFBGA 1 2 A NC NC B NC 3 4 5 6 8 7 C WP# ALE Vss CE# WE# R/B# D Vcc 1 RE# CLE NC NC NC E NC NC NC NC NC NC F NC NC NC NC Vss 1 NC G NC Vcc PT NC NC NC H NC I/O0 NC NC NC Vcc J NC IO1 NC Vcc IO5 IO7 K Vss IO2 IO3 IO4 I/O6 Vss 1 9 10 NC NC NC NC L NC NC NC NC M NC NC NC NC Note 1. These pins might not be connected internally; however, it is recommended to connect these pins to power (or ground) as designated for ONFI compatibility. P/N: PM2129 REV. 1.4, January. 20, 2017 10 MX30LF2G18AC MX30LF4G18AC 3-1. PIN DESCRIPTIONS SYMBOL IO7 - IO0 PIN NAME Data I/O port CE# Chip Enable (Active Low) RE# Read Enable (Active Low) WE# Write Enable (Active Low) CLE Command Latch Enable ALE Address Latch Enable WP# R/B# Write Protect (Active Low) PT (Protection) pin connecting to high for entire chip protected and enabling the Block Protection. A weak pull-down internally. Ready/Busy (Open Drain) VSS Ground VCC Power Supply for Device Operation PT NC Not Connected Internally P/N: PM2129 REV. 1.4, January. 20, 2017 11 MX30LF2G18AC MX30LF4G18AC PIN FUNCTIONS COMMAND LATCH ENABLE: CLE The MX30LFxG18AC device is a sequential access memory that utilizes multiplexing input of Command/Address/Data. The CLE controls the command input. When the CLE goes high, the command data is latched at the rising edge of the WE#. I/O PORT: IO7 - IO0 ADDRESS LATCH ENABLE: ALE The IO7 to IO0 pins are for address/command input and data output to/from the device. The ALE controls the address input. When the ALE goes high, the address is latched at the rising edge of WE#. CHIP ENABLE: CE# The device goes into low-power Standby Mode when CE# goes high during a read operation and not at busy stage. WRITE PROTECT: WP# The WP# signal keeps low and then the memory will not accept the program/erase operation. It is recommended to keep WP# pin low during power on/off sequence. Please refer to the waveform of "Power On/Off Sequence". The CE# goes low to enable the device to be ready for standard operation. When the CE# goes high, the device is deselected. However, when the device is at busy stage, the device will not go to standby mode when CE# pin goes high. READY/Busy: R/B# READ ENABLE: RE# The R/B# is an open-drain output pin. The R/B# outputs the ready/busy status of read/program/ erase operation of the device. When the R/B# is at low, the device is busy for read or program or erase operation. When the R/B# is at high, the read/ program/erase operation is finished. The RE# (Read Enable) allows the data to be output by a tREA time after the falling edge of RE#. The internal address counter is automatically increased by one at the falling edge of RE#. Please refer to Section 8-1 for details. WRITE ENABLE: WE# When the WE# goes low, the address/data/ command are latched at the rising edge of WE#. PT: Protection When the PT pin is high at power on, the whole chip is protected even the WP# is at high; the unprotection procedure (through BP bits setting) is necessary before any program/erase operation. When the PT pin is connected to low or floating, the function of block protection is disabled. P/N: PM2129 REV. 1.4, January. 20, 2017 12 MX30LF2G18AC MX30LF4G18AC CE# High Voltage Circuit WE# WP# RE# PT IO Port CLE ALE Control Logic X-DEC 4. BLOCK DIAGRAM Memory Array (Two planes) Page Buffer ADDRESS COUNTER Y-DEC R/B# IO[7:0] Data Buffer P/N: PM2129 REV. 1.4, January. 20, 2017 13 MX30LF2G18AC MX30LF4G18AC 5. SCHEMATIC CELL LAYOUT AND ADDRESS ASSIGNMENT MX30LFxG18AC NAND device is divided into two planes, which is composed by 64 pages of (2,048+64)-byte in two NAND strings structure with 32 serial connected cells in each string. Each page has an additional 64 bytes for ECC and other purposes. The device has an on-chip buffer of 2,112 bytes for data load and access. Each 2K-Byte page has the two area, one is the main area which is 2048-bytes and the other is spare area which is 64-byte. There are five address cycles for the address allocation, please refer to the table below. Table 1. Address Allocation Addresses Column address - 1st cycle Column address - 2nd cycle Row address - 3rd cycle Row address - 4th cycle Row address - 5th cycle IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 A7 L A19 A27 L A6 L A181 A26 L A5 L A17 A25 L A4 L A16 A24 L A3 A11 A15 A23 L A2 A10 A14 A22 L A1 A9 A13 A21 A292 A0 A8 A12 A20 A28 Notes: 1. A18 is the plane selection. 2. A29 is for 4Gb, "L" (Low) is for 2Gb. P/N: PM2129 REV. 1.4, January. 20, 2017 14 MX30LF2G18AC MX30LF4G18AC 6. DEVICE OPERATIONS 6-1. Address Input/Command Input/Data Input Address input bus operation is for address input to select the memory address. The command input bus operation is for giving command to the memory. The data input bus is for data input to the memory device. Figure 2. AC Waveforms for Command / Address / Data Latch Timing CLE ALE CE# tCS / / tCLS / tALS tCH tCLH tWP WE# tDS tDH IO[7:0] Figure 3. AC Waveforms for Address Input Cycle tCLS CLE tWC tWC tWC tWC CE# tWP tWH tWP tWH tWP tWH tWP tWH tWP WE# tALS tALH ALE tDS IO[7:0] tDH 1st Address Cycle tDS tDH 2nd Address Cycle P/N: PM2129 tDS tDH 3rd Address Cycle tDS tDH 4th Address Cycle tDS tDH 5th Address Cycle REV. 1.4, January. 20, 2017 15 MX30LF2G18AC MX30LF4G18AC Figure 4. AC Waveforms for Command Input Cycle CLE tCLS tCLH tCS tCH CE# tWP WE# tALS tALH ALE tDS tDH IO[7:0] Figure 5. AC Waveforms for Data Input Cycle tCLH CLE tCH CE# tWC tWP tWH tWP tWH tWP tWP WE# ALE tALS tDS IO[7:0] tDH Din0 tDS tDH Din1 P/N: PM2129 tDS tDH Din2 tDS tDH DinN REV. 1.4, January. 20, 2017 16 MX30LF2G18AC MX30LF4G18AC 6-2. Page Read The MX30LFxG18AC array is accessed in Page of 2,112 bytes. External reads begins after the R/B# pin goes to READY. The Read operation may also be initiated by writing the 00h command and giving the address (column and row address) and being confirmed by the 30h command, the MX30LFxG18AC begins the internal read operation and the chip enters busy state. The data can be read out in sequence after the chip is ready. Refer to the waveform for Read Operation as below. If the host side uses a sequential access time (tRC) of less than 30ns, the data can be latched on the next falling edge of RE# as the waveform of EDO mode (Figure 9-2). To access the data in the same page randomly, a command of 05h may be written and only column address following and then confirmed by E0h command. Figure 6. AC Waveforms for Read Cycle CLE tCLS tCLS tCLH tCLH tCS CE# tWC WE# tALS tAR tALH tALH ALE tRR tR tRC tOH RE# tWB tDS IO[7:0] 00h tDH tDS tDH 1st Address Cycle tDS tDH 2nd Address Cycle tDS tDH 3rd Address Cycle tDS tDH 4th Address Cycle tDS tDH 5th Address Cycle tREA tDS tDH Dout 30h Dout R/B# Busy P/N: PM2129 REV. 1.4, January. 20, 2017 17 MX30LF2G18AC MX30LF4G18AC Figure 7. AC Waveforms for Read Operation (Intercepted by CE#) CLE tCHZ CE# WE# tAR ALE tOH tRC RE# tRR tR tWB IO[7:0] 00h 1st Address Cycle 2nd Address Cycle 3rd Address Cycle 4th Address Cycle 5th Address Cycle 30h Dout 0 Dout 1 Dout 2 Dout 3 R/B# Busy P/N: PM2129 REV. 1.4, January. 20, 2017 18 MX30LF2G18AC MX30LF4G18AC Figure 8. AC Waveforms for Read Operation (with CE# Don't Care) CLE CE# Don’t Care CE# WE# ALE RE# IO[7:0] Start Addr (5 Cycles) 00h Data Output (Sequential) 30h R/B# Busy Note: The CE# "Don't Care" feature may simplify the system interface, which allows controller to directly download the code from flash device, and the CE# transitions will not stop the read operation during the latency time. Figure 9-1. AC Waveforms for Sequential Data Out Cycle (After Read) t CEA CE# tRC tRP RE# t REH t RP t RHZ tREA IO[7:0] tOH Dout0 t REH t RP tRHZ t REA tOH Dout1 t REA t RP tCOH t CHZ t RHZ tRHZ t OH tOH Dout2 DoutN tRR R/B# P/N: PM2129 REV. 1.4, January. 20, 2017 19 MX30LF2G18AC MX30LF4G18AC Figure 9-2. AC Waveforms for Sequential Data Out Cycle (After Read) - EDO Mode t CEA CE# tRC tRP RE# t REH tRHZ t REA IO[7:0] t RP tRLOH t Dout0 t REH tRHZ REA t RP tRLOH t Dout1 t RP t REH t CHZ t COH tRHZ REA t RLOH Dout2 tOH DoutN tRR R/B# P/N: PM2129 REV. 1.4, January. 20, 2017 20 MX30LF2G18AC MX30LF4G18AC Figure 10. AC Waveforms for Random Data Output A tCLR CLE CE# WE# tAR ALE tRC RE# tRHW tRR tR tWB IO[7:0] 00h 1st Address Cycle 2nd Address Cycle 3rd Address Cycle 4th Address Cycle 5th Address Cycle Dout M 30h Dout M+1 05h R/B# CLE Busy A CE# WE# tWHR ALE RE# tREA IO[7:0] 05h 1st Address Cycle 2nd Address Cycle E0h Dout N Dout N+1 R/B# Repeat if needed P/N: PM2129 REV. 1.4, January. 20, 2017 21 MX30LF2G18AC MX30LF4G18AC 6-3. Cache Read Sequential The cache read sequential operation is for throughput enhancement by using the internal cache buffer. It allows the consecutive pages to be read-out without giving next page address, which reduces the latency time from tR to tRCBSY between pages or blocks. While the data is read out on one page, the data of next page can be read into the cache buffer. After writing the 00h command, the column and row address should be given for the start page selection, and followed by the 30h command for address confirmation. After that, the CACHE READ operation starts after a latency time tR and following a 31h command with the latency time of tRCBSY, the data can be readout sequentially from 1st column address (A[11:0]=00h) without giving next page address input. The 31h command is necessary to confirm the next cache read sequential operation and followed by a tRCBSY latency time before next page data is necessary. The CACHE READ SEQUENTIAL command is also valid for the consecutive page cross block. The random data out (05h-E0h) command set is available to change the column address of the current page data in the cache register. The user can check the chip status by the following method: - R/B# pin ("0" means the data is not ready, "1" means the user can read the data) - Status Register (SR[6] functions the same as R/B# pin, SR[5] indicates the internal chip operation, "0" means the chip is in internal operation and "1" means the chip is idle.) Status Register can be checked after the Read Status command (70h) is issued. Command 00h should be given to return to the cache read sequential operation. To confirm the last page to be read-out during the cache read sequential operation, a 3Fh command is needed to replace the 31h command prior to the last data-out. P/N: PM2129 REV. 1.4, January. 20, 2017 22 MX30LF2G18AC MX30LF4G18AC Figure 11-1. AC Waveforms for Cache Read Sequential A tCLR CLE CE# WE# tAR ALE tRC RE# tRR tRCBSY tR tWB IO[7:0] 00h 1st Address Cycle 3rd Address Cycle 2nd Address Cycle 4th Address Cycle 5th Address Cycle tWB Page 1 Dout 0 31h 30h Page 1 Dout 1 Page 1 Dout 2111 R/B# Busy Busy CLE A tCLR tCLR tAR tAR CE# WE# ALE tRC tRC RE# tRR tRR tRCBSY tRCBSY tWB tWB IO[7:0] Page 1 Dout 2111 Page 2 Dout 0 31h Page 2 Page 2 Dout 1 Dout 2111 Page 3 Dout 0 3Fh Page 3 Dout 1 Page 3 Dout 2111 R/B# Busy Busy P/N: PM2129 REV. 1.4, January. 20, 2017 23 MX30LF2G18AC MX30LF4G18AC 6-4. Cache Read Random The main difference from the Cache Read Sequential operation is the Cache Read Random operation may allow the random page to be read-out with cache operation not just for the consecutive page only. After writing the 00h command, the column and row address should be given for the start page selection, and followed by the 30h command for address confirmation. The column address is ignored in the cache read random operation. And then, the CACHE READ RANDOM operation starts after a latency time tR and following a 00h command with the selected page address and following a 31h command, the data can be read-out after the latency time of tRCBSY. After the previous selected page data out, a new selected page address can be given by writing the 00h-31h command set again. The CACHE READ RANDOM command is also valid for the consecutive page cross block. The random data out (05h-E0h) command set is available to change the column address of the current page data in the cache register. The user can check the chip status by the following method: - R/B# pin ("0" means the data is not ready, "1" means the user can read the data) - Status Register can be checked after the Read Status command (70h) is issued. (SR[6] behaves the same as R/B# pin, SR[5] indicates the internal chip operation, "0" means the chip is in internal operation and "1" means the chip is idle.) Command 00h should be given to return to the cache read operation. To confirm the last page to be read-out during the cache read operation, a 3Fh command is needed to replace the 31h command prior to the last data-out. P/N: PM2129 REV. 1.4, January. 20, 2017 24 MX30LF2G18AC MX30LF4G18AC Figure 11-2. AC Waveforms for Cache Read Random A tCLR CLE CE# WE# tAR ALE tRC RE# tRR tR tWB tWB IO[7:0] 00h 1st Address Cycle 2nd Address 3rd Address Cycle Cycle 4th Address Cycle 5th Address Cycle 1st Address Cycle 00h 30h 2nd Address Cycle 3rd Address Cycle 4th Address Cycle 5th Address Cycle tRCBSY Page n Dout 0 31h Page n Dout 1 Page n Dout 2111 Page m address Page n address R/B# Busy Busy A CLE tCLR CE# WE# tAR ALE tRC RE# tRR tWB IO[7:0] Page n Dout 0 Page n Dout 1 Page n Dout 2111 00h 1st Address Cycle 2nd Address 3rd Address Cycle Cycle 4th Address Cycle 5th Address Cycle tRCBSY Page m Dout 0 31h Page m Dout 1 Page m Dout 2111 Page x address R/B# Busy P/N: PM2129 REV. 1.4, January. 20, 2017 25 MX30LF2G18AC MX30LF4G18AC 6-5. Page Program The memory is programmed by page, which is 2,112 bytes. After Program load command (80h) is issued and the row and column address is given, the data will be loaded into the chip sequentially. Random Data Input command (85h) allows multi-data load in non-sequential address. After data load is complete, program confirm command (10h) is issued to start the page program operation. The page program operation in a block should start from the low address to high address. Partial program in a page is allowed up to 4 times. However, the random data input mode for programming a page is allowed and number of times is not limited. The status of the program completion can be detected by R/B# pin or Status register bit SR[6]. The program result is shown in the chip status bit (SR[0]). SR[0] = 1 indicates the Page Program is not successful and SR[0] = 0 means the program operation is successful. During the Page Program progressing, only the read status register command and reset command are accepted, others are ignored. Figure 12. AC Waveforms for Program Operation after Command 80H CLE tCLS tCLH CE# tCS tWC WE# tALS tWB tALH tALH ALE RE# tDS tDH IO[7:0] 80h tDS/tDH Din 0 - 1st Address Cycle 2nd Address 3rd Address 4th Address 5th Address Cycle Cycle Cycle Cycle Din n 10h 70h Status Output tPROG R/B# P/N: PM2129 REV. 1.4, January. 20, 2017 26 MX30LF2G18AC MX30LF4G18AC Figure 13. AC Waveforms for Random Data In (For Page Program) A CLE CE# tWC tADL WE# ALE RE# IO[7:0] 80h 1st Address 2nd Address 3rd Address 4th Address 5th Address Cycle Cycle Cycle Cycle Cycle Din A Din A+N R/B# A CLE CE# tWC tADL WE# tWB ALE RE# IO[7:0] 85h 1st Address 2nd Address Cycle Cycle Din B+M Din B 70h 10h Status tPROG R/B# Repeat if needed IO0 = 0; Pass IO0 = 1; Fail Note: Random Data In is also supported in cache program. P/N: PM2129 REV. 1.4, January. 20, 2017 27 MX30LF2G18AC MX30LF4G18AC Figure 14. AC Waveforms for Program Operation with CE# Don't Care A CLE CE# WE# ALE IO[7:0] Start Add. (5 Cycles) 80h Data Input A CLE CE# WE# ALE IO[7:0] Data Input Data Input 10h Note: The CE# "Don't Care" feature may simplify the system interface, which allows the controller to directly write data into flash device, and the CE# transitions will not stop the program operation during the latency time. P/N: PM2129 REV. 1.4, January. 20, 2017 28 MX30LF2G18AC MX30LF4G18AC 6-6. Cache Program The cache program feature enhances the program performance by using the cache buffer of 2,112-byte. The serial data can be input to the cache buffer while the previous data stored in the buffer are programming into the memory cell. Cache Program command sequence is almost the same as page program command sequence. Only the Program Confirm command (10h) is replaced by cache Program command (15h). After the Cache Program command (15h) is issued. The user can check the status by the following methods. - R/B# pin - Cache Status Bit (SR[6] = 0 indicates the cache is busy; SR[6] = 1 means the cache is ready). The user can issue another Cache Program Command Sequence after the Cache is ready. The user can always monitor the chip state by Ready/Busy Status Bit (SR[5]). The user can issues either program confirm command (10h) or cache program command (15h) for the last page if the user monitor the chip status by issuing Read Status Command (70h). However, if the user only monitors the R/B# pin, the user needs to issue the program confirm command (10h) for the last page. The user can check the Pass/Fail Status through P/F Status Bit (SR[0]) and Cache P/F Status Bit (SR[1]). SR[1] represents Pass/Fail Status of the previous page. SR[1] is updated when SR[6] change from 0 to 1 or Chip is ready. SR[0] shows the Pass/Fail status of the current page. It is updated when SR[5] change from "0" to "1" or the end of the internal programming. For more details, please refer to the related waveforms. P/N: PM2129 REV. 1.4, January. 20, 2017 29 MX30LF2G18AC MX30LF4G18AC Figure 15-1. AC Waveforms for Cache Program A CLE CE# tADL tWC WE# tWB ALE RE# IO[7:0] 80h 1st Address Cycle 2nd Address Cycle 3rd Address Cycle 4th Address Cycle 5th Address Cycle Din Din 15h tCBSY R/B# Busy A CLE CE# tADL WE# tWB ALE RE# IO[7:0] 80h 1st Address Cycle 2nd Address Cycle 3rd Address Cycle 4th Address Cycle 5th Address Cycle Din Din 70h 10h Status Output tPROG R/B# Note Busy Note: It indicates the last page Input & Program. P/N: PM2129 REV. 1.4, January. 20, 2017 30 MX30LF2G18AC MX30LF4G18AC Figure 15-2. AC Waveforms for Sequence of Cache Program A IO[7:0] 1st Address 2nd Address 3rd Address 4th Address 5th Address Cycle Cycle Cycle Cycle Cycle 80h Din Din 15h 80h 1st Address 2nd Address 3rd Address 4th Address 5th Address Cycle Cycle Cycle Cycle Cycle Din Din 15h 80h R/B# Busy - tCBSY Busy - tCBSY A IO[7:0] 80h 1st Address 2nd Address 3rd Address 4th Address 5th Address Cycle Cycle Cycle Cycle Cycle Din Din 15h 80h 1st Address 2nd Address 3rd Address 4th Address 5th Address Cycle Cycle Cycle Cycle Cycle Din Din 10h 70h R/B# Busy - tCBSY Busy - tPROG Note: tPROG = Page(Last) programming time + Page (Last-1) programming time - Input cycle time of command & address - Data loading time of page (Last). Note 2 P/N: PM2129 REV. 1.4, January. 20, 2017 31 MX30LF2G18AC MX30LF4G18AC 6-7. Block Erase The MX30LFxG18AC supports a block erase command. This command will erase a block of 64 pages associated with the most significant address bits. The completion of the erase operation can be detected by R/B# pin or Status register bit (IO6). Recommend to check the status register bit IO0 after the erase operation completes. During the erasing process, only the read status register command and reset command can be accepted, others are ignored. Figure 16. AC Waveforms for Erase Operation CLE tCLS tCLH CE# tCS tWC WE# tALH tALS ALE tWB RE# tDS IO[7:0] tDH tDS tDH tDS tDH 60h tDS tDH 70h D0h 3rd Address Cycle 4th Address Cycle 5th Address Cycle Stauts Output tERASE R/B# P/N: PM2129 REV. 1.4, January. 20, 2017 32 MX30LF2G18AC MX30LF4G18AC 6-8. ID Read The device contains ID codes that identify the device type and the manufacturer. The ID READ command sequence includes one command Byte (90h), one address byte (00h). The Read ID command 90h may provide the manufacturer ID (C2h) of one-byte and device ID (DAh for 2Gb, DCh for 4Gb) of one-byte, also Byte2, Byte3, and Byte4 ID code are followed. The device support ONFI Parameter Page Read, by sending the ID Read (90h) command and following one byte address (20h), the four-byte data returns the value of 4Fh-4Eh-46h-49h for the ASCII code of "O"-"N""F"-"I" to identify the ONFI parameter page. Table 2. ID Codes Read Out by ID Read Command 90H ID Codes Byte0-Manufacturer Byte1: Device ID Byte2 2Gb, x8, 3V C2h DAh 90h Byte3 Byte4 95h 06h 4Gb, x8, 3V C2h DCh 90h 95h 56h Byte0-Manufacturer Byte1: Device ID Byte2 Byte3 Byte4 P/N: PM2129 REV. 1.4, January. 20, 2017 33 MX30LF2G18AC MX30LF4G18AC Table 3. The Definition of Byte2~Byte4 of ID Table Terms Description IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 0 0 0 1 0 1 1 0 Byte 2 Die Number 1 2 Cell Structure SLC # of Concurrently Programmed page Interleaved operations between Multiple die Cache Program Byte 3 Page size (Exclude spare) Spare area size (Per 512B) Block size (Exclude spare) Organization 1 2 0 0 0 Not supported Supported 2KB 16B 128KB x8 25ns Sequential Read Cycle Time 20ns Byte 4 ECC level requirement 4-bit ECC/528B 1 #Plane per CE 2 4 1Gb Plane size 2Gb Reserved 0 0 1 0 1 1 0 1 0 0 1 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 P/N: PM2129 REV. 1.4, January. 20, 2017 34 MX30LF2G18AC MX30LF4G18AC Figure 17-1. AC Waveforms for ID Read Operation CLE tCLS tCS CE# tCHZ WE# tALH tALS tAR ALE tOH RE# tWHR tDS IO[7:0] 90h tREA tDH 00h C2h (note) (note) (note) (note) Note: See also Table 2. ID Codes Read Out by ID Read Command 90H. Figure 17-2. AC Waveforms for ID Read (ONFI Identifier) Operation CLE tCLS tCS CE# tCHZ WE# tALH tALS tAR ALE tOH RE# tWHR tDS IO[7:0] 90h tDH 20h tREA 4Fh P/N: PM2129 4Eh 46h 49h REV. 1.4, January. 20, 2017 35 MX30LF2G18AC MX30LF4G18AC 6-9. Status Read The MX30LFxG18AC provides a status register that outputs the device status by writing a command code 70h, and then the IO pins output the status at the falling edge of CE# or RE# which occurs last. Even though when multiple flash devices are connecting in system and the R/B#pins are common-wired, the two lines of CE# and RE# may be checked for individual devices status separately. The status read command 70h will keep the device at the status read mode unless next valid command is issued. The resulting information is outlined in Table 4 as below. Table 4. Status Output Pin SR[0] SR[1] SR[2-4] SR[5] SR[6] SR[7] Status Chip Status Cache Program Result Not Used Related Mode Value Page Program, Cache Program (Page N), Block Erase 0: Passed 1: Failed Cache Program (Page N-1) 0: Passed 1: Failed 0: Busy 1: Ready 0: Busy 1: Ready 0: Protected 1: Unprotected Cache Program/Cache Ready / Busy Read operation, other Page (For P/E/R Controller) Program/Block Erase/Read are same as IO6 (Note 1) Page Program, Block Erase, Ready / Busy Cache Program, Read, Cache Read (Note 2) Page Program, Block Erase, Write Protect Cache Program, Read Notes: 1. During the actual programming operation, the SR[5] is "0" value; however, when the internal operation is completed during the cache mode, the SR[5] returns to "1". 2. The SR[6] returns to "1" when the internal cache is available to receive new data. The SR[6] value is consistent with the R/B#. P/N: PM2129 REV. 1.4, January. 20, 2017 36 MX30LF2G18AC MX30LF4G18AC The following is an example of a HEX data bit assignment: Figure 18. Bit Assignment (HEX Data) Status Read: 70h 0 1 1 1 0 0 0 0 SR7 6 5 4 3 2 1 SR0 Figure 19. AC Waveforms for Status Read Operation tCLR CLE tCLS tCLH CE# tCS tWP WE# tCHZ tWHR RE# tOH tIR tDS tDH IO[7:0] tREA Status Output 70h P/N: PM2129 REV. 1.4, January. 20, 2017 37 MX30LF2G18AC MX30LF4G18AC 6-10. Status Enhance Read The MX30LFxG18AC supports the two-plane operation, the Status Enhanced Read command (78h) offers the alternative method besides the Status Read command to get the status of specific plane in the same NAND Flash device. The result information is outlined in Table 4. The [SR]6 and SR[5] bits are shared with all planes. However, the SR[0], SR[1], SR[3], SR[4] are for the status of specific plane in the row address. The Status Enhanced Read command is not allowed at power-on Reset (FFh) command, OTP enabled operation. Figure 20. AC Waveforms for Status Enhance Operation CLE tCLS tCS CE# tCHZ WE# tALH tALS tAR ALE tOH RE# tWHR tDS IO[7:0] 78h tREA tDH 3rd Address Cycle 4th Address Cycle 5th Address Cycle Status Output 6-11. Block Protection Status Read The Block Protection Status Read command (7Ah) may check the protect/un-protect status of blocks. The status output is shown in Table 5. Block Protection Status Output and the address cycle is referred to Table 6. Address Cycle Definition of Block. P/N: PM2129 REV. 1.4, January. 20, 2017 38 MX30LF2G18AC MX30LF4G18AC Table 5. Block-Protection Status Output Block-Protection Status Block is protected, and device is solid-protected Block is protected, and device is not solid-protected Block is un-protected, and device is solid-protected Block is un-protected, and device is not solid-protected IO[7:3] x IO2(PT#) 0 IO1(SP#) 0 IO0(SP) 1 x 0 1 0 x 1 0 1 x 1 1 0 Note: SP stands for Solid-protected. Once the SP bit sets as 1, the rest of the protection bits (BPx bits, Invert bit, Complementary bit) cannot be changed during the current power cycle. Table 6. Address Cycle Definition of Block Address Cycle IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 Block Address 1 A19 A18 L L L L L L Block Address 2 Block Address 3 A27 L A26 L A25 L A24 L A23 L A22 L A21 A29(Note) A20 A28 Note: A29 is for 4Gb, "L" (Low) is for 2Gb. Figure 21. AC Waveforms for Block Protection Status Read CLE CE# tWC WE# tWHR ALE WP# RE# IO[7:0] 7Ah Block address 0 Block address 2 Block address 1 Status Output R/B# P/N: PM2129 REV. 1.4, January. 20, 2017 39 MX30LF2G18AC MX30LF4G18AC 6-12. Reset The reset command FFh resets the read/program/erase operation and clear the status register to be E0h (when WP# is high). The reset command during the program/erase operation will result in the content of the selected locations(perform programming/erasing) might be partially programmed/erased. If the Flash memory has already been set to reset stage with reset command, the additional new reset command is invalid. Figure 22. AC waveforms for Reset Operation CLE CE# WE# ALE RE# tWB IO[7:0] FFh tRST R/B# P/N: PM2129 REV. 1.4, January. 20, 2017 40 MX30LF2G18AC MX30LF4G18AC 6-13. Parameter Page Read (ONFI) The NAND Flash device support ONFI Parameter Page Read and the parameter can be read out by sending the command of ECh and giving the address 00h. The NAND device information may refer to the table of parameter page(ONFI), there are three copies of 256-byte data and additional redundant parameter pages. Once sending the ECh command, the NAND device will remain in the Parameter Page Read mode until next valid command is sent. The Random Data Out command set (05h-E0h) can be used to change the parameter location for the specific parameter data random read out. The Status Read command (70h) can be used to check the completion with a following read command (00h) to enable the data out. Figure 23. AC waveforms for Parameter Page Read (ONFI) Operation tCLR CLE CE# WE# tAR ALE tRC RE# tRR tWB tR IO[7:0] ECh Parameter 0 Dout 0 00h Parameter 0 Dout 1 Parameter 0 Dout 255 Parameter 1 Dout 0 R/B# Busy P/N: PM2129 REV. 1.4, January. 20, 2017 41 MX30LF2G18AC MX30LF4G18AC Figure 24. AC Waveforms for Parameter Page Read (ONFI) Random Operation (For 05h-E0h) tCLR CLE CE# WE# tWHR tAR ALE tRC RE# tRR tWB tR IO[7:0] ECh tREA Parameter 0 Dout 0 00h Parameter 0 Dout 1 05h R/B# 1st Address Cycle 2nd Address Cycle E0h Parameter m Dout n Parameter m Dout n+1 Repeat if needed Busy P/N: PM2129 REV. 1.4, January. 20, 2017 42 MX30LF2G18AC MX30LF4G18AC Table 7. Parameter Page (ONFI) Byte# Revision Information and Features Block Description Data 0-3 Parameter Page Signature 4Fh, 4Eh, 46h, 49h 4-5 Revision Number 02h, 00h 6-7 Features Supported 18h, 00h 8-9 Optional Commands Supported 3Fh, 00h 00h 10-31 Reserved Manufacturer Information Block Description Data Byte# 32-43 Device Manufacturer (12 ASCII characters) MX30LF2G18AC 44-63 64 65-66 67-79 Byte# Device Model (20 ASCII Characters) MX30LF4G18AC JEDEC Manufacturer ID Date Code Reserved 4Dh,41h,43h,52h,4Fh,4Eh,49h,58h, 20h,20h,20h,20h 4Dh,58h,33h,30h,4Ch,46h,32h,47h, 31h,38h,41h,43h,20h,20h,20h,20h, 20h,20h,20h,20h, 4Dh,58h,33h,30h,4Ch,46h,34h,47h, 31h,38h,41h,43h,20h,20h,20h,20h, 20h,20h,20h,20h C2h 00h, 00h 00h Memory Organization Block Description 80-83 Number of Data Bytes per Page 84-85 86-89 90-91 92-95 Number of Spare Bytes per Page Number of Data Bytes per Partial Page Number of Spare Bytes per Partial Page Number of Pages per Block 96-99 Number of Blocks per Logical Unit 100 101 102 Number of Logical Units (LUNs) Number of Address Cycles Number of Bits per Cell 103-104 Bad Blocks Maximum per LUN 105-106 107 108-109 110 111 112 113 114 115-127 Block endurance Guarantee Valid Blocks at Beginning of Target Block endurance for guaranteed valid blocks Number of Programs per Page Partrial Programming Attributes Number of Bits ECC Correctability Number of Interleaved Address Bits Interleaved Operation Attributes Reserved P/N: PM2129 Data 204800h,08h,00h,00h byte 64-byte 40h,00h 512-byte 00h,02h,00h,00h 16-byte 10h,00h 40h,00h,00h,00h 2Gb 00h,08h,00h,00h 4Gb 00h,10h,00h,00h 01h 23h 01h 2Gb 28h,00h 4Gb 50h,00h 01h, 05h 01h 01h, 03h 04h 00h 04h 01h 0Eh 00h REV. 1.4, January. 20, 2017 43 MX30LF2G18AC MX30LF4G18AC Electrical Parameters Block Description Byte# Data 128 I/O Pin Capacitance 0Ah 129-130 Timing Mode Support 3Fh,00h 131-132 Program Cache Timing Mode Support 3Fh,00h 133-134 tPROG Maximum Page Program Time (uS) 600us 135-136 tBERS(tERASE) Maximum Block Erase Time (uS) 3,500us ACh,0Dh 137-138 tR Maximum Page Read Time (uS) 25us 19h,00h 139-140 tCCS Minimum Change Column Setup Time (ns) 60ns 3Ch,00h 141-163 Reserved Byte# 164-165 166-253 254-255 Byte# 256-511 512-767 768+ 58h,02h 00h Vendor Blocks Description Data Redundant Parameter Pages Description Data Vendor Specific Revision Number Vendor Specific Integrity CRC 00h 00h Set at Test (Note) Value of Bytes 0-255 Value of Bytes 0-255 Additional Redundant Parameter Pages Note: The Integrity CRC (Cycling Redundancy Check) field is used to verify that the contents of the parameters page were transferred correctly to the host. Please refer to ONFI 1.0 specifications for details. The CRC shall be calculated using the following 16-bit generator polynomial: G(X) = X16 + X15 +X2 + 1 P/N: PM2129 REV. 1.4, January. 20, 2017 44 MX30LF2G18AC MX30LF4G18AC 6-14. Unique ID Read (ONFI) The unique ID is 32-byte and with 16 copies for back-up purpose. After writing the Unique ID read command (EDh) and following the one address byte (00h), the host may read out the unique ID data. The host need to XOR the 1st 16-byte unique data and the 2nd 16-byte complement data to get the result, if the result is FFh, the unique ID data is correct; otherwise, host need to repeat the XOR with the next copy of Unique ID data. Once sending the EDh command, the NAND device will remain in the Unique ID read mode until next valid command is sent. To change the data output location, it is recommended to use the Random Data Out command set (05h-E0h). The Status Read command (70h) can be used to check the completion. To continue the read operation, a following read command (00h) to re-enable the data out is necessary. Figure 25. AC waveforms for Unique ID Read Operation tCLR CLE CE# WE# tAR ALE tRC RE# tRR tWB tR IO[7:0] EDh Unique ID 0 Dout 0 00h Unique ID 0 Dout 1 Unique ID 0 Dout 31 Unique ID 1 Dout 0 R/B# Busy P/N: PM2129 REV. 1.4, January. 20, 2017 45 MX30LF2G18AC MX30LF4G18AC Figure 26. AC waveforms for Unique ID Read Operation (For 05h-E0h) tCLR CLE CE# WE# tWHR tAR ALE tRC RE# tRR tWB tR IO[7:0] EDh tREA Unique ID 0 Dout 0 00h Unique ID 0 Dout 1 05h R/B# 1st Address Cycle 2nd Address Cycle E0h Unique ID m Dout n Unique ID m Dout n+1 Repeat if needed Busy P/N: PM2129 REV. 1.4, January. 20, 2017 46 MX30LF2G18AC MX30LF4G18AC 6-15. Feature Set Operation (ONFI) The Feature Set operation is to change the default power-on feature sets by using the Set Feature and Get Feature command and writing the specific parameter data (P1-P4) on the specific feature addresses. The NAND device may remain the current feature set until next power cycle since the feature set data is volatile. However, the reset command (FFh) can not reset the current feature set. Table 8-1. Definition of Feature Address Feature Address 00h-8Fh, 91h-9Fh, A1h-FFh 90h A0h Description Reserved Array Operation Mode Block Protection Operation Table 8-2. Sub-Feature Parameter Table of Feature Address - 90h (Array Operation Mode) Sub Feature Parameter Definition P1 Normal Array Operation OTP Operation Mode OTP Protection P2 P3 P4 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 Reserved (0) Reserved (0) 0 Reserved (0) 0 Reserved (0) Reserved (0) Reserved (0) 0 0 1 0 1 1 Values Notes 0000 0000b 0000 0001b 0000 0011b 0000 0000b 0000 0000b 0000 0000b 1 Note 1. The value is clear to 00h at power cycle. Table 8-3. Sub-Feature Parameter Table of Feature Address - A0h (Block Protection Operation) (note 1) Sub Feature Parameter P1 Definition Default Block mode Protection Protection Operation Bit Setting IO7 IO6 IO5 IO4 IO3 0 0 0 0 1 1 1 IO2 IO1 0 0 IO0 Values Notes 0 BP2 BP1 BP0 Invert Complementary P2 P3 P4 SP 38h note 2 note 3 note 4 Reserved (0) Reserved (0) Reserved (0) Notes: 1. If the PT pin is not connected to high, this sub-feature address A0h command is not valid. 2. The value is returned to 38h at power cycle. 3. The value is defined in the Table 9. Definition of Protection Bits. 4. The SP stands for Solide-Protection. Once the SP bit sets as 1, the rest of protection bits cannot be changed during the current power cycle. P/N: PM2129 REV. 1.4, January. 20, 2017 47 MX30LF2G18AC MX30LF4G18AC 6-15-1. Set Feature (ONFI) The Set Feature command is to change the power-on default feature set. After sending the Set Feature command (EFh) and following specific feature and then input the P1-P4 parameter data to change the default power-on feature set. Once sending the EFh command, the NAND device will remain in the Set Feature mode until next valid command is sent. The Status Read command (70h) may check the completion of the Set Feature. Figure 27. AC Waveforms for Set Feature (ONFI) Operation CLE CE# tADL tWC WE# tWB ALE RE# IO[7:0] EFh Feature Address Din Din Din Din tFEAT R/B# Busy P/N: PM2129 REV. 1.4, January. 20, 2017 48 MX30LF2G18AC MX30LF4G18AC 6-15-2. Get Feature (ONFI) The Get Feature command is to read sub-feature parameter. After sending the Get Feature command (EEh) and following specific feature, the host may read out the P1-P4 sub- feature parameter data. Once sending the EEh command, the NAND device will remain in the Get Feature mode until next valid command is sent. The Status Read command (70h) can be used to check the completion. To continue the read operation, a following read command (00h) to re-enable the data out is necessary. Please refer to the following waveform of Get Feature Operation for details. Figure 28. AC Waveforms for Get Feature (ONFI) Operation tCLR CLE CE# WE# tAR ALE tRC RE# tRR tWB tFEAT IO[7:0] EEh Feature Address Feature Dout 0 Feature Dout 1 Feature Dout 2 Feature Dout 3 R/B# Busy P/N: PM2129 REV. 1.4, January. 20, 2017 49 MX30LF2G18AC MX30LF4G18AC 6-15-3. Secure OTP (One-Time-Programmable) Feature There is an OTP area which has thirty full pages (30 x 2,112-byte) guarantee to be good for system device serial number storage or other fixed code storage. The OTP area is a non-erasable and one-timeprogrammable area, which is default to “1” and allows whole page or partial page program to be “0”, once the OTP protection mode is set, the OTP area becomes read-only and cannot be programmed again. The OTP operation is operated by the Set Feature/ Get Feature operation to access the OTP operation mode and OTP protection mode. To check the NAND device is ready or busy in the OTP operation mode, either checking the R/B# or writing the Status Read command (70h) may collect the status. To exit the OTP operation or protect mode, it can be done by writing 00h to P1 at feature address 90h. OTP Read/Program Operation To enter the OTP operation mode, it is by using the Set Feature command (EFh) and followed by the feature address (90h) and then input the 01h to P1 and 00h to P2-P4 of sub-Feature Parameter data( please refer to the sub-Feature Parameter table). After enter the OTP operation mode, the normal Read command (00h-30h) or Page program( 80h-10h) command can be used to read the OTP area or program it. The address of OTP is located on the 02h-1Fh of page address. Besides the normal Read command, the Random Data Output command (05h-E0h) can be used for read OTP data. However, the Cache Read command is not supported in the OTP area. Besides the normal page program command, the Random Data Input command (85h) allows multi-data load in non-sequential address. After data load is completed, a program confirm command (10h) is issued to start the page program operation. The number of partial-page OTP program is 8 per each OTP page. Figure 29. AC Waveforms for OTP Data Read tCLR CLE CE# WE# tAR ALE tRC RE# tRR tR tWB IO[7:0] 00h 1st Address 2nd Address Cycle Cycle OTP Page 00h 00h Dout 0 30h Dout 1 Dout n R/B# Busy P/N: PM2129 REV. 1.4, January. 20, 2017 50 MX30LF2G18AC MX30LF4G18AC Figure 30. AC Waveforms for OTP Data Read with Random Data Output A tCLR CLE CE# WE# tAR ALE tRC RE# tRHW tRR tWB IO[7:0] 00h 1st Address Cycle 2nd Address Cycle OTP Page 00h 00h tR Dout M 30h Dout M+1 05h R/B# Busy CLE A CE# WE# tWHR ALE RE# tREA IO[7:0] 05h 1st Address Cycle 2nd Address Cycle E0h Dout N Dout N+1 R/B# Repeat if needed P/N: PM2129 REV. 1.4, January. 20, 2017 51 MX30LF2G18AC MX30LF4G18AC Figure 31. AC Waveforms for OTP Data Program CLE CE# tADL WE# tWB ALE RE# IO[7:0] 80h 1st Address 2nd Address 3rd Address 4th Address Cycle Cycle Cycle Cycle 5th Address Cycle Din Din 70h 10h Status Output tPROG R/B# Busy P/N: PM2129 REV. 1.4, January. 20, 2017 52 MX30LF2G18AC MX30LF4G18AC Figure 32. AC Waveforms for OTP Data Program with Random Data Input A CLE CE# tADL tWC WE# ALE RE# IO[7:0] 80h 1st Address 2nd Address Cycle Cycle OTP Page 00h 00h Din Din R/B# A CLE CE# tADL WE# tWB ALE RE# IO[7:0] 85h 1st Address 2nd Address Cycle Cycle Din Din 70h 10h Status Output tPROG R/B# Busy P/N: PM2129 REV. 1.4, January. 20, 2017 53 MX30LF2G18AC MX30LF4G18AC OTP Protection Operation To prevent the further OTP data to be changed, the OTP protection mode operation is necessary. To enter the OTP protection mode, it can be done by using the Set Feature command (EFh) and followed by the feature address (90h) and then input the 03h to P1 and 00h to P2-P4 of sub-Feature Parameter data (please refer to the sub-Feature Parameter table). And then the normal page program command (80h-10h) with the address 00h before the 10h command is required. The OTP Protection mode is operated by the whole OTP area instead of individual OTP page. Once the OTP protection mode is set, the OTP area cannot be programmed or unprotected again. Figure 33. AC Waveforms for OTP Protection Operation CLE tCLS tCLH CE# tCS tWC WE# tALS tALH tWB tALH ALE RE# tDS IO[7:0] tDH - 80h 1st Address Cycle Note - 00h 00h 00h 10h 70h Status Output Dummy data input 2nd Address Cycle tPROG R/B# Note: This address cycle can be any value since the OTP protection protects the entire OTP area instead of individual OTP page. P/N: PM2129 REV. 1.4, January. 20, 2017 54 MX30LF2G18AC MX30LF4G18AC 6-15-4. Block Protection The block protect operation can protect the whole chip or selected blocks from erasing or programming. Through the PT pin at power-on stage, it decides the block protection operation is enabled or disabled. At power-on, if the PT pin is connected to high, the block protection operation is enabled, all the blocks are default to be protected from programming/erasing even the WP# is disabled. If the PT pin is low, block protection operation is disabled. Please refer to Figure 34. PT Pin and Block Protection Mode Operation When program or erase attempt at a protected block is happened, the R/B# keeps low for the time of tPBSY, and the Status Read command (70h) may get the 60h result. There are Temporary Protection/un-Protection and Solid Protection features as below description. Temporary Protection/un-Protection At power-on, if the PT pin is connected to high, all the blocks are default to be protected for the BPx protection bits are all “1”. The Set feature command with feature address A0h followed by the destined protection bits data is necessary to un-protect those selected blocks before those selected blocks to be updated. The WP# pin needs to connect to high before writing the Set Feature command for the block protection operation. After the selected blocks are un-protected, those un-protected blocks can be protected again by Block Protection procedure if required. Solid Protection The “solid-protection” feature can be set by writing the Set Feature command with address A0h and the “SP” solidprotection bit as “1”, after that, the selected block is solid-protected and cannot be up-protected until next power cycle. Table 9. Definition of Protection Bits BP2 0 0 0 0 1 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 BP1 0 0 1 1 0 0 1 1 0 1 1 0 0 1 0 1 1 0 0 1 0 1 1 0 0 1 BP0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Invert x 0 0 0 0 0 0 x 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 P/N: PM2129 Complementary x 0 0 0 0 0 0 x 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 Protection Area all unlocked upper 1/64 locked upper 1/32 locked upper 1/16 locked upper 1/8 locked upper 1/4 locked upper 1/2 locked all locked (default) lower 1/64 locked lower 1/32 locked lower 1/16 locked lower 1/8 locked lower 1/4 locked lower 1/2 locked lower 63/64 locked lower 31/32 locked lower 15/16 locked lower 7/8 locked lower 3/4 locked block 0 upper 63/64 locked upper 31/32 locked upper 15/16 locked upper 7/8 locked upper 3/4 locked block0 REV. 1.4, January. 20, 2017 55 MX30LF2G18AC MX30LF4G18AC Figure 34. PT Pin and Block Protection Mode Operation Power On PT pin = low PT pin = high WP# Protection Mode Block Protection Mode (PT) 1. WP# pin = low to protect whole chip 2. Block Protection mode disable 1. Blcok Protection mode enable with BPx bit = 1 2. Whole Blocks are protected after power on Temporary Protection/ Un-Proteciton (By CMD) 1. Set Feature command (EFh) sets BPx bit, Invert bit and complementary bit value Block Protection Area (By CMD) SP bit = 1 Solid Protection Mode 1. Set Feature command with SP bit = 1 fixes current block protecion/un-protection status 2. Only next Power On cycle can disable Solid Protection mode P/N: PM2129 REV. 1.4, January. 20, 2017 56 MX30LF2G18AC MX30LF4G18AC 6-16. Two-Plane Operations The device is divided into two planes for performance improvement, which provides ONFI two-plane commend set, and traditional two-plane command set. In the two-plane operation, the NAND device may proceed the same type operation (for example: Program or Erase) on the two planes concurrent or overlapped by the two-plane command sets. The different type operations cannot be done in the two-plane operations; for example, it cannot be done to erase one plane and program the other plane concurrently. The plane address A18 must be different from each selected plane address. The page address A12-A17 of individual plane must be the same for two-plane operation. The Status Read command (70h) may check the device status in the two-plane operation, if the result is failed and then the Status Enhanced Read (78h) may check which plane is failed. 6-17. Two-plane Program (ONFI & Traditional)and Two-plane Cache Program (ONFI & Traditional) The two-plane program command (80h-11h) may input data to cache buffer and wait for the final plane data input with command (80h-10h) and then transfer all data to NAND array. As for the two-plane cache program operation, it can be achieved by a two-plane program command (80h-11h) with a cache program command (80h-15h), and the final address input with the confirm command (80h-10h). Please refer to the waveforms of Figure 35-1. AC Waveforms for Two-plane Program (ONFI) and Figure 36. AC Waveforms for Two-plane Cache Program (ONFI) for details. The random data input command (85h) can be also used in the two-plane program operation for changing the column address, please refer to Figure 35-2. AC Waveforms for Page Program Random Data Two-plane (ONFI). The traditional two-plane page program and cache program commands describe in Figure 38. AC waveforms for Two-plane Program (Traditional) and Figure 39. AC waveforms for Two-plane Cache Program (Traditional). Notes: 1. Page number should be the same for both planes. 2. Block address [29:18] can be different. For examples: If the user issues 80h-(block address 5h, page address 5h) -11h - 80h (block address - 18h, page address 5h) - 10h, the programmed page is - Plane 0: block address 18h, page address 5h - Plane 1: block address 5h, page address 5h (Note: Block address = A[29:18], page address = A[17:12]) 6-18. Two-plane Block Erase (ONFI & Traditional) The two-plane erase command (60h-D1h) may erase the selected blocks in parallel from each plane, with setting the 1st and 2nd block address by (60h-D1h) & (60h-D0h) command and then erase two selected blocks from NAND array. Please refer to the following waveforms of two-plane erase for details. Traditional twoplane block erase command describes in Figure 40. AC waveforms for Two-plane Erase (Traditional). P/N: PM2129 REV. 1.4, January. 20, 2017 57 MX30LF2G18AC MX30LF4G18AC Figure 35-1. AC Waveforms for Two-plane Program (ONFI) A CLE CE# tADL tWC WE# tWB ALE RE# IO[7:0] 80h 1st Address 2nd Address 3rd Address Cycle Cycle Cycle 4th Address Cycle 5th Address Cycle Din Din 11h tDBSY R/B# Busy A CLE CE# tADL WE# tWB ALE RE# IO[7:0] 80h 1st Address 2nd Address 3rd Address 4th Address Cycle Cycle Cycle Cycle 5th Address Cycle Din Din 70h 10h Status Output tPROG R/B# Busy P/N: PM2129 REV. 1.4, January. 20, 2017 58 MX30LF2G18AC MX30LF4G18AC Figure 35-2. AC Waveforms for Page Program Random Data Two-plane (ONFI) A CLE CE# tADL tWC tADL tWC WE# tWB ALE RE# IO[7:0] 80h 1st Address 2nd Address 3rd Address 4th Address 5th Address Cycle Cycle Cycle Cycle Cycle Din Din 85h 1st Address 2nd Address Cycle Cycle Din Din 11h tDBSY R/B# Reapeat if needed Busy A CLE CE# tADL tADL tWC WE# tWB ALE RE# IO[7:0] 80h 1st Address 2nd Address 3rd Address 4th Address Cycle Cycle Cycle Cycle 5th Address Cycle Din 85h Din 1st Address 2nd Address Cycle Cycle Din Din 70h 10h Status Output tPROG R/B# Reapeat if needed P/N: PM2129 Busy REV. 1.4, January. 20, 2017 59 MX30LF2G18AC MX30LF4G18AC Figure 36. AC Waveforms for Two-plane Cache Program (ONFI) A CLE CE# tADL tWC tADL tWC WE# tWB tWB ALE RE# IO[7:0] 80h 1st Address Cycle 2nd Address Cycle 3rd Address Cycle 4th Address Cycle 5th Address Cycle Din Din 80h 11h 1st Address Cycle 2nd Address Cycle 3rd Address Cycle 4th Address Cycle 5th Address Cycle tDBSY Plane 0 Din Din 15h tCBSY Plane 1 R/B# Busy Busy Repeat if needed A CLE CE# tADL tADL tWC WE# tWB tWB ALE RE# IO[7:0] 80h 1st Address Cycle 2nd Address Cycle 3rd Address Cycle 4th Address Cycle 5th Address Cycle Plane 0 Din Din 11h 80h tDBSY 1st Address Cycle 2nd Address Cycle 3rd Address Cycle 4th Address Cycle 5th Address Cycle Plane 1 Din Din 10h 70h Status Output tPROG R/B# Busy Busy P/N: PM2129 REV. 1.4, January. 20, 2017 60 MX30LF2G18AC MX30LF4G18AC Figure 37. AC Waveforms for Two-plane Erase (ONFI) CLE tCLS tCLS tCLH CE# tCLH tCS tWC WE# tALH tWC tALS tALH tALS ALE tWB RE# tDH tDS IO[7:0] tDS tDH tDS tDH tDH tDS tDS 60h D1h 3rd Address Cycle R/B# tWB 4th Address Cycle 5th Address Cycle tDH tDS tDH tDS tDH tDS tDH 60h 3rd Address Cycle tDBSY 70h D0h 5th Address Cycle 4th Address Cycle Stauts Output tERASE Figure 38. AC waveforms for Two-plane Program (Traditional) IO[x:0] 1st Address 2nd Address 3rd Address 4th Address 5th Address Cycle Cycle Cycle Cycle Cycle 80h Din Din 11h 81h Amax - A19 : Fixed “Low” A18 : Fixed “Low” A12 - A17 : Fixed “Low” A11 - A0 : Valid 1st Address 2nd Address 3rd Address 4th Address 5th Address Cycle Cycle Cycle Cycle Cycle Din Din 10h 70h Amax - A19 : Valid A18 : Fixed “High” A12 - A17 : Valid A11 - A0 : Valid Plane 0 Plane 1 R/B# Busy - tPROG Busy - tDBSY Figure 39. AC waveforms for Two-plane Cache Program (Traditional) A IO[x:0] 1st Address 2nd Address 3rd Address 4th Address 5th Address Cycle Cycle Cycle Cycle Cycle 80h Din Din 11h 81h Amax - A19 : Fixed “Low” A18 : Fixed “Low” A12 - A17 : Fixed “Low” A11 - A0 : Valid 1st Address 2nd Address 3rd Address 4th Address 5th Address Cycle Cycle Cycle Cycle Cycle Din Din 15h 80h Amax - A19 : Valid A18 : Fixed “High” A12 - A17 : Valid A11 - A0 : Valid Plane 0 Plane 1 R/B# Busy - tDBSY Busy - tCBSY A IO[x:0] 80h 1st Address 2nd Address 3rd Address 4th Address 5th Address Cycle Cycle Cycle Cycle Cycle Din Din 11h 81h Amax - A19 : Fixed “Low” A18 : Fixed “Low” A12 - A17 : Fixed “Low” A11 - A0 : Valid 1st Address 2nd Address 3rd Address 4th Address 5th Address Cycle Cycle Cycle Cycle Cycle Din Din 10h 70h Amax - A19 : Valid A18 : Fixed “High” A12 - A17 : Valid A11 - A0 : Valid Plane 0 Plane 1 R/B# Busy - tDBSY P/N: PM2129 Busy - tPROG REV. 1.4, January. 20, 2017 61 MX30LF2G18AC MX30LF4G18AC Figure 40. AC waveforms for Two-plane Erase (Traditional) IO[x:0] 60h 3rd Address 4th Address 5th Address Cycle Cycle Cycle Amax - A19 : Fixed “Low” A18 : Fixed “Low” A12 - A17 : Fixed “Low” Plane 0 60h 3rd Address 4th Address 5th Address Cycle Cycle Cycle D0h 70h Amax - A19 : Valid A18 : Fixed “High” A12 - A17 : Fixed “Low” Plane 1 R/B# Busy - tERASE P/N: PM2129 REV. 1.4, January. 20, 2017 62 MX30LF2G18AC MX30LF4G18AC 7. PARAMETERS 7-1. ABSOLUTE MAXIMUM RATINGS Temperature under Bias -50°C to +125°C Storage temperature -65°C to +150°C All input voltages with respect to ground (Note 2) -0.6V to 4.6V VCC supply voltage with respect to ground (Note 2) -0.6V to 4.6V ESD protection >2000V Notes: 1. The reliability of device may be impaired by exposing to extreme maximum rating conditions for long range of time. 2. Permanent damage may be caused by the stresses higher than the "Absolute Maximum Ratings" listed. 3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see the two waveforms as below. Figure 41. Maximum Negative Overshoot Waveform 20ns Figure 42. Maximum Positive Overshoot Waveform 20ns 20ns Vss Vcc + 2.0V Vss-2.0V Vcc 20ns 20ns P/N: PM2129 20ns REV. 1.4, January. 20, 2017 63 MX30LF2G18AC MX30LF4G18AC Table 10. Operating Range VCC Tolerance +3.3V 2.7 ~ 3.6V Temperature -40°C to +85°C Table 11. DC Characteristics Symbol Parameter Test Conditions Min. Typical Max. Unit Notes VIL Input low level -0.3 0.2VCC V VIH Input high level 0.8VCC VCC + 0.3 V 0.2 V VOL VOH ISB1 ISB2 ICC0 ICC1 ICC2 ICC3 IOL= 2.1mA, VCC= VCC Min. IOH= -400uA, VCC= Output high voltage VCC-0.2 VCC Min. CE# = VCC -0.2V, VCC standby current (CMOS) WP# = 0/VCC CE# = VIH Min., VCC standby current (TTL) WP# = 0/VCC Power on current (Including POR current) VCC active current tRC Min., CE# = VIL, (Sequential Read) IOUT= 0mA VCC active current (Program) Output low voltage VCC active current (Erase) V 10 50 uA 1 mA 50 mA 15 30 mA 15(Note) 30 mA 15 30 mA ILI Input leakage current VIN= 0 to VCC Max. +/- 10 uA ILO Output leakage current VOUT= 0 to VCC Max. +/- 10 uA ILO Output current of R/B# pin (R/B#) VOL=0.4V 8 10 mA Note: The typical program current (ICC2) for two-plane program operation is 25mA. P/N: PM2129 REV. 1.4, January. 20, 2017 64 MX30LF2G18AC MX30LF4G18AC Table 12. Capacitance TA = +25°C, F = 1 MHz Symbol Parameter CIN COUT Typ. Max. Units Conditions Input capacitance 10 pF VIN = 0 V Output capacitance 10 pF VOUT = 0 V Table 13. AC Testing Conditions Testing Conditions Value Unit 0 to VCC V 1TTL+CL(50) pF 5 VCC/2 VCC/2 ns V V Input pulse level Output load capacitance Input rise and fall time Input timing measurement reference levels Output timing measurement reference levels Table 14. Program and Erase Characteristics Symbol tPROG tCBSY (Program) tRCBSY (Read) tDBSY tFEAT tOBSY tPBSY NOP tERASE (Block) Parameter Page programming time Dummy busy time for cache program Dummy busy time for cache read The busy time for two-plane program/erase operation The busy time for Set Feature/ Get Feature The busy time for OTP program at OTP protection mode The busy time for program/erase at protected blocks Number of partial program cycles in same page Block erase time P/N: PM2129 Min. Typ. Max. Unit Note 300 5 3.5 0.5 1 600 us 600 us 25 us 1 us 1 us 30 us 3 us 4 cycles 3.5 ms REV. 1.4, January. 20, 2017 65 MX30LF2G18AC MX30LF4G18AC Table 15. AC Characteristics Symbol Parameter Min. Typical Max. Unit Note tCLS tCLH tCS tCH tWP tALS CLE setup time CLE hold time CE# setup time CE# hold time Write pulse width ALE setup time 10 5 15 5 10 10 ns ns ns ns ns ns 1 1 1 1 1 1 tALH ALE hold time 5 ns 1 tDS Data setup time 7 ns 1 tDH Data hold time 5 ns 1 tWC Write cycle time 20 ns 1 tWH WE# high hold time 7 ns 1 tADL 70 ns 1 tWW tRR Last address latched to data loading time during program operations WP# transition to WE# high Ready to RE# falling edge 100 20 ns ns 1 1 tRP Read pulse width 10 ns 1 tRC Read cycle time 20 ns 1 tREA RE# access time (serial data access) 16 ns 1 tCEA CE# access time 25 ns 1 tRLOH RE#-low to data hold time (EDO) 5 ns tOH Data output hold time 15 ns 1 tRHZ RE#-high to output-high impedance 60 ns 1 tCHZ CE#-high to output-high impedance 50 ns 1 tCOH CE# high to output hold time 15 ns tREH RE# high hold time 7 ns 1 tIR Output high impedance to RE# falling edge 0 ns 1 tRHW RE# high to WE# low 60 ns 1 tWHR WE# high to RE# low 60 ns 1 tR The data transfering from array to buffer 25 us 1 tWB WE# high to busy 100 ns 1 tCLR CLE low to RE# low 10 ns 1 tAR ALE low to RE# low 10 ns 1 tRST Device reset time (Idle/ Read/ Program/ Erase) us 1 5/5/10/500 Note 1. ONFI Mode 5 compliant P/N: PM2129 REV. 1.4, January. 20, 2017 66 MX30LF2G18AC MX30LF4G18AC 8. OPERATION MODES: LOGIC AND COMMAND TABLES Address input, command input and data input/output are managed by the CLE, ALE, CE#, WE#, RE# and WP# signals, as shown in Table 16. Logic Table below. Program, Erase, Read and Reset are four major operations modes controlled by command sets, please refer to Table 17-1 and 17-2. Table 16. Logic Table Mode CE# RE# Address Input (Read Mode) L Address Input (Write Mode) WE# CLE ALE WP# H L H X L H L H H Command Input (Read Mode) L H H L X Command Input (Write Mode) L H H L H Data Input L H L L H Data Output L H L L X During Read (Busy) X H H L L X During Programming (Busy) X X X X X H During Erasing (Busy) X X X X X H Program/Erase Inhibit X X X X X L Stand-by H X X X X 0V/VCC Notes: 1. H = VIH; L = VIL; X = VIH or VIL 2. WP# should be biased to CMOS high or CMOS low for stand-by. P/N: PM2129 REV. 1.4, January. 20, 2017 67 MX30LF2G18AC MX30LF4G18AC Table 17-1. HEX Command Table First Cycle Second Cycle 00H 85H 05H 00H 31H 3FH 90H ECH EDH EFH EEH FFH 80H 80H 60H 70H 78H 7AH 30H E0H 31H 10H 15H D0H - Read Mode Random Data Input Random Data Output Cache Read Random Cache Read Sequential Cache Read End ID Read Parameter Page Read (ONFI) Unique ID Read (ONFI) Set Feature (ONFI) Get Feature (ONFI) Reset Page Program Cache Program Block Erase Status Read Status Enhanced Read (ONFI) Block Protection Status Read Acceptable While Busy V V V Table 17-2. Two-plane Command Set First Cycle Two-plane Program (ONFI) Two-plane Cache Program (ONFI) Two-plane Block Erase (ONFI) Two-plane Program (Traditional) Two-Plane Cache Program (Traditional) Two-plane Erase (Traditional) 80H 80H 60H 80H 80H 60H Second Cycle 11H 11H D1H 11H 11H 60H Third Cycle Fourth Cycle 80H 80H 60H 81H 81H D0H 10H 15H D0H 10H 15H Caution: None of the undefined command inputs can be accepted except for the command set in the above table. P/N: PM2129 REV. 1.4, January. 20, 2017 68 MX30LF2G18AC MX30LF4G18AC 8-1. R/B#: Termination for The Ready/Busy# Pin (R/B#) The R/B# is an open-drain output pin and a pull-up resistor is necessary to add on the R/B# pin. The R/B# outputs the ready/busy status of read/program/ erase operation of the device. When the R/B# is at low, the device is busy for read or program or erase operation. When the R/B# is at high, the read/program/erase operation is finished. Rp Value Guidence The rise time of the R/B# signal depends on the combination of Rp and capacitive loading of the R/B# circuit. It is approximately two times constants (Tc) between the 10% and 90% points on the R/B# waveform. TC = R × C Where R = Rp (Resistance of pull-up resistor), and C = CL (Total capacitive load) The fall time of the R/B# signal majorly depends on the output impedance of the R/B# signal and the total load capacitance. Rp (Min.) = Vcc (Max.) - VOL (Max.) IOL+ΣIL Notes: 1. Considering of the variation of device-by-device, the above data is for reference to decide the resistor value. 2. Rp maximum value depends on the maximum permissible limit of tr. 3. IL is the total sum of the input currents of all devices tied to the R/B pin. P/N: PM2129 REV. 1.4, January. 20, 2017 69 MX30LF2G18AC MX30LF4G18AC Figure 43. R/B# Pin Timing Information @ Vcc = 3.3 V, Ta = 25°C, CL=100pF Tc 800 800ns 600 400 400ns 200 2k 4k 6k 8k Rp (ohm) @ Vcc = 3.3 V, Ta = 25°C, CL=100pF 1.6 ibusy 1mA 0.83 0.4mA 0.55 0.41 2k 4k 6k 8k Rp (ohm) VCC VCC Device Ready State Rp CL R/B# ~90% VCC ~90% VOH VOH VOL VOL ~10% VSS tf P/N: PM2129 Busy State ~10% tr REV. 1.4, January. 20, 2017 70 MX30LF2G18AC MX30LF4G18AC 8-2. Power On/Off Sequence After the Chip reaches the power on level (Vth = Vcc min.), the internal power on reset sequence will be triggered. During the internal power on reset period, no any external command is accepted. There are two ways to identify the termination of the internal power on reset sequence. Please refer to Figure 44. Power On/Off Sequence. • R/B# pin • Wait 1 ms During the power on and power off sequence, it is recommended to keep the WP# = Low for internal data protection. Figure 44. Power On/Off Sequence VCC (Min.) Vcc WP# CE# WE# 1 ms (Max.) 10us (Max.) R/B# P/N: PM2129 REV. 1.4, January. 20, 2017 71 MX30LF2G18AC MX30LF4G18AC 8-2-1. WP# Signal WP# going Low can cause program and erase operations automatically reset. The enabling & disabling of the both operations are as below: Figure 45-1. Enable Programming of WP# Signal WE# IO[7:0] WP# Figure 45-2. Disable Programming of WP# Signal 80h 10h tWW WE# IO[7:0] 80h 10h tWW WP# Figure 45-3. Enable Erasing of WP# Signal WE# IO[7:0] WP# Figure 45-4. Disable Erasing of WP# Signal 60h D0h tWW WE# IO[7:0] 60h D0h tWW WP# P/N: PM2129 REV. 1.4, January. 20, 2017 72 MX30LF2G18AC MX30LF4G18AC 9. SOFTWARE ALGORITHM 9-1. Invalid Blocks (Bad Blocks) The bad blocks are included in the device while it gets shipped. During the time of using the device, the additional bad blocks might be increasing; therefore, it is recommended to check the bad block marks and avoid using the bad blocks. Furthermore, please read out the bad block information before any erase operation since it may be cleared by any erase operation. Figure 46. Bad Blocks Bad Block Bad Block While the device is shipped, the value of all data bytes of the good blocks are FFh. The 1st byte of the 1st and 2nd page in the spare area for bad block will be 00h. The erase operation at the bad blocks is not recommended. After the device is installed in the system, the bad block checking is recommended. The figure shows the brief test flow by the system software managing the bad blocks while the bad blocks were found. When a block gets damaged, it should not be used any more. Due to the blocks are isolated from bit-line by the selected gate, the performance of good blocks will not be impacted by bad ones. Table 18. Valid Blocks Valid (Good) Block Number Density Min. 2Gb 4Gb Typ. Max. Unit 2008 2048 Block 4016 4096 Block P/N: PM2129 Remark Block 0 is guaranteed to be good upto 1K P/E cycle (with ECC). REV. 1.4, January. 20, 2017 73 MX30LF2G18AC MX30LF4G18AC 9-2. Bad Block Test Flow Although the initial bad blocks are marked by the flash vendor, they could be inadvertently erased and destroyed by a user that does not pay attention to them. To prevent this from occurring, it is necessary to always know where any bad blocks are located. Continually checking for bad block markers during normal use would be very time consuming, so it is highly recommended to initially locate all bad blocks and build a bad block table and reference it during normal NAND flash use. This will prevent having the initial bad block markers erased by an unexpected program or erase operation. Failure to keep track of bad blocks can be fatal for the application. For example, if boot code is programmed into a bad block, a boot up failure may occur. The following section shows the recommended flow for creating a bad block table. Figure 47. Bad Block Test Flow Start Block No. = 0 Yes (Note1) Read 00h Check Create (or Update) Bad Block Table No Block No. = 2047 Block No. = Block No. + 1 (Note2) No Yes End Note 1: Read 00h check is at the 1st byte of the 1st and 2nd pages of the block spare area. Note 2: The block No. = 2047 for 2Gb, 4095 for 4Gb. 9-3. Failure Phenomena for Read/Program/Erase Operations The device may fail during a Read, Program or Erase operation. The following possible failure modes should be considered when implementing a highly reliable system: Table 19. Failure Modes Failure Mode Detection and Countermeasure Sequence Erase Failure Status Read after Erase Block Replacement Programming Failure Read Failure Status Read after Program Read Failure Block Replacement ECC P/N: PM2129 REV. 1.4, January. 20, 2017 74 MX30LF2G18AC MX30LF4G18AC 9-4. Program It is feasible to reprogram the data into another page (Page B) when an error occurred in Page A by loading from an external buffer. Then create a bad block table or by using another appropriate scheme to prevent further system accesses to Page A. Figure 48. Failure Modes Program error occurs in Page A Buffer Memory Block Another good block Page B Figure 49. Program Flow Chart Start Command 80h Program Command Flow Set Address Write Data Write 10h Read Status Register No SR[6] = 1 ? (or R/B# = 1 ?) Yes * Program Error No SR[0] = 0 ? Yes Program Completed 9-5. Erase To prevent future accesses to this bad block, it is feasible to create a table within the system or by using another appropriate scheme when an error occurs in an Erase operation. P/N: PM2129 REV. 1.4, January. 20, 2017 75 MX30LF2G18AC MX30LF4G18AC Figure 50. Erase Flow Chart Start Command 60h Set Block Address Command D0h Read Status Register No SR[6] = 1 ? (or R/B# = 1 ?) Yes No SR[0] = 0 ? * Erase Error Yes Erase Completed * The failed blocks will be identified and given errors in status register bits for attempts on erasing them. Figure 51. Read Flow Chart Start Command 00h Set Address Command 30h Read Status Register SR[6] = 1 ? (or R/B# = 1 ?) No Yes Read Data Out ECC Generation ECC handling by the host controller Verify ECC No Reclaim the Error Yes Page Read Completed P/N: PM2129 REV. 1.4, January. 20, 2017 76 MX30LF2G18AC MX30LF4G18AC 10. PACKAGE INFORMATION P/N: PM2129 REV. 1.4, January. 20, 2017 77 MX30LF2G18AC MX30LF4G18AC Title: Package Outline for 63-VFBGA (9x11x1.0mm, Ball-pitch: 0.8mm, Ball-diameter: 0.45mm) P/N: PM2129 REV. 1.4, January. 20, 2017 78 MX30LF2G18AC MX30LF4G18AC 11. REVISION HISTORY Rev. No. Descriptions Page Date 0.01 Modified title from Advanced Information to Preliminary ALL JUL/04/2014 0.02 1. Added the tRC spec for 4Gb and related ID value P6, 7, 33, SEP/05/2014 2. Revised typical spec of tCBSY/tRCBSY= 5us/3.5us 3. Revised the IO3 of feature address 90h from"x" to "Reserved (0)" P47 4. Removed redundant DNU from pin description 1.0 1. Removed Advanced information title of 2Gb. And revised the 4Gb from "advanced information" to "Preliminary information". P63 P11 P6, 8 2. Corrected tALS timing waveform as ALE high till WE# high P26, 54 1.1 1. Removed "preliminary information" from 4Gb P6, 8 2. ICC1/ICC2 (typical) are improved from 20mA to 15mA P62 1.2 1. Corrected waveform of OTP protection tWB timing from WE# high to busy P54 2. Supplemented with Figure 34. PT pin and Block Protection Mode Operation 3. Revised the bad block mark from non-FFh to 00h, P72, 73 also revised the page of bad block mark from 1st or 2nd page to 1st and 2nd page OCT/23/2014 NOV/18/2014 JAN/06/2015 P56 1.3 1. Added Overshoot/Undershoot waveforms. P62 JUL/10/2015 2. Removed redundant Note mark for Table 15. P65 3. Added traditional two-plane operation P57, 61, 62 4. Align the term of "plane1" & "plane 2" as "plane 0" & "plane 1" P60 1.4 1. Added a product statement for Ordering Information P8 2. Added the tRST=5us for the device reset time from idle P66 3. Modification of the power-on/off sequence: supplement the CE# signal, supplement the WE# single waveform with WE#=0 without toggle during the power-on period. P71 P/N: PM2129 JAN/20/2017 REV. 1.4, January. 20, 2017 79 MX30LF2G18AC MX30LF4G18AC Except for customized products which have been expressly identified in the applicable agreement, Macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. In the event Macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or distributors shall be released from any and all liability arisen therefrom. Copyright© Macronix International Co., Ltd. 2017. All rights reserved, including the trademarks and tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, Nbit, Macronix NBit, eLiteFlash, HybridNVM, HybridFlash, HybridXFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC, Kingtech, MXSMIO, Macronix vEE, Macronix MAP, Rich Book, Rich TV, OctaRAM, OctaBus, OctaFlash and FitCAM. The names and brands of third party referred thereto (if any) are for identification purposes only. For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com MACRONIX INTERNATIONAL CO., LTD. http://www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. P/N: PM2129 REV. 1.4, January. 20, 2017 80