MX66L51235FZ2I-10G

MX66L51235F (J Grade) MX66L51235F - J Grade 3V, 512M-BIT [x 1/x 2/x 4] CMOS MXSMIO® (SERIAL MULTI I/O) FLASH MEMORY Key Features • J Grade (Temperature = -40°C to 105°C) • Multi I/O Support - Single I/O, Dual I/O and Quad I/O • Quad Peripheral Interface (QPI) Mode • Program Suspend/Resume & Erase Suspend/Resume P/N: PM2003 MX66L51235F (J Grade) Contents 1. FEATURES............................................................................................................................................................... 4 2. GENERAL DESCRIPTION...................................................................................................................................... 6 Table 1. Read performance Comparison.....................................................................................................6 3. PIN CONFIGURATIONS .......................................................................................................................................... 7 4. PIN DESCRIPTION................................................................................................................................................... 7 5. BLOCK DIAGRAM.................................................................................................................................................... 8 6. DATA PROTECTION................................................................................................................................................. 9 Table 2. Protected Area Sizes....................................................................................................................10 Table 3. 4K-bit Secured OTP Definition..................................................................................................... 11 7. Memory Organization............................................................................................................................................ 12 Table 4. Memory Organization...................................................................................................................12 8. DEVICE OPERATION............................................................................................................................................. 13 8-1. Address Protocol...................................................................................................................................... 15 8-2. Quad Peripheral Interface (QPI) Read Mode........................................................................................... 17 9. COMMAND DESCRIPTION.................................................................................................................................... 18 9-1. 9-2. 9-3. 9-4. 9-5. 9-6. 9-7. 9-8. 9-9. 9-10. 9-11. 9-12. 9-13. 9-14. 9-15. 9-16. 9-17. 9-18. 9-19. 9-20. 9-21. 9-22. 9-23. 9-24. P/N: PM2003 Table 5. Command Set...............................................................................................................................18 Write Enable (WREN)............................................................................................................................... 23 Write Disable (WRDI)................................................................................................................................ 24 Read Identification (RDID)........................................................................................................................ 25 Release from Deep Power-down (RDP), Read Electronic Signature (RES)............................................ 26 Read Electronic Manufacturer ID & Device ID (REMS)............................................................................ 28 QPI ID Read (QPIID)................................................................................................................................ 29 Table 6. ID Definitions ...............................................................................................................................29 Read Status Register (RDSR).................................................................................................................. 30 Read Configuration Register (RDCR)....................................................................................................... 31 Write Status Register (WRSR).................................................................................................................. 37 Table 7. Protection Modes..........................................................................................................................38 Enter 4-byte mode (EN4B)....................................................................................................................... 41 Exit 4-byte mode (EX4B).......................................................................................................................... 41 Read Data Bytes (READ)......................................................................................................................... 42 Read Data Bytes at Higher Speed (FAST_READ)................................................................................... 43 Dual Output Read Mode (DREAD)........................................................................................................... 44 2 x I/O Read Mode (2READ).................................................................................................................... 45 Quad Read Mode (QREAD)..................................................................................................................... 46 4 x I/O Read Mode (4READ).................................................................................................................... 47 4 Byte Address Command Set.................................................................................................................. 49 Burst Read................................................................................................................................................ 51 Performance Enhance Mode.................................................................................................................... 52 Performance Enhance Mode Reset.......................................................................................................... 55 Fast Boot.................................................................................................................................................. 57 Sector Erase (SE)..................................................................................................................................... 60 Block Erase (BE32K)................................................................................................................................ 61 2 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-25. 9-26. 9-27. 9-28. 9-29. 9-30. 9-31. 9-32. 9-33. Block Erase (BE)...................................................................................................................................... 62 Chip Erase (CE)........................................................................................................................................ 63 Page Program (PP).................................................................................................................................. 64 4 x I/O Page Program (4PP)..................................................................................................................... 66 Deep Power-down (DP)............................................................................................................................ 67 Enter Secured OTP (ENSO)..................................................................................................................... 68 Exit Secured OTP (EXSO)........................................................................................................................ 68 Read Security Register (RDSCUR).......................................................................................................... 68 Write Security Register (WRSCUR).......................................................................................................... 68 Table 8. Security Register Definition..........................................................................................................69 9-34. Write Protection Selection (WPSEL)......................................................................................................... 70 9-35. Advanced Sector Protection..................................................................................................................... 72 9-36. Program/Erase Suspend/Resume............................................................................................................ 80 9-37. Erase Suspend......................................................................................................................................... 80 9-38. Program Suspend..................................................................................................................................... 80 9-39. Write-Resume........................................................................................................................................... 82 9-40. No Operation (NOP)................................................................................................................................. 82 9-41. Software Reset (Reset-Enable (RSTEN) and Reset (RST)).................................................................... 82 9-42. Read SFDP Mode (RDSFDP)................................................................................................................... 84 Table 9. Signature and Parameter Identification Data Values ...................................................................85 Table 10. Parameter Table (0): JEDEC Flash Parameter Tables...............................................................86 Table 11. Parameter Table (1): Macronix Flash Parameter Tables.............................................................88 10. RESET.................................................................................................................................................................. 90 Table 12. Reset Timing-(Power On)...........................................................................................................90 Table 13. Reset Timing-(Other Operation).................................................................................................90 11. POWER-ON STATE.............................................................................................................................................. 91 12. ELECTRICAL SPECIFICATIONS......................................................................................................................... 92 Table 14. ABSOLUTE MAXIMUM RATINGS.............................................................................................92 Table 15. CAPACITANCE TA = 25°C, f = 1.0 MHz.....................................................................................92 Table 16. DC CHARACTERISTICS (Temperature = -40°C to 105°C, VCC = 2.7V ~ 3.6V) ......................94 Table 17. AC CHARACTERISTICS (Temperature = -40°C to 105°C, VCC = 2.7V ~ 3.6V) .....................95 13. OPERATING CONDITIONS.................................................................................................................................. 96 Table 18. Power-Up/Down Voltage and Timing .........................................................................................98 13-1. INITIAL DELIVERY STATE....................................................................................................................... 98 14. ERASE AND PROGRAMMING PERFORMANCE............................................................................................... 99 15. DATA RETENTION............................................................................................................................................... 99 16. LATCH-UP CHARACTERISTICS......................................................................................................................... 99 17. ORDERING INFORMATION............................................................................................................................... 100 18. PART NAME DESCRIPTION.............................................................................................................................. 101 19. PACKAGE INFORMATION................................................................................................................................. 102 20. REVISION HISTORY .......................................................................................................................................... 103 P/N: PM2003 3 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 3V 512M-BIT [x 1/x 2/x 4] CMOS MXSMIO® (SERIAL MULTI I/O) FLASH MEMORY 1. FEATURES GENERAL • Serial Peripheral Interface compatible -- Mode 0 and Mode 3 • Single Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations • 512Mb: 536,870,912 x 1 bit structure or 268,435,456 x 2 bits (two I/O mode) structure or 134,217,728 x 4 bits (four I/O mode) structure • Protocol Support - Single I/O, Dual I/O and Quad I/O • Latch-up protected to 100mA from -1V to Vcc +1V • Low Vcc write inhibit is from 2.3V to 2.5V • Fast read for SPI mode - Support clock frequency up to 133MHz for all protocols - Support Fast Read, 2READ, DREAD, 4READ, QREAD instructions. - Configurable dummy cycle number for fast read operation • Quad Peripheral Interface (QPI) available • Equal Sectors with 4K byte each, or Equal Blocks with 32K byte each or Equal Blocks with 64K byte each - Any Block can be erased individually • Programming : - 256byte page buffer - Quad Input/Output page program(4PP) to enhance program performance • Typical 100,000 erase/program cycles • 20 years data retention SOFTWARE FEATURES • Input Data Format - 1-byte Command code • Advanced Security Features - Block lock protection The BP0-BP3 and T/B status bits define the size of the area to be protected against program and erase instructions - Advanced sector protection function (Solid and Password Protect) • Additional 4K bit security OTP - Features unique identifier - Factory locked identifiable, and customer lockable • Command Reset • Program/Erase Suspend and Resume operation • Electronic Identification - JEDEC 1-byte manufacturer ID and 2-byte device ID - RES command for 1-byte Device ID - REMS command for 1-byte manufacturer ID and 1-byte device ID • Support Serial Flash Discoverable Parameters (SFDP) mode P/N: PM2003 4 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) HARDWARE FEATURES • SCLK Input - Serial clock input • SI/SIO0 - Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode • SO/SIO1 - Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode • WP#/SIO2 - Hardware write protection or serial data Input/Output for 4 x I/O read mode • DNU/SIO3 - Do not use or serial data Input/Output for 4 x I/O read mode • RESET# - Hardware Reset pin • PACKAGE -16-pin SOP (300mil) -All devices are RoHS Compliant and Halogen-free P/N: PM2003 5 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 2. GENERAL DESCRIPTION MX66L51235F is 512Mb bits Serial Flash memory, which is configured as 67,108,864 x 8 internally. When it is in two or four I/O mode, the structure becomes 268,435,456 bits x 2 or 134,217,728 bits x 4. MX66L51235F features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single I/O mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input. When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# and RESET# pin become SIO0 pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output. The MX66L51235F MXSMIO® (Serial Multi I/O) provides sequential read operation on the whole chip. After program/erase command is issued, auto program/erase algorithms which program/erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256 bytes) basis, or word basis. Erase command is executed on 4K-byte sector, 32K-byte block, or 64K-byte block, or whole chip basis. To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. Advanced security features enhance the protection and security functions, please see security features section for more details. When the device is not in operation and CS# is high, it is put in standby mode. The MX66L51235F utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles. Table 1. Read performance Comparison Numbers of Dummy Cycles Fast Read (MHz) Dual Output Fast Read (MHz) Quad Output Fast Read (MHz) Dual IO Fast Read (MHz) Quad IO Fast Read (MHz) 4 - - - 84* 70 6 104 104 84 104 84* 8 104* 104* 104* 104 104 10 133 133 133 133 133 Note: * mean default status P/N: PM2003 6 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 4. PIN DESCRIPTION 3. PIN CONFIGURATIONS 16-PIN SOP (300mil) DNU/SIO3 VCC RESET# NC NC NC CS# SO/SIO1 1 2 3 4 5 6 7 8 SYMBOL CS# 16 15 14 13 12 11 10 9 SCLK SI/SIO0 NC NC NC NC GND WP#/SIO2 SI/SIO0 SO/SIO1 SCLK WP#/SIO2 RESET# DNU/SIO3 Note 2 VCC GND DESCRIPTION Chip Select Serial Data Input (for 1 x I/O)/ Serial Data Input & Output (for 2xI/O or 4xI/O read mode) Serial Data Output (for 1 x I/O)/ Serial Data Input & Output (for 2xI/O or 4xI/O read mode) Clock Input Write protection: connect to GND or Serial Data Input & Output (for 4xI/O read mode) Hardware Reset Pin Active low Note 1 Do Not Use or Serial Data Input & Output (for 4xI/O read mode) + 3V Power Supply Ground Notes: (1). RESET# pin has internal pull up. (2). When using 1 I/O or 2 I/O (QE bit not enabled), the DNU/SIO3 pin can not connect to GND. We suggest user to connect this pin to VCC or floating. P/N: PM2003 7 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 5. BLOCK DIAGRAM X-Decoder Address Generator SI/SIO0 SO/SIO1 SIO2 * DNU/SIO3 * WP# * HOLD# * RESET# * CS# SCLK Memory Array Y-Decoder Data Register Sense Amplifier SRAM Buffer Mode Logic State Machine HV Generator Clock Generator Output Buffer * Depends on part number options. P/N: PM2003 8 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 6. DATA PROTECTION During power transition, there may be some false system level signals which result in inadvertent erasure or programming. The device is designed to protect itself from these accidental write cycles. The state machine will be reset as standby mode automatically during power up. In addition, the control register architecture of the device constrains that the memory contents can only be changed after specific command sequences have completed successfully. In the following, there are several features to protect the system from the accidental write cycles during VCC powerup and power-down or from system noise. • Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary. • Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other command to change data. • Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing all commands except Release from deep power down mode command (RDP) and Read Electronic Signature command (RES), and softreset command. • Advanced Security Features: there are some protection and security features which protect content from inadvertent write and hostile access. I. Block lock protection - The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0 and T/B) bits to allow part of memory to be protected as read only. The protected area definition is shown as Table 2 Protected Area Sizes, the protected areas are more flexible which may protect various area by setting value of BP0-BP3 bits. - The Hardware Proteced Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and Status Register Write Protect bit. - In four I/O and QPI mode, the feature of HPM will be disabled. P/N: PM2003 9 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) Table 2. Protected Area Sizes Protected Area Sizes (T/B bit = 0) Status bit BP3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BP2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BP1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BP0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Protect Level 512Mb 0 (none) 1 (1 block, protected block 1023rd) 2 (2 blocks, protected block 1022nd~1023rd) 3 (4 blocks, protected block 1020th~1023rd) 4 (8 blocks, protected block 1016th~1023rd) 5 (16 blocks, protected block 1008th~1023rd) 6 (32 blocks, protected block 992nd~1023rd) 7 (64 blocks, protected block 960th~1023rd) 8 (128 blocks, protected block 896th~1023rd) 9 (256 blocks, protected block 768th~1023rd) 10 (512 blocks, protected block 512nd~1023rd) 11 (1024 blocks, protected all) 12 (1024 blocks, protected all) 13 (1024 blocks, protected all) 14 (1024 blocks, protected all) 15 (1024 blocks, protected all) Protected Area Sizes (T/B bit = 1) Status bit BP3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 P/N: PM2003 BP2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BP1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Protect Level BP0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 512Mb 0 (none) 1 (1 block, protected block 0th) 2 (2 blocks, protected block 0th~1th) 3 (4 blocks, protected block 0th~3rd) 4 (8 blocks, protected block 0th~7th) 5 (16 blocks, protected block 0th~15th) 6 (32 blocks, protected block 0th~31st) 7 (64 blocks, protected block 0th~63rd) 8 (128 blocks, protected block 0th~127th) 9 (256 blocks, protected block 0th~255th) 10 (512 blocks, protected block 0th~511st) 11 (1024 blocks, protected all) 12 (1024 blocks, protected all) 13 (1024 blocks, protected all) 14 (1024 blocks, protected all) 15 (1024 blocks, protected all) 10 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) II. Additional 4K-bit secured OTP for unique identifier: to provide 4K-bit one-time program area for setting device unique serial number - Which may be set by factory or system customer. - Security register bit 0 indicates whether the chip is locked by factory or not. - To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with Enter Security OTP command), and going through normal program procedure, and then exiting 4K-bit secured OTP mode by writing Exit Security OTP command. - Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register) command to set customer lock-down bit1 as "1". Please refer to "Table 8. Security Register Definition" for security register bit definition and "Table 3. 4K-bit Secured OTP Definition" for address range definition. - Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit secured OTP mode, array access is not allowed. Table 3. 4K-bit Secured OTP Definition Address range Size Standard Factory Lock xxx000~xxx00F 128-bit ESN (electrical serial number) xxx010~xxx1FF 3968-bit N/A P/N: PM2003 11 Customer Lock Determined by customer REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 7. Memory Organization Table 4. Memory Organization Sector 1021 2042 … 3FF0000h 3FF0FFFh 16367 3FEF000h 3FEFFFFh … 16368 … individual 16 sectors lock/unlock unit:4K-byte … … … … 3FF7FFFh 3FE8000h 3FE8FFFh 16359 3FE7000h 3FE7FFFh … 16360 3FE0000h 3FE0FFFh 16351 3FDF000h 3FDFFFFh … 16352 16344 3FD8000h 3FD8FFFh 16343 3FD7000h 3FD7FFFh … 2043 3FF7000h … 2044 individual block lock/unlock unit:64K-byte 16375 … 1022 3FF8FFFh … 2045 3FF8000h … 2046 16376 … 1023 3FFFFFFh … 2047 Address Range 3FFF000h … 16383 … Block(64K-byte) Block(32K-byte) 16336 3FD0000h 3FD0FFFh 47 002F000h 002FFFFh P/N: PM2003 … … … … 0020FFFh 001F000h 001FFFFh … 0020000h 31 0018000h 0018FFFh 23 0017000h 0017FFFh … 24 0010FFFh 000F000h 000FFFFh … 0010000h 15 … 16 8 0008000h 0008FFFh 7 0007000h 0007FFFh … … … 0 0 32 … 1 0027FFFh … 1 2 0028FFFh 027000h … 3 0028000h 39 … 4 individual block lock/unlock unit:64K-byte 40 … 2 … 5 … individual block lock/unlock unit:64K-byte 0 0000000h 0000FFFh 12 individual 16 sectors lock/unlock unit:4K-byte REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 8. DEVICE OPERATION 1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation. 2. When incorrect command is inputted to this device, this device becomes standby mode and keeps the standby mode until next CS# falling edge. In standby mode, SO pin of this device should be High-Z. 3. When correct command is inputted to this device, this device becomes active mode and keeps the active mode until next CS# rising edge. 4. Input data is latched on the rising edge of Serial Clock (SCLK) and data shifts out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as "Serial Modes Supported". 5. For the following instructions: RDID, RDSR, RDSCUR, READ/READ4B, FAST_READ/FAST_READ4B, 2READ/2READ4B, DREAD/DREAD4B, 4READ/4READ4B, QREAD/QREAD4B, RDSFDP, RES, REMS, QPIID, RDDPB, RDSPB, RDPASS, RDLR, RDEAR, RDFBR, RDSPBLK, RDCR, the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE/SE4B, BE32K/BE32K4B, BE/BE4B, CE, PP/PP4B, 4PP/4PP4B, DP, ENSO, EXSO, WRSCUR, EN4B, EX4B, WPSEL, GBLK, GBULK, SPBLK, SUSPEND, RESUME, NOP, RSTEN, RST, EQIO, RSTQIO the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglected and not affect the current operation of Write Status Register, Program, Erase. Figure 1. Serial Modes Supported CPOL CPHA shift in (Serial mode 0) 0 0 SCLK (Serial mode 3) 1 1 SCLK SI shift out MSB SO MSB Note: CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is supported. P/N: PM2003 13 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) Figure 2. Serial Input Timing tSHSL CS# tCHSL tSLCH tCHSH tSHCH SCLK tDVCH tCHCL tCHDX tCLCH LSB MSB SI High-Z SO Figure 3. Output Timing CS# tCH SCLK tCLQV tCLQX tCL tCLQV tCLQX LSB SO SI P/N: PM2003 tSHQZ ADDR.LSB IN 14 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 8-1. Address Protocol The original 24 bit address protocol of serial Flash can only access density size below 128Mb. For the memory above 128Mb, the 32bit address is requested for access higher memory size. The MX66L51235F has three different methods ot access the whole density: (1)Command entry 4-byte address mode (2)Extended Address Register (EAR) (3)4-byte Address Command Set Enter 4-Byte Address Mode In 4-byte Address mode, all instructions are 32-bits address clock cycles. Two dedicated instructions are available to enter/exit this modality: ● Enter 4-byte address mode (EN4B) ● Exit 4-byte address mode (EX4B) When 4-byte address mode is enabled, the EAR becomes "don't care" for all instructions requiring 4-byte address. Extended Address Register (Configurable) The device provides an 8-bit volatile register for extended Address Register: it indentifies the extended address (A31~A24) above 128Mb density by using original 3-byte address. Extended Address Register (EAR) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 A31 A30 A29 A28 A27 A26 A25 A24 For the MX66L51235F the A31 to A26 are Don’t Care. During EAR, reading these bits will read as 0. The bit is default as "0". P/N: PM2003 15 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) Figure 4. EAR Operation Segments 03FFFFFFh EAR= 11 03000000h 02FFFFFFh EAR= 10 02000000h 01FFFFFFh EAR= 01 01000000h 00FFFFFFh EAR= 00 00000000h When under EAR mode, Read, Program, Erase operates in the selected segment by using 3-byte address mode. For the read operation, the whole array data can be continually read out with one command. Data output starts from the selected 128Mb, but it can cross the boundary. When the last byte of the segment is reached, the next byte (in a continuous reading) is the first byte of the next segment. However, the EAR (Extended Address Register) value does not change. The random access reading can only be operated in the selected segment. The Chip erase command will erase the whole chip and is not limited by EAR selected segment. P/N: PM2003 16 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 8-2. Quad Peripheral Interface (QPI) Read Mode QPI protocol enables user to take full advantage of Quad I/O Serial Flash by providing the Quad I/O interface in command cycles, address cycles and as well as data output cycles. Enable QPI mode By issuing 35H command, the QPI mode is enabled. After QPI mode is enabled, the device enters quad mode (4-4-4) without QE bit status changed. Figure 5. Enable QPI Sequence CS# MODE 3 SCLK 0 1 2 3 4 5 6 7 MODE 0 SIO0 35h SIO[3:1] Reset QPI (RSTQIO) To reset the QPI mode, the RSTQIO (F5H) command is required. After the RSTQIO command is issued, the device returns from QPI mode (4 I/O interface in command cycles) to SPI mode (1 I/O interface in command cycles). Note: For EQIO and RSTQIO commands, CS# high width has to follow "write spec" tSHSL for next instruction. Figure 6. Reset QPI Mode CS# SCLK SIO[3:0] P/N: PM2003 F5h 17 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9. COMMAND DESCRIPTION Table 5. Command Set Read/Write Array Commands Command (byte) READ (normal read) FAST READ (fast read data) Mode 1st byte SPI 3/4 03 (hex) SPI 3/4 0B (hex) 2nd byte ADD1 3rd byte 4th byte Address Bytes 2READ DREAD (1I 2O read) 4READ QREAD (1I 4O read) SPI 3/4 BB (hex) SPI 3/4 3B (hex) SPI/QPI 3/4 EB (hex) SPI 3/4 6B (hex) ADD1 ADD1 ADD1 ADD1 ADD1 ADD2 ADD2 ADD2 ADD2 ADD2 ADD2 ADD3 ADD3 ADD3 ADD3 ADD3 ADD3 Dummy* Dummy* Dummy* Dummy* Dummy* n bytes read out until CS# goes high n bytes read out by 2 x I/O until CS# goes high n bytes read out by Dual output until CS# goes high Quad I/O read with 6 dummy cycles n bytes read out by Quad output until CS# goes high BE 32K (block erase 32KB) SPI/QPI BE (block erase 64KB) SPI/QPI 5th byte (2 x I/O read command) Data Cycles Action n bytes read out until CS# goes high Command (byte) PP (page program) Mode SPI/QPI 4PP (quad page program) SPI SE (sector erase) SPI/QPI CE (chip erase) SPI/QPI Address Bytes 3/4 3/4 3/4 3/4 3/4 0 1st byte 02 (hex) 38 (hex) 20 (hex) 52 (hex) D8 (hex) 60 or C7 (hex) 2nd byte ADD1 ADD1 ADD1 ADD1 3rd byte ADD2 ADD2 ADD2 ADD2 4th byte ADD3 ADD3 ADD3 ADD3 1-256 quad input to program the selected page to erase the selected sector to erase the selected 32K block to erase the selected block 5th byte Data Cycles Action 1-256 to program the selected page to erase whole chip * Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in configuration register. P/N: PM2003 18 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) Read/Write Array Commands (4 Byte Address Command Set) Command (byte) Mode READ4B FAST READ4B 2READ4B DREAD4B 4READ4B QREAD4B Address Bytes SPI 4 SPI 4 SPI 4 SPI 4 SPI/QPI 4 SPI 4 1st byte 13 (hex) 0C (hex) BC (hex) 3C (hex) EC (hex) 6C (hex) 2nd byte ADD1 ADD1 ADD1 ADD1 ADD1 ADD1 3rd byte ADD2 ADD2 ADD2 ADD2 ADD2 ADD2 4th byte ADD3 ADD3 ADD3 ADD3 ADD3 ADD3 5th byte ADD4 6th byte ADD4 ADD4 ADD4 ADD4 ADD4 Dummy Dummy Dummy Dummy Dummy Data Cycles Action Command (byte) read data byte by read data byte by read data byte by Read data byte by read data byte by Read data byte by 4 byte address 4 byte address 2 x I/O with 4 byte Dual Output with 4 x I/O with 4 byte Quad Output with address 4 byte address address 4 byte address SPI 4 BE4B (block erase 64KB) SPI/QPI 4 BE32K4B (block erase 32KB) SPI/QPI 4 SE4B (Sector erase 4KB) SPI/QPI 4 PP4B 4PP4B Address Bytes SPI/QPI 4 Mode 1st byte 12 (hex) 3E (hex) DC (hex) 5C (hex) 21 (hex) 2nd byte ADD1 ADD1 ADD1 ADD1 ADD1 3rd byte ADD2 ADD2 ADD2 ADD2 ADD2 4th byte ADD3 ADD3 ADD3 ADD3 ADD3 5th byte ADD4 ADD4 ADD4 ADD4 ADD4 1-256 to program the selected page with 4byte address 1-256 Quad input to program the selected page with 4byte address to erase the selected (64KB) block with 4byte address 6th byte Data Cycles Action P/N: PM2003 19 to erase the to erase the selected (32KB) selected (4KB) block with 4byte sector with 4byte address address REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) Register/Setting Commands Mode SPI/QPI SPI/QPI SPI/QPI RDCR (read configuration register) SPI/QPI 1st byte 06 (hex) 04 (hex) 05 (hex) 15 (hex) Command (byte) WREN WRDI (write enable) (write disable) RDSR (read status register) WRSR RDEAR WREAR (write status/ (read extended (write extended configuration address address register) register) register) SPI/QPI SPI/QPI SPI/QPI 01 (hex) 2nd byte Values 3rd byte Values C8 (hex) C5 (hex) 4th byte 5th byte Data Cycles Action sets the (WEL) resets the to read out the to read out the write enable (WEL) write values of the values of the latch bit enable latch bit status register configuration register Command (byte) WPSEL (Write Protect Selection) EQIO (Enable QPI) Mode 1st byte SPI/QPI 68 (hex) SPI 35 (hex) Action to enter and enable individal block protect mode Entering the QPI mode Command (byte) DP (Deep power down) Mode 1st byte 1-2 to write new values of the status/ configuration register RSTQIO (Reset QPI) EN4B (enter 4-byte mode) EX4B (exit 4-byte mode) QPI F5 (hex) SPI/QPI B7 (hex) SPI/QPI E9 (hex) 1 read extended write extended address address register register PGM/ERS Suspend (Suspends Program/ Erase) SPI/QPI B0 (hex) PGM/ERS Resume (Resumes Program/ Erase) SPI/QPI 30 (hex) 2nd byte 3rd byte 4th byte 5th byte Data Cycles Exiting the QPI to enter 4-byte to exit 4-byte mode mode and set mode and clear 4BYTE bit as 4BYTE bit to "1" be "0" SPI/QPI B9 (hex) RDP (Release from deep power down) SPI/QPI AB (hex) SBL (Set Burst Length) SPI/QPI C0 (hex) enters deep power down mode release from deep power down mode to set Burst length RDFBR WRFBR ESFBR (read fast boot (write fast boot (erase fast register) register) boot register) SPI SPI SPI 16(hex) 17(hex) 18(hex) 2nd byte 3rd byte 4th byte 5th byte Data Cycles Action P/N: PM2003 1-4 20 4 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) ID/Security Commands Command (byte) Mode Address Bytes 1st byte REMS RDID RES (read electronic QPIID (read identific- (read electronic manufacturer & (QPI ID Read) ation) ID) device ID) SPI SPI/QPI SPI QPI 0 0 0 0 9F (hex) AB (hex) 90 (hex) AF (hex) 2nd byte x 3rd byte x 4th byte Address Bytes SPI/QPI 0 1st byte 2B (hex) 2F (hex) Mode RDSCUR (read security register) EXSO (exit secured OTP) SPI/QPI 3 5A (hex) SPI/QPI 0 B1 (hex) SPI/QPI 0 C1 (hex) ADD1 x ADD2 ADD1 (Note 1) ADD3 outputs JEDEC to read out output the ID: 1-byte 1-byte Device Manufacturer Manufacturer ID ID & Device ID ID & 2-byte Device ID WRSCUR (write security register) SPI/QPI 0 Command (byte) ENSO (enter secured OTP) x 5th byte Action RDSFDP Dummy (8) Read SFDP mode ID in QPI interface to enter the to exit the 4K-bit secured 4K-bit secured OTP mode OTP mode SPI 0 WRPASS (write password register) SPI 0 RDPASS (read password register) SPI 0 2C (hex) 2D (hex) 28 (hex) 27 (hex) 2 2 1-8 1-8 GBLK (gang block lock) GBULK (gang block unlock) WRLR (write Lock register) RDLR (read Lock register) SPI/QPI 0 SPI/QPI 0 SPI 0 7E (hex) 98 (hex) 2nd byte 3rd byte 4th byte 5th byte Data Cycles Action whole chip to read value to set the of security lock-down bit write protect register as "1" (once lock-down, cannot be updated) whole chip unprotect Address Bytes PASSULK (password unlock) SPI 0 WRSPB (SPB bit program) SPI 4 ESSPB (all SPB bit erase) SPI 0 RDSPB (read SPB status) SPI 4 SPBLK (SPB lock set) SPI 0 1st byte 29 (hex) E3 (hex) E4 (hex) E2 (hex) A6 (hex) Command (byte) Mode RDSPBLK WRDPB (SPB lock (write DPB register read) register) SPI SPI 0 4 A7 (hex) RDDPB (read DPB register) SPI 4 E1 (hex) E0 (hex) 2nd byte ADD1 ADD1 ADD1 ADD1 3rd byte ADD2 ADD2 ADD2 ADD2 4th byte ADD3 ADD3 ADD3 ADD3 5th byte ADD4 ADD4 ADD4 ADD4 1 1 Data Cycles 8 1 2 Action P/N: PM2003 21 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) Reset Commands Mode SPI/QPI SPI/QPI RST (Reset Memory) SPI/QPI 1st byte 00 (hex) 66 (hex) 99 (hex) Command (byte) NOP RSTEN (No Operation) (Reset Enable) 2nd byte 3rd byte 4th byte 5th byte Action Note 1: The count base is 4-bit for ADD(2) and Dummy(2) because of 2 x I/O. And the MSB is on SO/SIO1 which is different from 1 x I/O condition. Note 2: ADD=00H will output the manufacturer ID first and AD=01H will output device ID first. Note 3: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden mode. Note 4: Before executing RST command, RSTEN command must be executed. If there is any other command to interfere, the reset operation will be disabled. Note 5: The number in parentheses after "ADD" or "Data" stands for how many clock cycles it has. For example, "Data(8)" represents there are 8 clock cycles for the data in. Please note the number after "ADD" are based on 3-byte address mode, for 4-byte address mode, which will be increased. P/N: PM2003 22 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-1. Write Enable (WREN) The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP/ PP4B, 4PP/4PP4B, SE/SE4B, BE32K/BE32K4B, BE/BE4B, CE, and WRSR, which are intended to change the device content WEL bit should be set every time after the WREN instruction setting the WEL bit. The sequence of issuing WREN instruction is: CS# goes low→sending WREN instruction code→ CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care in SPI mode. Figure 7. Write Enable (WREN) Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 SCLK Mode 0 Command SI 06h High-Z SO Figure 8. Write Enable (WREN) Sequence (QPI Mode) CS# 0 Mode 3 1 SCLK Mode 0 Command 06h SIO[3:0] P/N: PM2003 23 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-2. Write Disable (WRDI) The Write Disable (WRDI) instruction is to reset Write Enable Latch (WEL) bit. The sequence of issuing WRDI instruction is: CS# goes low→sending WRDI instruction code→CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care in SPI mode. The WEL bit is reset by following situations: - Power-up - Reset# pin driven low - WRDI command completion - WRSR command completion - PP/PP4B command completion - 4PP/4PP4B command completion - SE/SE4B command completion - BE32K/BE32K4B command completion - BE/BE4B command completion - CE command completion - PGM/ERS Suspend command completion - Reset command completion - WRSCUR command completion - WPSEL command completion - GBLK command completion - GBULK command completion - WREAR command completion - WRLR command completion - WRPASS command completion - PASSULK command completion - SPBLK command completion - WRSPB command completion - ESSPB command completion - WRDPB command completion - WRFBR command completion - ESFBR command completion Figure 9. Write Disable (WRDI) Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 SCLK Mode 0 SI SO P/N: PM2003 Command 04h High-Z 24 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) Figure 10. Write Disable (WRDI) Sequence (QPI Mode) CS# 0 Mode 3 1 SCLK Mode 0 Command 04h SIO[3:0] 9-3. Read Identification (RDID) The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Macronix Manufacturer ID and Device ID are listed as Table 6 ID Definitions. The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code→24-bits ID data out on SO→ to end RDID operation can drive CS# to high at any time during data out. While Program/Erase operation is in progress, it will not decode the RDID instruction, therefore there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage. Figure 11. Read Identification (RDID) Sequence (SPI mode only) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 28 29 30 31 SCLK Mode 0 Command SI 9Fh Manufacturer Identification SO High-Z 7 6 5 2 MSB P/N: PM2003 1 Device Identification 0 15 14 13 3 2 1 0 MSB 25 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-4. Release from Deep Power-down (RDP), Read Electronic Signature (RES) The Release from Deep Power-down (RDP) instruction is completed by driving Chip Select (CS#) High. When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2(max), as specified in Table 17 AC Characteristics. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. The RDP instruction is only for releasing from Deep Power Down Mode. Reset# pin goes low will release the Flash from deep power down mode. RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as Table 6 ID Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new design, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction. Figure 12. Read Electronic Signature (RES) Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 SCLK Mode 0 Command SI ABh tRES2 3 Dummy Bytes 23 22 21 3 2 1 0 MSB SO Electronic Signature Out High-Z 7 6 5 4 3 2 1 0 MSB Deep Power-down Mode P/N: PM2003 26 Stand-by Mode REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) Figure 13. Read Electronic Signature (RES) Sequence (QPI Mode) CS# MODE 3 0 1 2 3 4 5 6 7 SCLK MODE 0 3 Dummy Bytes Command SIO[3:0] X ABh X X X X X H0 L0 MSB LSB Data In Data Out Stand-by Mode Deep Power-down Mode Figure 14. Release from Deep Power-down (RDP) Sequence (SPI Mode) CS# 0 Mode 3 1 2 3 4 5 6 tRES1 7 SCLK Mode 0 Command SI ABh High-Z SO Deep Power-down Mode Stand-by Mode Figure 15. Release from Deep Power-down (RDP) Sequence (QPI Mode) CS# Mode 3 tRES1 0 1 SCLK Mode 0 Command SIO[3:0] ABh Deep Power-down Mode P/N: PM2003 27 Stand-by Mode REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-5. Read Electronic Manufacturer ID & Device ID (REMS) The REMS instruction is an alternative to the Release from Power-down/Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. The REMS instruction is very similar to the Release from Power-down/Device ID instruction. The instruction is initiated by driving the CS# pin low and shift the instruction code "90h" followed by two dummy bytes and one bytes address (A7~A0). After which, the Manufacturer ID for Macronix (C2h) and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first. The Device ID values are listed in Table 6 of ID Definitions. If the one-byte address is initially set to 01h, then the device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high. Figure 16. Read Electronic Manufacturer & Device ID (REMS) Sequence (SPI Mode only) CS# SCLK Mode 3 0 1 2 Mode 0 3 4 5 6 7 8 Command SI 9 10 2 Dummy Bytes 15 14 13 90h 3 2 1 0 High-Z SO CS# 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK ADD (1) SI 7 6 5 4 3 2 1 0 Manufacturer ID SO 7 6 5 4 3 2 1 Device ID 0 7 6 5 4 3 2 MSB MSB 1 0 7 MSB Notes: (1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first. P/N: PM2003 28 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-6. QPI ID Read (QPIID) User can execute this QPIID Read instruction to identify the Device ID and Manufacturer ID. The sequence of issue QPIID instruction is CS# goes low→sending QPI ID instruction→Data out on SO→CS# goes high. Most significant bit (MSB) first. After the command cycle, the device will immediately output data on the falling edge of SCLK. The manufacturer ID, memory type, and device ID data byte will be output continuously, until the CS# goes high. Table 6. ID Definitions Command Type RDID 9Fh RES ABh REMS 90h QPIID AFh P/N: PM2003 MX66L51235F Manufactory ID C2 Manufactory ID C2 Manufactory ID C2 Memory type 20 Electronic ID 19 Device ID 19 Memory type 20 29 Memory density 1A Memory density 1A REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-7. Read Status Register (RDSR) The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in program/erase/write status register condition). It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in progress. The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register data out on SO. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. Figure 17. Read Status Register (RDSR) Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK Mode 0 command 05h SI SO Status Register Out High-Z 7 6 5 4 3 2 1 Status Register Out 0 7 6 5 4 3 2 1 0 7 MSB MSB Figure 18. Read Status Register (RDSR) Sequence (QPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 N SCLK Mode 0 SIO[3:0] 05h H0 L0 H0 L0 H0 L0 H0 L0 MSB LSB Status Byte Status Byte Status Byte P/N: PM2003 30 Status Byte REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-8. Read Configuration Register (RDCR) The RDCR instruction is for reading Configuration Register Bits. The Read Configuration Register can be read at any time (even in program/erase/write configuration register condition). It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write configuration register operation is in progress. The sequence of issuing RDCR instruction is: CS# goes low→ sending RDCR instruction code→ Configuration Register data out on SO. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. Figure 19. Read Configuration Register (RDCR) Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK Mode 0 command 15h SI SO Configuration register Out High-Z 7 6 5 4 3 2 1 0 Configuration register Out 7 6 5 4 3 2 1 0 7 MSB MSB Figure 20. Read Configuration Register (RDCR) Sequence (QPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 N SCLK Mode 0 SIO[3:0] 15h H0 L0 H0 L0 H0 L0 H0 L0 MSB LSB Config. Byte Config. Byte Config. Byte P/N: PM2003 31 Config. Byte REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) For user to check if Program/Erase operation is finished or not, RDSR instruction flow are shown as follows: Figure 21. Program/Erase flow with read array data start WREN command RDSR command* WEL=1? No Yes Program/erase command Write program data/address (Write erase address) RDSR command WIP=0? No Yes RDSR command Read WEL=0, BP[3:0], QE, and SRWD data Read array data (same address of PGM/ERS) No Verify OK? Yes Program/erase successfully Program/erase another block? No Program/erase fail Yes * Issue RDSR to check BP[3:0]. * If WPSEL = 1, issue RDSPB and RDDPB to check the block status. Program/erase completed P/N: PM2003 32 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) Figure 22. Program/Erase flow without read array data (read P_FAIL/E_FAIL flag) start WREN command RDSR command* WEL=1? No Yes Program/erase command Write program data/address (Write erase address) RDSR command WIP=0? No Yes RDSR command Read WEL=0, BP[3:0], QE, and SRWD data RDSCUR command Yes P_FAIL/E_FAIL =1 ? No Program/erase fail Program/erase successfully Program/erase another block? No Yes * Issue RDSR to check BP[3:0]. * If WPSEL = 1, issue RDSPB and RDDPB to check the block status. Program/erase completed P/N: PM2003 33 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) Status Register The definition of the status register bits is as below: WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. The program/erase command will be ignored if it is applied to a protected memory area. To ensure both WIP bit & WEL bit are both set to 0 and available for next program/erase/operations, WIP bit needs to be confirm to be 0 before polling WEL bit. After WIP bit confirmed, WEL bit needs to be confirm to be 0. BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area (as defined in Table 2) of the device to against the program/erase instruction without hardware protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase 32KB (BE32K), Block Erase (BE) and Chip Erase (CE) instructions (only if Block Protect bits (BP3:BP0) set to 0, the CE instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as default. Which is unprotected. QE bit. The Quad Enable (QE) bit, non-volatile bit, while it is "0" (factory default), it performs non-Quad and WP#, RESET# are enable. While QE is "1", it performs Quad I/O mode and WP#, RESET# are disabled. In the other word, if the system goes into four I/O mode (QE=1), the feature of HPM and RESET# will be disabled. SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection (WP#/SIO2) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are read only. The SRWD bit defaults to be "0". Status Register bit7 SRWD (status register write protect) bit6 QE (Quad Enable) bit5 BP3 (level of protected block) bit4 BP2 (level of protected block) 1=Quad 1=status Enable register write (note 1) (note 1) 0=not Quad disable Enable Non-volatile Non-volatile Non-volatile Non-volatile bit bit bit bit Note 1: see the Table 2 "Protected Area Size". P/N: PM2003 bit3 BP1 (level of protected block) bit2 BP0 (level of protected block) (note 1) (note 1) Non-volatile bit Non-volatile bit 34 bit1 bit0 WEL WIP (write enable (write in latch) progress bit) 1=write 1=write enable operation 0=not write 0=not in write enable operation volatile bit volatile bit REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) Configuration Register The Configuration Register is able to change the default status of Flash memory. Flash memory will be configured after the CR bit is set. ODS bit The output driver strength (ODS2, ODS1, ODS0) bits are volatile bits, which indicate the output driver level (as defined in "Output Driver Strength Table") of the device. The Output Driver Strength is defaulted as 30 Ohms when delivered from factory. To write the ODS bits requires the Write Status Register (WRSR) instruction to be executed. TB bit The Top/Bottom (TB) bit is a non-volatile OTP bit. The Top/Bottom (TB) bit is used to configure the Block Protect area by BP bit (BP3, BP2, BP1, BP0), starting from TOP or Bottom of the memory array. The TB bit is defaulted as “0”, which means Top area protect. When it is set as “1”, the protect area will change to Bottom area of the memory device. To write the TB bits requires the Write Status Register (WRSR) instruction to be executed. 4BYTE Indicator bit By writing EN4B instruction, the 4BYTE bit may be set as "1" to access the address length of 32-bit for memory area of higher density (large than 128Mb). The default state is "0" as the 24-bit address mode. The 4BYTE bit may be cleared by power-off or writing EX4B instruction to reset the state to be "0". Configuration Register bit7 DC1 (Dummy cycle 1) bit6 DC0 (Dummy cycle 0) (note 2) (note 2) volatile bit volatile bit bit5 bit4 4 BYTE Reserved 0=3-byte address mode 1=4-byte address mode (Default=0) volatile bit bit3 bit2 bit1 bit0 TB ODS 2 ODS 1 ODS 0 (top/bottom (output driver (output driver (output driver selected) strength) strength) strength) x 0=Top area protect 1=Bottom area protect (Default=0) (note 1) (note 1) (note 1) x OTP volatile bit volatile bit volatile bit Note 1: see "Output Driver Strength Table" Note 2: see "Dummy Cycle and Frequency Table (MHz)" P/N: PM2003 35 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) Output Driver Strength Table ODS2 0 0 0 0 1 1 1 1 ODS1 0 0 1 1 0 0 1 1 ODS0 0 1 0 1 0 1 0 1 Description Reserved 90 Ohms 60 Ohms 45 Ohms Reserved 20 Ohms 15 Ohms 30 Ohms (Default) Note Impedance at VCC/2 Dummy Cycle and Frequency Table (MHz) DC[1:0] 00 (default) 01 10 11 DC[1:0] 00 (default) 01 10 11 DC[1:0] 00 (default) 01 10 11 P/N: PM2003 Numbers of Dummy clock cycles 8 6 8 10 Numbers of Dummy clock cycles 4 6 8 10 Fast Read 104 104 104 133 Dual Output Fast Read 104 104 104 133 Quad Output Fast Read 104 84 104 133 Dual IO Fast Read 84 104 104 133 Numbers of Dummy Quad IO Fast Read clock cycles 6 84 4 70 8 104 10 133 36 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-9. Write Status Register (WRSR) The WRSR instruction is for changing the values of Status Register Bits and Configuration Register Bits. Before sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1, BP0) bits to define the protected area of memory (as shown in Table 2). The WRSR also can set or reset the Quad enable (QE) bit and set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#/ SIO2) pin signal, but has no effect on bit1(WEL) and bit0 (WIP) of the status register. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered. The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register data on SI→CS# goes high. The CS# must go high exactly at the 8 bits or 16 bits data boundary; otherwise, the instruction will be rejected and not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset. Figure 23. Write Status Register (WRSR) Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCLK Mode 0 SI SO command 01h Status Register In 7 6 4 5 Configuration Register In 2 3 0 15 14 13 12 11 10 9 1 8 MSB High-Z Note : The CS# must go high exactly at 8 bits or 16 bits data boundary to completed the write register command. Figure 24. Write Status Register (WRSR) Sequence (QPI Mode) CS# Mode 3 0 1 2 3 4 5 Mode 3 SCLK Mode 0 Mode 0 SR in Command SIO[3:0] P/N: PM2003 01h H0 37 L0 CR in H1 L1 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) Software Protected Mode (SPM): - When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0 and T/B bit, is at software protected mode (SPM). - When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0 and T/B bit, is at software protected mode (SPM) Note: If SRWD bit=1 but WP#/SIO2 is low, it is impossible to write the Status Register even if the WEL bit has previously been set. It is rejected to write the Status Register and not be executed. Hardware Protected Mode (HPM): - When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2, BP1, BP0 and T/B bit and hardware protected mode by the WP#/SIO2 to against data modification. Note: To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is entered. If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via BP3, BP2, BP1, BP0 and T/B bit. If the system enter QPI or set QE=1, the feature of HPM will be disabled. Table 7. Protection Modes Mode Software protection mode (SPM) Hardware protection mode (HPM) Status register condition WP# and SRWD bit status Memory Status register can be written in (WEL bit is set to "1") and the SRWD, BP0-BP3 bits can be changed WP#=1 and SRWD bit=0, or WP#=0 and SRWD bit=0, or WP#=1 and SRWD=1 The protected area cannot be program or erase. The SRWD, BP0-BP3 of status register bits cannot be changed WP#=0, SRWD bit=1 The protected area cannot be program or erase. Note: 1. As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in Table 2. P/N: PM2003 38 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) Figure 25. WRSR flow start WREN command RDSR command WEL=1? No Yes WRSR command Write status register data RDSR command WIP=0? No Yes RDSR command Read WEL=0, BP[3:0], QE, and SRWD data Verify OK? No Yes WRSR successfully P/N: PM2003 WRSR fail 39 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) Figure 26. WP# Setup Timing and Hold Timing during WRSR when SRWD=1 WP# tSHWL tWHSL CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK 01h SI SO High-Z Note: WP# must be kept high until the embedded operation finish. P/N: PM2003 40 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-10. Enter 4-byte mode (EN4B) The EN4B instruction enables accessing the address length of 32-bit for the memory area of higher density (larger than 128Mb). The device default is in 24-bit address mode; after sending out the EN4B instruction, the bit5 (4BYTE bit) of security register will be automatically set to "1" to indicate the 4-byte address mode has been enabled. Once the 4-byte address mode is enabled, the address length becomes 32-bit instead of the default 24-bit. There are three methods to exit the 4-byte mode: writing exit 4-byte mode (EX4B) instruction, Reset or power-off. All instructions are accepted normally, and just the address bit is changed from 24-bit to 32-bit. The following command don't support 4bye address: RDSFDP, RES and REMS. The sequence of issuing EN4B instruction is: CS# goes low → sending EN4B instruction to enter 4-byte mode( automatically set 4BYTE bit as "1") → CS# goes high. 9-11. Exit 4-byte mode (EX4B) The EX4B instruction is executed to exit the 4-byte address mode and return to the default 3-bytes address mode. After sending out the EX4B instruction, the bit5 (4BYTE bit) of Configuration register will be cleared to be "0" to indicate the exit of the 4-byte address mode. Once exiting the 4-byte address mode, the address length will return to 24-bit. The sequence of issuing EX4B instruction is: CS# goes low → sending EX4B instruction to exit 4-byte mode (automatically clear the 4BYTE bit to be "0") → CS# goes high. P/N: PM2003 41 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-12. Read Data Bytes (READ) The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling edge of SCLK at a maximum frequency fR. The first address can't be any location if the device is still in 3-Byte mode. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached. The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode or to define EAR bit. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B) Mode section. The sequence of issuing READ instruction is: CS# goes low→sending READ instruction code→ 3-byte or 4-byte address on SI→ data out on SO→to end READ operation can use CS# to high at any time during data out. Figure 27. Read Data Bytes (READ) Sequence (SPI Mode only) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK Mode 0 SI command 03h 24-Bit Address (Note) 23 22 21 3 2 1 0 MSB SO Data Out 1 High-Z 7 6 5 4 3 2 Data Out 2 1 0 7 MSB Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address cycles will be increased. P/N: PM2003 42 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-13. Read Data Bytes at Higher Speed (FAST_READ) The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address can't be any location if the device is still in 3-Byte mode. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has been reached. The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode or to define EAR bit. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B) Mode section. Read on SPI Mode The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ instruction code→ 3-byte or 4-byte address on SI→ 8 dummy cycles (default)→ data out on SO→ to end FAST_ READ operation can use CS# to high at any time during data out. While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. Figure 28. Read at Higher Speed (FAST_READ) Sequence (SPI Mode) CS# SCLK Mode 3 0 1 2 Mode 0 3 5 6 7 8 9 10 Command SI SO 4 28 29 30 31 24-Bit Address (Note) 23 22 21 0Bh 3 2 1 0 High-Z CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Configurable Dummy Cycle SI 7 6 5 4 3 2 1 0 DATA OUT 2 DATA OUT 1 SO 7 6 5 4 3 2 1 0 7 MSB MSB 6 5 4 3 2 1 0 7 MSB Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address cycles will be increased. P/N: PM2003 43 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-14. Dual Output Read Mode (DREAD) The DREAD instruction enable double throughput of Serial Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address can't be any location if the device is still in 3-Byte mode. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruction, the following data out will perform as 2-bit instead of previous 1-bit. The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode or to define EAR bit. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B) Mode section. The sequence of issuing DREAD instruction is: CS# goes low→ sending DREAD instruction→3-byte or 4-byte address on SIO0→ 8 dummy cycles (default) on SIO0→ data out interleave on SIO1 & SIO0→ to end DREAD operation can use CS# to high at any time during data out. While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. Figure 29. Dual Read Mode Sequence CS# 0 1 2 3 4 5 6 7 8 … Command SI/SIO0 SO/SIO1 30 31 32 9 SCLK 3B … 24 ADD Cycle A23 A22 … 39 40 41 42 43 44 45 A1 A0 High Impedance Configurable Dummy Cycle Data Out 1 Data Out 2 D6 D4 D2 D0 D6 D4 D7 D5 D3 D1 D7 D5 Notes: 1. Please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. P/N: PM2003 44 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-15. 2 x I/O Read Mode (2READ) The 2READ instruction enable double throughput of Serial Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address can't be any location if the device is still in 3-Byte mode. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit. The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode or to define EAR bit. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B) Mode section. The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 3-byte or 4-byte address interleave on SIO1 & SIO0→ 4 dummy cycles (default) on SIO1 & SIO0→ data out interleave on SIO1 & SIO0→ to end 2READ operation can use CS# to high at any time during data out. While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. Figure 30. 2 x I/O Read Mode Sequence (SPI Mode only) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Mode 3 SCLK Mode 0 Command SI/SIO0 SO/SIO1 BBh 12 ADD Cycles (Note) Configurable Dummy Cycle Data Out 1 Data Out 2 A22 A20 A18 A4 A2 A0 D6 D4 D2 D0 D6 D4 D2 D0 A23 A21 A19 A5 A3 A1 D7 D5 D3 D1 D7 D5 D3 D1 Mode 0 Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address cycles will be increased. P/N: PM2003 45 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-16. Quad Read Mode (QREAD) The QREAD instruction enable quad throughput of Serial Flash in read mode. The address is latched on rising edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ. The first address can't be any location if the device is still in 3-Byte mode. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single QREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing QREAD instruction, the following data out will perform as 4-bit instead of previous 1-bit. The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode or to define EAR bit. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B) Mode section. The sequence of issuing QREAD instruction is: CS# goes low→ sending QREAD instruction → 3-byte or 4-byte address on SI → 8 dummy cycle (Default) → data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end QREAD operation can use CS# to high at any time during data out. While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. Figure 31. Quad Read Mode Sequence CS# 0 1 2 3 4 5 6 7 8 … Command SIO0 SIO1 SIO2 SIO3 29 30 31 32 33 9 SCLK 6B … 24 ADD Cycles A23 A22 … High Impedance 38 39 40 41 42 A2 A1 A0 Configurable dummy cycles Data Data Data Out 1 Out 2 Out 3 D4 D0 D4 D0 D4 D5 D1 D5 D1 D5 High Impedance D6 D2 D6 D2 D6 High Impedance D7 D3 D7 D3 D7 Notes: 1. Please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. P/N: PM2003 46 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-17. 4 x I/O Read Mode (4READ) The 4READ instruction enable quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ. The first address can't be any location if the device is still in 3-Byte mode. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit. The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode or to define EAR bit. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B) Mode section. 4 x I/O Read on SPI Mode (4READ) The sequence of issuing 4READ instruction is: CS# goes low→ sending 4READ instruction→ 3-byte or 4-byte address interleave on SIO3, SIO2, SIO1 & SIO0→ 6 dummy cycles (Default) →data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end 4READ operation can use CS# to high at any time during data out. 4 x I/O Read on QPI Mode (4READ) The 4READ instruction also support on QPI command mode. The sequence of issuing 4READ instruction QPI mode is: CS# goes low→ sending 4READ instruction→ 3-byte or 4-byte address interleave on SIO3, SIO2, SIO1 & SIO0→ 6 dummy cycles (Default) →data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end 4READ operation can use CS# to high at any time during data out. While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. P/N: PM2003 47 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) Figure 32. 4 x I/O Read Mode Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 8 Mode 3 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SCLK Mode 0 Command 6 ADD Cycles Data Out 1 Performance enhance indicator (Note 1) Data Out 2 Mode 0 Data Out 3 Configurable Dummy Cycle (Note 3) EBh A20 A16 A12 A8 A4 A0 P4 P0 D4 D0 D4 D0 D4 D0 SIO1 A21 A17 A13 A9 A5 A1 P5 P1 D5 D1 D5 D1 D5 D1 SIO2 A22 A18 A14 A10 A6 A2 P6 P2 D6 D2 D6 D2 D6 D2 SIO3 A23 A19 A15 A11 A7 A3 P7 P3 D7 D3 D7 D3 D7 D3 SIO0 Notes: 1. Hi-impedance is inhibited for the two clock cycles. 2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited. 3. Configuration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in configuration register. Figure 33. 4 x I/O Read Mode Sequence (QPI Mode) CS# MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 MODE 3 SCLK MODE 0 SIO[3:0] MODE 0 EB A5 A4 A3 A2 A1 A0 Data In 24-bit Address (Note) X X X X Configurable Dummy Cycle X X H0 L0 H1 L1 H2 L2 H3 L3 MSB Data Out Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address cycles will be increased. P/N: PM2003 48 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-18. 4 Byte Address Command Set The operation of 4-byte address command set was very similar to original 3-byte address command set. The only different is all the 4-byte command set request 4-byte address (A31-A0) followed by instruction code. The command set support 4-byte address including: READ4B, Fast_Read4B, DREAD4B, 2READ4B, QREAD4B, 4READ4B, PP4B, 4PP4B, SE4B, BE32K4B, BE4B. Please note that it is not necessary to issue EN4B command before issuing any of 4-byte command set. Figure 34. Read Data Bytes using 4 Byte Address Sequence (READ4B) CS# 0 1 2 3 4 5 6 7 8 36 37 38 39 40 41 42 43 44 45 46 47 9 10 SCLK Command 32-bit address 31 30 29 13h SI 3 2 1 0 MSB Data Out 1 High Impedance SO 7 6 5 4 3 Data Out 2 2 1 7 0 MSB Figure 35. Read Data Bytes at Higher Speed using 4 Byte Address Sequence (FASTREAD4B) CS# 0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 SCLK Command 32-bit address 31 30 29 0Ch SI 3 2 1 0 High Impedance SO CS# 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SCLK Configurable Dummy cycles SI 7 6 5 4 3 2 1 0 DATA OUT 2 DATA OUT 1 SO 7 6 5 4 MSB P/N: PM2003 3 2 1 0 7 6 MSB 49 5 4 3 2 1 0 7 MSB REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) Figure 36. 2 x I/O Fast Read using 4 Byte Address Sequence (2READ4B) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Mode 3 SCLK Mode 0 BCh SI/SIO0 Configurable Dummy Cycle (Note) 16 ADD Cycles Command SO/SIO1 Data Out 1 Data Out 2 A30 A28 A26 A4 A2 A0 D6 D4 D2 D0 D6 D4 D2 D0 A31 A29 A27 A5 A3 A1 D7 D5 D3 D1 D7 D5 D3 D1 Mode 0 Note: Configuration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in configuration register. Figure 37. 4 I/O Fast Read using 4 Byte Address sequence (4READ4B) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Mode 3 SCLK Mode 0 Command 8 ADD Cycles Data Out 1 Performance enhance indicator Data Out 2 Data Out 3 Mode 0 Configurable Dummy Cycle SIO0 ECh A28 A24 A20 A16 A12 A8 A4 A0 P4 P0 (Note) D4 D0 D4 D0 D4 D0 SIO1 A29 A25 A21 A17 A13 A9 A5 A1 P5 P1 D5 D1 D5 D1 D5 D1 SIO2 A30 A26 A22 A18 A14 A10 A6 A2 P6 P2 D6 D2 D6 D2 D6 D2 SIO3 A31 A27 A23 A19 A15 A11 A7 A3 P7 P3 D7 D3 D7 D3 D7 D3 Note: Configuration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in configuration register. P/N: PM2003 50 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-19. Burst Read This device supports Burst Read in both SPI and QPI mode. To set the Burst length, following command operation is required to issue command: “C0h” in the first Byte (8-clocks), following 4 clocks defining wrap around enable with “0h” and disable with“1h”. The next 4 clocks are to define wrap around depth. Their definitions are as the following table: Data 00h 01h 02h 03h 1xh Wrap Around Yes Yes Yes Yes No Wrap Depth 8-byte 16-byte 32-byte 64-byte X The wrap around unit is defined within the 256Byte page, with random initial address. It is defined as “wrap-around mode disable” for the default state of the device. To exit wrap around, it is required to issue another “C0” command in which data=‘1xh”. Otherwise, wrap around status will be retained until power down or reset command. To change wrap around depth, it is requried to issue another “C0” command in which data=“0xh”. QPI “EBh” and SPI “EBh” support wrap around feature after wrap around is enabled. Burst read is supported in both SPI and QPI mode. The device is default without Burst read. Figure 38. SPI Mode CS# Mode 3 0 1 2 3 4 5 6 7 8 9 D7 D6 10 11 12 13 14 15 SCLK Mode 0 SIO C0h D5 D4 D3 D2 D1 D0 Figure 39. QPI Mode CS# Mode 3 0 1 2 3 SCLK Mode 0 SIO[3:0] C0h H0 MSB L0 LSB Note: MSB=Most Significant Bit LSB=Least Significant Bit P/N: PM2003 51 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-20. Performance Enhance Mode The device could waive the command cycle bits if the two cycle bits after address cycle toggles. Performance enhance mode is supported in both SPI and QPI mode. In QPI mode, “EBh” "ECh" and SPI “EBh” "ECh" commands support enhance mode. The performance enhance mode is not supported in dual I/O mode. To enter performance-enhancing mode, P[7:4] must be toggling with P[3:0]; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh can make this mode continue and skip the next 4READ instruction. To leave enhance mode, P[7:4] is no longer toggling with P[3:0]; likewise P[7:0]=FFh, 00h, AAh or 55h along with CS# is afterwards raised and then lowered. Issuing ”FFh” data cycle can also exit enhance mode. The system then will leave performance enhance mode and return to normal operation. After entering enhance mode, following CS# go high, the device will stay in the read mode and treat CS# go low of the first clock as address instead of command cycle. Another sequence of issuing 4READ instruction especially useful in random access is: CS# goes low→sending 4 READ instruction→3-bytes or 4-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 →performance enhance toggling bit P[7:0]→ 4 dummy cycles (Default) →data out still CS# goes high → CS# goes low (reduce 4 Read instruction) → 3-bytes or 4-bytes random access address. P/N: PM2003 52 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) Figure 40. 4 x I/O Read enhance performance Mode Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 n SCLK Mode 0 Data Out 2 Data Out n A20 A16 A12 A8 A4 A0 P4 P0 D4 D0 D4 D0 D4 D0 SIO1 A21 A17 A13 A9 A5 A1 P5 P1 D5 D1 D5 D1 D5 D1 SIO2 A22 A18 A14 A10 A6 A2 P6 P2 D6 D2 D6 D2 D6 D2 SIO3 A23 A19 A15 A11 A7 A3 P7 P3 D7 D3 D7 D3 D7 D3 Command 6 ADD Cycles (Note 2) Data Out 1 Performance enhance indicator (Note 1) Configurable Dummy Cycle (Note 2) EBh SIO0 CS# n+1 ........... n+7 ...... n+9 ........... n+13 ........... Mode 3 SCLK 6 ADD Cycles (Note 2) Performance enhance indicator (Note 1) Data Out 1 Data Out 2 Data Out n Mode 0 Configurable Dummy Cycle (Note 2) SIO0 A20 A16 A12 A8 A4 A0 P4 P0 D4 D0 D4 D0 D4 D0 SIO1 A21 A17 A13 A9 A5 A1 P5 P1 D5 D1 D5 D1 D5 D1 SIO2 A22 A18 A14 A10 A6 A2 P6 P2 D6 D2 D6 D2 D6 D2 SIO3 A23 A19 A15 A11 A7 A3 P7 P3 D7 D3 D7 D3 D7 D3 Notes: 1. If not using performance enhance recommend to keep 1 or 0 in performance enhance indicator. 2. Configuration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in configuration register. P/N: PM2003 53 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) Figure 41. 4 x I/O Read enhance performance Mode Sequence (QPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 A1 A0 8 9 10 11 12 13 14 15 16 17 H0 L0 H1 L1 SCLK Mode 0 SIO[3:0] EBh A5 A4 A3 A2 X X X X MSB LSB MSB LSB P(7:4) P(3:0) Data In Data Out performance enhance indicator Configurable Dummy Cycle (Note 1) CS# n+1 ............. SCLK Mode 0 SIO[3:0] A5 A4 A3 A2 A1 X A0 X X 6 Address cycles (Note) X H0 L0 H1 L1 MSB LSB MSB LSB P(7:4) P(3:0) Data Out performance enhance indicator Configurable Dummy Cycle (Note 1) Notes: 1. Configuration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in configuration register. P/N: PM2003 54 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-21. Performance Enhance Mode Reset To conduct the Performance Enhance Mode Reset operation in SPI mode, FFh data cycle(8 clocks in 3-byte address mode)/3FFh data cycle(10 clocks in 4-byte address mode), should be issued in 1I/O sequence. In QPI Mode, FFFFFFFFh data cycle(8 clocks in 3-byte address mode)/FFFFFFFFFFh data cycle (10 clocks in 4-byte address mode), in 4I/O should be issued. If the system controller is being Reset during operation, the flash device will return to the standard SPI operation. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. Figure 42. Performance Enhance Mode Reset for Fast Read Quad I/O (SPI Mode) Mode Bit Reset for Quad I/O CS# Mode 3 SCLK ０ 1 2 3 4 5 6 Mode 3 7 Mode ０ Mode ０ SIO0 FFh SIO1 Don’t Care SIO2 Don’t Care SIO3 Don’t Care Figure 43. Performance Enhance Mode Reset for Fast Read Quad I/O (QPI Mode) Mode Bit Reset for Quad I/O CS# Mode 3 SCLK SIO[3:0] P/N: PM2003 ０ 1 2 3 4 5 6 Mode ０ 7 Mode 3 Mode ０ FFFFFFFFh 55 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) Figure 44. Performance Enhance Mode Reset for Fast Read Quad I/O using 4Byte Address Sequence (SPI Mode) Mode Bit Reset for Quad I/O CS# Mode 3 SCLK 0 1 2 3 4 5 6 7 8 Mode 3 9 Mode ０ Mode ０ SIO0 3FFh SIO1 Don’t Care SIO2 Don’t Care SIO3 Don’t Care Figure 45. Performance Enhance Mode Reset for Fast Read Quad I/O using 4Byte Address Sequence (QPI Mode) Mode Bit Reset for Quad I/O CS# Mode 3 SCLK SIO[3:0] P/N: PM2003 0 1 2 3 4 5 6 7 Mode ０ 8 9 Mode 3 Mode ０ FFFFFFFFFFh 56 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-22. Fast Boot The Fast Boot Feature provides the ability to automatically execute read operation after power on cycle or reset without any read instruction. A Fast Boot Register is provided on this device. It can enable the Fast Boot function and also define the number of delay cycles and start address (where boot code being transferred). Instruction WRFBR (write fast boot register) and ESFBR (erase fast boot register) can be used for the status configuration or alternation of the Fast Boot Register bit. RDFBR (read fast boot register) can be used to verify the program state of the Fast Boot Register. The default number of delay cycles is 13 cycles, and there is a 16bytes boundary address for the start of boot code access. When CS# starts to go low, data begins to output from default address after the delay cycles (default as 13 cycles). After CS# returns to go high, the device will go back to standard SPI mode and user can start to input command. In the fast boot data out process from CS# goes low to CS# goes high, a minimum of one byte must be output. Once Fast Boot feature has been enabled, the device will automatically start a read operation after power on cycle, reset command, or hardware reset operation. The fast Boot feature can support Single I/O and Quad I/O interface. If the QE bit of Status Register is “0”, the data is output by Single I/O interface. If the QE bit of Status Register is set to “1”, the data is output by Quad I/O interface. Fast Boot Register (FBR) Bits 31 to 4 Description FBSA (FastBoot Start Address) 3 x 2 to 1 FBSD (FastBoot Start Delay Cycle) 0 FBE (FastBoot Enable) Bit Status Default State 16 bytes boundary address for the start of boot FFFFFFF code access. 1 00: 7 delay cycles 01: 9 delay cycles 10: 11 delay cycles 11: 13 delay cycles 0=FastBoot is enabled. 1=FastBoot is not enabled. Type NonVolatile NonVolatile 11 NonVolatile 1 NonVolatile Note: If FBSD = 11, the maximum clock frequency is 133 MHz If FBSD = 10, the maximum clock frequency is 104 MHz If FBSD = 01, the maximum clock frequency is 84 MHz If FBSD = 00, the maximum clock frequency is 70 MHz P/N: PM2003 57 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) Figure 46. Fast Boot Sequence (QE Bit=0) CS# Mode 3 0 - - - - - - n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11n+12n+13n+14n+15 SCLK Mode 0 SI Delay Cycles Don’t care or High Impedance Data Out 1 SO High Impedance 7 6 5 4 3 Data Out 2 2 1 0 MSB 7 6 5 MSB 4 3 2 1 0 7 MSB Note: If FBSD = 11, delay cycles is 13 and n is 12. If FBSD = 10, delay cycles is 11 and n is 10. If FBSD = 01, delay cycles is 9 and n is 8. If FBSD = 00, delay cycles is 7 and n is 6. Figure 47. Fast Boot Sequence (QE Bit=1) CS# Mode 3 0 - - - - - - - n n+1 n+2 n+3 n+5 n+6 n+7 n+8 n+9 SCLK Mode 0 SIO0 SIO1 SIO2 SIO3 Delay Cycles High Impedance High Impedance High Impedance High Impedance Data Data Out 1 Out 2 Data Out 3 Data Out 4 4 0 4 0 4 0 4 0 4 5 1 5 1 5 1 5 1 5 6 2 6 2 6 2 6 2 6 7 3 7 3 7 3 7 3 7 MSB Note: If FBSD = 11, delay cycles is 13 and n is 12. If FBSD = 10, delay cycles is 11 and n is 10. If FBSD = 01, delay cycles is 9 and n is 8. If FBSD = 00, delay cycles is 7 and n is 6. P/N: PM2003 58 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) Figure 48. Read Fast Boot Register (RDFBR) Sequence CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 37 38 39 40 41 SCLK Mode 0 Command SI 16h Data Out 1 High-Z SO 7 6 5 Data Out 2 26 25 24 7 6 MSB MSB Figure 49. Write Fast Boot Register (WRFBR) Sequence CS# 0 Mode 3 1 2 3 4 5 6 7 8 9 10 37 38 39 SCLK Mode 0 Command SI Fast Boot Register 17h 7 6 5 6 7 26 25 24 MSB High-Z SO Figure 50. Erase Fast Boot Register (ESFBR) Sequence CS# Mode 3 0 1 2 3 4 5 SCLK Mode 0 SI SO P/N: PM2003 Command 18h High-Z 59 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-23. Sector Erase (SE) The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector (see "Table 4. Memory Organization") is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of the address byte been latched-in); otherwise, the instruction will be rejected and not executed. The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode or to define EAR bit. Address bits [Am-A12] (Am is the most significant address) select the sector address. To enter the 4-byte address mode, please refer to the enter 4-byte mode (EN4B) Mode section. The sequence of issuing SE instruction is: CS# goes low→ sending SE instruction code→ 3-byte or 4-byte address on SI→ CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets 1 during the tSE timing, and clears when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the Block is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector Protect Mode), the Sector Erase (SE) instruction will not be executed on the block. Figure 51. Sector Erase (SE) Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK Mode 0 24-Bit Address (Note) Command SI 20h A23 A22 A2 A1 A0 MSB Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address cycles will be increased. Figure 52. Sector Erase (SE) Sequence (QPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 SCLK Mode 0 24-Bit Address (Note) Command SIO[3:0] 20h A5 A4 A3 A2 A1 A0 MSB Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address cycles will be increased. P/N: PM2003 60 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-24. Block Erase (BE32K) The Block Erase (BE32K) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 32K-byte block erase operation. A Write Enable (WREN) instruction be executed to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE32K). Any address of the block (see "Table 4. Memory Organization") is a valid address for Block Erase (BE32K) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed. Address bits [Am-A15] (Am is the most significant address) select the 32KB block address. The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode or to define EAR bit. To enter the 4-byte address mode, please refer to the enter 4-byte mode (EN4B) Mode section. The sequence of issuing BE32K instruction is: CS# goes low→ sending BE32K instruction code→ 3-byte or 4-byte address on SI→CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. The self-timed Block Erase Cycle time (tBE32K) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while during the Block Erase cycle is in progress. The WIP sets during the tBE32K timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the Block is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector Protect Mode), the Block Erase (BE32K) instruction will not be executed on the block. Figure 53. Block Erase 32KB (BE32K) Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK Mode 0 Command SI 24-Bit Address (Note) 52h A23 A22 A2 A1 A0 MSB Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address cycles will be increased. Figure 54. Block Erase 32KB (BE32K) Sequence (QPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 SCLK Mode 0 24-Bit Address (Note) Command SIO[3:0] 52h A5 A4 A3 A2 A1 A0 MSB Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address cycles will be increased. P/N: PM2003 61 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-25. Block Erase (BE) The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 64K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (Please refer to "Table 4. Memory Organization") is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode or to define EAR bit. To enter the 4-byte address mode, please refer to the enter 4-byte mode (EN4B) Mode section. The sequence of issuing BE instruction is: CS# goes low→ sending BE instruction code→ 3-byte or 4-byte address on SI→ CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets during the tBE timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the Block is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector Protect Mode), the Block Erase (BE) instruction will not be executed on the block. Figure 55. Block Erase (BE) Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK Mode 0 Command SI 24-Bit Address (Note) D8h A23 A22 A2 A1 A0 MSB Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address cycles will be increased. Figure 56. Block Erase (BE) Sequence (QPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 SCLK Mode 0 SIO[3:0] Command 24-Bit Address (Note) D8h A5 A4 A3 A2 A1 A0 MSB Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address cycles will be increased. P/N: PM2003 62 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-26. Chip Erase (CE) The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not executed. The sequence of issuing CE instruction is: CS# goes low→sending CE instruction code→CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Chip Erase cycle is in progress. The WIP sets during the tCE timing, and clears when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. When the chip is under "Block protect (BP) Mode" (WPSEL=0). The Chip Erase (CE) instruction will not be executed, if one (or more) sector is protected by BP3-BP0 bits. It will be only executed when BP3-BP0 all set to "0". When the chip is under "Advanced Sector Protect Mode" (WPSEL=1). The Chip Erase (CE) instruction will be executed on unprotected block. The protected Block will be skipped. If one (or more) 4K byte sector was protected in top or bottom 64K byte block, the protected block will also skip the chip erase command. Figure 57. Chip Erase (CE) Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 SCLK Mode 0 Command SI 60h or C7h Figure 58. Chip Erase (CE) Sequence (QPI Mode) CS# Mode 3 0 1 SCLK Mode 0 SIO[3:0] P/N: PM2003 Command 60h or C7h 63 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-27. Page Program (PP) The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device programs only the last 256 data bytes sent to the device. If the entire 256 data bytes are going to be programmed, A7-A0 (The eight least significant address bits) should be set to 0. The last address byte (the 8 least significant address bits, A7-A0) should be set to 0 for 256 bytes page program. If A7-A0 are not all zero, transmitted data that exceed page length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently selected page. If the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the request page and previous data will be disregarded. If the data bytes sent to the device has not exceeded 256, the data will be programmed at the request address of the page. There will be no effort on the other data bytes of the same page. The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode or to define EAR bit. To enter the 4-byte address mode, please refer to the enter 4-byte mode (EN4B) Mode section. The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte or 4-byte address on SI→ at least 1-byte on data on SI→ CS# goes high. The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte boundary( the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed. The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Page Program cycle is in progress. The WIP sets during the tPP timing, and clears when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the Block is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector Protect Mode), the Page Program (PP) instruction will not be executed. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. P/N: PM2003 64 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) Figure 59. Page Program (PP) Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK 1 0 7 6 5 3 2 1 0 2079 2 2078 3 2077 23 22 21 02h SI Data Byte 1 24-Bit Address (Note) 2076 Command 2075 Mode 0 4 1 0 MSB MSB 2074 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2073 2072 CS# SCLK Data Byte 2 7 SI 6 5 4 3 2 Data Byte 3 1 MSB 0 7 6 5 4 3 2 Data Byte 256 1 7 0 MSB 6 5 4 3 2 MSB Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address cycles will be increased. Figure 60. Page Program (PP) Sequence (QPI Mode) CS# Mode 3 0 1 2 SCLK Mode 0 Command SIO[3:0] 02h Data In 24-Bit Address (Note) A5 A4 A3 A2 A1 A0 H0 L0 H1 L1 H2 L2 H3 L3 Data Byte Data Byte Data Byte Data Byte 1 2 3 4 H255 L255 ...... Data Byte 256 Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address cycles will be increased. P/N: PM2003 65 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-28. 4 x I/O Page Program (4PP) The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1" before sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1, SIO2, and SIO3 as address and data input, which can improve programmer performance and the effectiveness of application. The other function descriptions are as same as standard page program. The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode or to define EAR bit. To enter the 4-byte address mode, please refer to the enter 4-byte mode (EN4B) Mode section. The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte or 4-byte address on SIO[3:0]→ at least 1-byte on data on SIO[3:0]→CS# goes high. If the page is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector Protect Mode), the Quad Page Program (4PP) instruction will not be executed. Figure 61. 4 x I/O Page Program (4PP) Sequence (SPI Mode only) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 SCLK Mode 0 Command Data Data Data Data Byte 1 Byte 2 Byte 3 Byte 4 6 Address cycle A0 4 0 4 0 4 0 4 0 SIO1 A21 A17 A13 A9 A5 A1 5 1 5 1 5 1 5 1 SIO2 A22 A18 A14 A10 A6 A2 6 2 6 2 6 2 6 2 SIO3 A23 A19 A15 A11 A7 A3 7 3 7 3 7 3 7 3 SIO0 38h A20 A16 A12 A8 A4 Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address cycles will be increased. P/N: PM2003 66 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-29. Deep Power-down (DP) The Deep Power-down (DP) instruction is for setting the device to minimum power consumption (the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction are ignored. When CS# goes high, the device is in deep power-down mode, not standby mode. The sequence of issuing DP instruction is: CS# goes low→sending DP instruction code→CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP) and Read Electronic Signature (RES) instruction and softreset command. (those instructions allow the ID being reading out). When Power-down, or software reset command the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. For DP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode. Figure 62. Deep Power-down (DP) Sequence (SPI Mode) CS# 0 Mode 3 1 2 3 4 5 6 tDP 7 SCLK Mode 0 Command B9h SI Stand-by Mode Deep Power-down Mode Figure 63. Deep Power-down (DP) Sequence (QPI Mode) CS# Mode 3 0 1 tDP SCLK Mode 0 Command SIO[3:0] B9h Stand-by Mode P/N: PM2003 67 Deep Power-down Mode REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-30. Enter Secured OTP (ENSO) The ENSO instruction is for entering the additional 4K-bit secured OTP mode. While device is in 4K-bit secured OTPmode, main array access is not available. The additional 4K-bit secured OTP is independent from main array and may be used to store unique serial number for system identifier. After entering the Secured OTP mode, follow standard read or program procedure to read out the data or update data. The Secured OTP data cannot be updated again once it is lock-down. The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP mode→ CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. Please note that after issuing ENSO command user can only access secure OTP region with standard read or program procedure. Furthermore, once security OTP is lock down, only read related commands are valid. 9-31. Exit Secured OTP (EXSO) The EXSO instruction is for exiting the additional 4K-bit secured OTP mode. The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP mode→ CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. 9-32. Read Security Register (RDSCUR) The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read at any time (even in program/erase/write status register/write security register condition) and continuously. The sequence of issuing RDSCUR instruction is : CS# goes low→sending RDSCUR instruction→Security Register data out on SO→ CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. 9-33. Write Security Register (WRSCUR) The WRSCUR instruction sets the LDSO bit of the Security Register. The WREN (Write Enable) instruction is required before issuing WRSCUR instruction. The WRSCUR instruction may change the values of bit1 (LDSO bit) for customer to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area cannot be updated any more. The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. P/N: PM2003 68 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) Security Register The definition of the Security Register bits is as below: Write Protection Selection bit. Please reference to "Write Protection Selection bit" Erase Fail bit. The Erase Fail bit is a status flag, which shows the status of last Erase operation. It will be set to "1", if the erase operation fails. It will be set to "0", if the last operation is successful. Please note that it will not interrupt or stop any operation in the flash memory. Program Fail bit. The Program Fail bit is a status flag, which shows the status of last Program operation. It will be set to "1", if the program operation fails or the program region is protected. It will be set to "0", if the last operation is successful. Please note that it will not interrupt or stop any operation in the flash memory. Erase Suspend bit. Erase Suspend Bit (ESB) indicates the status of Erase Suspend operation. Users may use ESB to identify the state of flash memory. After the flash memory is suspended by Erase Suspend command, ESB is set to "1". ESB is cleared to "0" after erase operation resumes. Program Suspend bit. Program Suspend Bit (PSB) indicates the status of Program Suspend operation. Users may use PSB to identify the state of flash memory. After the flash memory is suspended by Program Suspend command, PSB is set to "1". PSB is cleared to "0" after program operation resumes. Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory or not. When it is "0", it indicates non-factory lock; "1" indicates factory-lock. Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for customer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 4K-bit Secured OTP area cannot be updated any more. While it is in 4K-bit secured OTP mode, main array access is not allowed. Table 8. Security Register Definition bit7 bit6 bit5 bit4 WPSEL E_FAIL P_FAIL Reserved 0=normal WP mode 1=individual mode (default=0) 0=normal Erase succeed 1=indicate Erase failed (default=0) 0=normal Program succeed 1=indicate Program failed (default=0) - 0=Erase is not suspended 1= Erase suspended (default=0) Non-volatile bit (OTP) Volatile bit Volatile bit Volatile bit Volatile bit P/N: PM2003 bit3 bit2 ESB PSB (Erase (Program Suspend bit) Suspend bit) 69 bit1 bit0 LDSO Secured OTP (indicate if indicator bit lock-down) 0 = not lock0=Program down 0 = nonis not 1 = lock-down factory suspended (cannot lock 1= Program program/ 1 = factory suspended erase lock (default=0) OTP) Non-volatile Non-volatile Volatile bit bit bit (OTP) (OTP) REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-34. Write Protection Selection (WPSEL) There are two write protection methods provided on this device, (1) Block Lock (BP) protection mode (2) Advanced Sector protection mode. If WPSEL=0, flash is under BP protection mode . If WPSEL=1, flash is under Advanced Sector protection mode. The default value of WPSEL is “0”. WPSEL command can be used to set WPSEL=1. Please note that WPSEL is an OTP bit. Once WPSEL is set to 1, there is no chance to recovery WPSEL back to “0”. If the flash is put on BP mode, the Advanced Sector protection mode is disabled. Contrarily, if flash is on the Advanced Sector protection mode, the BP mode is disabled. Every time after the system is powered-on, and the Security Register bit 7 is checked to be WPSEL=1, all the blocks or sectors will be write protected by Dynamic Protected Bit (DPB) in default. User may only unlock the blocks or sectors via GBULK instruction. Program or erase functions can only be operated after the Unlock instruction is conducted. When WPSEL = 0: Block Lock (BP) protection mode, Array is protected by BP3~BP0 and BP bits are protected by “SRWD=1 and WP#=0”, where SRWD is bit 7 of status register that can be set by WRSR command. When WPSEL =1: Advanced Sector protection mode, Blocks are individually protected by their own SPB or DPB lock bits which are set to “1” after power up. When the system accepts and executes WPSEL instruction, the bit 7 in security register will be set. It will activate WRLR, RDLR, WRPASS, RDPASS, PASSULK, WRSPB, ESSPB, SPBLK, RDSPBLK, WRDPB, RDDPB, GBLK, GBULK etc instructions to conduct block lock protection and replace the original Software Protect Mode (SPM) use (BP3~BP0) indicated block methods. Under the Advanced Sector protection mode (WPSEL=1), hardware protection is performed by driving WP#=0. Once WP#=0 all array blocks/sectors are protected regardless of the contents of SPB or DPB lock bits. The sequence of issuing WPSEL instruction is: CS# goes low → sending WPSEL instruction to enter the individual block protect mode → CS# goes high. The WREN command must be executed before issuing the WPSEL command. Write Protection Selection Start (Default in BP Mode) WPSEL=1 Set WPSEL Bit Advanced Sector Protection Set Lock Register WPSEL=0 Block Protection (BP) Bit 1 =0 Bit 2 =0 Password Protection P/N: PM2003 Solid Protection 70 Dynamic Protection REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) Figure 64. WPSEL Flow start WREN command RDSCUR command Yes WPSEL=1? No WPSEL disable, block protected by BP[3:0] WPSEL command RDSR command WIP=0? No Yes RDSCUR command WPSEL=1? No Yes WPSEL set successfully WPSEL set fail WPSEL enable. Block protected by Advance Sector Protection P/N: PM2003 71 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-35. Advanced Sector Protection There are two ways to implement software Advanced Sector Protection on this device: Password method or Sol­id method. Through these two protection methods, user can disable or enable the programming or erasing op­eration to any individual sector or all sectors. There is a non-volatile (SPB) and volatile (DPB) protection bit related to the single sector in main flash array. Each of the sectors is protected from programming or erasing operation when the bit is set. The temporary unprotect solid write protect bit (USPB) can temporarily unprotect the sectors protected by SPB. The figure below helps describing an overview of these methods. The device is default to the Solid mode when shipped from factory. The detail algorithm of advanced sector protection is shown as follows: Figure 65. Advanced Sector Protection Overview Start Bit 1=0 Bit 2=0 Set Lock Register ? Solid Protection Mode Password Protection Mode Set 64 bit Password Set SPB Lock Bit ? SPBLK = 0 SPB Lock bit locked All SPB can not be changeable SPBLK = 1 SPB Lock bit Unlocked SPB is changeable Dynamic Protect Bit Register (DPB) DPB=1 sector protect Sector Array DPB=0 sector unprotect P/N: PM2003 SPB Access Register (SPB) Temporary Unprotect SPB bit (USPB) SPB=1 Write Protect USPB=0 SPB bit is disabled SPB=0 Write Unprotect USPB=1 SPB bit is effective DPB 0 SA 0 SPB 0 DPB 1 SA 1 SPB 1 DPB 2 SA 2 SPB 2 : : : : : : DPB N-1 SA N-1 SPB N-1 DPB N SA N SPB N 72 USPB REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-35-1. Lock Register User can choose favorite sector protecting method via setting Lock Register bits 1 and 2. Lock Register is a 16bit one-time programmable register. Once bit 1 or bit 2 has been programmed (cleared to "0"), they will be locked in that mode and the others will be disabled permanently. Bit 1 and Bit 2 can not be programmed at the same time, otherwise the device will abort the operation. If user selects Password Protection mode, the password setting is required. User can set password by issuing WRPASS command. Lock Register Bit 15-3 Reserved x Bit 2 Password Protection Mode Lock Bit 0=Password Protection Mode Enable 1= Password Protection Mode not enable (Default =1) OTP Bit 1 Solid Protection Mode Lock Bit Bit0 Reserved 0=Solid Protection Mode Enable 1= Solid Protection Mode not enable (Default =1) x OTP OTP OTP Notes: 1. While bit 2 or bit 1 has been "0" status, other bits can't be changed any more. If set lock register program mode, program fail will be set to "1". 2. While bit 2 and bit 1 is "1" status,other bits can be programmed, program fail will be set to "1". Figure 66. Read Lock Register (RDLR) Sequence CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK Mode 0 command 2Dh SI Register Out High-Z SO 7 6 5 4 3 2 Register Out 0 15 14 13 12 11 10 9 1 8 7 MSB MSB Figure 67. Write Lock Register (WRLR) Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCLK Mode 0 SI SO P/N: PM2003 Command 2Ch High-Z Lock Register In 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 MSB 73 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-35-2. SPB Lock Bit (SPBLB) The Solid Protection Bit Lock Bit (SPBLB) is assigned to control all SPB status. It is unique and volatile. The default status of this register is determined by Lock Register bit 1 and bit 2 status. Refer to SPB Lock Register for more SPB Lock information. When under Solid Protect Mode, there is no software command sequence requested to unlock this bit. To clear the SPB lock bit, just take the device through a reset or a power-up cycle. When under Password Protection Mode, in order to prevent modification, the SPB Lock Bit must be set after all SPBs are setting the desired status. SPB Lock Register Bit Description 7-1 Reserved 0 Bit Status X 0= SPB bit protected 1= SPB bit unprotected SPBLK (Lock SPB Bit) Default 0000000 Solid protected Mode=1 Password Protected Mode=0 Type Volatile Volatile Figure 68. SPB Lock Bit Set (SPBLK) Sequence CS# 0 Mode 3 1 2 3 4 5 6 7 SCLK Mode 0 Command SI A6h High-Z SO Figure 69. Read SPB Lock Register (RDSPBLK) Sequence CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK Mode 0 command A7h SI SO High-Z Register Out 7 6 5 4 2 1 0 7 6 5 4 3 2 1 0 7 MSB MSB P/N: PM2003 3 Register Out 74 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-35-3. Solid Protection Bits The Solid write Protection bit (SPB) is a nonvolatile bit with the same endurances as the Flash memory. It is assigned to each sector individually. When a SPB is set to “1”, the associated sector may be protected, preventing any program or erase operation on this sector. The SPB bits are set individually by WRSPB command. However, it cannot be cleared individually. Issuing the ESSPB command will erase all SPB in the same time. To unprotect a protected sector (corresponding SPB cleared to “0”), the SPB lock bit must be unlocked first. Under password protection mode (lock register bit 2 set as "0"), a PASSULK command is requested before unlocking SPB lock bit. However, while the device is under Solid Protection mode (lock register bit 1 set as "0"), just a reset or a power-up cycle can unlock the SPB lock bit. After the SPB lock bit unlocked, the SPB status can be changed for desired settings. To lock the Solid Protection Bits after the modification has finished, the SPB Lock Bit must be set once again. To verify the programming state of the SPB for a given sector, issuing a RDSPB Command to the device is required. Note: 1. Once SPB Lock Bit is set, its program or erase command will not be executed and time-out without programming or erasing the SPB. SPB Register Bit Description 7 to 0 SPB (Solid protected Bit) P/N: PM2003 Bit Status 00h= SPB for the sector address unprotected FFh= SPB for the sector address protected 75 Default Type 00h Non-volatile REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) Figure 70. Read SPB Status (RDSPB) Sequence CS# Mode 3 0 1 2 3 4 5 6 7 8 37 38 39 40 41 42 43 44 45 46 47 9 SCLK Mode 0 Command SI 32-Bit Address E2h A31 A30 A2 A1 A0 MSB Data Out High-Z SO 7 6 5 4 3 2 1 0 MSB Figure 71. SPB Erase (ESSPB) Sequence CS# 1 0 Mode 3 2 3 4 5 6 7 SCLK Mode 0 Command SI E4h High-Z SO Figure 72. SPB Program (WRSPB) Sequence CS# Mode 3 0 1 2 3 4 5 6 7 8 9 37 38 39 SCLK Mode 0 SI Command 32-Bit Address E3h A31 A30 A2 A1 A0 MSB P/N: PM2003 76 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-35-4. Dynamic Write Protection Bits The Dynamic Protection features a volatile type protection to each individual sector. It can protect sectors from unintentional change, and is easy to disable when there are necessary changes. All DPBs are default as protected (FFh) after reset or upon power up cycle. Via setting up Dynamic Protection bit (DPB) by write DPB command (WRDPB), user can cancel the Dynamic Protection of associated sector. The Dynamic Protection only works on those unprotected sectors whose SPBs are cleared. After the DPB state is cleared to “0”, the sector can be modified if the SPB state is unprotected state. DPB Register Bit Description 7 to 0 DPB (Dynamic protected Bit) Bit Status Default 00h= DPB for the sector address unprotected FFh FFh= DPB for the sector address protected Type Volatile Figure 73. Read DPB Register (RDDPB) Sequence CS# 0 Mode 3 1 2 3 4 5 6 7 8 37 38 39 40 41 42 43 44 45 46 47 9 SCLK Mode 0 Command SI 32-Bit Address E0h A31 A30 A2 A1 A0 MSB Data Out High-Z SO 7 6 5 4 3 2 1 0 MSB Figure 74. Write DPB Register (WRDPB) Sequence CS# Mode 3 0 1 2 3 4 5 6 7 8 37 38 39 40 41 42 43 44 45 46 47 9 SCLK Mode 0 SI Command E1h A31 A30 A2 A1 A0 MSB P/N: PM2003 Data Byte 1 32-Bit Address 7 6 5 4 3 2 1 0 MSB 77 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-35-5. Temporary Un-protect Solid write protect bit (USPB) Temporary Un-protect Solid write Protect Bit is volatile bit. Software can temporarily unprotect write protect sectors despite of SPBs' property when DPBs are cleared. While the USPB=1, all the SPBs’ property is masked. Notes: 1. Upon power up, the USPB status is default protected. The USPB can be unprotected (to “0”) or protected (to “1”) as often as needed. The hardware reset will reset USPB/DPB to their default values. 2. Please refer to "9-35-7. Sector Protection States Summary Table" for the sector state with the protection status of DPB/SPB/USPB bits. 9-35-6. Gang Block Lock/Unlock (GBLK/GBULK) These instructions are only effective after WPSEL was executed. The GBLK/GBULK instruction is a chip-based protected or unprotected operation. It can enable or disable all DPB. The WREN (Write Enable) instruction is required before issuing GBLK/GBULK instruction. The sequence of issuing GBLK/GBULK instruction is: CS# goes low → send GBLK/GBULK (7Eh/98h) instruction →CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. The CS# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed. 9-35-7. Sector Protection States Summary Table DPB bit 0 0 0 0 1 1 1 1 P/N: PM2003 Protection Status SPB bit 0 0 1 1 0 0 1 1 Sector State USPB bit 0 1 0 1 0 1 0 1 Unprotect Unprotect Unprotect Protect Protect Protect Protect Protect 78 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-35-8. SPB Password Protection Mode The security level of Password Protection Method is higher than the Solid protection mode. The 64 bit password is requested before modify SPB lock bit status. When device is under password protection mode, the SPB lock bit is cleared to “0”, after a power-up cycle or Reset Command. A correct password is required for PASSULK command, to unlock the SPB lock bit. Await 2us is necessary to unlocked the device after valid password is given. After that, the SPB bits are allows to be changed. The PASSULK command are issued slower than 2 μs every time, to prevent hacker from trying all the 64-bit password combinations. To place the device in password protection mode, a few more steps are required. First, prior to entering the password protection mode, it is necessary to set a 64-bit password to verify it. Password verification is only allowed during the password programming operation. Second, the password protection mode is then activated by programming the Password Protection Mode Lock Bit to clear to ”0”. This operation is not reversible. Once the bit is programmed, it cannot be erased, and the device remains permanently in password protection mode, and the 64-bit password can neither be retrieved nor reprogrammed. Moreover, all commands to the address where the password is stored are disabled. The password is all “1”s when shipped from the factory, it is only capable of programming "0"s under WRPASS command. All 64-bit password combinations are valid as a password. No special address is required for programming the password. The password is no longer readable after the Password Protection mode is selected by programming Lock register bit 2 to "0". Once sector under protected status, device will ignores the program/erase command, enable status polling and returns to read mode without contents change. The DPB, SPB and SPB lock bit status of each sector can be verified by issuing RDDPB, RDSPB, and RDSPBLK commands. ● The unlock operation may fail if the password provided by PASSULK command does not match the previously entered password. It causes the same result when a programming operation is performed on a protected sector. The P_ERR bit is set to 1 and the WIP Bit remains set. ● It is not allowed to execute the PASSULK command faster than every 100us ± 20us. The reason behind it is to make it impossible to hack into the system by running through all the combinations of a set of 64-bit password (58 million years). To verify if the device has completed the password unlock command and is available to process a new password command, the Read Status Register command is needed to read the WIP bit. When a valid password is provided the password unlock command does not insert the 100us delay before returning the WIP bit to zero. ● It is not feasible to set the SPB Lock bit if the password is missing after the Password Mode is selected. Password Register (PASS) Bits Field Function Type Name 63 to 0 PWD P/N: PM2003 Description Default State Non-volatile OTP storage of 64 bit password. The Hidden password is no longer readable after the password OTP FFFFFFFFFFFFFFFFh Password protection mode is selected by programming Lock register bit 2 to zero. 79 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-36. Program/Erase Suspend/Resume The device allow the interruption of Sector-Erase, Block-Erase or Page-Program operations and conduct other operations. After issue suspend command, the system can determine if the device has entered the Erase-Suspended mode through Bit2 (PSB) and Bit3 (ESB) of security register. (please refer to "Table 8. Security Register Definition") The latency time of erase operation : Suspend to suspend ready timing: 20us. Resume to another suspend timing: 1ms. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. 9-37. Erase Suspend Erase suspend allow the interruption of all erase operations. After the device has entered Erase-Suspended mode, the system can read any sector(s) or Block(s) except those being erased by the suspended erase operation. Reading the sector or Block being erase suspended is invalid. After erase suspend, WEL bit will be clear, only read related, resume and reset command can be accepted. (including: 03h, 0Bh, 3Bh, 6Bh, BBh, EBh, 5Ah, C0h, 06h, 04h, 2Bh, 9Fh, AFh, 05h, ABh, 90h, B1h, C1h, B0h, 30h, 66h, 99h, 00h, 35h, F5h, 15h, 2Dh, 27h, A7h, E2h, E0h, 16h) If the system issues an Erase Suspend command after the sector erase operation has already begun, the device will not enter Erase-Suspended mode until 20us time has elapsed. Erase Suspend Bit (ESB) indicates the status of Erase Suspend operation. Users may use ESB to identify the state of flash memory. After the flash memory is suspended by Erase Suspend command, ESB is set to "1". ESB is cleared to "0" after erase operation resumes. 9-38. Program Suspend Program suspend allows the interruption of all program operations. After the device has entered ProgramSuspended mode, the system can read any sector(s) or Block(s) except those be­ing programmed by the suspended program operation. Reading the sector or Block being program suspended is invalid. After program suspend, WEL bit will be cleared, only read related, resume and reset command can be accepted. (including: 03h, 0Bh, 3Bh, 6Bh, BBh, EBh, 5Ah, C0h, 06h, 04h, 2Bh, 9Fh, AFh, 05h, ABh, 90h, B1h, C1h, B0h, 30h, 66h, 99h, 00h, 35h, F5h, 15h, 2Dh, 27h, A7h, E2h, E0h, 16h) Program Suspend Bit (PSB) indicates the status of Program Suspend operation. Users may use PSB to identify the state of flash memory. After the flash memory is suspended by Program Suspend command, PSB is set to "1". PSB is cleared to "0" after program operation resumes. P/N: PM2003 80 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) Figure 75. Suspend to Read Latency CS# Suspend Command [B0] Program latency : 20us Erase latency:20us Read Command Figure 76. Resume to Read Latency CS# Resume Command [30] TSE/TBE/TPP Read Command Figure 77. Resume to Suspend Latency CS# P/N: PM2003 Resume Command [30] 1ms 81 Suspend Command [B0] REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-39. Write-Resume The Write operation is being resumed when Write-Resume instruction issued. ESB or PSB (suspend status bit) in Status register will be changed back to “0” The operation of Write-Resume is as follows: CS# drives low → send write resume command cycle (30h) → drive CS# high. By polling Busy Bit in status register, the internal write operation status could be checked to be completed or not. The user may also wait the time lag of TSE, TBE, TPP for Sector-erase, Block-erase or Page-programming. WREN (command "06") is not required to issue before resume. Resume to another suspend operation requires latency time of 1ms. Please note that, if "performance enhance mode" is executed during suspend operation, the device can not be resumed. To restart the write command, disable the "performance enhance mode" is required. After the "performance enhance mode" is disabled, the write-resume command is effective. 9-40. No Operation (NOP) The “No Operation” command is only able to terminate the Reset Enable (RSTEN) command and will not affect any other command. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. 9-41. Software Reset (Reset-Enable (RSTEN) and Reset (RST)) The Software Reset operation combines two instructions: Reset-Enable (RSTEN) command following a Reset (RST) command. It returns the device to a standby mode. All the volatile bits and settings will be cleared then, which makes the device return to the default status as power on. To execute Reset command (RST), the Reset-Enable (RSTEN) command must be executed first to perform the Reset operation. If there is any other command to interrupt after the Reset-Enable command, the Reset-Enable will be invalid. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. If the Reset command is executed during program or erase operation, the operation will be disabled, the data under processing could be damaged or lost. The reset time is different depending on the last operation. For details, please refer to "Table 13. Reset Timing(Other Operation)" for tREADY2. P/N: PM2003 82 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) Figure 78. Software Reset Recovery Stand-by Mode 66 CS# 99 tReady2 Mode Note: Refer to "Table 13. Reset Timing-(Other Operation)" for tReady2 data. Figure 79. Reset Sequence (SPI mode) tSHSL CS# SCLK Mode 3 Mode 3 Mode 0 Mode 0 Command Command 99h 66h SIO0 Figure 80. Reset Sequence (QPI mode) tSHSL CS# MODE 3 MODE 3 MODE 3 SCLK MODE 0 SIO[3:0] P/N: PM2003 Command MODE 0 66h Command MODE 0 99h 83 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 9-42. Read SFDP Mode (RDSFDP) The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on CFI. The sequence of issuing RDSFDP instruction is CS# goes low→send RDSFDP instruction (5Ah)→send 3 address bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP operation can use CS# to high at any time during data out. SFDP is a JEDEC standard, JESD216. Figure 81. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI SO 24 BIT ADDRESS 23 22 21 5Ah 3 2 1 0 High-Z CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Cycle SI 7 6 5 4 3 2 1 0 DATA OUT 2 DATA OUT 1 SO 7 6 5 3 2 1 0 7 MSB MSB P/N: PM2003 4 84 6 5 4 3 2 1 0 7 MSB REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) Table 9. Signature and Parameter Identification Data Values SFDP Table below is for MX66L51235FMJ-10G Description SFDP Signature Comment Fixed: 50444653h Add (h) DW Add Data (h/b) Data (Byte) (Bit) (Note1) (h) 00h 07:00 53h 53h 01h 15:08 46h 46h 02h 23:16 44h 44h 03h 31:24 50h 50h SFDP Minor Revision Number Start from 00h 04h 07:00 00h 00h SFDP Major Revision Number Start from 01h This number is 0-based. Therefore, 0 indicates 1 parameter header. 05h 15:08 01h 01h 06h 23:16 01h 01h 07h 31:24 FFh FFh 00h: it indicates a JEDEC specified header. 08h 07:00 00h 00h Start from 00h 09h 15:08 00h 00h Start from 01h 0Ah 23:16 01h 01h How many DWORDs in the Parameter table 0Bh 31:24 09h 09h 0Ch 07:00 30h 30h 0Dh 15:08 00h 00h 0Eh 23:16 00h 00h 0Fh 31:24 FFh FFh it indicates Macronix manufacturer ID 10h 07:00 C2h C2h Start from 00h 11h 15:08 00h 00h Start from 01h 12h 23:16 01h 01h How many DWORDs in the Parameter table 13h 31:24 04h 04h 14h 07:00 60h 60h 15h 15:08 00h 00h 16h 23:16 00h 00h 17h 31:24 FFh FFh Number of Parameter Headers Unused ID number (JEDEC) Parameter Table Minor Revision Number Parameter Table Major Revision Number Parameter Table Length (in double word) Parameter Table Pointer (PTP) First address of JEDEC Flash Parameter table Unused ID number (Macronix manufacturer ID) Parameter Table Minor Revision Number Parameter Table Major Revision Number Parameter Table Length (in double word) Parameter Table Pointer (PTP) First address of Macronix Flash Parameter table Unused P/N: PM2003 85 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) Table 10. Parameter Table (0): JEDEC Flash Parameter Tables SFDP Table below is for MX66L51235FMJ-10G Description Comment Block/Sector Erase sizes 00: Reserved, 01: 4KB erase, 10: Reserved, 11: not support 4KB erase Write Granularity 0: 1Byte, 1: 64Byte or larger Write Enable Instruction Required 0: not required 1: required 00h to be written to the for Writing to Volatile Status status register Registers Add (h) DW Add Data (h/b) (Byte) (Bit) (Note1) 01b 02 1b 03 0b 30h 0: use 50h opcode, 1: use 06h opcode Write Enable Opcode Select for Note: If target flash status register is Writing to Volatile Status Registers nonvolatile, then bits 3 and 4 must be set to 00b. Contains 111b and can never be Unused changed 4KB Erase Opcode 01:00 31h Data (h) E5h 04 0b 07:05 111b 15:08 20h 16 1b 18:17 01b 19 0b 20 1b 20h (1-1-2) Fast Read (Note2) 0=not support 1=support Address Bytes Number used in addressing flash array Double Transfer Rate (DTR) Clocking 00: 3Byte only, 01: 3 or 4Byte, 10: 4Byte only, 11: Reserved (1-2-2) Fast Read 0=not support 1=support (1-4-4) Fast Read 0=not support 1=support 21 1b (1-1-4) Fast Read 0=not support 1=support 22 1b 23 1b 33h 31:24 FFh 37h:34h 31:00 1FFF FFFFh 0=not support 1=support 32h Unused Unused Flash Memory Density (1-4-4) Fast Read Number of Wait states (Note3) (1-4-4) Fast Read Number of Mode Bits (Note4) 0 0000b: Not supported; 0 0100b: 4 0 0110b: 6; 0 1000b: 8 Mode Bits: 000b: Not supported; 010b: 2 bits (1-4-4) Fast Read Opcode (1-1-4) Fast Read Number of Wait states (1-1-4) Fast Read Number of Mode Bits 39h 0 0000b: Not supported; 0 0100b: 4 0 0110b: 6; 0 1000b: 8 Mode Bits: 000b: Not supported; 010b: 2 bits (1-1-4) Fast Read Opcode P/N: PM2003 38h 3Ah 3Bh 86 04:00 0 0100b 07:05 010b 15:08 EBh 20:16 0 1000b 23:21 000b 31:24 6Bh F3h FFh 44h EBh 08h 6Bh REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) SFDP Table below is for MX66L51235FMJ-10G Description Comment (1-1-2) Fast Read Number of Wait states (1-1-2) Fast Read Number of Mode Bits 0 0000b: Not supported; 0 0100b: 4 0 0110b: 6; 0 1000b: 8 Mode Bits: 000b: Not supported; 010b: 2 bits (1-1-2) Fast Read Opcode (1-2-2) Fast Read Number of Wait states (1-2-2) Fast Read Number of Mode Bits 0 0000b: Not supported; 0 0100b: 4 0 0110b: 6; 0 1000b: 8 Mode Bits: 000b: Not supported; 010b: 2 bits 3Eh 3Fh 0=not support 1=support Unused (4-4-4) Fast Read 3Ch 3Dh (1-2-2) Fast Read Opcode (2-2-2) Fast Read Add (h) DW Add Data (h/b) (Byte) (Bit) (Note1) 0=not support 1=support 40h Unused 04:00 0 1000b 07:05 000b 15:08 3Bh 20:16 0 0100b 23:21 000b 31:24 BBh 00 0b 03:01 111b 04 1b 07:05 111b Data (h) 08h 3Bh 04h BBh FEh Unused 43h:41h 31:08 FFh FFh Unused 45h:44h 15:00 FFh FFh 20:16 0 0000b 23:21 000b 47h 31:24 FFh FFh 49h:48h 15:00 FFh FFh 20:16 0 0100b 23:21 010b 4Bh 31:24 EBh EBh 4Ch 07:00 0Ch 0Ch 4Dh 15:08 20h 20h 4Eh 23:16 0Fh 0Fh 4Fh 31:24 52h 52h 50h 07:00 10h 10h 51h 15:08 D8h D8h 52h 23:16 00h 00h 53h 31:24 FFh FFh (2-2-2) Fast Read Number of Wait states (2-2-2) Fast Read Number of Mode Bits 0 0000b: Not supported; 0 0100b: 4 0 0110b: 6; 0 1000b: 8 Mode Bits: 000b: Not supported; 010b: 2 bits (2-2-2) Fast Read Opcode Unused (4-4-4) Fast Read Number of Wait states (4-4-4) Fast Read Number of Mode Bits 0 0000b: Not supported; 0 0100b: 4 0 0110b: 6; 0 1000b: 8 Mode Bits: 000b: Not supported; 010b: 2 bits (4-4-4) Fast Read Opcode Sector Type 1 Size Sector/block size = 2^N bytes (Note5) 0Ch: 4KB; 0Fh: 32KB; 10h: 64KB Sector Type 1 erase Opcode Sector Type 2 Size Sector/block size = 2^N bytes 00h: N/A; 0Fh: 32KB; 10h: 64KB Sector Type 2 erase Opcode Sector Type 3 Size Sector/block size = 2^N bytes 00h: N/A; 0Fh: 32KB; 10h: 64KB Sector Type 3 erase Opcode Sector Type 4 Size 00h: N/A, This sector type doesn't exist Sector Type 4 erase Opcode P/N: PM2003 87 46h 4Ah 00h 44h REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) Table 11. Parameter Table (1): Macronix Flash Parameter Tables SFDP Table below is for MX66L51235FMJ-10G Description Vcc Supply Maximum Voltage Vcc Supply Minimum Voltage Comment 2000h=2.000V 2700h=2.700V 3600h=3.600V 1650h=1.650V, 1750h=1.750V 2250h=2.250V, 2300h=2.300V 2350h=2.350V, 2650h=2.650V 2700h=2.700V Add (h) DW Add Data (h/b) (Byte) (Bit) (Note1) Data (h) 61h:60h 07:00 15:08 00h 36h 00h 36h 63h:62h 23:16 31:24 00h 27h 00h 27h H/W Reset# pin 0=not support 1=support 00 1b H/W Hold# pin 0=not support 1=support 01 0b Deep Power Down Mode 0=not support 1=support 02 1b S/W Reset 0=not support 1=support 03 1b S/W Reset Opcode Reset Enable (66h) should be issued before Reset Opcode Program Suspend/Resume 0=not support 1=support 12 1b Erase Suspend/Resume 0=not support 1=support 13 1b 14 1b 15 1b 66h 23:16 C0h C0h 67h 31:24 64h 64h 65h:64h Unused Wrap-Around Read mode 0=not support 1=support Wrap-Around Read mode Opcode 11:04 1001 1001b F99Dh (99h) Wrap-Around Read data length 08h:support 8B wrap-around read 16h:8B&16B 32h:8B&16B&32B 64h:8B&16B&32B&64B Individual block lock 0=not support 1=support 00 1b Individual block lock bit (Volatile/Nonvolatile) 0=Volatile 1=Nonvolatile 01 0b 09:02 1110 0001b (E1h) 10 0b 11 1b Individual block lock Opcode Individual block lock Volatile protect bit default protect status 0=protect 1=unprotect Secured OTP 0=not support 1=support Read Lock 0=not support 1=support 12 0b Permanent Lock 0=not support 1=support 13 0b Unused 15:14 11b Unused 31:16 FFh FFh 31:00 FFh FFh Unused 6Bh:68h 6Fh:6Ch CB85h MX66L51235FMJ-10G-SFDP_2015-01-15,SF10 P/N: PM2003 88 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) Note 1: h/b is hexadecimal or binary. Note 2: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x), address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1), (2-2-2), and (4-4-4) Note 3: Wait States is required dummy clock cycles after the address bits or optional mode bits. Note 4: Mode Bits is optional control bits that follow the address bits. These bits are driven by the system controller if they are specified. (eg,read performance enhance toggling bits) Note 5: 4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h Note 6: All unused and undefined area data is blank FFh for SFDP Tables that are defined in Parameter Identification Header. All other areas beyond defined SFDP Table are reserved by Macronix. P/N: PM2003 89 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 10. RESET Driving the RESET# pin low for a period of tRLRH or longer will reset the device. After reset cycle, the device is at the following states: - Standby mode - All the volatile bits such as WEL/WIP/SRAM lock bit will return to the default status as power on. - 3-byte address mode If the device is under programming or erasing, driving the RESET# pin low will also terminate the operation and data could be lost. During the resetting cycle, the SO data becomes high impedance and the current will be reduced to minimum. Figure 82. RESET Timing CS# tRHSL SCLK tRH tRS RESET# tRLRH tREADY1 / tREADY2 Table 12. Reset Timing-(Power On) Symbol Parameter tRHSL Reset# high before CS# low tRS Reset# setup time tRH Reset# hold time tRLRH Reset# low pulse width tREADY1 Reset Recovery time Min. 10 15 15 10 35 Typ. Max. Unit us ns ns us us Min. 10 15 15 10 40 35 310 12 25 100 40 Typ. Max. Unit us ns ns us us us us ms ms ms ms Table 13. Reset Timing-(Other Operation) Symbol tRHSL tRS tRH tRLRH Parameter Reset# high before CS# low Reset# setup time Reset# hold time Reset# low pulse width Reset Recovery time (During instruction decoding) Reset Recovery time (for read operation) Reset Recovery time (for program operation) tREADY2 Reset Recovery time(for SE4KB operation) Reset Recovery time (for BE64K/BE32KB operation) Reset Recovery time (for Chip Erase operation) Reset Recovery time (for WRSR operation) P/N: PM2003 90 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 11. POWER-ON STATE The device is at the following states after power-up: - Standby mode (please note it is not deep power-down mode) - Write Enable Latch (WEL) bit is reset The device must not be selected during power-up and power-down stage until the VCC reaches the following levels: - VCC minimum at power-up stage and then after a delay of tVSL - GND at power-down Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level. An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change during power up state. When VCC is lower than VWI (POR threshold voltage value), the internal logic is reset and the flash device has no response to any command. For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The write, erase, and program command should be sent after the below time delay: - tVSL after VCC reached VCC minimum level The device can accept read command after VCC reached VCC minimum and a time delay of tVSL. Please refer to the "power-up timing". Note: - To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended. (generally around 0.1uF) - At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response to any command. The data corruption might occur during this stage if a write, program, erase cycle is in progress. P/N: PM2003 91 REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) 12. ELECTRICAL SPECIFICATIONS Table 14. ABSOLUTE MAXIMUM RATINGS RATING VALUE Ambient Operating Temperature Industrial grade -40°C to 105°C Storage Temperature -65°C to 150°C Applied Input Voltage -0.5V to VCC+0.5V Applied Output Voltage -0.5V to VCC+0.5V VCC to Ground Potential -0.5V to 4.0V NOTICE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. 2. Specifications contained within the following tables are subject to change. 3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see Figure 83, and Figure 84. Figure 84. Maximum Positive Overshoot Waveform Figure 83. Maximum Negative Overshoot Waveform 20ns 20ns 20ns Vss Vcc + 2.0V Vss-2.0V Vcc 20ns 20ns 20ns Table 15. CAPACITANCE TA = 25°C, f = 1.0 MHz Symbol Parameter CIN COUT P/N: PM2003 Min. Typ. Max. Unit Input Capacitance 35 pF VIN = 0V Output Capacitance 32 pF VOUT = 0V 92 Conditions REV. 1.0, JAN. 20, 2015 MX66L51235F (J Grade) Figure 85. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL Input timing reference level 0.8VCC Output timing reference level 0.7VCC AC Measurement Level 0.8V 0.2VCC 0.5VCC Note: Input pulse rise and fall time are