MX66U1G45G
MX66U1G45G
1.8V, 1G-BIT [x 1/x 2/x 4]
CMOS MXSMIO® (SERIAL MULTI I/O)
FLASH MEMORY
Key Features
• Multi I/O Support - Single I/O, Dual I/O and Quad I/O
• Support DTR (Double Transfer Rate) Mode
• 8/16/32/64 byte Wrap-Around Read Mode
Macronix Proprietary
Downloaded from Arrow.com.
MX66U1G45G
Contents
1. FEATURES............................................................................................................................................................... 5
2. GENERAL DESCRIPTION...................................................................................................................................... 7
Table 1. Read performance Comparison.....................................................................................................7
3. PIN CONFIGURATIONS .......................................................................................................................................... 8
Table 2. PIN DESCRIPTION........................................................................................................................8
4. BLOCK DIAGRAM.................................................................................................................................................... 9
5. MEMORY ORGANIZATION.................................................................................................................................... 10
6. DATA PROTECTION............................................................................................................................................... 11
6-1.
Block lock protection................................................................................................................................. 12
Table 3. Protected Area Sizes....................................................................................................................12
6-2. Additional 8K-bit secured OTP ................................................................................................................. 13
Table 4. 8K-bit Secured OTP Definition.....................................................................................................13
7. DEVICE OPERATION............................................................................................................................................. 14
7-1. 256Mb Address Protocol........................................................................................................................... 17
7-2. Quad Peripheral Interface (QPI) Read Mode........................................................................................... 21
8. COMMAND SET..................................................................................................................................................... 22
Table 5. Read/Write Array Commands.......................................................................................................22
Table 6. Read/Write Array Commands (4 Byte Address Command Set)...................................................23
Table 7. Register/Setting Commands.........................................................................................................24
Table 8. ID/Security Commands.................................................................................................................25
Table 9. Reset Commands.........................................................................................................................26
9. REGISTER DESCRIPTION..................................................................................................................................... 27
9-1.
9-2.
9-3.
Status Register......................................................................................................................................... 27
Configuration Register.............................................................................................................................. 28
Security Register...................................................................................................................................... 30
Table 10. Security Register Definition........................................................................................................30
10. COMMAND DESCRIPTION.................................................................................................................................. 31
10-1.
10-2.
10-3.
10-4.
10-5.
10-6.
Write Enable (WREN)............................................................................................................................... 31
Write Disable (WRDI)................................................................................................................................ 32
Read Identification (RDID)........................................................................................................................ 33
Release from Deep Power-down (RDP), Read Electronic Signature (RES)............................................ 34
Read Electronic Manufacturer ID & Device ID (REMS)............................................................................ 36
QPI ID Read (QPIID)................................................................................................................................ 37
Table 11. ID Definitions .............................................................................................................................37
10-7. Read Status Register (RDSR).................................................................................................................. 38
10-8. Read Configuration Register (RDCR)....................................................................................................... 39
10-9. Write Status Register (WRSR).................................................................................................................. 42
Table 12. Protection Modes........................................................................................................................43
10-10. Enter 4-byte mode (EN4B)....................................................................................................................... 46
10-11. Exit 4-byte mode (EX4B).......................................................................................................................... 46
10-12. Read Data Bytes (READ)......................................................................................................................... 47
10-13. Read Data Bytes at Higher Speed (FAST_READ)................................................................................... 48
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
2
Rev. 1.4, July 27, 2020
MX66U1G45G
10-14. Dual Output Read Mode (DREAD)........................................................................................................... 49
10-15. 2 x I/O Read Mode (2READ).................................................................................................................... 50
10-16. Quad Read Mode (QREAD)..................................................................................................................... 51
10-17. 4 x I/O Read Mode (4READ).................................................................................................................... 52
10-18. 4 x I/O Double Transfer Rate Read Mode (4DTRD)................................................................................. 54
10-19. Preamble Bit ............................................................................................................................................ 56
10-20. 4 Byte Address Command Set.................................................................................................................. 60
10-21. Performance Enhance Mode - XIP (execute-in-place)............................................................................. 65
10-22. Burst Read................................................................................................................................................ 70
10-23. Fast Boot.................................................................................................................................................. 71
10-24. Sector Erase (SE)..................................................................................................................................... 74
10-25. Block Erase (BE32K)................................................................................................................................ 75
10-26. Block Erase (BE)...................................................................................................................................... 76
10-27. Chip Erase (CE)........................................................................................................................................ 77
10-28. Page Program (PP).................................................................................................................................. 78
10-29. 4 x I/O Page Program (4PP)..................................................................................................................... 80
10-30. Deep Power-down (DP)............................................................................................................................ 81
10-31. Enter Secured OTP (ENSO)..................................................................................................................... 82
10-32. Exit Secured OTP (EXSO)........................................................................................................................ 82
10-33. Read Security Register (RDSCUR).......................................................................................................... 82
10-34. Write Security Register (WRSCUR).......................................................................................................... 82
10-35. Write Protection Selection (WPSEL)......................................................................................................... 83
10-36. Advanced Sector Protection..................................................................................................................... 85
10-37. Program Suspend and Erase Suspend.................................................................................................... 93
Table 13. Acceptable Commands During Suspend...................................................................................94
10-38. Program Resume and Erase Resume...................................................................................................... 95
10-39. No Operation (NOP)................................................................................................................................. 96
10-40. Software Reset (Reset-Enable (RSTEN) and Reset (RST)).................................................................... 96
11. Serial Flash Discoverable Parameter (SFDP)................................................................................................... 98
11-1. Read SFDP Mode (RDSFDP)................................................................................................................... 98
Table 14. Signature and Parameter Identification Data Values .................................................................99
Table 15. Parameter Table (0): JEDEC Flash Parameter Tables.............................................................101
Table 16. Parameter Table (1): 4-Byte Instruction Tables........................................................................108
Table 17. Parameter Table (2): Macronix Flash Parameter Tables.......................................................... 110
12. RESET................................................................................................................................................................ 112
Table 18. Reset Timing-(Power On)......................................................................................................... 112
Table 19. Reset Timing-(Other Operation)............................................................................................... 112
13. POWER-ON STATE............................................................................................................................................ 113
14. ELECTRICAL SPECIFICATIONS....................................................................................................................... 114
Table 20. ABSOLUTE MAXIMUM RATINGS........................................................................................... 114
Table 21. CAPACITANCE TA = 25°C, f = 1.0 MHz................................................................................... 114
Table 22. DC CHARACTERISTICS......................................................................................................... 116
Table 23. AC CHARACTERISTICS.......................................................................................................... 117
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
3
Rev. 1.4, July 27, 2020
MX66U1G45G
15. OPERATING CONDITIONS................................................................................................................................ 119
Table 24. Power-Up/Down Voltage and Timing .......................................................................................121
15-1. INITIAL DELIVERY STATE..................................................................................................................... 121
16. ERASE AND PROGRAMMING PERFORMANCE............................................................................................. 122
17. DATA RETENTION............................................................................................................................................. 122
18. LATCH-UP CHARACTERISTICS....................................................................................................................... 122
19. ORDERING INFORMATION............................................................................................................................... 123
20. PART NAME DESCRIPTION.............................................................................................................................. 124
21. PACKAGE INFORMATION................................................................................................................................. 125
22. REVISION HISTORY .......................................................................................................................................... 127
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
4
Rev. 1.4, July 27, 2020
MX66U1G45G
1.8V 1G-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O)
FLASH MEMORY
1. FEATURES
GENERAL
• Supports Serial Peripheral Interface -- Mode 0 and Mode 3
• Single Power Supply Operation
- 1.65 to 2.0 volt for read, erase, and program operations
• Protocol Support
- Single I/O, Dual I/O and Quad I/O
• Latch-up protected to 100mA from -1V to Vcc +1V
• Fast read for SPI mode
- Support fast clock frequency up to 166MHz
- Support Fast Read, 2READ, DREAD, 4READ, QREAD instructions
- Support DTR (Double Transfer Rate) Mode
- Configurable dummy cycle number for fast read operation
• Support Performance Enhance Mode - XIP (execute-in-place)
• Quad Peripheral Interface (QPI) available
• Equal Sectors with 4K byte each, or Equal Blocks with 32K byte each or Equal Blocks with 64K byte each
- Any Block can be erased individually
• Programming :
- 256byte page buffer
- Quad Input/Output page program(4PP) to enhance program performance
• Typical 100,000 erase/program cycles
• 20 years data retention
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block lock protection
The BP0-BP3 and T/B status bits define the size of the area to be protected against program and erase
instructions
- Advanced sector protection function
• Additional 8K bit security OTP
- Features unique identifier
- Factory locked identifiable, and customer lockable
• Command Reset
• Program/Erase Suspend and Resume operation
• Electronic Identification
- JEDEC 1-byte manufacturer ID and 2-byte device ID
- RES command for 1-byte Device ID
- REMS command for 1-byte manufacturer ID and 1-byte device ID
• Support Serial Flash Discoverable Parameters (SFDP) mode
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
5
Rev. 1.4, July 27, 2020
MX66U1G45G
HARDWARE FEATURES
• SCLK Input
- Serial clock input
• SI/SIO0
- Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
• SO/SIO1
- Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
• WP#/SIO2
- Hardware write protection or serial data Input/Output for 4 x I/O read mode
• NC/SIO3
- No Connection or Serial input & Output for 4 x I/O read mode
• RESET#
- Hardware Reset pin
• PACKAGE
- 24-Ball BGA (5x5 ball array)
- 16-pin SOP (300mil)
- All devices are RoHS Compliant and Halogen-free
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
6
Rev. 1.4, July 27, 2020
MX66U1G45G
2. GENERAL DESCRIPTION
MX66U1G45G is 1Gb bits Serial NOR Flash memory, which is configured as 134,217,728 x 8 internally. When
it is in two or four I/O mode, the structure becomes 536,870,912 bits x 2 or 268,435,456 bits x 4. MX66U1G45G
features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in
single I/O mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO).
Serial access to the device is enabled by CS# input.
When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits
input and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# and RESET# pin become SIO0
pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output.
The MX66U1G45G MXSMIO (Serial Multi I/O) provides sequential read operation on whole chip.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the
specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis, or word basis for erase command is executed on sector (4K-byte), block (32K-byte), or block (64K-byte),
or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
Advanced security features enhance the protection and security functions, please see security features section for
more details.
When the device is not in operation and CS# is high, it is put in standby mode.
The MX66U1G45G utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after
100,000 program and erase cycles.
Table 1. Read performance Comparison
Numbers of
Dummy Cycles
Fast Read
(MHz)
Dual Output
Fast Read
(MHz)
Quad Output
Fast Read
(MHz)
Dual IO
Fast Read
(MHz)
Quad IO
Fast Read
(MHz)
Quad I/O DT
Read
4
-
-
-
84*
70
42
6
133
133
104
104
84*
52*
8
133*
133*
133*
133
104
66
10
166
166
166
166
133
100
(MHz)
Note: * mean default status
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
7
Rev. 1.4, July 27, 2020
MX66U1G45G
3. PIN CONFIGURATIONS
16-PIN SOP (300mil)
NC/SIO3
VCC
RESET#
NC
DNU
DNU
CS#
SO/SIO1
1
2
3
4
5
6
7
8
Table 2. PIN DESCRIPTION
16
15
14
13
12
11
10
9
SYMBOL
CS#
SCLK
RESET#
DESCRIPTION
Chip Select
Clock Input
Hardware Reset Pin Active low (Note1)
Serial Data Input (for 1 x I/O)/ Serial
SI/SIO0 Data Input & Output (for 2xI/O or 4xI/O
read mode)
Serial Data Output (for 1 x I/O)/ Serial
SO/SIO1 Data Input & Output (for 2xI/O or 4xI/O
read mode)
Write Protection Active Low or Serial
WP#/SIO2 Data Input & Output (for 4xI/O read
mode)
No Connection or Serial Data Input &
NC/SIO3
Output (for 4xI/O read mode)
VCC
Power Supply
GND
Ground
NC
No Connection
Do Not Use (It may connect to internal
DNU
signal inside)
SCLK
SI/SIO0
NC
NC
DNU
DNU
GND
WP#/SIO2
24-Ball BGA (5x5 ball array)
1
2
3
4
5
NC
NC
RESET#
DNU
NC
SCLK
GND
VCC
NC
NC
CS#
NC
WP#/SIO2
NC
NC
SO/SIO1
SI/SIO0
NC/SIO3
NC
NC
NC
NC
NC
NC
A
B
C
D
E
P/N: PM2352
Downloaded from Arrow.com.
Note:
1. The pin of RESET# or WP#/SIO2 will remain internal
pull up function while this pin is not physically
connected in system configuration.
H owever, the internal pull up function will be
disabled if the system has physical connection to
RESET# or WP#/SIO2 pin.
Macronix Proprietary
8
Rev. 1.4, July 27, 2020
MX66U1G45G
4. BLOCK DIAGRAM
X-Decoder
Address
Generator
SI/SIO0
SO/SIO1
SIO2 *
SIO3 *
WP# *
HOLD# *
RESET# *
CS#
Y-Decoder
Data
Register
Sense
Amplifier
SRAM
Buffer
Mode
Logic
SCLK
Memory Array
State
Machine
HV
Generator
Clock Generator
Output
Buffer
* Depends on part number options.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
9
Rev. 1.4, July 27, 2020
MX66U1G45G
5. MEMORY ORGANIZATION
Sector
2045
4090
…
…
…
…
7FF0FFFh
7FEF000h
7FEFFFFh
32744
7FE8000h
7FE8FFFh
32743
7FE7000h
7FE7FFFh
…
…
7FF0000h
32751
…
32752
…
individual 16 sectors
lock/unlock unit:4K-byte
32736
7FE0000h
7FE0FFFh
32735
7FDF000h
7FDFFFFh
…
4091
7FF7FFFh
32728
7FD8000h
7FD8FFFh
32727
7FD7000h
7FD7FFFh
…
individual block
lock/unlock unit:64K-byte
7FF7000h
…
4092
32759
…
2046
7FF8FFFh
…
4093
7FF8000h
…
4094
32760
…
2047
7FFFFFFh
…
4095
Address Range
7FFF000h
…
32767
…
Block(64K-byte) Block(32K-byte)
32720
7FD0000h
7FD0FFFh
47
002F000h
002FFFFh
0
0
P/N: PM2352
Downloaded from Arrow.com.
…
…
…
…
…
0020FFFh
001F000h
001FFFFh
…
…
0020000h
31
0018000h
0018FFFh
23
0017000h
0017FFFh
…
…
24
0010000h
0010FFFh
15
000F000h
000FFFFh
…
16
8
0008000h
0008FFFh
7
0007000h
0007FFFh
…
1
32
…
2
0027FFFh
…
1
0028FFFh
027000h
…
3
0028000h
39
…
4
individual block
lock/unlock unit:64K-byte
40
…
2
…
5
…
individual block
lock/unlock unit:64K-byte
0
0000000h
0000FFFh
Macronix Proprietary
10
individual 16 sectors
lock/unlock unit:4K-byte
Rev. 1.4, July 27, 2020
MX66U1G45G
6. DATA PROTECTION
During power transition, there may be some false system level signals which result in inadvertent erasure or
programming. The device is designed to protect itself from these accidental write cycles.
The state machine will be reset as standby mode automatically during power up. In addition, the control register
architecture of the device constrains that the memory contents can only be changed after specific command
sequences have completed successfully.
In the following, there are several features to protect the system from the accidental write cycles during VCC powerup and power-down or from system noise.
• Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
other command to change data.
• Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from
writing all commands except Release from deep power down mode command (RDP) and Read Electronic
Signature command (RES), Erase/Program suspend command, Erase/Program resume command and softreset
command.
• Advanced Security Features: there are some protection and security features which protect content from
inadvertent write and hostile access.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
11
Rev. 1.4, July 27, 2020
MX66U1G45G
6-1. Block lock protection
- The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0 and T/B) bits to allow part of memory to be
protected as read only. The protected area definition is shown as "Table 3. Protected Area Sizes", the protected
areas are more flexible which may protect various area by setting value of BP0-BP3 bits.
- The Hardware Protected Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and Status
Register Write Protect bit.
- In four I/O and QPI mode, the feature of HPM will be disabled.
Table 3. Protected Area Sizes
Protected Area Sizes (T/B bit = 0)
Status bit
BP3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
BP2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
BP1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Protect Level
BP0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1Gb
0 (none)
1 (1 block, protected block 2047th)
2 (2 blocks, protected block 2046th~2047th)
3 (4 blocks, protected block 2044th~2047th)
4 (8 blocks, protected block 2040th~2047th)
5 (16 blocks, protected block 2032nd~2047th)
6 (32 blocks, protected block 2016th~2047th)
7 (64 blocks, protected block 1984th~2047th)
8 (128 blocks, protected block 1920th~2047th)
9 (256 blocks, protected block 1792nd~2047th)
10 (512 blocks, protected block 1536th~2047th)
11 (1024 blocks, protected block 1024th~2047th)
12 (2048 blocks, protected all)
13 (2048 blocks, protected all)
14 (2048 blocks, protected all)
15 (2048 blocks, protected all)
Protected Area Sizes (T/B bit = 1)
Status bit
BP3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
P/N: PM2352
Downloaded from Arrow.com.
BP2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
BP1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Protect Level
BP0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1Gb
0 (none)
1 (1 block, protected block 0th)
2 (2 blocks, protected block 0th~1st)
3 (4 blocks, protected block 0th~3rd)
4 (8 blocks, protected block 0th~7th)
5 (16 blocks, protected block 0th~15th)
6 (32 blocks, protected block 0th~31st)
7 (64 blocks, protected block 0th~63rd)
8 (128 blocks, protected block 0th~127th)
9 (256 blocks, protected block 0th~255th)
10 (512 blocks, protected block 0th~511th)
11 (1024 blocks, protected block 0th~1023rd)
12 (2048 blocks, protected all)
13 (2048 blocks, protected all)
14 (2048 blocks, protected all)
15 (2048 blocks, protected all)
Macronix Proprietary
12
Rev. 1.4, July 27, 2020
MX66U1G45G
6-2. Additional 8K-bit secured OTP
The secured OTP for unique identifier: to provide 8K-bit one-time program area for setting device unique serial
number. Which may be set by factory or system customer.
- Security register bit 0 indicates whether the chip is locked by factory or not.
- To program the 8K-bit secured OTP by entering secured OTP mode (with Enter Security OTP command), and
going through normal program procedure, and then exiting secured OTP mode by writing Exit Security OTP
command.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register)
command to set customer lock-down bit1 as "1". Please refer to "Table 10. Security Register Definition" for
security register bit definition and "Table 4. 8K-bit Secured OTP Definition" for address range definition.
- Note: Once lock-down by factory or customer, the corresponding range cannot be changed any more. While in
secured OTP mode, array access is not allowed.
Table 4. 8K-bit Secured OTP Definition
Address range
Size
Lock-down
xxx000~xxx1FF
4096-bit
Determined by Customer
xxx200~xxx3FF
4096-bit
Determined by Factory
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
13
Rev. 1.4, July 27, 2020
MX66U1G45G
7. DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended
operation.
2. When incorrect command is inputted to this device, this device becomes standby mode and keeps the standby
mode until next CS# falling edge. In standby mode, SO pin of this device should be High-Z.
3. When correct command is inputted to this device, this device becomes active mode and keeps the active mode
until next CS# rising edge.
4. Input data is latched on the rising edge of Serial Clock (SCLK) and data shifts out on the falling edge of SCLK.
The difference of Serial mode 0 and mode 3 is shown as "Serial Modes Supported".
5. For the following instructions: RDID, RDSR, RDSCUR, READ/READ4B, FAST_READ/FAST_READ4B,
2READ/2READ4B, DREAD/DREAD4B, 4READ/4READ4B, QREAD/QREAD4B, RDSFDP, RES, REMS,
QPIID, RDDPB, RDSPB, RDLR, RDEAR, RDFBR, RDCR the shifted-in instruction sequence is followed by a
data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions:
WREN, WRDI, WRSR, SE/SE4B, BE32K/BE32K4B, BE/BE4B, CE, PP/PP4B, 4PP/4PP4B, DP, ENSO, EXSO,
WRSCUR, EN4B, EX4B, WPSEL, GBLK, GBULK, SUSPEND, RESUME, NOP, RSTEN, RST, EQIO, RSTQIO
the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is
neglected and not affect the current operation of Write Status Register, Program, Erase.
Figure 1. Serial Modes Supported
CPOL
CPHA
shift in
(Serial mode 0)
0
0
SCLK
(Serial mode 3)
1
1
SCLK
SI
shift out
MSB
SO
MSB
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is
supported.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
14
Rev. 1.4, July 27, 2020
MX66U1G45G
Figure 2. Serial Input Timing (STR mode)
tSHSL
CS#
tCHSL
tSLCH
tCHSH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
tCLCH
LSB
MSB
SI
SO
High-Z
Figure 3. Serial Input Timing (DTR mode)
tSHSL
CS#
tCHSL
tSLCH
tSHCH
SCLK
tDVCH
tCHDX
SIO[3:0]
P/N: PM2352
Downloaded from Arrow.com.
tCHCL
tCLDX
tDVCL
MSB
tCLCH
LSB
Macronix Proprietary
15
Rev. 1.4, July 27, 2020
MX66U1G45G
Figure 4. Output Timing (STR mode)
CS#
tCH
SCLK
tCLQV
tCL
tCLQV
tCLQX
tSHQZ
tCLQX
LSB
SO
SI
ADDR.LSB IN
Figure 5. Output Timing (DTR mode)
CS#
tCH
SCLK
tCLQV
tCLQX
tCL
tCLQV
tCLQX
LSB
SO
SI
tSHQZ
ADDR.LSB IN
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
16
Rev. 1.4, July 27, 2020
MX66U1G45G
7-1. 256Mb Address Protocol
The original 24 bit address protocol of Serial NOR Flash can only access density size below 128Mb. For the
memory device of 256Mb and above, the 32bit address is requested for access higher memory size. The
MX66U1G45G provides three different methods to access the whole density:
(1) Command entry 4-byte address mode:
Issue Enter 4-Byte mode command to set up the 4BYTE bit in Configuration Register bit. After 4BYTE bit has
been set, the number of address cycle become 32-bit.
(2) Extended Address Register (EAR):
configure the memory device into eight 128Mb segments to select which one is active through the EAR.
(3) 4-byte Address Command Set:
When issuing 4-byte address command set, 4-byte address (A31-A0) is requested after the instruction code.
Please note that it is not necessary to issue EN4B command before issuing any of 4-byte command set.
Enter 4-Byte Address Mode
In 4-byte Address mode, all instructions are 32-bits address clock cycles. By using EN4B and EX4B to enable and
disable the 4-byte address mode.
When 4-byte address mode is enabled, the EAR becomes "don't care" for all instructions requiring 4-byte
address. The EAR function will be disabled when 4-byte mode is enabled.
Extended Address Register
The device provides an 8-bit volatile register for extended Address Register: it identifies the extended address (A31~A24)
above 128Mb density by using original 3-byte address.
Extended Address Register (EAR)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
A31
A30
A29
A28
A27
A26
A25
A24
For the MX66U1G45G the A31 to A27 are Don't Care. During EAR, reading these bits will read as 0. The bit 0 is
default as "0".
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
17
Rev. 1.4, July 27, 2020
MX66U1G45G
Figure 6. EAR Operation Segments
07FFFFFFh
EAR= 111
07000000h
06FFFFFFh
EAR= 110
06000000h
05FFFFFFh
EAR= 101
05000000h
04FFFFFFh
EAR= 100
04000000h
03FFFFFFh
EAR= 011
03000000h
02FFFFFFh
EAR= 010
02000000h
01FFFFFFh
EAR= 001
01000000h
00FFFFFFh
EAR= 000
00000000h
When under EAR mode, Read, Program, Erase operates in the selected segment by using 3-byte address mode.
For the read operation, the whole array data can be continually read out with one command. Data output starts from
the selected 128Mb block, but it can cross the boundary. When the last byte of the segment is reached, the next byte (in
a continuous reading) is the first byte of the next segment. However, the EAR (Extended Address Register) value
does not change. The random access reading can only be operated in the selected segment.
The Chip erase command will erase the whole chip and is not limited by EAR selected segment. However, the
sector erase ,block erase , program operation are limited in selected segment and will not cross the boundary.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
18
Rev. 1.4, July 27, 2020
MX66U1G45G
Figure 7. Write EAR Register (WREAR) Sequence (SPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
Mode 0
command
SI
EAR In
C5h
7
4
5
3
2
1
0
MSB
High-Z
SO
6
Figure 8. Write EAR Register (WREAR) Sequence (QPI Mode)
CS#
Mode 3
0
1
2
3
Mode 3
SCLK
Mode 0
Mode 0
Command EAR in
SIO[3:0]
P/N: PM2352
Downloaded from Arrow.com.
C5h
H0
L0
Macronix Proprietary
19
Rev. 1.4, July 27, 2020
MX66U1G45G
Figure 9. Read EAR (RDEAR) Sequence (SPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
Mode 0
command
C8h
SI
SO
EAR Out
High-Z
7
6
5
4
3
EAR Out
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
Figure 10. Read EAR (RDEAR) Sequence (QPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
N
SCLK
Mode 0
SIO[3:0]
C8h
H0 L0 H0 L0 H0 L0
H0 L0
MSB LSB
EAR Out
P/N: PM2352
Downloaded from Arrow.com.
EAR Out
EAR Out
Macronix Proprietary
20
EAR Out
Rev. 1.4, July 27, 2020
MX66U1G45G
7-2. Quad Peripheral Interface (QPI) Read Mode
QPI protocol enables user to take full advantage of Quad I/O Serial Flash by providing the Quad I/O interface in
command cycles, address cycles and as well as data output cycles.
Enable QPI mode
By issuing 35H command, the QPI mode is enable.
Figure 11. Enable QPI Sequence
CS#
MODE 3
SCLK
0
1
2
3
4
5
6
7
MODE 0
SIO0
35h
SIO[3:1]
Reset QPI (RSTQIO)
To reset the QPI mode, the RSTQIO (F5H) command is required. After the RSTQIO command is issued, the device
returns from QPI mode (4 I/O interface in command cycles) to SPI mode (1 I/O interface in command cycles).
Note:
For EQIO and RSTQIO commands, CS# high width has to follow "write spec" tSHSL for next instruction.
Figure 12. Reset QPI Mode
CS#
SCLK
SIO[3:0]
P/N: PM2352
Downloaded from Arrow.com.
F5h
Macronix Proprietary
21
Rev. 1.4, July 27, 2020
MX66U1G45G
8. COMMAND SET
Table 5. Read/Write Array Commands
Command
READ
FAST READ
2READ
(byte)
(normal read) (fast read data) (2 x I/O read)
Mode
SPI
SPI
SPI
Address Bytes
3/4
3/4
3/4
1st byte
03 (hex)
0B (hex)
BB (hex)
DREAD
(1I 2O read)
SPI
3/4
3B (hex)
4READ
(4 I/O read)
SPI/QPI
3/4
EB (hex)
QREAD
(1I 4O read)
SPI
3/4
6B (hex)
4DTRD (Quad
I/O DT Read)
SPI/QPI
3/4
ED (hex)
2nd byte
ADD1
ADD1
ADD1
ADD1
ADD1
ADD1
ADD1
3rd byte
ADD2
ADD2
ADD2
ADD2
ADD2
ADD2
ADD2
4th byte
ADD3
ADD3
ADD3
ADD3
ADD3
ADD3
ADD3
Dummy*
Dummy*
Dummy*
Dummy*
Dummy*
Dummy*
5th byte
Data Cycles
Action
n bytes read
out until CS#
goes high
Command
(byte)
PP
(page program)
n bytes read
n bytes read
n bytes read
n bytes read
n bytes read
n bytes read
out until CS# out by 2 x I/O
out by Dual
out by 4 x I/O out by Quad
out (Double
goes high
until CS# goes output until until CS# goes output until Transfer Rate)
high
CS# goes high
high
CS# goes high by 4xI/O until
CS# goes high
Mode
SPI/QPI
4PP
(quad page
program)
SPI
SPI/QPI
BE 32K
(block erase
32KB)
SPI/QPI
Address Bytes
3/4
3/4
3/4
3/4
3/4
0
1st byte
02 (hex)
38 (hex)
20 (hex)
52 (hex)
D8 (hex)
60 or C7 (hex)
2nd byte
ADD1
ADD1
ADD1
ADD1
ADD1
3rd byte
ADD2
ADD2
ADD2
ADD2
ADD2
4th byte
ADD3
ADD3
ADD3
ADD3
ADD3
SE
(sector erase)
BE
(block erase
64KB)
SPI/QPI
CE
(chip erase)
SPI/QPI
5th byte
Data Cycles
Action
1-256
1-256
to program the quad input to
to erase the
to erase the
selected page program the selected sector selected 32K
selected page
block
to erase the to erase whole
selected block
chip
* Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in configuration register.
Notes 2: Please note the address cycles above are based on 3-byte address mode. After enter 4-byte address
mode by EN4B command, the address cycles will be increased to 4byte.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
22
Rev. 1.4, July 27, 2020
MX66U1G45G
Table 6. Read/Write Array Commands (4 Byte Address Command Set)
Command
(byte)
READ4B
FAST
READ4B
2READ4B
DREAD4B
4READ4B
QREAD4B
Mode
Address Bytes
SPI
4
SPI
4
SPI
4
SPI
4
SPI/QPI
4
SPI
4
4DTRD4B
(Quad I/O DT
Read)
SPI/QPI
4
1st byte
13 (hex)
0C (hex)
BC (hex)
3C (hex)
EC (hex)
6C (hex)
EE (hex)
2nd byte
ADD1
ADD1
ADD1
ADD1
ADD1
ADD1
ADD1
3rd byte
ADD2
ADD2
ADD2
ADD2
ADD2
ADD2
ADD2
4th byte
ADD3
ADD3
ADD3
ADD3
ADD3
ADD3
ADD3
5th byte
ADD4
6th byte
ADD4
ADD4
ADD4
ADD4
ADD4
ADD4
Dummy*
Dummy*
Dummy*
Dummy*
Dummy*
Dummy*
Data Cycles
Action
n bytes read
read data byte read data byte read data byte Read data byte read data byte
Read data
by
by
by 2 x I/O with by Dual Output by 4 x I/O with byte by Quad
out (Double
4 byte address 4 byte address 4 byte address with 4 byte 4 byte address Output with 4 Transfer Rate)
address
byte address by 4xI/O until
CS# goes high
SPI
4
BE4B
(block erase
64KB)
SPI/QPI
4
BE32K4B
(block erase
32KB)
SPI/QPI
4
SE4B
(Sector erase
4KB)
SPI/QPI
4
12 (hex)
3E (hex)
DC (hex)
5C (hex)
21 (hex)
2nd byte
ADD1
ADD1
ADD1
ADD1
ADD1
3rd byte
ADD2
ADD2
ADD2
ADD2
ADD2
4th byte
ADD3
ADD3
ADD3
ADD3
ADD3
5th byte
ADD4
ADD4
ADD4
ADD4
ADD4
Command
(byte)
PP4B
4PP4B
Mode
Address Bytes
SPI/QPI
4
1st byte
6th byte
Data Cycles
Action
P/N: PM2352
Downloaded from Arrow.com.
1-256
1-256
to erase the
to erase the
to erase the
to program the Quad input to
selected page program the selected (64KB) selected (32KB) selected (4KB)
block with
block with
sector with
with 4byte
selected page
with 4byte
4byte address 4byte address 4byte address
address
address
Macronix Proprietary
23
Rev. 1.4, July 27, 2020
MX66U1G45G
Table 7. Register/Setting Commands
Mode
SPI/QPI
SPI/QPI
SPI/QPI
RDCR
(read
configuration
register)
SPI/QPI
1st byte
06 (hex)
04 (hex)
05 (hex)
15 (hex)
Command
(byte)
WREN
WRDI
(write enable) (write disable)
RDSR
(read status
register)
WRSR
RDEAR
WREAR
(write status/ (read extended (write extended
configuration
address
address
register)
register)
register)
SPI/QPI
SPI/QPI
SPI/QPI
01 (hex)
2nd byte
Values
3rd byte
Values
C8 (hex)
C5 (hex)
4th byte
5th byte
Data Cycles
sets the (WEL)
resets the
to read out the to read out the
write enable
(WEL) write
values of the values of the
latch bit
enable latch bit status register configuration
register
1-2
to write new
values of the
status/
configuration
register
Command
(byte)
WPSEL
(Write Protect
Selection)
EQIO
(Enable QPI)
RSTQIO
(Reset QPI)
EN4B
(enter 4-byte
mode)
EX4B
(exit 4-byte
mode)
Mode
1st byte
SPI
68 (hex)
SPI
35 (hex)
QPI
F5 (hex)
SPI/QPI
B7 (hex)
SPI/QPI
E9 (hex)
to enter and
enable individal
block protect
mode
Entering the
QPI mode
DP
(Deep power
down)
SPI/QPI
B9 (hex)
RDP (Release
from deep
power down)
SPI/QPI
AB (hex)
SBL
(Set Burst
Length)
SPI/QPI
C0 (hex)
enters deep
power down
mode
release from
deep power
down mode
to set Burst
length
Action
1
read extended write extended
address
address
register
register
PGM/ERS
PGM/ERS
Resume
Suspend
(Suspends
(Resumes
Program/
Program/
Erase)
Erase)
SPI/QPI
SPI/QPI
B0 or 75 (hex) 30 or 7A (hex)
2nd byte
3rd byte
4th byte
5th byte
Data Cycles
Action
Command
(byte)
Mode
1st byte
Exiting the QPI to enter 4-byte to exit 4-byte
mode
mode and set mode and clear
4BYTE bit as 4BYTE bit to
"1"
be "0"
RDFBR
WRFBR
ESFBR
(read fast boot (write fast boot (erase fast
register)
register)
boot register)
SPI
SPI
SPI
16(hex)
17(hex)
18(hex)
2nd byte
3rd byte
4th byte
5th byte
Data Cycles
Action
P/N: PM2352
Downloaded from Arrow.com.
1-4
Macronix Proprietary
24
4
Rev. 1.4, July 27, 2020
MX66U1G45G
Table 8. ID/Security Commands
REMS
RDID
RES
(read electronic
QPIID
(read identific- (read electronic
manufacturer & (QPI ID Read)
ation)
ID)
device ID)
Mode
SPI
SPI/QPI
SPI
QPI
Address Bytes
0
0
0
0
1st byte
9F (hex)
AB (hex)
90 (hex)
AF (hex)
Command
(byte)
2nd byte
x
3rd byte
x
4th byte
x
RDSCUR
WRSCUR
(read security (write security
register)
register)
Mode
SPI/QPI
SPI/QPI
Address Bytes
0
0
1st byte
2B (hex)
2F (hex)
EXSO
(exit secured
OTP)
SPI/QPI
3
5A (hex)
SPI/QPI
0
B1 (hex)
SPI/QPI
0
C1 (hex)
x
ADD2
ADD1
ADD3
outputs JEDEC to read out
output the
ID: 1-byte
1-byte Device Manufacturer
Manufacturer
ID
ID & Device ID
ID & 2-byte
Device ID
Command
(byte)
ENSO
(enter secured
OTP)
ADD1
5th byte
Action
RDSFDP
ID in QPI
interface
Dummy(8)(Note 4)
Read SFDP
to enter the
mode
secured OTP
mode
to exit the
secured OTP
mode
GBLK
(gang block
lock)
SPI
0
GBULK
(gang block
unlock)
SPI
0
WRLR
(write Lock
register)
SPI
0
RDLR
(read Lock
register)
SPI
0
WRSPB
(SPB bit
program)
SPI
4
7E (hex)
98 (hex)
2C (hex)
2D (hex)
E3 (hex)
2nd byte
ADD1
3rd byte
ADD2
4th byte
ADD3
5th byte
ADD4
Data Cycles
Action
2
to read value to set the lockof security
down bit as
register
"1" (once lockdown, cannot
be updated)
whole chip
write protect
whole chip
unprotect
Mode
Address Bytes
ESSPB
(all SPB bit
erase)
SPI
0
RDSPB
(read SPB
status)
SPI
4
WRDPB
(write DPB
register)
SPI
4
RDDPB
(read DPB
register)
SPI
4
1st byte
E4 (hex)
E2 (hex)
E1 (hex)
E0 (hex)
Command
(byte)
2
RDPASS
WRPASS
(read password (write password
register)
register)
SPI
SPI
4
4
27 (hex)
28 (hex)
PASSULK
(password
unlock)
SPI
4
29 (hex)
2nd byte
ADD1
ADD1
ADD1
ADD1
ADD1
ADD1
3rd byte
ADD2
ADD2
ADD2
ADD2
ADD2
ADD2
4th byte
ADD3
ADD3
ADD3
ADD3
ADD3
ADD3
5th byte
ADD4
ADD4
ADD4
ADD4
ADD4
ADD4
8
8
Dummy(8)(Note 4)
6th byte
Data Cycles
1
1
1
8
Action
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
25
Rev. 1.4, July 27, 2020
MX66U1G45G
Table 9. Reset Commands
Mode
SPI/QPI
SPI/QPI
RST
(Reset
Memory)
SPI/QPI
1st byte
00 (hex)
66 (hex)
99 (hex)
Command
(byte)
NOP
RSTEN
(No Operation) (Reset Enable)
2nd byte
3rd byte
4th byte
5th byte
Action
Note 1: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first.
Note 2: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden mode.
Note 3: The RSTEN command must be executed before executing the RST command. If any other command is issued
in-between RSTEN and RST, the RST command will be ignored.
Note 4: The number in parentheses after “ADD” or “Data” or “Dummy” stands for how many clock cycles it has. For example,
"Data(8)" represents there are 8 clock cycles for the data in. Please note the number after "ADD" are based on 3-byte
address mode, for 4-byte address mode, which will be increased.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
26
Rev. 1.4, July 27, 2020
MX66U1G45G
9. REGISTER DESCRIPTION
9-1. Status Register
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write
status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status
register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status
register cycle.
WEL bit. The Write Enable Latch (WEL) bit is a volatile bit that is set to “1” by the WREN instruction. WEL needs to be
set to “1” before the device can accept program and erase instructions, otherwise the program and erase instructions
are ignored. WEL automatically clears to “0” when a program or erase operation completes. To ensure that both WIP
and WEL are “0” and the device is ready for the next program or erase operation, it is recommended that WIP be
confirmed to be “0” before checking that WEL is also “0”. If a program or erase instruction is applied to a protected
memory area, the instruction will be ignored and WEL will clear to “0”.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area
(as defined in Table 3) of the device to against the program/erase instruction without hardware protection mode being
set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to
be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE),
Block Erase 32KB (BE32K), Block Erase (BE) and Chip Erase (CE) instructions (only if Block Protect bits (BP3:BP0)
set to 0, the CE instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as default. Which is un-protected.
QE bit. The Quad Enable (QE) bit is a non-volatile bit with a factory default of “0”. When QE is “0”, Quad mode
commands are ignored; pins WP#/SIO2 and NC/SIO3 function as WP# and NC, respectively. When QE is “1”, Quad
mode is enabled and Quad mode commands are supported along with Single and Dual mode commands. Pins WP#/
SIO2 and NC/SIO3 function as SIO2 and SIO3, respectively, and their alternate pin functions are disabled. Enabling
Quad mode also disables the HPM feature.
SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection
(WP#/SIO2) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and
WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is
no longer accepted for execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are read only. The
SRWD bit defaults to be "0".
Status Register
bit7
SRWD (status
register write
protect)
bit6
QE
(Quad
Enable)
1=status
register write
1=Quad
disabled
Enable
0=status
0=not Quad
register write
Enable
enabled
Non-volatile Non-volatile
bit
bit
bit5
BP3
(level of
protected
block)
bit4
BP2
(level of
protected
block)
bit3
BP1
(level of
protected
block)
bit2
BP0
(level of
protected
block)
(note 1)
(note 1)
(note 1)
(note 1)
Non-volatile
bit
Non-volatile
bit
Non-volatile
bit
Non-volatile
bit
bit1
bit0
WEL
WIP
(write enable
(write in
latch)
progress bit)
1=write
1=write
enable
operation
0=not write 0=not in write
enable
operation
volatile bit
volatile bit
Note 1: see the "Table 3. Protected Area Sizes".
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
27
Rev. 1.4, July 27, 2020
MX66U1G45G
9-2. Configuration Register
The Configuration Register is able to change the default status of Flash memory. Flash memory will be configured
after the CR bit is set.
ODS bit
The output driver strength (ODS2, ODS1, ODS0) bits are volatile bits, which indicate the output driver level (as
defined in Output Driver Strength Table) of the device. To write the ODS bits requires the Write Status Register (WRSR)
instruction to be executed.
TB bit
The Top/Bottom (TB) bit is a non-volatile OTP bit. The Top/Bottom (TB) bit is used to configure the Block Protect
area by BP bit (BP3, BP2, BP1, BP0), starting from TOP or Bottom of the memory array. The TB bit is defaulted as
“0”, which means Top area protect. When it is set as “1”, the protect area will change to Bottom area of the memory
device. To write the TB bits requires the Write Status Register (WRSR) instruction to be executed.
PBE bit
The Preamble Bit Enable (PBE) bit is a volatile bit. It is used to enable or disable the preamble bit data pattern
output on dummy cycles. The PBE bit is defaulted as “0”, which means preamble bit is disabled. When it is set as “1”,
the preamble bit will be enabled, and inputted into dummy cycles. To write the PBE bits requires the Write Status
Register (WRSR) instruction to be executed.
4BYTE Indicator bit
By writing EN4B instruction, the 4BYTE bit may be set as "1" to access the address length of 32-bit for memory area
of higher density (large than 128Mb). The default state is "0" as the 24-bit address mode. The 4BYTE bit may be
cleared by power-off or writing EX4B instruction to reset the state to be "0".
Configuration Register
bit7
DC1
(Dummy
cycle 1)
bit6
DC0
(Dummy
cycle 0)
(note 2)
(note 2)
volatile bit
volatile bit
bit5
4 BYTE
0=3-byte
address
mode
1=4-byte
address
mode
(Default=0)
volatile bit
bit4
bit3
bit2
bit1
bit0
PBE
TB
ODS 2
ODS 1
ODS 0
(Preamble bit (top/bottom (output driver (output driver (output driver
Enable)
selected)
strength)
strength)
strength)
0=Disable
1=Enable
volatile bit
0=Top area
protect
1=Bottom
area protect
(Default=0)
(note 1)
(note 1)
(note 1)
OTP
volatile bit
volatile bit
volatile bit
Note 1: see "Output Driver Strength Table"
Note 2: see "Dummy Cycle and Frequency Table (MHz)"
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
28
Rev. 1.4, July 27, 2020
MX66U1G45G
Output Driver Strength Table
ODS2
ODS1
ODS0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
24-Ball BGA
Resistance (Ohm)
146 Ohms
76 Ohms
52 Ohms
41 Ohms
34 Ohms
30 Ohms
26 Ohms
24 Ohms (Default)
16-SOP
Resistance (Ohm)
163 Ohms
92 Ohms
70 Ohms
60 Ohms
54 Ohms
50 Ohms
48 Ohms
46 Ohms (Default)
Note
Impedance at
VCC/2
(Typical)
Dummy Cycle and Frequency Table (MHz)
DC[1:0]
00 (default)
01
10
11
DC[1:0]
00 (default)
01
10
11
DC[1:0]
00 (default)
01
10
11
P/N: PM2352
Downloaded from Arrow.com.
Numbers of
Dummy clock
cycles
8
6
8
10
Numbers of
Dummy clock
cycles
4
6
8
10
Numbers of
Dummy clock
cycles
6
4
8
10
Fast Read
Dual Output Fast
Read
Quad Output
Fast Read
133
133
133
166
133
133
133
166
133
104
133
166
Dual IO Fast
Read
84
104
133
166
Quad IO Fast
Read
Quad I/O DTR
Read
84
70
104
133
52
42
66
100
Macronix Proprietary
29
Rev. 1.4, July 27, 2020
MX66U1G45G
9-3. Security Register
The definition of the Security Register bits is as below:
Write Protection Selection bit. Please reference to "Write Protection Selection bit"
Erase Fail bit. The Erase Fail bit shows the status of last Erase operation. The bit will be set to "1" if the erase
operation failed or the erase region was protected. It will be automatically cleared to "0" if the next erase operation
succeeds. Please note that it will not interrupt or stop any operation in the flash memory.
Program Fail bit. The Program Fail bit shows the status of the last Program operation. The bit will be set to "1" if
the program operation failed or the program region was protected. It will be automatically cleared to "0" if the next
program operation succeeds. Please note that it will not interrupt or stop any operation in the flash memory.
Erase Suspend bit. Erase Suspend Bit (ESB) indicates the status of Erase Suspend operation. Users may use
ESB to identify the state of flash memory. After the flash memory is suspended by Erase Suspend command, ESB
is set to "1". ESB is cleared to "0" after erase operation resumes.
Program Suspend bit. Program Suspend Bit (PSB) indicates the status of Program Suspend operation. Users may
use PSB to identify the state of flash memory. After the flash memory is suspended by Program Suspend command,
PSB is set to "1". PSB is cleared to "0" after program operation resumes.
Secured OTP Indicator bit. The Secured OTP indicator bit shows the secured OTP area is locked by factory or
not. When it is "0", it indicates non-factory lock; "1" indicates factory-lock.
Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for
customer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the Secured OTP
area cannot be updated any more. While it is in secured OTP mode, main array access is not allowed.
Table 10. Security Register Definition
bit7
bit6
bit5
bit4
WPSEL
E_FAIL
P_FAIL
Reserved
0=normal
WP mode
1=individual
mode
(default=0)
0=normal
Erase
succeed
1=indicate
Erase failed
(default=0)
0=normal
Program
succeed
1=indicate
Program
failed
(default=0)
-
0=Erase
is not
suspended
1= Erase
suspended
(default=0)
Non-volatile
bit (OTP)
Volatile bit
Volatile bit
Volatile bit
Volatile bit
P/N: PM2352
Downloaded from Arrow.com.
bit3
bit2
ESB
PSB
(Erase
(Program
Suspend bit) Suspend bit)
Macronix Proprietary
30
bit1
bit0
LDSO
Secured OTP
(indicate if
indicator bit
lock-down)
0 = not lock0=Program
down
0 = nonis not
1 = lock-down
factory
suspended
(cannot
lock
1= Program
program/
1 = factory
suspended
erase
lock
(default=0)
OTP)
Non-volatile
Non-volatile
Volatile bit
bit
bit (OTP)
(OTP)
Rev. 1.4, July 27, 2020
MX66U1G45G
10. COMMAND DESCRIPTION
10-1. Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP/
PP4B, 4PP/4PP4B, SE/SE4B, BE32K/BE32K4B, BE/BE4B, CE, and WRSR, which are intended to change the
device content WEL bit should be set every time after the WREN instruction setting the WEL bit.
The sequence of issuing WREN instruction is: CS# goes low→sending WREN instruction code→ CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care in
SPI mode.
Figure 13. Write Enable (WREN) Sequence (SPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
SCLK
Mode 0
Command
SI
06h
High-Z
SO
Figure 14. Write Enable (WREN) Sequence (QPI Mode)
CS#
0
Mode 3
1
SCLK
Mode 0
Command
06h
SIO[3:0]
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
31
Rev. 1.4, July 27, 2020
MX66U1G45G
10-2. Write Disable (WRDI)
The Write Disable (WRDI) instruction is to reset Write Enable Latch (WEL) bit.
The sequence of issuing WRDI instruction is: CS# goes low→sending WRDI instruction code→CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care in
SPI mode.
The WEL bit is reset by following situations:
- Power-up
- Reset# pin driven low
- WRDI command completion
- WRSR command completion
- PP/PP4B command completion
- 4PP/4PP4B command completion
- SE/SE4B command completion
- BE32K/BE32K4B command completion
- BE/BE4B command completion
- CE command completion
- PGM/ERS Suspend command completion
- Softreset command completion
- WRSCUR command completion
- WPSEL command completion
- GBLK command completion
- GBULK command completion
- WREAR command completion
- WRLR command completion
- WRSPB command completion
- ESSPB command completion
- WRDPB command completion
- WRFBR command completion
- ESFBR command completion
Figure 15. Write Disable (WRDI) Sequence (SPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
SCLK
Mode 0
SI
SO
P/N: PM2352
Downloaded from Arrow.com.
Command
04h
High-Z
Macronix Proprietary
32
Rev. 1.4, July 27, 2020
MX66U1G45G
Figure 16. Write Disable (WRDI) Sequence (QPI Mode)
CS#
0
Mode 3
1
SCLK
Mode 0
Command
04h
SIO[3:0]
10-3. Read Identification (RDID)
The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Macronix
Manufacturer ID and Device ID are listed as "Table 11. ID Definitions".
The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code→24-bits ID data out
on SO→ to end RDID operation can drive CS# to high at any time during data out.
While Program/Erase operation is in progress, it will not decode the RDID instruction, therefore there's no effect on
the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby
stage.
Figure 17. Read Identification (RDID) Sequence (SPI mode only)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10
13 14 15 16 17 18
28 29 30 31
SCLK
Mode 0
Command
SI
9Fh
Manufacturer Identification
SO
High-Z
7
6
5
2
1
MSB
P/N: PM2352
Downloaded from Arrow.com.
Device Identification
0 15 14 13
3
2
1
0
MSB
Macronix Proprietary
33
Rev. 1.4, July 27, 2020
MX66U1G45G
10-4. Release from Deep Power-down (RDP), Read Electronic Signature (RES)
The Release from Deep Power-down (RDP) instruction is completed by driving Chip Select (CS#) High. When Chip
Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the
Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in
the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES1, and Chip
Select (CS#) must remain High for at least tRES1(max), as specified in "Table 23. AC CHARACTERISTICS".
Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute
instructions. The RDP instruction is only for releasing from Deep Power Down Mode. Reset# pin goes low will
release the Flash from deep power down mode.
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as Table 11 ID
Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new design,
please use RDID instruction.
Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device is in
progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly
if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in
Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in Deep
Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least
tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute
instruction.
Figure 18. Read Electronic Signature (RES) Sequence (SPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38
SCLK
Mode 0
Command
SI
ABh
tRES2
3 Dummy Bytes
23 22 21
3
2
1
0
MSB
SO
Electronic Signature Out
High-Z
7
6
5
4
3
2
1
0
MSB
Deep Power-down Mode
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
34
Stand-by Mode
Rev. 1.4, July 27, 2020
MX66U1G45G
Figure 19. Read Electronic Signature (RES) Sequence (QPI Mode)
CS#
MODE 3
0
1
2
3
4
5
6
7
SCLK
MODE 0
SIO[3:0]
tRES2
3 Dummy Bytes
Command
X
ABh
X
X
X
X
X
H0
L0
MSB LSB
Data In
Data Out
Stand-by Mode
Deep Power-down Mode
Figure 20. Release from Deep Power-down (RDP) Sequence (SPI Mode)
CS#
0
Mode 3
1
2
3
4
5
6
tRES1
7
SCLK
Mode 0
Command
SI
ABh
High-Z
SO
Deep Power-down Mode
Stand-by Mode
Figure 21. Release from Deep Power-down (RDP) Sequence (QPI Mode)
CS#
Mode 3
tRES1
0
1
SCLK
Mode 0
Command
SIO[3:0]
ABh
Deep Power-down Mode
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
35
Stand-by Mode
Rev. 1.4, July 27, 2020
MX66U1G45G
10-5. Read Electronic Manufacturer ID & Device ID (REMS)
The REMS instruction returns both the JEDEC assigned manufacturer ID and the device ID. The Device ID values
are listed in Table 11 of ID Definitions.
The REMS instruction is initiated by driving the CS# pin low and sending the instruction code "90h" followed by two
dummy bytes and one address byte (A7~A0). After which the manufacturer ID for Macronix (C2h) and the device
ID are shifted out on the falling edge of SCLK with the most significant bit (MSB) first. If the address byte is 00h,
the manufacturer ID will be output first, followed by the device ID. If the address byte is 01h, then the device ID will
be output first, followed by the manufacturer ID. While CS# is low, the manufacturer and device IDs can be read
continuously, alternating from one to the other. The instruction is completed by driving CS# high.
Figure 22. Read Electronic Manufacturer & Device ID (REMS) Sequence (SPI Mode only)
CS#
SCLK
Mode 3
0
1
2
Mode 0
3
4
5
6
7
8
Command
SI
9 10
2 Dummy Bytes
15 14 13
90h
3
2
1
0
High-Z
SO
CS#
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
ADD (1)
SI
7
6
5
4
3
2
1
0
Manufacturer ID
SO
7
6
5
4
3
2
1
Device ID
0
7
6
5
4
3
2
MSB
MSB
1
0
7
MSB
Notes:
(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
36
Rev. 1.4, July 27, 2020
MX66U1G45G
10-6. QPI ID Read (QPIID)
User can execute this QPIID Read instruction to identify the Device ID and Manufacturer ID. The sequence of issue
QPIID instruction is CS# goes low→sending QPI ID instruction→Data out on SO→CS# goes high. Most significant
bit (MSB) first.
After the command cycle, the device will immediately output data on the falling edge of SCLK. The manufacturer ID,
memory type, and device ID data byte will be output continuously, until the CS# goes high.
Table 11. ID Definitions
Command Type
RDID
9Fh
RES
ABh
REMS
90h
QPIID
AFh
P/N: PM2352
Downloaded from Arrow.com.
MX66U1G45G
Manufacturer ID
C2
Manufacturer ID
C2
Manufacturer ID
C2
Memory type
25
Electronic ID
3B
Device ID
3B
Memory type
25
Macronix Proprietary
37
Memory density
3B
Memory density
3B
Rev. 1.4, July 27, 2020
MX66U1G45G
10-7. Read Status Register (RDSR)
The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even
in program/erase/write status register condition). It is recommended to check the Write in Progress (WIP) bit before
sending a new instruction when a program, erase, or write status register operation is in progress.
The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register data
out on SO.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
Figure 23. Read Status Register (RDSR) Sequence (SPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
Mode 0
command
05h
SI
SO
Status Register Out
High-Z
7
6
5
4
3
2
1
Status Register Out
0
7
6
5
4
3
2
1
0
7
MSB
MSB
Figure 24. Read Status Register (RDSR) Sequence (QPI Mode)
CS#
Mode 3 0
1
2
3
4
5
6
7
N
SCLK
Mode 0
SIO[3:0]
05h H0 L0 H0 L0 H0 L0
H0 L0
MSB LSB
Status Byte Status Byte Status Byte
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
38
Status Byte
Rev. 1.4, July 27, 2020
MX66U1G45G
10-8. Read Configuration Register (RDCR)
The RDCR instruction is for reading Configuration Register Bits. The Read Configuration Register can be read at
any time (even in program/erase/write configuration register condition). It is recommended to check the Write in
Progress (WIP) bit before sending a new instruction when a program, erase, or write configuration register operation
is in progress.
The sequence of issuing RDCR instruction is: CS# goes low→ sending RDCR instruction code→ Configuration
Register data out on SO.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
Figure 25. Read Configuration Register (RDCR) Sequence (SPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
Mode 0
command
15h
SI
SO
Configuration register Out
High-Z
7
6
5
4
3
2
1
0
Configuration register Out
7
6
5
4
3
2
1
0
7
MSB
MSB
Figure 26. Read Configuration Register (RDCR) Sequence (QPI Mode)
CS#
Mode 3 0
1
2
3
4
5
6
7
N
SCLK
Mode 0
SIO[3:0]
15h H0 L0 H0 L0 H0 L0
H0 L0
MSB LSB
Config. Byte Config. Byte Config. Byte
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
39
Config. Byte
Rev. 1.4, July 27, 2020
MX66U1G45G
For user to check if Program/Erase operation is finished or not, RDSR instruction flow are shown as follows:
Figure 27. Program/Erase flow with read array data
start
WREN command
RDSR command*
WEL=1?
No
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
WIP=0?
No
Yes
RDSR command
Read WEL=0, BP[3:0], QE,
and SRWD data
Read array data
(same address of PGM/ERS)
No
Verify OK?
Yes
Program/erase successfully
Program/erase
another block?
No
Program/erase fail
Yes
* Issue RDSR to check BP[3:0].
* If WPSEL = 1, issue RDSPB and RDDPB to check the block status.
Program/erase completed
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
40
Rev. 1.4, July 27, 2020
MX66U1G45G
Figure 28. Program/Erase flow without read array data (read P_FAIL/E_FAIL flag)
start
WREN command
RDSR command*
WEL=1?
No
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
WIP=0?
No
Yes
RDSR command
Read WEL=0, BP[3:0], QE,
and SRWD data
RDSCUR command
Yes
P_FAIL/E_FAIL =1 ?
No
Program/erase fail
Program/erase successfully
Program/erase
another block?
No
Yes
* Issue RDSR to check BP[3:0].
* If WPSEL = 1, issue RDSPB and RDDPB to check the block status.
Program/erase completed
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
41
Rev. 1.4, July 27, 2020
MX66U1G45G
10-9. Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits and Configuration Register Bits. Before
sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write
Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1,
BP0) bits to define the protected area of memory (as shown in Table 3). The WRSR also can set or reset the Quad
enable (QE) bit and set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#/
SIO2) pin signal, but has no effect on bit1(WEL) and bit0 (WIP) of the status register. The WRSR instruction cannot
be executed once the Hardware Protected Mode (HPM) is entered.
The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register
data on SI→CS# goes high.
The CS# must go high exactly at the 8 bits or 16 bits data boundary; otherwise, the instruction will be rejected and
not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes
high. The Write in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress.
The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write
Enable Latch (WEL) bit is reset.
Figure 29. Write Status Register (WRSR) Sequence (SPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Mode 0
SI
SO
command
01h
Status
Register In
7
6
4
5
Configuration
Register In
2
3
0 15 14 13 12 11 10 9
1
8
MSB
High-Z
Note : The CS# must go high exactly at 8 bits or 16 bits data boundary to completed the write register command.
Figure 30. Write Status Register (WRSR) Sequence (QPI Mode)
CS#
Mode 3
0
1
2
3
4
5
Mode 3
SCLK
Mode 0
Mode 0
SR in
Command
SIO[3:0]
P/N: PM2352
Downloaded from Arrow.com.
01h
H0
L0
CR in
H1
Macronix Proprietary
42
L1
Rev. 1.4, July 27, 2020
MX66U1G45G
Software Protected Mode (SPM):
- When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can
change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1,
BP0 and T/B bit, is at software protected mode (SPM).
- When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values
of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0 and T/B bit, is at
software protected mode (SPM)
Note:
If SRWD bit=1 but WP#/SIO2 is low, it is impossible to write the Status Register even if the WEL bit has previously
been set. It is rejected to write the Status Register and not be executed.
Hardware Protected Mode (HPM):
- When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware
protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2,
BP1, BP0 and T/B bit and hardware protected mode by the WP#/SIO2 to against data modification.
Note:
To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is entered.
If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be entered; only
can use software protected mode via BP3, BP2, BP1, BP0 and T/B bit.
If the system enter QPI or set QE=1, the feature of HPM will be disabled.
Table 12. Protection Modes
Mode
Software protection
mode (SPM)
Hardware protection
mode (HPM)
Status register condition
WP# and SRWD bit status
Memory
Status register can be written
in (WEL bit is set to "1") and
the SRWD, BP0-BP3
bits can be changed
WP#=1 and SRWD bit=0, or
WP#=0 and SRWD bit=0, or
WP#=1 and SRWD=1
The protected area
cannot
be program or erase.
The SRWD, BP0-BP3 of
status register bits cannot be
changed
WP#=0, SRWD bit=1
The protected area
cannot
be program or erase.
Note:
1. As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in
Table 3.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
43
Rev. 1.4, July 27, 2020
MX66U1G45G
Figure 31. WRSR flow
start
WREN command
RDSR command
No
WEL=1?
Yes
WRSR command
Write status register data
RDSR command
No
WIP=0?
Yes
RDSR command
Read WEL=0, BP[3:0], QE,
and SRWD data
No
Verify OK?
Yes
WRSR successfully
P/N: PM2352
Downloaded from Arrow.com.
WRSR fail
Macronix Proprietary
44
Rev. 1.4, July 27, 2020
MX66U1G45G
Figure 32. WP# Setup Timing and Hold Timing during WRSR when SRWD=1
WP#
tSHWL
tWHSL
CS#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCLK
01h
SI
SO
High-Z
Note: WP# must be kept high until the embedded operation finish.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
45
Rev. 1.4, July 27, 2020
MX66U1G45G
10-10. Enter 4-byte mode (EN4B)
The EN4B instruction enables accessing the address length of 32-bit for the memory area of higher density (larger
than 128Mb). The device default is in 24-bit address mode; after sending out the EN4B instruction, the bit5 (4BYTE
bit) of Configuration Register will be automatically set to "1" to indicate the 4-byte address mode has been enabled.
Once the 4-byte address mode is enabled, the address length becomes 32-bit instead of the default 24-bit. There
are three methods to exit the 4-byte mode: writing exit 4-byte mode (EX4B) instruction, Reset or power-off.
All instructions are accepted normally, and just the address bit is changed from 24-bit to 32-bit.
The following command don't support 4bye address: RDSFDP, RES and REMS.
The sequence of issuing EN4B instruction is: CS# goes low → sending EN4B instruction to enter 4-byte mode(
automatically set 4BYTE bit as "1") → CS# goes high.
10-11. Exit 4-byte mode (EX4B)
The EX4B instruction is executed to exit the 4-byte address mode and return to the default 3-bytes address mode.
After sending out the EX4B instruction, the bit5 (4BYTE bit) of Configuration Register will be cleared to be "0" to
indicate the exit of the 4-byte address mode. Once exiting the 4-byte address mode, the address length will return to
24-bit.
The sequence of issuing EX4B instruction is: CS# goes low → sending EX4B instruction to exit 4-byte mode
(automatically clear the 4BYTE bit to be "0") → CS# goes high.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
46
Rev. 1.4, July 27, 2020
MX66U1G45G
10-12. Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on
the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address
is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can
be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been
reached.
The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the
4-byte address read mode or to define EAR bit. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B)
Mode section.
The sequence of issuing READ instruction is: CS# goes low→sending READ instruction code→ 3-byte or 4-byte
address on SI→ data out on SO→to end READ operation can use CS# to high at any time during data out.
Figure 33. Read Data Bytes (READ) Sequence (SPI Mode only)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Mode 0
SI
command
03h
24-Bit Address
(Note)
23 22 21
3
2
1
0
MSB
SO
Data Out 1
High-Z
7
6
5
4
3
2
Data Out 2
1
0
7
MSB
Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the
address cycles will be increased.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
47
Rev. 1.4, July 27, 2020
MX66U1G45G
10-13. Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and
data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at
any location. The address is automatically increased to the next higher address after each byte data is shifted out,
so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when
the highest address has been reached.
The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the
4-byte address read mode or to define EAR bit. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B)
Mode section.
Read on SPI Mode The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ
instruction code→ 3-byte or 4-byte address on SI→ 8 dummy cycles (default)→ data out on SO→ to end FAST_
READ operation can use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
Figure 34. Read at Higher Speed (FAST_READ) Sequence (SPI Mode)
CS#
SCLK
Mode 3
0
1
2
Mode 0
3
5
6
7
8
9 10
Command
SI
SO
4
28 29 30 31
24-Bit Address
(Note)
23 22 21
0Bh
3
2
1
0
High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Configurable
Dummy Cycle
SI
7
6
5
4
3
2
1
0
DATA OUT 2
DATA OUT 1
SO
7
6
5
4
3
2
1
0
7
MSB
MSB
6
5
4
3
2
1
0
7
MSB
Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the
address cycles will be increased.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
48
Rev. 1.4, July 27, 2020
MX66U1G45G
10-14. Dual Output Read Mode (DREAD)
The DREAD instruction enable double throughput of Serial NOR Flash in read mode. The address is latched on
rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a
maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the
next higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD
instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD
instruction, the following data out will perform as 2-bit instead of previous 1-bit.
The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the
4-byte address read mode or to define EAR bit. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B)
Mode section.
The sequence of issuing DREAD instruction is: CS# goes low→ sending DREAD instruction→3-byte or 4-byte
address on SIO0→ 8 dummy cycles (default) on SIO0→ data out interleave on SIO1 & SIO0→ to end DREAD
operation can use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
Figure 35. Dual Read Mode Sequence
CS#
0
1
2
3
4
5
6
7
8
…
Command
SI/SIO0
SO/SIO1
30 31 32
9
SCLK
3B
…
24 ADD Cycle
A23 A22
…
39 40 41 42 43 44 45
Configurable
Dummy Cycle
A1 A0
High Impedance
Data Out
1
Data Out
2
D6 D4 D2 D0 D6 D4
D7 D5 D3 D1 D7 D5
Notes:
1. Please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address
cycles will be increased.
2. Configuration Dummy cycle numbers will be different depending on the bit6 & bit7 (DC0 & DC1) setting in
configuration register.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
49
Rev. 1.4, July 27, 2020
MX66U1G45G
10-15. 2 x I/O Read Mode (2READ)
The 2READ instruction enable double throughput of Serial NOR Flash in read mode. The address is latched on
rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a
maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the
next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ
instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ
instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit.
The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the
4-byte address read mode or to define EAR bit. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B)
Mode section.
The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 3-byte or 4-byte
address interleave on SIO1 & SIO0→ 4 dummy cycles (default) on SIO1 & SIO0→ data out interleave on SIO1 &
SIO0→ to end 2READ operation can use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
Figure 36. 2 x I/O Read Mode Sequence (SPI Mode only)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10
17 18 19 20 21 22 23 24 25 26 27 28 29 30
Mode 3
SCLK
Mode 0
Command
SI/SIO0
SO/SIO1
BBh
12 ADD Cycles
(Note)
Configurable
Dummy Cycle
Data
Out 1
Data
Out 2
A22 A20 A18
A4 A2 A0
D6 D4 D2 D0 D6 D4 D2 D0
A23 A21 A19
A5 A3 A1
D7 D5 D3 D1 D7 D5 D3 D1
Mode 0
Notes:
1. Please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address
cycles will be increased.
2. Configuration Dummy cycle numbers will be different depending on the bit6 & bit7 (DC0 & DC1) setting in
configuration register.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
50
Rev. 1.4, July 27, 2020
MX66U1G45G
10-16. Quad Read Mode (QREAD)
The QREAD instruction enable quad throughput of Serial NOR Flash in read mode. The address is latched on
rising edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a
maximum frequency fQ. The first address byte can be at any location. The address is automatically increased to the
next higher address after each byte data is shifted out, so the whole memory can be read out at a single QREAD
instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing QREAD
instruction, the following data out will perform as 4-bit instead of previous 1-bit.
The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the
4-byte address read mode or to define EAR bit. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B)
Mode section.
The sequence of issuing QREAD instruction is: CS# goes low→ sending QREAD instruction → 3-byte or 4-byte
address on SI → 8 dummy cycle (Default) → data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end QREAD
operation can use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
Figure 37. Quad Read Mode Sequence
CS#
0
1
2
3
4
5
6
7
8
…
Command
SIO0
SIO1
SIO2
SIO3
29 30 31 32 33
9
SCLK
6B
…
24 ADD Cycles
A23 A22
…
38 39 40 41 42
A2 A1 A0
High Impedance
Configurable
dummy cycles
Data Data Data
Out 1 Out 2 Out 3
D4 D0 D4 D0 D4
D5 D1 D5 D1 D5
High Impedance
D6 D2 D6 D2 D6
High Impedance
D7 D3 D7 D3 D7
Notes:
1. Please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address
cycles will be increased.
2. Configuration Dummy cycle numbers will be different depending on the bit6 & bit7 (DC0 & DC1) setting in
configuration register.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
51
Rev. 1.4, July 27, 2020
MX66U1G45G
10-17. 4 x I/O Read Mode (4READ)
The 4READ instruction enable quad throughput of Serial NOR Flash in read mode. A Quad Enable (QE) bit of status
Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCLK,
and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency
fQ. The first address byte can be at any location. The address is automatically increased to the next higher address
after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address
counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following
address/dummy/data out will perform as 4-bit instead of previous 1-bit.
The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the
4-byte address read mode or to define EAR bit. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B)
Mode section.
4 x I/O Read on SPI Mode (4READ) The sequence of issuing 4READ instruction is: CS# goes low→ sending
4READ instruction→ 3-byte or 4-byte address interleave on SIO3, SIO2, SIO1 & SIO0→ 6 dummy cycles (Default)
→data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end 4READ operation can use CS# to high at any time
during data out.
4 x I/O Read on QPI Mode (4READ) The 4READ instruction also support on QPI command mode. The sequence
of issuing 4READ instruction QPI mode is: CS# goes low→ sending 4READ instruction→ 3-byte or 4-byte address
interleave on SIO3, SIO2, SIO1 & SIO0→ 6 dummy cycles (Default) →data out interleave on SIO3, SIO2, SIO1 &
SIO0→ to end 4READ operation can use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
52
Rev. 1.4, July 27, 2020
MX66U1G45G
Figure 38. 4 x I/O Read Mode Sequence (SPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
Mode 3
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SCLK
Mode 0
Command
6 ADD Cycles
Data
Out 1
Performance
enhance
indicator (Note 1)
Data
Out 2
Data
Out 3
Mode 0
Configurable
Dummy Cycle (Note 3)
EA/EBh
A20 A16 A12 A8 A4 A0 P4 P0
D4 D0 D4 D0 D4 D0
SIO1
A21 A17 A13 A9 A5 A1 P5 P1
D5 D1 D5 D1 D5 D1
SIO2
A22 A18 A14 A10 A6 A2 P6 P2
D6 D2 D6 D2 D6 D2
SIO3
A23 A19 A15 A11 A7 A3 P7 P3
D7 D3 D7 D3 D7 D3
SIO0
Notes:
1. Hi-impedance is inhibited for the two clock cycles.
2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited.
3. Configuration Dummy cycle numbers will be different depending on the bit6 & bit7 (DC0 & DC1) setting in
configuration register.
4. Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the
address cycles will be increased.
Figure 39. 4 x I/O Read Mode Sequence (QPI Mode)
CS#
MODE 3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
MODE 3
SCLK
MODE 0
SIO[3:0]
MODE 0
EBh
Data In
A20A23
A16A19
A12A15
A8A11
24-bit Address
(Note)
A4A7
A0A3
X
X
X
X
X
Configurable
Dummy Cycle
X
H0
L0
H1
L1
H2
L2
H3
L3
MSB
Data Out
Notes:
1. Please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address
cycles will be increased.
2. Configuration Dummy cycle numbers will be different depending on the bit6 & bit7 (DC0 & DC1) setting in
configuration register.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
53
Rev. 1.4, July 27, 2020
MX66U1G45G
10-18. 4 x I/O Double Transfer Rate Read Mode (4DTRD)
The 4DTRD instruction enables Double Transfer Rate throughput on quad I/O of Serial Flash in read mode. A Quad
Enable (QE) bit of status Register must be set to "1" before sending the 4DTRD instruction. The address (interleave
on 4 I/O pins) is latched on both rising and falling edge of SCLK, and data (interleave on 4 I/O pins) shift out on
both rising and falling edge of SCLK. The 8-bit address can be latched-in at one clock, and 8-bit data can be read
out at one clock, which means four bits at rising edge of clock, the other four bits at falling edge of clock. The first
address byte can be at any location. The address is automatically increased to the next higher address after each
byte data is shifted out, so the whole memory can be read out at a single 4DTRD instruction. The address counter
rolls over to 0 when the highest address has been reached. Once writing 4DTRD instruction, the following address/
dummy/data out will perform as 8-bit instead of previous 1-bit.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
While Program/Erase/Write Status Register cycle is in progress, 4DTRD instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
54
Rev. 1.4, July 27, 2020
MX66U1G45G
Figure 40. Fast Quad I/O DT Read (4DTRD) Sequence (SPI Mode)
CS#
Mode 3
0
7
SCLK
8
9
10
11
16
…
Mode 0
17
18
…
Command
Performance
Enhance Indicator
3 ADD Cycles
Configurable
Dummy Cycle
A20 A16
…
A4 A0
P4 P0
D4 D0 D4 D0 D4
SIO1
A21 A17
…
A5 A1
P5 P1
D5 D1 D5 D1 D5
SIO2
A22 A18
…
A6 A2
P6
P2
D6 D2 D6 D2 D6
SIO3
A23 A19
…
A7 A3
P7
P3
D7 D3 D7 D3 D7
SIO0
EDh
Notes:
1. Hi-impedance is inhibited for this clock cycle.
2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) will result in entering the performance enhance mode.
3. Configuration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in
configuration register.
4. Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address
cycles will be increased.
Figure 41. Fast Quad I/O DT Read (4DTRD) Sequence (QPI Mode)
CS#
Mode 3
0
1
2
3
4
5
11
10
SCLK
12
…
Mode 0
Command
3 ADD Cycles
Performance
Enhance Indicator
Configurable
Dummy Cycle
SIO[3:0]
EDh
A20
|
A23
A16
|
A19
A12
|
A15
A8
|
A11
A4
|
A7
A0
|
A3
P1
P0
H0
L0
H1
L1
H2
Notes:
1. Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address
cycles will be increased.
2. Configuration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in
configuration register.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
55
Rev. 1.4, July 27, 2020
MX66U1G45G
10-19. Preamble Bit
The Preamble Bit data pattern supports system/memory controller to determine valid window of data output more
easily and improve data capture reliability while the flash memory is running in high frequency.
Preamble Bit data pattern can be enabled or disabled by setting the bit4 of Configuration register (Preamble bit
Enable bit). Once the CR is set, the preamble bit is inputted into dummy cycles.
Enabling preamble bit will not affect the function of enhance mode bit. In Dummy cycles, performance enhance
mode bit still operates with the same function. Preamble bit will output after performance enhance mode bit.
The preamble bit is a fixed 8-bit data pattern (00110100). While dummy cycle number reaches 10, the complete
8 bits will start to output right after the performance enhance mode bit. While dummy cycle is not sufficient of 10
cycles, the rest of the preamble bits will be cut. For example, 8 dummy cycles will cause 6 preamble bits to output,
and 6 dummy cycles will cause 4 preamble bits to output.
Figure 42. SDR 1I/O (10DC)
CS#
SCLK
…
…
Dummy cycle
Command
cycle
SI
CMD
Address cycle
An
…
Preamble bits
A0
SO
7
6
5
4
3
2
1
0
D7
D6
D7
D6
…
Figure 43. SDR 1I/O (8DC)
CS#
SCLK
…
…
Dummy cycle
Command
cycle
SI
SO
P/N: PM2352
Downloaded from Arrow.com.
CMD
Address cycle
An
…
Preamble bits
A0
7
6
5
Macronix Proprietary
56
4
3
2
D5
D4
…
Rev. 1.4, July 27, 2020
MX66U1G45G
Figure 44. SDR 2I/O (10DC)
CS#
SCLK
…
…
Dummy cycle
Command
cycle
SIO0
CMD
SIO1
Address cycle
Toggle
bits
Preamble bits
A(n-1)
…
A0
7
6
5
4
3
2
1
0
D6
D4
D2
D0
An
…
A1
7
6
5
4
3
2
1
0
D7
D5
D3
D1
…
…
Figure 45. SDR 2I/O (8DC)
CS#
SCLK
…
…
Dummy cycle
Command
cycle
SIO0
SIO1
P/N: PM2352
Downloaded from Arrow.com.
CMD
Address cycle
Toggle
bits
Preamble bits
A(n-1)
…
A0
7
6
5
4
3
2
D6
D4
D2
D0
An
…
A1
7
6
5
4
3
2
D7
D5
D3
D1
Macronix Proprietary
57
…
…
Rev. 1.4, July 27, 2020
MX66U1G45G
Figure 46. SDR 4I/O (10DC)
CS#
SCLK
…
…
Dummy cycle
Command
cycle
Toggle
bits
Address cycle
Preamble bits
A(n-3)
…
A0
7
6
5
4
3
2
1
0
D4
D0
SIO1
A(n-2)
…
A1
7
6
5
4
3
2
1
0
D5
D1
SIO2
A(n-1)
…
A2
7
6
5
4
3
2
1
0
D6
D2
…
SIO3
An
…
A3
7
6
5
4
3
2
1
0
D7
D3
…
SIO0
CMD
…
…
Figure 47. SDR 4I/O (8DC)
CS#
SCLK
…
…
Dummy cycle
Command
cycle
Address cycle
Toggle
bits
Preamble bits
A(n-3)
…
A0
7
6
5
4
3
2
D4
D0
SIO1
A(n-2)
…
A1
7
6
5
4
3
2
D5
D1
SIO2
A(n-1)
…
A2
7
6
5
4
3
2
D6
D2
SIO3
An
…
A3
7
6
5
4
3
2
D7
D3
SIO0
P/N: PM2352
Downloaded from Arrow.com.
CMD
Macronix Proprietary
58
…
…
…
…
Rev. 1.4, July 27, 2020
MX66U1G45G
Figure 48. DTR4IO (6DC)
CS#
SCLK
…
…
Dummy cycle
Command
cycle
SIO0
Address cycle
CMD
Toggle
Bits
Preamble bits
…
A0
7 6 5 4 3 2 1 0 D4 D0 D4 D0 D4 D0 D4 D0
…
…
A1
7 6 5 4 3 2 1 0 D5 D1 D5 D1 D5 D1 D5 D1
…
…
A2
7 6 5 4 3 2 1 0 D6 D2 D6 D2 D6 D2 D6 D2
…
…
A3
7 6 5 4 3 2 1 0 D7 D3 D7 D3 D7 D3 D7 D3
…
A(n-3)
SIO1
A(n-2)
SIO2
A(n-1)
SIO3
An
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
59
Rev. 1.4, July 27, 2020
MX66U1G45G
10-20. 4 Byte Address Command Set
The operation of 4-byte address command set was very similar to original 3-byte address command set. The
only different is all the 4-byte command set request 4-byte address (A31-A0) followed by instruction code. The
command set support 4-byte address including: READ4B, Fast_Read4B, DREAD4B, 2READ4B, QREAD4B,
4READ4B, 4DTRD4B, PP4B, 4PP4B, SE4B, BE32K4B, BE4B. Please note that it is not necessary to issue EN4B
command before issuing any of 4-byte command set.
Figure 49. Read Data Bytes using 4 Byte Address Sequence (READ4B)
CS#
0
1
2
3
4
5
6
7
8
36 37 38 39 40 41 42 43 44 45 46 47
9 10
SCLK
Command
32-bit address
31 30 29
13h
SI
3
2
1
0
MSB
Data Out 1
High Impedance
SO
7
6
5
4
Data Out 2
2
3
1
0
7
MSB
Figure 50. Read Data Bytes at Higher Speed using 4 Byte Address Sequence (FASTREAD4B)
CS#
0
1
2
3
4
5
6
7
8
9 10
36 37 38 39
SCLK
Command
32-bit address
31 30 29
0Ch
SI
3
2
1
0
High Impedance
SO
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
Configurable
Dummy cycles
SI
7
6
5
4
3
2
1
0
DATA OUT 2
DATA OUT 1
SO
7
6
5
4
3
2
1
MSB
0
7
6
MSB
5
4
3
2
1
0
7
MSB
Note:
1. Configuration Dummy cycle numbers will be different depending on the bit6 & bit7 (DC0 & DC1) setting in
configuration register.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
60
Rev. 1.4, July 27, 2020
MX66U1G45G
Figure 51. 2 x I/O Fast Read using 4 Byte Address Sequence (2READ4B)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10
21 22 23 24 25 26 27 28 29 30 31 32 33 34
Mode 3
SCLK
Mode 0
BCh
SI/SIO0
SO/SIO1
Data
Out 1
Configurable
Dummy Cycle
16 ADD Cycles
Command
Mode 0
Data
Out 2
A30 A28 A26
A4 A2 A0
D6 D4 D2 D0 D6 D4 D2 D0
A31 A29 A27
A5 A3 A1
D7 D5 D3 D1 D7 D5 D3 D1
Note:
1. Configuration Dummy cycle numbers will be different depending on the bit6 & bit7 (DC0 & DC1) setting in
configuration register.
Figure 52. 4 I/O Fast Read using 4 Byte Address sequence (4READ4B)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
Mode 3
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
SCLK
Mode 0
Command
8 ADD Cycles
Performance
enhance
indicator
Data
Out 1
Data
Out 2
Data
Out 3
Mode 0
Configurable
Dummy Cycle
SIO0
ECh
A28 A24 A20 A16 A12 A8 A4 A0 P4 P0
D4 D0 D4 D0 D4 D0
SIO1
A29 A25 A21 A17 A13 A9 A5 A1 P5 P1
D5 D1 D5 D1 D5 D1
SIO2
A30 A26 A22 A18 A14 A10 A6 A2 P6 P2
D6 D2 D6 D2 D6 D2
SIO3
A31 A27 A23 A19 A15 A11 A7 A3 P7 P3
D7 D3 D7 D3 D7 D3
Note:
1. Configuration Dummy cycle numbers will be different depending on the bit6 & bit7 (DC0 & DC1) setting in
configuration register.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
61
Rev. 1.4, July 27, 2020
MX66U1G45G
Figure 53. Fast Quad I/O DT Read (4DTRD4B) Sequence (SPI Mode)
CS#
Mode 3
0
7
SCLK
8
9
10
11
12
17
…
Mode 0
18
19
…
Command
Performance
Enhance Indicator
4 ADD Cycles
Configurable
Dummy Cycle
A28 A24
…
A4
A0
P4
P0
D4 D0 D4 D0 D4
SIO1
A29 A25
…
A5
A1
P5
P1
D5 D1 D5 D1 D5
SIO2
A30 A26
…
A6
A2
P6
P2
D6 D2 D6 D2 D6
SIO3
A31 A27
…
A7
A3
P7
P3
D7 D3 D7 D3 D7
SIO0
EEh
Note:
1. Configuration Dummy cycle numbers will be different depending on the bit6 & bit7 (DC0 & DC1) setting in
configuration register.
Figure 54. Fast Quad I/O DT Read (4DTRD4B) Sequence (QPI Mode)
CS#
Mode 3
0
1
2
4
3
5
6
12
11
SCLK
13
…
Mode 0
Command
4 ADD Cycles
Performance
Enhance Indicator
Configurable
Dummy Cycle
SIO[3:0]
EEh
A28
|
A31
A24
|
A27
A20
|
A23
A16
|
A19
A12
|
A15
A8
|
A11
A4
|
A7
A0
|
A3
P1
P0
H0
L0
H1
L1
H2
Note:
1. Configuration Dummy cycle numbers will be different depending on the bit6 & bit7 (DC0 & DC1) setting in
configuration register.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
62
Rev. 1.4, July 27, 2020
MX66U1G45G
Figure 55. Sector Erase (SE4B) Sequence (SPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
37 38 39
9
SCLK
Mode 0
32-Bit Address
Command
SI
31 30
21h
2
1
0
MSB
Figure 56. Block Erase 32KB (BE32K4B) Sequence (SPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9
37 38 39
SCLK
Mode 0
Command
SI
32-Bit Address
2
31 30
5Ch
1
0
MSB
Figure 57. Block Erase (BE4B) Sequence (SPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9
37 38 39
SCLK
Mode 0
SI
Command
32-Bit Address
31 30
DCh
2
1
0
MSB
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
63
Rev. 1.4, July 27, 2020
MX66U1G45G
Figure 58. Page Program (PP4B) Sequence (SPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10
36 37 38 39 40 41 42 43 44 45 46 47
SCLK
1
0
7
6
5
3
2
1
0
2087
2
2086
3
2085
31 30 29
12h
SI
Data Byte 1
32-Bit Address
2084
Command
2083
Mode 0
4
1
0
MSB
MSB
2082
2081
48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
2080
CS#
SCLK
Data Byte 2
7
SI
6
5
4
3
Data Byte 3
2
1
0
7
MSB
6
5
4
3
2
Data Byte 256
1
0
MSB
7
6
5
4
3
2
MSB
Figure 59. 4 x I/O Page Program (4PP4B) Sequence (SPI Mode only)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Mode 0
Downloaded from Arrow.com.
Data Data Data Data
Byte 2 Byte 3 Byte 4 Byte 4
8 Address cycle
A0
4
0
4
0
4
0
4
0
SIO1
A29 A25 A21 A17 A13 A9 A5 A1
5
1
5
1
5
1
5
1
SIO2
A30 A26 A22 A18 A14 A10 A6 A2
6
2
6
2
6
2
6
2
SIO3
A31 A27 A23 A19 A15 A11 A7 A3
7
3
7
3
7
3
7
3
SIO0
P/N: PM2352
Command
3Eh
A28 A24 A20 A16 A12 A8 A4
Macronix Proprietary
64
Rev. 1.4, July 27, 2020
MX66U1G45G
10-21. Performance Enhance Mode - XIP (execute-in-place)
The device could waive the command cycle bits if the two cycle bits after address cycle toggles.
Performance enhance mode is supported in both SPI and QPI mode.
In QPI mode, “EBh” "ECh" "EDh" "EEh" and SPI “EBh” "ECh" "EDh" "EEh" commands support enhance mode. The
performance enhance mode is not supported in dual I/O mode.
To enter performance-enhancing mode, P[7:4] must be toggling with P[3:0]; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh
can make this mode continue and skip the next 4READ instruction. To leave enhance mode, P[7:4] is no longer
toggling with P[3:0]; likewise P[7:0]=FFh, 00h, AAh or 55h along with CS# is afterwards raised and then lowered.
Issuing ”FFh” data cycle can also exit enhance mode. The system then will leave performance enhance mode and
return to normal operation.
After entering enhance mode, following CS# go high, the device will stay in the read mode and treat CS# go low of
the first clock as address instead of command cycle.
Another sequence of issuing 4READ instruction especially useful in random access is : CS# goes low→sending
4 READ instruction→3-bytes or 4-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 →performance enhance
toggling bit P[7:0]→ 4 dummy cycles (Default) →data out still CS# goes high → CS# goes low (reduce 4 Read
instruction) → 3-bytes or 4-bytes random access address.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
65
Rev. 1.4, July 27, 2020
MX66U1G45G
Figure 60. 4 x I/O Read Performance Enhance Mode Sequence (SPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22
n
SCLK
Mode 0
Data
Out 2
Data
Out n
A20 A16 A12 A8 A4 A0 P4 P0
D4 D0 D4 D0
D4 D0
SIO1
A21 A17 A13 A9 A5 A1 P5 P1
D5 D1 D5 D1
D5 D1
SIO2
A22 A18 A14 A10 A6 A2 P6 P2
D6 D2 D6 D2
D6 D2
SIO3
A23 A19 A15 A11 A7 A3 P7 P3
D7 D3 D7 D3
D7 D3
Command
6 ADD Cycles
(Note 3)
Data
Out 1
Performance
enhance
indicator (Note 1)
Configurable
Dummy Cycle (Note 2)
EBh
SIO0
CS#
n+1
...........
n+7 ...... n+9
........... n+13
...........
Mode 3
SCLK
6 ADD Cycles
(Note 3)
Data
Out 1
Performance
enhance
indicator (Note 1)
Data
Out 2
Data
Out n
Mode 0
Configurable
Dummy Cycle (Note 2)
SIO0
A20 A16 A12 A8 A4 A0 P4 P0
D4 D0 D4 D0
D4 D0
SIO1
A21 A17 A13 A9 A5 A1 P5 P1
D5 D1 D5 D1
D5 D1
SIO2
A22 A18 A14 A10 A6 A2 P6 P2
D6 D2 D6 D2
D6 D2
SIO3
A23 A19 A15 A11 A7 A3 P7 P3
D7 D3 D7 D3
D7 D3
Notes:
1. If not using performance enhance recommend to keep 1 or 0 in performance enhance indicator.
Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF.
2. Configuration Dummy cycle numbers will be different depending on the bit6 & bit7 (DC0 & DC1) setting in
configuration register.
3. Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the
address cycles will be increased.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
66
Rev. 1.4, July 27, 2020
MX66U1G45G
Figure 61. 4 x I/O Read Performance Enhance Mode Sequence (QPI Mode)
CS#
Mode 3
0
1
2
3
4
A20A23
A16A19
A12A15
5
6
7
A4A7
A0A3
8
9
10
11
12
13
14
15
16
17
H0
L0
H1
L1
SCLK
Mode 0
SIO[3:0]
EBh
A8A11
X
X
X
X
MSB LSB MSB LSB
P(7:4) P(3:0)
Data In
Data Out
performance
enhance
indicator (Note 3)
Configurable
Dummy Cycle (Note 1)
CS#
n+1
.............
SCLK
Mode 0
SIO[3:0]
A20A23
A16A19
A12A15
A8A11
A4A7
A0A3
X
X
X
6 Address cycles
(Note 2)
X
H0
L0
H1
L1
MSB LSB MSB LSB
P(7:4) P(3:0)
performance
enhance
indicator (Note 3)
Data Out
Configurable
Dummy Cycle (Note 1)
Notes:
1. Configuration Dummy cycle numbers will be different depending on the bit6 & bit7 (DC0 & DC1) setting in
configuration register.
2. Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the
address cycles will be increased.
3. Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
67
Rev. 1.4, July 27, 2020
MX66U1G45G
Figure 62. 4 x I/O DT Read Performance Enhance Mode Sequence (SPI Mode)
CS#
Mode 3
SCLK
Mode 0
0
7
8
9
10
11
16
…
17
18
…
Command
n
…
Performance
Enhance Indicator
3 ADD Cycles
Configurable
Dummy Cycle
A20 A16
…
A4 A0
P4 P0
D4 D0 D4 D0
…
D4 D0
SIO1
A21 A17
…
A5 A1
P5 P1
D5 D1 D5 D1
…
D5 D1
SIO2
A22 A18
…
A6 A2
P6 P2
D6 D2 D6 D2
…
D6 D2
SIO3
A23 A19
…
A7 A3
P7
P3
D7 D3 D7 D3
…
D7 D3
SIO0
EDh
CS#
n+1
……
n+4
Mode 3
SCLK
…
3 ADD Cycles
Mode 0
Performance
Enhance Indicator
Configurable
Dummy Cycle
SIO0
A20 A16
…
A4 A0
P4 P0
D4 D0 D4 D0
SIO1
A21 A17
…
A5 A1
P5 P1
D5 D1 D5 D1
SIO2
A22 A18
…
A6 A2
P6 P2
D6 D2 D6 D2
SIO3
A23 A19
…
A7 A3
P7
P3
D7 D3 D7 D3
Notes:
1. Configuration Dummy cycle numbers will be different depending on the bit6 & bit7 (DC0 & DC1) setting in
configuration register.
2. Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address
cycles will be increased.
3. Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
68
Rev. 1.4, July 27, 2020
MX66U1G45G
Figure 63. 4 x I/O DT Read Performance Enhance Mode Sequence (QPI Mode)
CS#
Mode 3
0
1
2
3
4
5
10
SCLK
11
12
…
Mode 0
Command
3 ADD Cycles
n
…
Performance
Enhance Indicator
Configurable
Dummy Cycle
SIO[3:0]
A20
|
A23
EDh
A16
|
A19
A12
|
A15
A8
|
A11
A0
|
A3
A4
|
A7
P1
P0
H0 L0
H1 L1
…
Hn Ln
CS#
…
n+1
…
n+4
SCLK
Mode 3
…
3 ADD Cycles
Mode 0
Performance
Enhance Indicator
Configurable
Dummy Cycle
SIO[3:0]
A20
|
A23
A16
|
A19
A12
|
A15
A8
|
A11
A4
|
A7
A0
|
A3
P1
P0
H0 L0
H1 L1
Notes:
1. Configuration Dummy cycle numbers will be different depending on the bit6 & bit7 (DC0 & DC1) setting in
configuration register.
2. Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address
cycles will be increased.
3. Reset the performance enhance mode, if P1=P0, ex: AA, 00, FF.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
69
Rev. 1.4, July 27, 2020
MX66U1G45G
10-22. Burst Read
To set the Burst length, following command operation is required to issue command: “C0h” in the first Byte (8-clocks),
following 4 clocks defining wrap around enable with “0h” and disable with“1h”.
The next 4 clocks are to define wrap around depth. Their definitions are as the following table:
Data
00h
01h
02h
03h
1xh
Wrap Around
Yes
Yes
Yes
Yes
No
Wrap Depth
8-byte
16-byte
32-byte
64-byte
X
The wrap around unit is defined with the 8/16/32/64Byte with random initial address. It is defined as “wrap-around
mode disable” for the default state of the device. To exit wrap around, it is required to issue another “C0h” command
in which data=‘1xh”. Otherwise, wrap around status will be retained until power down or reset command. To change
wrap around depth, it is requried to issue another “C0h” command in which data=“0xh”. QPI “EBh” "ECh" and SPI “EBh”
"ECh" support wrap around feature after wrap around is enabled. Both SPI (8 clocks) and QPI (2 clocks) command
cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode.
Figure 64. SPI Mode
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9
D7
D6
10
11
12
13
14
15
SCLK
Mode 0
SI
C0h
D5
D4
D3
D2
D1
D0
Figure 65. QPI Mode
CS#
Mode 3
0
1
2
3
SCLK
Mode 0
SIO[3:0]
C0h
H0
MSB
L0
LSB
Note: MSB=Most Significant Bit
LSB=Least Significant Bit
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
70
Rev. 1.4, July 27, 2020
MX66U1G45G
10-23. Fast Boot
The Fast Boot Feature provides the ability to automatically execute read operation after power on cycle or reset
without any read instruction.
A Fast Boot Register is provided on this device. It can enable the Fast Boot function and also define the number of
delay cycles and start address (where boot code being transferred). Instruction WRFBR (write fast boot register) and
ESFBR (erase fast boot register) can be used for the status configuration or alternation of the Fast Boot Register
bit. RDFBR (read fast boot register) can be used to verify the program state of the Fast Boot Register. The default
number of delay cycles is 13 cycles, and there is a 16bytes boundary address for the start of boot code access.
When CS# starts to go low, data begins to output from default address after the delay cycles (default as 13 cycles).
After CS# returns to go high, the device will go back to standard SPI mode and user can start to input command. In
the fast boot data out process from CS# goes low to CS# goes high, a minimum of one byte must be output.
Once Fast Boot feature has been enabled, the device will automatically start a read operation after power on cycle,
reset command, or hardware reset operation.
The fast Boot feature can support Single I/O and Quad I/O interface. If the QE bit of Status Register is “0”, the data
is output by Single I/O interface. If the QE bit of Status Register is set to “1”, the data is output by Quad I/O interface.
Fast Boot Register (FBR)
Bits
31 to 4
Description
FBSA (FastBoot Start
Address)
3
x
2 to 1
FBSD (FastBoot Start
Delay Cycle)
0
FBE (FastBoot Enable)
Bit Status
Default State
16 bytes boundary address for the start of boot
FFFFFFF
code access.
1
00: 7 delay cycles
01: 9 delay cycles
10: 11 delay cycles
11: 13 delay cycles
0=FastBoot is enabled.
1=FastBoot is not enabled.
Type
NonVolatile
NonVolatile
11
NonVolatile
1
NonVolatile
Note: If FBSD = 11, the maximum clock frequency is 133 MHz
If FBSD = 10, the maximum clock frequency is 104 MHz
If FBSD = 01, the maximum clock frequency is 84 MHz
If FBSD = 00, the maximum clock frequency is 70 MHz
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
71
Rev. 1.4, July 27, 2020
MX66U1G45G
Figure 66. Fast Boot Sequence (QE=0)
CS#
Mode 3
0
-
-
-
-
-
-
n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11n+12n+13n+14n+15
n
SCLK
Mode 0
Delay Cycles
Don’t care or High Impedance
SI
Data Out 1
High Impedance
SO
7
6
5
4
3
Data Out 2
2
1
0
MSB
7
6
5
4
3
2
MSB
1
0
7
MSB
Note: If FBSD = 11, delay cycles is 13 and n is 12.
If FBSD = 10, delay cycles is 11 and n is 10.
If FBSD = 01, delay cycles is 9 and n is 8.
If FBSD = 00, delay cycles is 7 and n is 6.
Figure 67. Fast Boot Sequence (QE=1)
CS#
Mode 3
0
-
-
-
-
-
-
-
n
n+1 n+2 n+3 n+5 n+6 n+7 n+8 n+9
SCLK
Mode 0
SIO0
SIO1
SIO2
SIO3
Delay Cycles
Data Data
Out 1 Out 2
High Impedance
High Impedance
High Impedance
High Impedance
Data
Out 3
Data
Out 4
4
0
4
0
4
0
4
0
4
5
1
5
1
5
1
5
1
5
6
2
6
2
6
2
6
2
6
7
3
7
3
7
3
7
3
7
MSB
Note: If FBSD = 11, delay cycles is 13 and n is 12.
If FBSD = 10, delay cycles is 11 and n is 10.
If FBSD = 01, delay cycles is 9 and n is 8.
If FBSD = 00, delay cycles is 7 and n is 6.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
72
Rev. 1.4, July 27, 2020
MX66U1G45G
Figure 68. Read Fast Boot Register (RDFBR) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10
37 38 39 40 41
SCLK
Mode 0
Command
SI
16h
Data Out 1
High-Z
SO
7
6
Data Out 2
5
26 25 24 7
6
MSB
MSB
Figure 69. Write Fast Boot Register (WRFBR) Sequence
CS#
0
Mode 3
1
2
3
4
5
6
7
8
9 10
37 38 39
SCLK
Mode 0
Command
SI
Fast Boot Register
17h
7
6
5
26 25 24
MSB
High-Z
SO
Figure 70. Erase Fast Boot Register (ESFBR) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
SCLK
Mode 0
SI
SO
P/N: PM2352
Downloaded from Arrow.com.
Command
18h
High-Z
Macronix Proprietary
73
Rev. 1.4, July 27, 2020
MX66U1G45G
10-24. Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used
for any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit
before sending the Sector Erase (SE). Any address of the sector (Please refer to "5. MEMORY ORGANIZATION")
is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the least
significant bit of the address byte been latched-in); otherwise, the instruction will be rejected and not executed.
The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the
4-byte address read mode or to define EAR bit. Address bits [Am-A12] (Am is the most significant address) select
the sector address.
To enter the 4-byte address mode, please refer to the enter 4-byte mode (EN4B) Mode section.
The sequence of issuing SE instruction is: CS# goes low→ sending SE instruction code→ 3-byte or 4-byte address
on SI→ CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets 1 during the tSE
timing, and clears when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the
Block is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector Protect
Mode), the Sector Erase (SE) instruction will not be executed on the block.
Figure 71. Sector Erase (SE) Sequence (SPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Mode 0
24-Bit Address
(Note)
Command
SI
20h
A23 A22
A2 A1 A0
MSB
Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the
address cycles will be increased.
Figure 72. Sector Erase (SE) Sequence (QPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
A4A7
A0A3
SCLK
Mode 0
24-Bit Address
(Note)
Command
SIO[3:0]
20h
A20- A16- A12- A8A23 A19 A15 A11
MSB
Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the
address cycles will be increased.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
74
Rev. 1.4, July 27, 2020
MX66U1G45G
10-25. Block Erase (BE32K)
The Block Erase (BE32K) instruction is for erasing the data of the chosen block to be "1". The instruction is used
for 32K-byte block erase operation. A Write Enable (WREN) instruction be executed to set the Write Enable
Latch (WEL) bit before sending the Block Erase (BE32K). Any address of the block (Please refer to "5. MEMORY
ORGANIZATION") is a valid address for Block Erase (BE32K) instruction. The CS# must go high exactly at the byte
boundary (the least significant bit of address byte been latched-in); otherwise, the instruction will be rejected and not
executed.
Address bits [Am-A15] (Am is the most significant address) select the 32KB block address. The default read mode
is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode
or to define EAR bit. To enter the 4-byte address mode, please refer to the enter 4-byte mode (EN4B) Mode section.
The sequence of issuing BE32K instruction is: CS# goes low→ sending BE32K instruction code→ 3-byte or 4-byte
address on SI→CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
The self-timed Block Erase Cycle time (tBE32K) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while during the Block Erase cycle is in progress. The WIP sets during the
tBE32K timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared.
If the Block is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector
Protect Mode), the Block Erase (BE32K) instruction will not be executed on the block.
Figure 73. Block Erase 32KB (BE32K) Sequence (SPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Mode 0
Command
SI
24-Bit Address
(Note)
52h
A23 A22
A2 A1 A0
MSB
Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the
address cycles will be increased.
Figure 74. Block Erase 32KB (BE32K) Sequence (QPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
A4A7
A0A3
SCLK
Mode 0
24-Bit Address
(Note)
Command
SIO[3:0]
52h
A20- A16- A12A23 A19 A15
A8A11
MSB
Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the
address cycles will be increased.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
75
Rev. 1.4, July 27, 2020
MX66U1G45G
10-26. Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used
for 64K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable
Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (Please refer to "5. MEMORY
ORGANIZATION") is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte
boundary (the least significant bit of address byte been latched-in); otherwise, the instruction will be rejected and not
executed.
The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the
4-byte address read mode or to define EAR bit. To enter the 4-byte address mode, please refer to the enter 4-byte
mode (EN4B) Mode section.
The sequence of issuing BE instruction is: CS# goes low→ sending BE instruction code→ 3-byte or 4-byte address
on SI→ CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets during the tBE
timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the Block
is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector Protect Mode),
the Block Erase (BE) instruction will not be executed on the block.
Figure 75. Block Erase (BE) Sequence (SPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Mode 0
Command
SI
24-Bit Address
(Note)
D8h
A23 A22
A2 A1 A0
MSB
Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the
address cycles will be increased.
Figure 76. Block Erase (BE) Sequence (QPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
A4A7
A0A3
SCLK
Mode 0
24-Bit Address
(Note)
Command
SIO[3:0]
D8h
A20- A16- A12- A8A23 A19 A15 A11
MSB
Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the
address cycles will be increased.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
76
Rev. 1.4, July 27, 2020
MX66U1G45G
10-27. Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN)
instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS#
must go high exactly at the byte boundary, otherwise the instruction will be rejected and not executed.
The sequence of issuing CE instruction is: CS# goes low→sending CE instruction code→CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Chip Erase cycle is in progress. The WIP sets during the tCE
timing, and clears when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared.
When the chip is under "Block protect (BP) Mode" (WPSEL=0). The Chip Erase (CE) instruction will not be
executed, if one (or more) sector is protected by BP3-BP0 bits. It will be only executed when BP3-BP0 all set to "0".
When the chip is under "Advances Sector Protect Mode" (WPSEL=1). The Chip Erase (CE) instruction will be
executed on unprotected block. The protected Block will be skipped. If one (or more) 4K byte sector was protected
in top or bottom 64K byte block, the protected block will also skip the chip erase command.
Figure 77. Chip Erase (CE) Sequence (SPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
SCLK
Mode 0
Command
SI
60h or C7h
Figure 78. Chip Erase (CE) Sequence (QPI Mode)
CS#
Mode 3
0
1
SCLK
Mode 0
SIO[3:0]
P/N: PM2352
Downloaded from Arrow.com.
Command
60h or C7h
Macronix Proprietary
77
Rev. 1.4, July 27, 2020
MX66U1G45G
10-28. Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction
must be executed to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device
programs only the last 256 data bytes sent to the device. If the entire 256 data bytes are going to be programmed,
A7-A0 (The eight least significant address bits) should be set to 0. The last address byte (the 8 least significant
address bits, A7-A0) should be set to 0 for 256 bytes page program. If A7-A0 are not all zero, transmitted data that
exceed page length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently
selected page. If the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the request
page and previous data will be disregarded. If the data bytes sent to the device has not exceeded 256, the data
will be programmed at the request address of the page. There will be no effort on the other data bytes of the same
page.
The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the
4-byte address read mode or to define EAR bit. To enter the 4-byte address mode, please refer to the enter 4-byte
mode (EN4B) Mode section.
The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte or 4-byte address
on SI→ at least 1-byte on data on SI→ CS# goes high.
The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte
boundary( the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be
executed.
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Page Program cycle is in progress. The WIP sets during the tPP
timing, and clears when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the
page is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector Protect
Mode), the Page Program (PP) instruction will not be executed.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
78
Rev. 1.4, July 27, 2020
MX66U1G45G
Figure 79. Page Program (PP) Sequence (SPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
1
0
7
6
5
3
2
1
0
2079
2
2078
3
2077
23 22 21
02h
SI
Data Byte 1
24-Bit Address
(Note)
2076
Command
2075
Mode 0
4
1
0
MSB
MSB
2074
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
2073
2072
CS#
SCLK
Data Byte 2
7
SI
6
5
4
3
2
Data Byte 3
1
MSB
0
7
6
5
4
3
2
Data Byte 256
1
7
0
MSB
6
5
4
3
2
MSB
Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the
address cycles will be increased.
Figure 80. Page Program (PP) Sequence (QPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9
H0
L0
SCLK
Mode 0
Command
SIO[3:0]
02h
Data In
24-Bit Address
(Note)
A20A23
A16A19
A12A15
A8A11
A4A7
A0A3
H1
L1
H2
L2
H3
L3
Data Byte Data Byte Data Byte Data Byte
1
2
3
4
H255 L255
......
Data Byte
256
Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the
address cycles will be increased.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
79
Rev. 1.4, July 27, 2020
MX66U1G45G
10-29. 4 x I/O Page Program (4PP)
The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN)
instruction must be executed to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to
"1" before sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1,
SIO2, and SIO3 as address and data input, which can improve programmer performance and the effectiveness of
application. The other function descriptions are as same as standard page program.
The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the
4-byte address read mode or to define EAR bit. To enter the 4-byte address mode, please refer to the enter 4-byte
mode (EN4B) Mode section.
The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte or 4-byte
address on SIO[3:0]→ at least 1-byte on data on SIO[3:0]→CS# goes high.
If the page is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector
Protect Mode), the Quad Page Program (4PP) instruction will not be executed.
Figure 81. 4 x I/O Page Program (4PP) Sequence (SPI Mode only)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21
SCLK
Mode 0
Command
Data Data Data Data
Byte 1 Byte 2 Byte 3 Byte 4
6 Address cycle
A0
4
0
4
0
4
0
4
0
SIO1
A21 A17 A13 A9 A5 A1
5
1
5
1
5
1
5
1
SIO2
A22 A18 A14 A10 A6 A2
6
2
6
2
6
2
6
2
SIO3
A23 A19 A15 A11 A7 A3
7
3
7
3
7
3
7
3
SIO0
38h
A20 A16 A12 A8 A4
Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the
address cycles will be increased.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
80
Rev. 1.4, July 27, 2020
MX66U1G45G
10-30. Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device to minimum power consumption (the standby
current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction
to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction are
ignored. When CS# goes high, it's only in deep power-down mode not standby mode. It's different from Standby
mode.
The sequence of issuing DP instruction is: CS# goes low→sending DP instruction code→CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP)
and Read Electronic Signature (RES) instruction and softreset command. (those instructions allow the ID being
reading out). When Power-down, or software reset command the deep power-down mode automatically stops, and
when power-up, the device automatically is in standby mode. For DP instruction the CS# must go high exactly at the
byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed.
As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode.
Figure 82. Deep Power-down (DP) Sequence (SPI Mode)
CS#
0
Mode 3
1
2
3
4
5
6
tDP
7
SCLK
Mode 0
Command
B9h
SI
Stand-by Mode
Deep Power-down Mode
Figure 83. Deep Power-down (DP) Sequence (QPI Mode)
CS#
Mode 3
0
tDP
1
SCLK
Mode 0
Command
SIO[3:0]
B9h
Stand-by Mode
P/N: PM2352
Downloaded from Arrow.com.
Deep Power-down Mode
Macronix Proprietary
81
Rev. 1.4, July 27, 2020
MX66U1G45G
10-31. Enter Secured OTP (ENSO)
The ENSO instruction is for entering the additional 8K-bit secured OTP mode. While device is in secured OTPmode,
main array access is not available. The additional 8K-bit secured OTP is independent from main array and may be
used to store unique serial number for system identifier. After entering the Secured OTP mode, follow standard read
or program procedure to read out the data or update data. The Secured OTP data cannot be updated again once it
is lock-down.
The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP
mode→ CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
Please note that after issuing ENSO command user can only access secure OTP region with standard read or
program procedure. Furthermore, once security OTP is lock down, only read related commands are valid.
10-32. Exit Secured OTP (EXSO)
The EXSO instruction is for exiting the secured OTP mode.
The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP
mode→ CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
10-33. Read Security Register (RDSCUR)
The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read
at any time (even in program/erase/write status register/write security register condition) and continuously.
The sequence of issuing RDSCUR instruction is : CS# goes low→sending RDSCUR instruction→Security Register
data out on SO→ CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
10-34. Write Security Register (WRSCUR)
The WRSCUR instruction is for changing the values of Security Register Bits. The WREN (Write Enable) instruction
is required before issuing WRSCUR instruction. The WRSCUR instruction may change the values of bit1 (LDSO bit)
for customer to lock-down the Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area cannot be
updated any more.
The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
82
Rev. 1.4, July 27, 2020
MX66U1G45G
10-35. Write Protection Selection (WPSEL)
There are two write protection methods provided on this device, (1) Block Protection (BP) mode or (2) Advanced
Sector Protection mode. The protection modes are mutually exclusive. The WPSEL bit selects which protection
mode is enabled. If WPSEL=0 (factory default), BP mode is enabled and Advanced Sector Protection mode is
disabled. If WPSEL=1, Advanced Sector Protection mode is enabled and BP mode is disabled. The WPSEL
command is used to set WPSEL=1. A WREN command must be executed to set the WEL bit before sending the
WPSEL command. Please note that the WPSEL bit is an OTP bit. Once WPSEL is set to “1”, it cannot be
programmed back to “0”.
When WPSEL = 0: Block Protection (BP) mode,
The memory array is write protected by the BP3~BP0 bits.
When WPSEL =1: Advanced Sector Protection mode,
Blocks are individually protected by their own SPB or DPB. On power-up, all blocks are write protected by the
Dynamic Protection Bits (DPB) by default. The Advanced Sector Protection instructions WRLR, RDLR, WRPASS,
RDPASS, PASSULK, WRSPB, ESSPB, WRDPB, RDDPB, GBLK, and GBULK are activated. The BP3~BP0 bits
of the Status Register are disabled and have no effect. Hardware protection is performed by driving WP#=0. Once
WP#=0 all blocks and sectors are write protected regardless of the state of each SPB or DPB.
The sequence of issuing WPSEL instruction is: CS# goes low → send WPSEL instruction to enable the Advanced
Sector Protect mode → CS# goes high.
Write Protection Selection
Start
(Default in BP Mode)
WPSEL=1
Set
WPSEL Bit
Advanced
Sector Protection
Set
Lock Register
WPSEL=0
Block Protection
(BP)
Bit 2 =1
Bit 2 =0
Password
Protection
P/N: PM2352
Downloaded from Arrow.com.
Solid
Protection
Macronix Proprietary
83
Dynamic
Protection
Rev. 1.4, July 27, 2020
MX66U1G45G
Figure 84. WPSEL Flow
start
WREN command
RDSCUR command
Yes
WPSEL=1?
No
WPSEL disable,
block protected by BP[3:0]
WPSEL command
RDSR command
WIP=0?
No
Yes
RDSCUR command
WPSEL=1?
No
Yes
WPSEL set successfully
WPSEL set fail
WPSEL enable.
Block protected by Advance Sector Protection
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
84
Rev. 1.4, July 27, 2020
MX66U1G45G
10-36. Advanced Sector Protection
There are two ways to implement software Advanced Sector Protection on this device. Through these two protection
methods, user can disable or enable the programming or erasing operation to any individual sector or all sectors.
There is a non-volatile (SPB) and volatile (DPB) protection bit related to the single sector in main flash array. Each
of the sectors is protected from programming or erasing operation when the bit is set.
The figure below helps describing an overview of these methods. The device is default to the Solid mode when
shipped from factory. The detail algorithm of advanced sector protection is shown as follows:
Figure 85. Advanced Sector Protection Overview
Start
Bit 2=1
Bit 2=0
Set
Lock Register ?
Solid Protection Mode
Password Protection Mode
Set 64 bit Password
Set
SPB Lock Down Bit ?
(SPBLKDN)
Bit 6 = 0
SPB Locked
All SPB can not be changeable
Bit 6 = 1
SPB Unlocked
SPB is changeable
Solid Protection Bits
(SPB)
Dynamic Protect Bit Register
(DPB)
DPB=1 sector protect
Sector Array
SPB=1 Write Protect
SPB=0 Write Unprotect
DPB=0 sector unprotect
P/N: PM2352
Downloaded from Arrow.com.
DPB 0
SA 0
SPB 0
DPB 1
SA 1
SPB 1
DPB 2
SA 2
SPB 2
:
:
:
:
:
:
DPB N-1
SA N-1
SPB N-1
DPB N
SA N
SPB N
Macronix Proprietary
85
Rev. 1.4, July 27, 2020
MX66U1G45G
10-36-1. Lock Register
The Lock Register is a 16-bit register. Lock Register Bit[6] is SPB Lock Down Bit (SPBLKDN) which is assigned to
control all SPB bit status. Lock Register Bit[2] is Password Protection Mode Lock Bit. Both bits are defaulted as 1
when shipping from factory.
When SPBLKDN is 1, SPB can be changed. When it is locked as 0, all SPB can not be changed.
Users can choose their favorite sector protecting method via setting Lock Register Bit[2] using WRLR command.
The device default status was in Solid Protection Mode (Bit[2]=1), Once Bit[2] has been programmed (cleared to
"0"), the device will enable the Password Protection Mode and lock in that mode permanently.
In Solid Protection Mode (Bit[2]=1, factory default), the SPBLKDN can be programmed using the WRLR command
and permanently lock down the SPB bits. After programming SPBLKDN to 0, all SPB can not be changed anymore,
and neither Lock Register Bit[2] nor Bit[6] can be altered anymore.
In Password Protection Mode (Bit[2]=0), the SPBLKDN becomes a volatile bit with default 0 (SPB bit protected).
A correct password is required with PASSULK command to set SPBLKDN to 1. To clear SPBLKDN back to 0, a
Hardware/Software Reset or power-up cycle is required.
If user selects Password Protection mode, the password setting is required. User can set password by issuing
WRPASS command before Lock Register Bit[2] set to 0.
Lock Register
Bits
Description
Bit Status
15 to 7
Reserved
SPB Lock Down bit
6
(SPBLKDN)
5 to 3
Reserved
2
Default
Reserved
0: SPB bit Protected
1: SPB bit Unprotected
Reserved
Reserved
Solid Protection Mode: 1
Bit 2=1: OTP
Password Protection Mode: 0 Bit 2=0: Volatile
Reserved
Password Protection 0=Password Protection Mode Enable
Mode Lock Bit
1= Solid Protection Mode
1 to 0
Reserved
Type
1
OTP
Reserved
Reserved
Figure 86. Read Lock Register (RDLR) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
Mode 0
command
2Dh
SI
SO
High-Z
Register Out
7
6
5
4
3
2
Register Out
1
Downloaded from Arrow.com.
8
7
MSB
MSB
P/N: PM2352
0 15 14 13 12 11 10 9
Macronix Proprietary
86
Rev. 1.4, July 27, 2020
MX66U1G45G
Figure 87. Write Lock Register (WRLR) Sequence (SPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Mode 0
SI
Command
2Ch
SO
High-Z
Lock Register In
7
6
5
4
3
2
1
0 15 14 13 12 11 10 9
8
MSB
10-36-2. Solid Protection Bits
The Solid Protection Bits (SPBs) are nonvolatile bits for enabling or disabling write-protection to sectors and blocks.
The SPB bits have the same endurance as the Flash memory. An SPB is assigned to each 4KB sector in the bottom
and top 64KB of memory and to each 64KB block in the remaining memory. The factory default state of the SPB bits
is “0”, which has the sector/block write-protection disabled.
When an SPB is set to “1”, the associated sector or block is write-protected. Program and erase operations on the
sector or block will be inhibited. SPBs can be individually set to “1” by the WRSPB command. However, the SPBs
cannot be individually cleared to “0”. Issuing the ESSPB command clears all SPBs to “0”. A WREN command must
be executed to set the WEL bit before sending the WRSPB or ESSPB command.
The SPBLKDN bit must be “1” before any SPB can be modified. In Solid Protection mode the SPBLKDN bit defaults to “1”
after power-on or reset. Under Password Protection mode, the SPBLKDN bit defaults to “0” after power-on or reset,
and a PASSULK command with a correct password is required to set the SPBLKDN bit to “1”.
The RDSPB command reads the status of the SPB of a sector or block. The RDSPB command returns 00h if the
SPB is “0”, indicating write-protection is disabled. The RDSPB command returns FFh if the SPB is “1”, indicating
write-protection is enabled.
Note: If SPBLKDN=0, commands to set or clear the SPB bits will be ignored.
SPB Register
Bit
Description
7 to 0
SPB (Solid protected Bit)
P/N: PM2352
Downloaded from Arrow.com.
Bit Status
00h= SPB for the sector address unprotected
FFh= SPB for the sector address protected
Macronix Proprietary
87
Default
Type
00h
Non-volatile
Rev. 1.4, July 27, 2020
MX66U1G45G
Figure 88. Read SPB Status (RDSPB) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
37 38 39 40 41 42 43 44 45 46 47
9
SCLK
Mode 0
Command
SI
32-Bit Address
E2h
A31 A30
A2 A1 A0
MSB
Data Out
High-Z
SO
7
6
5
4
3
2
1
0
MSB
Figure 89. SPB Erase (ESSPB) Sequence
CS#
1
0
Mode 3
2
3
4
5
6
7
SCLK
Mode 0
Command
SI
E4h
High-Z
SO
Figure 90. SPB Program (WRSPB) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
37 38 39
9
SCLK
Mode 0
SI
Command
32-Bit Address
E3h
A31 A30
A2 A1 A0
MSB
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
88
Rev. 1.4, July 27, 2020
MX66U1G45G
10-36-3. Dynamic Write Protection Bits
The Dynamic Protection features a volatile type protection to each individual sector. It can protect sectors from
unintentional change, and is easy to disable when there are necessary changes.
All DPBs are default as protected (FFh) after reset or upon power up cycle. Via setting up Dynamic Protection bit (DPB)
by write DPB command (WRDPB), user can cancel the Dynamic Protection of associated sector.
The Dynamic Protection only works on those unprotected sectors whose SPBs are cleared. After the DPB state is
cleared to “0”, the sector can be modified if the SPB state is unprotected state.
DPB Register
Bit
Description
7 to 0
DPB (Dynamic protected Bit)
Bit Status
Default
00h= DPB for the sector address unprotected
FFh
FFh= DPB for the sector address protected
Type
Volatile
Figure 91. Read DPB Register (RDDPB) Sequence
CS#
0
Mode 3
1
2
3
4
5
6
7
8
37 38 39 40 41 42 43 44 45 46 47
9
SCLK
Mode 0
Command
SI
32-Bit Address
E0h
A31 A30
A2 A1 A0
MSB
Data Out
High-Z
SO
7
6
5
4
3
2
1
0
MSB
Figure 92. Write DPB Register (WRDPB) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
37 38 39 40 41 42 43 44 45 46 47
9
SCLK
Mode 0
SI
Command
E1h
A31 A30
A2 A1 A0
MSB
P/N: PM2352
Downloaded from Arrow.com.
Data Byte 1
32-Bit Address
7
6
5
4
3
2
1
0
MSB
Macronix Proprietary
89
Rev. 1.4, July 27, 2020
MX66U1G45G
10-36-4. Password Protection Mode
Password Protection mode potentially provides a higher level of security than Solid Protection mode. In Password
Protection mode, the SPBLKDN bit defaults to “0” after a power-on cycle or reset. When SPBLKDN=0, the SPBs
are locked and cannot be modified. A 64-bit password must be provided to unlock the SPBs.
The PASSULK command with the correct password will set the SPBLKDN bit to “1” and unlock the SPB bits. After
the correct password is given, a wait of 2us is necessary for the SPB bits to unlock. The Status Register WIP bit will
clear to “0” upon completion of the PASSULK command. Once unlocked, the SPB bits can be modified. A WREN
command must be executed to set the WEL bit before sending the PASSULK command.
Several steps are required to place the device in Password Protection mode. Prior to entering the Password
Protection mode, it is necessary to set the 64-bit password and verify it. The WRPASS command writes the
password and the RDPASS command reads back the password. Password verification is permitted until the
Password Protection Mode Lock Bit has been written to “0”. Password Protection mode is activated by programming
the Password Protection Mode Lock Bit to “0”. This operation is not reversible. Once the bit is programmed, it
cannot be erased. The device remains permanently in Password Protection mode and the 64-bit password can
neither be retrieved nor reprogrammed.
The password is all “1’s” when shipped from the factory. The WRPASS command can only program password bits to “0”.
The WRPASS command cannot program “0’s” back to “1’s”. All 64-bit password combinations are valid password
options. A WREN command must be executed to set the WEL bit before sending the WRPASS command.
● The unlock operation will fail if the password provided by the PASSULK command does not match the stored
password. This will set the P_FAIL bit to “1” and insert a delay before clearing the WIP bit to “0”. User has to
wait 150us before issuing another PASSULK command. This restriction makes it impractical to attempt all
combinations of a 64-bit password (such an effort would take millions of years). Monitor the WIP bit to determine
whether the device has completed the PASSULK command.
● When a valid password is provided, the PASSULK command does not insert the delay before returning the WIP
bit to zero. The SPBLKDN bit will set to “1” and the P_FAIL bit will be “0”.
● It is not possible to set the SPBLKDN bit to “1” if the password had not been set prior to the Password Protection
mode being selected.
Password Register (PASS)
Bits
Field
Function Type
Name
63 to 0 PWD
P/N: PM2352
Downloaded from Arrow.com.
Description
Default State
Non-volatile OTP storage of 64 bit password. The
Hidden
password is no longer readable after the Password
OTP FFFFFFFFFFFFFFFFh
Password
Protection mode is selected by programming Lock
Register bit 2 to zero.
Macronix Proprietary
90
Rev. 1.4, July 27, 2020
MX66U1G45G
Figure 93. Read Password Register (RDPASS) Sequence
CS#
Mode 3
0
1
2
3
4 5
6
7
8
39 40
47 48
109 110
SCLK
Mode 0
Command
SI
32-bit Address
27h
0
0
0
8 Dummy
0
Data Out
High-Z
SO
7
6
58 57 56
High-Z
MSB
Figure 94. Write Password Register (WRPASS) Sequence
CS#
Mode 3
0
1
2
3
4 5
6
7
39 40
8
102 103
SCLK
Mode 0
32-bit Address
Command
SI
28h
0
0
0
Password
0
7
6
58 57 56
MSB
SO
High-Z
Figure 95. Password Unlock (PASSULK) Sequence
CS#
Mode 3
0
1
2
3
4 5
6
7
39 40
8
102 103
SCLK
Mode 0
32-bit Address
Command
SI
29h
0
0
0
Password
0
7
6
58 57 56
MSB
SO
P/N: PM2352
Downloaded from Arrow.com.
High-Z
Macronix Proprietary
91
Rev. 1.4, July 27, 2020
MX66U1G45G
10-36-5. Gang Block Lock/Unlock (GBLK/GBULK)
These instructions are only effective after WPSEL was executed. The GBLK/GBULK instruction is a chip-based
protected or unprotected operation. It can enable or disable all DPB.
The WREN (Write Enable) instruction is required before issuing GBLK/GBULK instruction.
The sequence of issuing GBLK/GBULK instruction is: CS# goes low → send GBLK/GBULK (7Eh/98h) instruction
→CS# goes high.
The CS# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed.
10-36-6. Sector Protection States Summary Table
Protection Status
DPB bit
SPB bit
0
0
0
1
1
0
1
1
P/N: PM2352
Downloaded from Arrow.com.
Sector State
Unprotect
Protect
Protect
Protect
Macronix Proprietary
92
Rev. 1.4, July 27, 2020
MX66U1G45G
10-37. Program Suspend and Erase Suspend
The Suspend instruction interrupts a Program or Erase operation to allow the device conduct other operations.
After the device has entered the suspended state, the memory array can be read except for the page being
programmed or the sector being erased.
Security Register bit 2 (PSB) and bit 3 (ESB) can be read to check the suspend status. The PSB (Program Suspend
Bit) sets to “1” when a program operation is suspended. The ESB (Erase Suspend Bit) sets to “1” when an erase
operation is suspended. The PSB or ESB clears to “0” when the program or erase operation is resumed.
When the Serial NOR Flash receives the Suspend instruction, Program Suspend Latency(tPSL) or Erase Suspend
latency(tESL) is required to complete suspend operation. (Refer to"Table 23. AC CHARACTERISTICS") After the
device has entered the suspended state, the WEL bit is clears to “0” and the PSB or ESB in security register is set to “1”,
then the device is ready to acceptanother command.
However, some commands can be executed without tPSL or tESL latency during the program/erase suspend, and
can be issued at any time during the Suspend.
Please refer to "Table 13. Acceptable Commands During Suspend".
Figure 96. Suspend to Read Latency
tPSL / tESL
CS#
P/N: PM2352
Downloaded from Arrow.com.
Suspend Command
Macronix Proprietary
93
Read Command
Rev. 1.4, July 27, 2020
MX66U1G45G
Table 13. Acceptable Commands During Suspend
Command Name
Command Code
Suspend Type
Program Suspend
Erase Suspend
03h
0Bh
BBh
3Bh
EBh
6Bh
ECh
EDh
EEh
0Ch
BCh
3Ch
5Ah
9Fh
AFh
C0h
B1h
C1h
06h
30h
2Dh
E2h
16h
E0h
35h
F5h
90h
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
04h
05h
15h
2Bh
ABh
66h
99h
00h
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Commands which require tPSL/tESL delay
READ
FAST READ
2READ
DREAD
4READ
QREAD
4READ4B
4DTRD
4DTRD4B
FASTREAD4B
2READ4B
DREAD4B
RDSFDP
RDID
QPIID
SBL
ENSO
EXSO
WREN
RESUME
RDLR
RDSPB
RDFBR
RDDPB
EQIO
RSTQIO
REMS
Commands not required tPSL/tESL delay
WRDI
RDSR
RDCR
RDSCUR
RES
RSTEN
RST
NOP
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
94
Rev. 1.4, July 27, 2020
MX66U1G45G
10-38. Program Resume and Erase Resume
The Resume instruction resumes a suspended Program or Erase operation. After the device receives the Resume
instruction, the WEL and WIP bits are set to “1” and the PSB or ESB is cleared to “0”.The program or erase
operation will continue until it is completed or until another Suspend instruction is received.
To issue another Suspend instruction, the minimum resume-to-suspend latency (tPRS or tERS) is required.
However, in order to finish the program or erase progress, a period equal to or longer than the typical timing is
required.
To issue other command except suspend instruction, a latency of the self-timed Page Program Cycle time (tPP) or
Sector Erase (tSE) is required. The WEL and WIP bits are cleared to “0” after the Program or Erase operation is
completed.
Note:
The Resume instruction will be ignored during Performance Enhance Mode. Make sure the Serial NOR Flash has
exited the Performance Enhance Mode before issuing the Resume instruction.
Figure 97. Resume to Read Latency
CS#
Resume Command
tSE / tBE / tPP
Read Command
Figure 98. Resume to Suspend Latency
CS#
P/N: PM2352
Downloaded from Arrow.com.
Resume
Command
tPRS / tERS
Macronix Proprietary
95
Suspend
Command
Rev. 1.4, July 27, 2020
MX66U1G45G
10-39. No Operation (NOP)
The “No Operation” command is only able to terminate the Reset Enable (RSTEN) command and will not affect any
other command.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
during SPI mode.
10-40. Software Reset (Reset-Enable (RSTEN) and Reset (RST))
The Software Reset operation combines two instructions: Reset-Enable (RSTEN) command and Reset (RST)
command. It returns the device to standby mode. All the volatile bits and settings will be cleared then, which makes
the device return to the default status as power on.
To execute Reset command (RST), the Reset-Enable (RSTEN) command must be executed first to perform the
Reset operation. If there is any other command to interrupt after the Reset-Enable command, the Reset-Enable will
be invalid.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
If the Reset command is executed during program or erase operation, the operation will be disabled, the data under
processing could be damaged or lost.
The reset time is different depending on the last operation. For details, please refer to "Table 19. Reset Timing(Other Operation)" for tREADY2.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
96
Rev. 1.4, July 27, 2020
MX66U1G45G
Figure 99. Software Reset Recovery
Stand-by Mode
66
CS#
99
tREADY2
Mode
Note: Refer to "Table 19. Reset Timing-(Other Operation)" for tREADY2.
Figure 100. Reset Sequence (SPI mode)
tSHSL
CS#
SCLK
Mode 3
Mode 3
Mode 0
Mode 0
Command
Command
99h
66h
SIO0
Figure 101. Reset Sequence (QPI mode)
tSHSL
CS#
MODE 3
MODE 3
MODE 3
SCLK
MODE 0
SIO[3:0]
P/N: PM2352
Downloaded from Arrow.com.
Command
MODE 0
66h
Command
MODE 0
99h
Macronix Proprietary
97
Rev. 1.4, July 27, 2020
MX66U1G45G
11. Serial Flash Discoverable Parameter (SFDP)
11-1. Read SFDP Mode (RDSFDP)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional
and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables
can be interrogated by host system software to enable adjustments needed to accommodate divergent features
from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on
CFI.
The sequence of issuing RDSFDP instruction is CS# goes low→send RDSFDP instruction (5Ah)→send 3 address
bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP operation can use CS#
to high at any time during data out.
SFDP is a JEDEC Standard, JESD216B.
Figure 102. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
SO
24 BIT ADDRESS
23 22 21
5Ah
3
2
1
0
High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Cycle
SI
7
6
5
4
3
2
1
0
DATA OUT 2
DATA OUT 1
SO
7
6
5
4
3
2
P/N: PM2352
Downloaded from Arrow.com.
1
0
7
MSB
MSB
Macronix Proprietary
98
6
5
4
3
2
1
0
7
MSB
Rev. 1.4, July 27, 2020
MX66U1G45G
Table 14. Signature and Parameter Identification Data Values
SFDP Table (JESD216B) below is for MX66U1G45GXDI0A, MX66U1G45GMI00 and MX66U1G45GXDI00
Description
SFDP Signature
Comment
Fixed: 50444653h
Add (h) DW Add Data (h/b) Data
(Byte)
(Bit)
(Note1)
(h)
00h
07:00
53h
53h
01h
15:08
46h
46h
02h
23:16
44h
44h
03h
31:24
50h
50h
SFDP Minor Revision Number
Start from 00h
04h
07:00
06h
06h
SFDP Major Revision Number
Start from 01h
This number is 0-based. Therefore,
0 indicates 1 parameter header.
05h
15:08
01h
01h
06h
23:16
02h
02h
07h
31:24
FFh
FFh
00h: it indicates a JEDEC specified
header.
08h
07:00
00h
00h
Start from 00h
09h
15:08
06h
06h
Start from 01h
0Ah
23:16
01h
01h
How many DWORDs in the
Parameter table
0Bh
31:24
10h
10h
0Ch
07:00
30h
30h
0Dh
15:08
00h
00h
0Eh
23:16
00h
00h
0Fh
31:24
FFh
FFh
Number of Parameter Headers
Unused
ID number (JEDEC)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length
(in double word)
Parameter Table Pointer (PTP)
First address of JEDEC Flash
Parameter table
Unused
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
99
Rev. 1.4, July 27, 2020
MX66U1G45G
SFDP Table below is for MX66U1G45GXDI0A, MX66U1G45GMI00 and MX66U1G45GXDI00
Description
ID number
(Macronix manufacturer ID)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length
(in double word)
Parameter Table Pointer (PTP)
Comment
it indicates Macronix manufacturer
ID
10h
07:00
C2h
C2h
Start from 00h
11h
15:08
00h
00h
Start from 01h
12h
23:16
01h
01h
How many DWORDs in the
Parameter table
13h
31:24
04h
04h
14h
07:00
10h
10h
15h
15:08
01h
01h
16h
23:16
00h
00h
17h
31:24
FFh
FFh
4-byte Address Instruction
parameter ID
18h
07:00
84h
84h
Start from 00h
19h
15:08
00h
00h
Start from 01h
1Ah
23:16
01h
01h
How many DWORDs in the
Parameter table
1Bh
31:24
02h
02h
1Ch
07:00
C0h
C0h
1Dh
15:08
00h
00h
1Eh
23:16
00h
00h
1Fh
31:24
FFh
FFh
First address of Macronix Flash
Parameter table
Unused
ID number
(4-byte Address Instruction)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length
(in double word)
Parameter Table Pointer (PTP)
First address of 4-byte Address
Instruction table
Unused
P/N: PM2352
Downloaded from Arrow.com.
Add (h) DW Add Data (h/b) Data
(Byte)
(Bit)
(Note1)
(h)
Macronix Proprietary
100
Rev. 1.4, July 27, 2020
MX66U1G45G
Table 15. Parameter Table (0): JEDEC Flash Parameter Tables
SFDP Table below is for MX66U1G45GXDI0A, MX66U1G45GMI00 and MX66U1G45GXDI00
Description
Comment
Block/Sector Erase sizes
00: Reserved, 01: 4KB erase,
10: Reserved,
11: not supported 4KB erase
Write Granularity
0: 1Byte, 1: 64Byte or larger
Write Enable Instruction Required 0: not required
1: required 00h to be written to the
for Writing to Volatile Status
status register
Registers
0: use 50h instruction
1: use 06h instruction
Write Enable Instruction Select for
Note: If target flash status register is
Writing to Volatile Status Registers
nonvolatile, then bits 3 and 4 must
be set to 00b.
Contains 111b and can never be
Unused
changed
4KB Erase Instruction
Add (h) DW Add Data (h/b)
(Byte)
(Bit)
(Note1)
01:00
01b
02
1b
03
0b
30h
31h
E5h
04
0b
07:05
111b
15:08
20h
(1-1-2) Fast Read (Note2)
0=not supported 1=supported
16
1b
Address Bytes Number used in
addressing flash array
Double Transfer Rate (DTR)
Clocking
00: 3Byte only, 01: 3 or 4Byte,
10: 4Byte only, 11: Reserved
18:17
01b
0=not supported 1=supported
19
1b
20
1b
32h
Data
(h)
20h
FBh
(1-2-2) Fast Read
0=not supported 1=supported
(1-4-4) Fast Read
0=not supported 1=supported
21
1b
(1-1-4) Fast Read
0=not supported 1=supported
22
1b
23
1b
33h
31:24
FFh
37h:34h
31:00
3FFF FFFFh
Unused
Unused
Flash Memory Density
(1-4-4) Fast Read Number of Wait
states (Note3)
(1-4-4) Fast Read Number of
Mode Bits (Note4)
0 0000b: Not supported; 0 0100b: 4
0 0110b: 6; 0 1000b: 8; 0 1010b: 10
Mode Bits:
000b: Not supported; 010b: 2 bits
(1-4-4) Fast Read Instruction
(1-1-4) Fast Read Number of Wait
states
(1-1-4) Fast Read Number of
Mode Bits
39h
0 0000b: Not supported; 0 0100b: 4
0 0110b: 6; 0 1000b: 8; 0 1010b: 10
Mode Bits:
000b: Not supported; 010b: 2 bits
(1-1-4) Fast Read Instruction
P/N: PM2352
Downloaded from Arrow.com.
38h
3Ah
3Bh
Macronix Proprietary
101
04:00
0 0100b
07:05
010b
15:08
EBh
20:16
0 1000b
23:21
000b
31:24
6Bh
FFh
44h
EBh
08h
6Bh
Rev. 1.4, July 27, 2020
MX66U1G45G
SFDP Table below is for MX66U1G45GXDI0A, MX66U1G45GMI00 and MX66U1G45GXDI00
Description
Comment
(1-1-2) Fast Read Number of Wait
states
(1-1-2) Fast Read Number of
Mode Bits
0 0000b: Not supported; 0 0100b: 4
0 0110b: 6; 0 1000b: 8; 0 1010b: 10
Mode Bits:
000b: Not supported; 010b: 2 bits
(1-1-2) Fast Read Instruction
(1-2-2) Fast Read Number of Wait
states
(1-2-2) Fast Read Number of
Mode Bits
0 0000b: Not supported; 0 0100b: 4
0 0110b: 6; 0 1000b: 8; 0 1010b: 10
Mode Bits:
000b: Not supported; 010b: 2 bits
3Eh
3Fh
0=not supported 1=supported
Unused
(4-4-4) Fast Read
3Ch
3Dh
(1-2-2) Fast Read Instruction
(2-2-2) Fast Read
Add (h) DW Add Data (h/b)
(Byte)
(Bit)
(Note1)
0=not supported 1=supported
40h
Unused
04:00
0 1000b
07:05
000b
15:08
3Bh
20:16
0 0100b
23:21
000b
31:24
BBh
00
0b
03:01
111b
04
1b
07:05
111b
Data
(h)
08h
3Bh
04h
BBh
FEh
Unused
43h:41h
31:08
FFh
FFh
Unused
45h:44h
15:00
FFh
FFh
20:16
0 0000b
23:21
000b
47h
31:24
FFh
FFh
49h:48h
15:00
FFh
FFh
20:16
0 0100b
23:21
010b
4Bh
31:24
EBh
EBh
4Ch
07:00
0Ch
0Ch
4Dh
15:08
20h
20h
4Eh
23:16
0Fh
0Fh
4Fh
31:24
52h
52h
50h
07:00
10h
10h
51h
15:08
D8h
D8h
52h
23:16
00h
00h
53h
31:24
FFh
FFh
(2-2-2) Fast Read Number of Wait
states
(2-2-2) Fast Read Number of
Mode Bits
0 0000b: Not supported; 0 0100b: 4
0 0110b: 6; 0 1000b: 8
Mode Bits:
000b: Not supported; 010b: 2 bits
(2-2-2) Fast Read Instruction
Unused
(4-4-4) Fast Read Number of Wait
states
(4-4-4) Fast Read Number of
Mode Bits
0 0000b: Not supported; 0 0100b: 4
0 0110b: 6; 0 1000b: 8; 0 1010b: 10
Mode Bits:
000b: Not supported; 010b: 2 bits
(4-4-4) Fast Read Instruction
Erase Type 1 Size
Sector/block size = 2^N bytes (Note5)
0Ch: 4KB; 0Fh: 32KB; 10h: 64KB
Erase Type 1 Erase Instruction
Erase Type 2 Size
Sector/block size = 2^N bytes
00h: N/A; 0Fh: 32KB; 10h: 64KB
Erase Type 2 Erase Instruction
Erase Type 3 Size
Sector/block size = 2^N bytes
00h: N/A; 0Fh: 32KB; 10h: 64KB
Erase Type 3 Erase Instruction
Erase Type 4 Size
00h: N/A, This sector type doesn't
exist
Erase Type 4 Erase Instruction
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
102
46h
4Ah
00h
44h
Rev. 1.4, July 27, 2020
MX66U1G45G
SFDP Table below is for MX66U1G45GXDI0A, MX66U1G45GMI00 and MX66U1G45GXDI00
Description
Comment
Multiplier value: 0h~Fh (0~15)
Multiplier from typical erase time
Max. time = 2 * (Multiplier + 1) *
to maximum erase time
Typical Time
Erase Type 1 Erase Time
(Typical)
EraseType 2 Erase Time
(Typical)
Erase Type 3 Erase Time
(Typical)
Erase Type 4 Erase Time
(Typical)
Multiplier from typical time
to max time for Page or byte
program
Page Program Size
Page Program Time
(Typical)
Byte Program Time, First Byte
(Typical)
Byte Program Time, Additional
Byte
(Typical)
P/N: PM2352
Downloaded from Arrow.com.
Add (h) DW Add
(Byte)
(Bit)
Data (h/b)
(Note1)
03:00
0111b
07:04
08
1 1000b
10:09
00b
Count value: 00h~1Fh (0~31)
Typical Time = (Count + 1) * Units
15:11
0 1001b
Units
00: 1ms, 01: 16ms
10b: 128ms, 11b: 1s
17:16
01b
22:18
0 1101b
24:23
01b
29:25
0 0000b
31:30
00b
03:00
0010b
07:04
1000h
12:08
1 0010b
13
0b
15:14
17:16
0011b
18
1b
22:19
0000b
23
0b
54h
Count value: 00h~1Fh (0~31)
Typical Time = (Count + 1) * Units
Units
00: 1ms, 01: 16ms
10b: 128ms, 11b: 1s
55h
Count value: 00h~1Fh (0~31)
Typical Time = (Count + 1) * Units
Units
00: 1 ms, 01: 16 ms
10b: 128ms, 11b: 1s
Count value: 00h~1Fh (0~31)
Typical Time = (Count + 1) * Units
Units
00: 1ms, 01: 16ms
10b: 128 ms, 11b: 1 s
Multiplier value: 0h~Fh (0~15)
Max. time = 2 * (Multiplier + 1)
*Typical Time
Page size = 2^N bytes
2^8 = 256 bytes, 8h = 1000b
56h
57h
58h
Count value: 00h~1Fh (0~31)
Typical Time = (Count + 1) * Units
59h
Units
0: 8us, 1: 64us
Count value: 0h~Fh (0~15)
Typical Time = (Count + 1) * Units
Units
0: 1us, 1: 8us
Count value: 0h~Fh (0~15)
Typical Time = (Count + 1) * Units
Units
0: 1us, 1: 8us
Macronix Proprietary
103
5Ah
Data
(h)
87h
49h
B5h
00h
82h
D2h
04h
Rev. 1.4, July 27, 2020
MX66U1G45G
SFDP Table below is for MX66U1G45GXDI0A, MX66U1G45GMI00 and MX66U1G45GXDI00
Description
Chip Erase Time
(Typical)
Reserved
Prohibited Operations During
Program Suspend
Prohibited Operations During
Erase Suspend
Reserved
Program Resume to Suspend
Interval (Typical)
Program Suspend Latency
(Max.)
Erase Resume to Suspend
Interval (Typical)
Erase Suspend Latency
(Max.)
Suspend / Resume supported
Program Resume Instruction
Program Suspend Instruction
Erase Resume Instruction
Erase Suspend Instruction
P/N: PM2352
Downloaded from Arrow.com.
Comment
Count value: 00h~1Fh (0~31)
Typical Time = (Count + 1) * Units
Units
00: 16ms, 01: 256ms
10: 4s, 11: 64s
Reserved: 1b
xxx0b: May not initiate a new erase
anywhere
xx0xb: May not initiate a new page
program anywhere
x1xxb:
May
not initiate a read in
the program suspended
page size
1xxxb: The erase and program
restrictions in bits 1:0 are
sufficient
xxx0b: May not initiate a new erase
anywhere
xx1xb: May not initiate a page
program in the erase
suspended sector size
xx0xb: May not initiate a page
program anywhere
x1xxb: May not initiate a read in
the erase suspended sector
size
1xxxb: The erase and program
restrictions in bits 5:4 are
sufficient
Reserved: 1b
Count value: 0h~Fh (0~15)
Typical Time = (Count + 1) * 64us
Count value: 00h~1Fh (0~31)
Maximum Time = (Count + 1) * Units
Units
00: 128ns, 01: 1us
10: 8us, 11: 64us
Count value: 0h~Fh (0~15)
Typical Time = (Count + 1) * 64us
Count value: 00h~1Fh (0~31)
Maximum Time = (Count + 1) * Units
Units
00: 128ns, 01: 1us
10: 8us, 11: 64us
0= Support 1= Not supported
Instruction to Resume a Program
Instruction to Suspend a Program
Instruction to Resume Write/Erase
Instruction to Suspend Write/Erase
Macronix Proprietary
104
Add (h) DW Add
(Byte)
(Bit)
27:24
28
5Bh
Data (h/b)
(Note1)
0 0010b
E2h
30:29
11b
31
1b
03:00
0100b
5Ch
5Dh
5Eh
5Fh
60h
61h
62h
63h
Data
(h)
44h
07:04
0100b
08
1b
12:09
0001b
15:13
17:16
1 1000b
19:18
01b
23:20
0110b
28:24
1 1000b
30:29
01b
31
07:00
15:08
23:16
31:24
0b
30h
B0h
30h
B0h
03h
67h
38h
30h
B0h
30h
B0h
Rev. 1.4, July 27, 2020
MX66U1G45G
SFDP Table below is for MX66U1G45GXDI0A, MX66U1G45GMI00 and MX66U1G45GXDI00
Description
Comment
Reserved
Reserved: 11b
Bit 2: Read WIP bit [0] by 05h Read
instruction
Bit 3: Read bit 7 of Status Register
Status Register Polling Device
by 70h Read instruction
Busy
(0=not supported 1=support)
Bit 07:04, Reserved: 1111b
Count value: 00h~1Fh (0~31)
Release from Deep Power-down Maximum Time = (Count + 1) * Units
Units
(RDP) Delay
00: 128ns, 01: 1us
(Max.)
10: 8us, 11: 64us
Release from Deep Power-down Instruction to Exit Deep Power Down
(RDP) Instruction
FFh: Don't need command
Enter Deep Power Down
Instruction to Enter Deep Power
Instruction
Down
Deep Power Down Supported
0: Supported 1: Not supported
Methods to exit 4-4-4 mode
4-4-4 Mode Disable Sequences
xx1xb: issue F5h instruction
Methods to enter 4-4-4 mode
4-4-4 Mode Enable Sequences
x_x1xxb: issue instruction 35h
Performance Enhance Mode,
0-4-4 Mode Supported
Continuous Read, Execute in Place
0: Not supported 1: Supported
xx_xxx1b: Mode Bits[7:0] = 00h will
terminate this mode at the end
of the current read operation.
xx_xx1xb:
If 3-Byte address active,
input Fh on DQ0-DQ3 for 8
clocks. If 4-Byte address active,
input Fh on DQ0-DQ3 for 10
0-4-4 Mode Exit Method
clocks.
xx_x1xxb: Reserved
xx_1xxxb: Input Fh (mode bit reset)
on DQ0-DQ3 for 8 clocks.
x1_xxxxb: Mode Bit[7:0]≠Axh
1x_xxxxb: Reserved
xxx1b: Mode Bits[7:0] = A5h Note:
QE must be set prior to using
this mode
0-4-4 Mode Entry Method
x1xxb: Mode Bit[7:0]=Axh
1xxxb: Reserved
000b: No QE bit. Detects 1-1-4/1-4
4 reads based on instruction
Quad Enable (QE) bit
010b: QE is bit 6 of Status Register.
Requirements
where 1=Quad Enable or
0=not Quad Enable
111b:
Not
Supported
HOLD and RESET Disable by bit
0: Not supported
4 of Ext. Configuration Register
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
105
Add (h) DW Add
(Byte)
(Bit)
01:00
64h
65h
66h
67h
68h
Data (h/b)
(Note1)
11b
07:02
11 1101b
12:08
1 1101b
14:13
01b
15
22:16
23
30:24
31
1010 1011b
(ABh)
1011 1001b
(B9h)
0b
03:00
1010b
07:04
08
0 0100b
09
1b
Data
(h)
F7h
BDh
69h
D5h
5Ch
4Ah
9Eh
15:10
10 0111b
19:16
1001h
6Ah
29h
22:20
010b
23
0b
Rev. 1.4, July 27, 2020
MX66U1G45G
SFDP Table below is for MX66U1G45GXDI0A, MX66U1G45GMI00 and MX66U1G45GXDI00
Description
Comment
Reserved
Add (h) DW Add
(Byte)
(Bit)
6Bh
xxx_xxx1b: Non-Volatile Status
Register 1, powers-up to last
Volatile or Non-Volatile Register
written value, use instruction
and Write Enable Instruction for
06h to enable write
Status Register 1
x1x_xxxxb: Reserved
1xx_xxxxb: Reserved
6Ch
Reserved
Soft Reset and Rescue
Sequence Support
Exit 4-Byte Addressing
P/N: PM2352
Downloaded from Arrow.com.
Return the device to its default
power-on state
x1_xxxxb: issue reset enable
instruction 66h, then issue reset
instruction 99h.
xx_xxxx_xxx1b: issue instruction
E9h to exit 4-Byte address
mode (write enable instruction
06h is not required)
xx_xxxx_x1xxb: 8-bit volatile
extended address register used
to define A[31:A24] bits. Read
with instruction C8h. Write
instruction is C5h, data length
is 1 byte. Return to lowest
memory segment by setting
A[31:24] to 00h and use 3-Byte
addressing.
xx_xx1x_xxxxb: Hardware reset
xx_x1xx_xxxxb: Software reset
(see bits 13:8 in this DWORD)
xx_1xxx_xxxxb: Power cycle
x1_xxxx_xxxxb: Reserved
1x_xxxx_xxxxb: Reserved
Macronix Proprietary
106
6Dh
6Eh
Data (h/b)
(Note1)
Data
(h)
31:24
FFh
FFh
06:00
111 0000b
07
1b
13:08
01 0000b
15:14
01b
23:16
1111 1001b
F0h
50h
F9h
Rev. 1.4, July 27, 2020
MX66U1G45G
SFDP Table below is for MX66U1G45GXDI0A, MX66U1G45GMI00 and MX66U1G45GXDI00
Description
Enter 4-Byte Addressing
P/N: PM2352
Downloaded from Arrow.com.
Comment
xxxx_xxx1b: issue instruction
B7h (preceding write
enable not required)
xxxx_x1xxb: 8-bit volatile extended
address register used
to define A[31:24] bits.
Read with instruction
C8h. Write instruction
is C5h with 1 byte of
data. Select the active
128 Mbit memory
segment by setting the
appropriate A[31:24]
bits and use 3-Byte
addressing.
xx1x_xxxxb: Supports dedicated
4-Byte address
instruction set. Consult
vendor data sheet
for the instruction set
definition.
1xxx_xxxxb: Reserved
Macronix Proprietary
107
Add (h) DW Add
(Byte)
(Bit)
6Fh
31:24
Data (h/b)
(Note1)
Data
(h)
1000 0101b
85h
Rev. 1.4, July 27, 2020
MX66U1G45G
Table 16. Parameter Table (1): 4-Byte Instruction Tables
SFDP Table below is for MX66U1G45GXDI0A, MX66U1G45GMI00 and MX66U1G45GXDI00
Description
Support for (1-1-1) READ
Command, Instruction=13h
Support for (1-1-1) FAST_READ
Command, Instruction=0Ch
Support for (1-1-2) FAST_READ
Command, Instruction=3Ch
Support for (1-2-2) FAST_READ
Command, Instruction=BCh
Support for (1-1-4) FAST_READ
Command, Instruction=6Ch
Support for (1-4-4) FAST_READ
Command, Instruction=ECh
Support for (1-1-1) Page Program
Command, Instruction=12h
Support for (1-1-4) Page Program
Command, Instruction=34h
Support for (1-4-4) Page Program
Command, Instruction=3Eh
Support for Erase Command –
Type 1 size, Instruction lookup in
next Dword
Support for Erase Command –
Type 2 size, Instruction lookup in
next Dword
Support for Erase Command –
Type 3 size, Instruction lookup in
next Dword
Support for Erase Command –
Type 4 size, Instruction lookup in
next Dword
Support for (1-1-1) DTR_Read
Command, Instruction=0Eh
Support for (1-2-2) DTR_Read
Command, Instruction=BEh
Support for (1-4-4) DTR_Read
Command, Instruction=EEh
P/N: PM2352
Downloaded from Arrow.com.
Comment
Add (h) DW Add Data (h/b) Data
(Byte)
(Bit)
(Note1)
(h)
0=not supported 1=supported
00
1b
0=not supported 1=supported
01
1b
0=not supported 1=supported
02
1b
03
1b
04
1b
0=not supported 1=supported
05
1b
0=not supported 1=supported
06
1b
0=not supported 1=supported
07
0b
0=not supported 1=supported
08
1b
0=not supported 1=supported
09
1b
0=not supported 1=supported
10
1b
11
1b
0=not supported 1=supported
12
0b
0=not supported 1=supported
13
0b
0=not supported 1=supported
14
0b
0=not supported 1=supported
15
1b
0=not supported 1=supported
0=not supported 1=supported
0=not supported 1=supported
Macronix Proprietary
108
C0h
C1h
7Fh
8Fh
Rev. 1.4, July 27, 2020
MX66U1G45G
SFDP Table below is for MX66U1G45GXDI0A, MX66U1G45GMI00 and MX66U1G45GXDI00
Description
Support for volatile individual
sector lock Read command,
Instruction=E0h
Support for volatile individual
sector lock Write command,
Instruction=E1h
Support for non-volatile individual
sector lock read command,
Instruction=E2h
Support for non-volatile individual
sector lock write command,
Instruction=E3h
Comment
Add (h) DW Add Data (h/b) Data
(Byte)
(Bit)
(Note1)
(h)
0=not supported 1=supported
16
1b
0=not supported 1=supported
17
1b
18
1b
19
1b
23:20
1111b
0=not supported 1=supported
C2h
0=not supported 1=supported
FFh
Reserved
Reserved
Reserved
Reserved
C3h
31:24
FFh
FFh
Instruction for Erase Type 1
FFh=not supported
C4h
07:00
21h
21h
Instruction for Erase Type 2
FFh=not supported
C5h
15:08
5Ch
5Ch
Instruction for Erase Type 3
FFh=not supported
C6h
23:16
DCh
DCh
Instruction for Erase Type 4
FFh=not supported
C7h
31:24
FFh
FFh
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
109
Rev. 1.4, July 27, 2020
MX66U1G45G
Table 17. Parameter Table (2): Macronix Flash Parameter Tables
SFDP Table below is for MX66U1G45GXDI0A, MX66U1G45GMI00 and MX66U1G45GXDI00
Description
Comment
Add (h)
(Byte)
DW Add Data (h/b)
(Bit)
(Note1)
Data
(h)
Vcc Supply Maximum Voltage
2000h=2.000V
2700h=2.700V
3600h=3.600V
111h:110h
07:00
15:08
00h
20h
00h
20h
Vcc Supply Minimum Voltage
1650h=1.650V, 1750h=1.750V
2250h=2.250V, 2300h=2.300V
2350h=2.350V, 2650h=2.650V
2700h=2.700V
113h: 112h
23:16
31:24
50h
16h
50h
16h
H/W Reset# pin
0=not supported 1=supported
00
1b
H/W Hold# pin
0=not supported 1=supported
01
0b
Deep Power Down Mode
0=not supported 1=supported
02
1b
S/W Reset
0=not supported 1=supported
03
1b
S/W Reset Instruction
Reset Enable (66h) should be
issued before Reset Instruction
Program Suspend/Resume
0=not supported 1=supported
12
1b
Erase Suspend/Resume
0=not supported 1=supported
13
1b
14
1b
15
1b
116h
23:16
C0h
C0h
117h
31:24
64h
64h
115h: 114h
Unused
Wrap-Around Read mode
0=not supported 1=supported
Wrap-Around Read mode
Instruction
11:04
1001 1001b F99Dh
(99h)
Wrap-Around Read data length
08h:support 8B wrap-around read
16h:8B&16B
32h:8B&16B&32B
64h:8B&16B&32B&64B
Individual block lock
0=not supported 1=supported
00
1b
Individual block lock bit
(Volatile/Nonvolatile)
0=Volatile 1=Nonvolatile
01
0b
09:02
1110 0001b
(E1h)
10
0b
11
1b
Individual block lock Instruction
Individual block lock Volatile
protect bit default protect status
0=protect 1=unprotect
Secured OTP
0=not supported 1=supported
Read Lock
0=not supported 1=supported
12
0b
Permanent Lock
0=not supported 1=supported
13
0b
Unused
15:14
11b
Unused
31:16
FFh
FFh
31:00
FFh
FFh
Unused
P/N: PM2352
Downloaded from Arrow.com.
11Bh: 118h
11Fh: 11Ch
Macronix Proprietary
110
CB85h
Rev. 1.4, July 27, 2020
MX66U1G45G
Note 1: h/b is hexadecimal or binary.
Note 2: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x),
address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1),
(2-2-2), and (4-4-4)
Note 3: Wait States is required dummy clock cycles after the address bits or optional mode bits.
Note 4: Mode Bits is optional control bits that follow the address bits. These bits are driven by the system
controller if they are specified. (eg,read performance enhance toggling bits)
Note 5: 4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h
Note 6: All unused and undefined area data is blank FFh for SFDP Tables that are defined in Parameter
Identification Header. All other areas beyond defined SFDP Table are reserved by Macronix.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
111
Rev. 1.4, July 27, 2020
MX66U1G45G
12. RESET
Driving the RESET# pin low for a period of tRLRH or longer will reset the device. After reset cycle, the device is at
the following states:
- Standby mode
- All the volatile bits such as WEL/WIP/SRAM lock bit will return to the default status as power on.
- 3-byte address mode
If the device is under programming or erasing, driving the RESET# pin low will also terminate the operation and data
could be lost. During the resetting cycle, the SO data becomes high impedance and the current will be reduced to
minimum.
Figure 103. RESET Timing
CS#
tRHSL
SCLK
tRH tRS
RESET#
tRLRH
tREADY1 / tREADY2
Table 18. Reset Timing-(Power On)
Symbol Parameter
tRHSL Reset# high before CS# low
tRS
Reset# setup time
tRH
Reset# hold time
tRLRH Reset# low pulse width
tREADY1 Reset Recovery time
Min.
10
15
15
10
35
Typ.
Max.
Unit
us
ns
ns
us
us
Min.
10
15
15
10
40
40
310
12
25
1000
40
Typ.
Max.
Unit
us
ns
ns
us
us
us
us
ms
ms
ms
ms
Table 19. Reset Timing-(Other Operation)
Symbol
tRHSL
tRS
tRH
tRLRH
Parameter
Reset# high before CS# low
Reset# setup time
Reset# hold time
Reset# low pulse width
Reset Recovery time (During instruction decoding)
Reset Recovery time (for read operation)
Reset Recovery time (for program operation)
tREADY2 Reset Recovery time(for SE4KB operation)
Reset Recovery time (for BE64K/BE32KB operation)
Reset Recovery time (for Chip Erase operation)
Reset Recovery time (for WRSR operation)
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
112
Rev. 1.4, July 27, 2020
MX66U1G45G
13. POWER-ON STATE
The device is at below states when power-up:
- Standby mode (please note it is not deep power-down mode)
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage unless the VCC achieves below correct
level:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change
during power up state. When VCC is lower than VWI (POR threshold voltage value), the internal logic is reset and
the flash device has no response to any command.
For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not
guaranteed. The write, erase, and program command should be sent after the below time delay:
- tVSL after VCC reached VCC minimum level
The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.
Please refer to the "power-up timing".
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is
recommended. (generally around 0.1uF)
- At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response
to any command. The data corruption might occur during the stage while a write, program, erase cycle is in
progress.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
113
Rev. 1.4, July 27, 2020
MX66U1G45G
14. ELECTRICAL SPECIFICATIONS
Table 20. ABSOLUTE MAXIMUM RATINGS
Rating
Value
Ambient Operating Temperature
Industrial grade
-40°C to 85°C
Storage Temperature
-65°C to 150°C
Applied Input Voltage
-0.5V to VCC+0.5V
Applied Output Voltage
-0.5V to VCC+0.5V
VCC to Ground Potential
-0.5V to 2.5V
NOTICE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage
to the device. This is stress rating only and functional operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended period may affect reliability.
2. Specifications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot to VCC+1.0V or -1.0V for period up to 20ns.
Figure 105. Maximum Positive Overshoot Waveform
Figure 104. Maximum Negative Overshoot Waveform
20ns
0V
VCC+1.0V
-1.0V
2.0V
20ns
Table 21. CAPACITANCE TA = 25°C, f = 1.0 MHz
Symbol Parameter
CIN
COUT
P/N: PM2352
Downloaded from Arrow.com.
Min.
Typ.
Max.
Unit
Input Capacitance
16
pF
VIN = 0V
Output Capacitance
16
pF
VOUT = 0V
Macronix Proprietary
114
Conditions
Rev. 1.4, July 27, 2020
MX66U1G45G
Figure 106. DATA INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL
Input timing reference level
0.8VCC
Output timing reference level
0.7VCC
AC
Measurement
Level
0.3VCC
0.2VCC
0.5VCC
Note: Input pulse rise and fall time are 2). The number of (n/16) will be round up to next integer. In the formula,
while n=1, byte program time=32us. While n=17, byte program time=48us.
7. By default dummy cycle value. Please refer to the "Table 1. Read performance Comparison".
8. Latency time is required to complete Erase/Program Suspend operation until WIP bit is "0".
9. For tPRS, minimum timing must be observed before issuing the next program suspend command. However, a
period equal to or longer than the typical timing is required in order for the program operation to make progress.
10. For tERS, minimum timing must be observed before issuing the next erase suspend command. However, a
period equal to or longer than the typical timing is required in order for the erase operation to make progress.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
118
Rev. 1.4, July 27, 2020
MX66U1G45G
15. OPERATING CONDITIONS
At Device Power-Up and Power-Down
AC timing illustrated in Figure 109 and Figure 110 are for the supply voltages and the control signals at device
power-up and power-down. If the timing in the figures is ignored, the device will not operate correctly.
During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be
selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL.
Figure 109. AC Timing at Device Power-Up
VCC
VCC(min)
GND
tVR
tSHSL
CS#
tSLCH
tCHSL
tCHSH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
LSB IN
MSB IN
SI
High Impedance
SO
Symbol
tVR
tCLCH
Parameter
VCC Rise Time
Notes
1
Min.
Max.
500000
Unit
us/V
Notes :
1. Sampled, not 100% tested.
2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to
Table 23. AC CHARACTERISTICS.
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
119
Rev. 1.4, July 27, 2020
MX66U1G45G
Figure 110. Power-Down Sequence
During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.
VCC
CS#
SCLK
Figure 111. Power-up Timing
VCC
VCC(max)
Chip Selection is Not Allowed
VCC(min)
tVSL
Device is fully accessible
VWI
time
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
120
Rev. 1.4, July 27, 2020
MX66U1G45G
Figure 112. Power Up/Down and Voltage Drop
When powering down the device, VCC must drop below VPWD for at least tPWD to ensure the device will initialize
correctly during power up. Please refer to "Figure 112. Power Up/Down and Voltage Drop" and "Table 24. Power-Up/
Down Voltage and Timing" below for more details.
VCC
VCC (max.)
Chip Select is not allowed
VCC (min.)
V_keep
tVSL
VWI
Full Device
Access
Allowed
VPWD (max.)
tPWD
Time
Table 24. Power-Up/Down Voltage and Timing
Symbol
Min.
tPWD
Parameter
VCC voltage needed to below VPWD for ensuring initialization will
occur
Voltage that a re-initialization is necessary if VDD drop
below to VKEEP
The minimum duration for ensuring initialization will occur
tVSL
VPWD
V_keep
Max.
Unit
0.8
V
1.5
V
300
us
VCC(min.) to device operation
1500
us
VCC
VCC Power Supply
1.65
2.0
V
VWI
Write Inhibit Voltage
1.0
1.5
V
Note: These parameters are characterized only.
15-1. INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status
Register contains 00h (all Status Register bits are 0).
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
121
Rev. 1.4, July 27, 2020
MX66U1G45G
16. ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ. (1)
Min.
Max. (2)
Unit
40
ms
Write Status Register Cycle Time
Sector Erase Cycle Time (4KB)
25
400
ms
Block Erase Cycle Time (32KB)
150
1000
ms
Block Erase Cycle Time (64KB)
220
2000
ms
Chip Erase Cycle Time
150
300
s
Byte Program Time (via page program command)
25
60
us
0.15
0.75
ms
Page Program Time
Erase/Program Cycle
100,000
cycles
Note:
1. Typical program and erase time assumes the following conditions: 25°C, 1.8V, and checkerboard pattern.
2. Under worst conditions of 85°C and 1.65V.
3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming
command.
17. DATA RETENTION
Parameter
Condition
Min.
Data retention
55˚C
20
Max.
Unit
years
18. LATCH-UP CHARACTERISTICS
Min.
Input Voltage with respect to GND on all power pins
Max.
1.5 VCCmax
Input Current on all non-power pins
-100mA
+100mA
Test conditions: VCC = VCCmax, one pin at a time (compliant to JEDEC JESD78 standard).
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
122
Rev. 1.4, July 27, 2020
MX66U1G45G
19. ORDERING INFORMATION
Please contact Macronix regional sales for the latest product selection and available form factors.
PART NO.
TEMPERATURE
PACKAGE
MX66U1G45GXDI0A
-40°C to 85°C
24-Ball BGA
(5x5 ball array)
MX66U1G45GXDI00
-40°C to 85°C
24-Ball BGA
(5x5 ball array)
Supported password
protection feature
MX66U1G45GMI00
-40°C to 85°C
16-Pin SOP
(300mil)
Supported password
protection feature
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
123
Remark
Rev. 1.4, July 27, 2020
MX66U1G45G
20. PART NAME DESCRIPTION
MX 66
U 1G45G
XD
I
0A
MODEL CODE:
0A: STR, x1 I/O enable
00: STR, x1 I/O enable
TEMPERATURE RANGE:
I: Industrial (-40°C to 85°C)
PACKAGE:
XD: 24-Ball BGA (5x5 ball array)
M: 16-SOP (300mil)
DENSITY & MODE:
1G45G: 1Gb
TYPE:
U: 1.8V
DEVICE:
66: Serial NOR Flash
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
124
Rev. 1.4, July 27, 2020
MX66U1G45G
21. PACKAGE INFORMATION
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
125
Rev. 1.4, July 27, 2020
MX66U1G45G
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
126
Rev. 1.4, July 27, 2020
MX66U1G45G
22. REVISION HISTORY
Revision No. Description
Page
Date
0.01
1. Changed Document status to "Preliminary"
All
APR/14/2016
2. Updated parameters for DC/AC Characteristics P102,103,108
3. Updated VWI values
P107
4. Added Password Protection
P24,82,84,85,89,
P90,109,110
5. Content correction
P21,55-58,65-68,
P77,93,101,108
1.0
1. Removed "Preliminary" to align with the product status
2. Added 16-SOP package information
3. Added SFDP table
4. Updated tVR values
5. Content correction
All
AUG/12/2016
P6,8,116,122,123,
P125
P97-110
P118,120
P24,25,82,84-86,
P89,116
1.1
1. Updated tPP values and note
2. Updated the note for the internal pull up status of RESET#
and WP#/SIO2
3. Content correction.
P116-117
P8
1.2
1. Updated tPP values and note
2. Format modification.
P116-117
P124-125
OCT/28/2016
P45,58
AUG/09/2017
1.3
1. Corrected SFDP typo
P109 AUG/16/2018
2. Added "Figure 108. SCLK TIMING DEFINITION" P114
3. Added Note for "Table 24. Power-Up/Down Voltage and Timing" P120
4. Content correction
P8,16,21,25-29,
P33,36,69,85,
P91,116,121
1.4
1. Modified "LATCH-UP CHARACTERISTICS" description
2. Added "Support Performance Enhance Mode - XIP
(execute-in-place)"
3. Modified "Program Suspend and Erase Suspend" description
4. Modified Serial Input Timing (STR mode/DTR mode)
5. Added tDVCL and tCLDX values
6. Modified Output Driver Strength Table
7. Corrected "Read Electronic Signature (RES) Sequence"
8. Added 75h and 7Ah for PGM/ERS Suspend and
PGM/ERS Resume
P/N: PM2352
Downloaded from Arrow.com.
Macronix Proprietary
127
P122
P5,65
JUL/27/2020
P93
P15
P117
P29
P34,35
P24
Rev. 1.4, July 27, 2020
MX66U1G45G
Except for customized products which have been expressly identified in the applicable agreement, Macronix's
products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or
household applications only, and not for use in any applications which may, directly or indirectly, cause death,
personal injury, or severe property damages. In the event Macronix products are used in contradicted to their
target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its
actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/
or distributors shall be released from any and all liability arisen therefrom.
Copyright© Macronix International Co., Ltd. 2016-2020. All rights reserved, including the trademarks and
tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, Nbit,
Macronix NBit, HybridNVM, HybridFlash, HybridXFlash, XtraROM, KH Logo, BE-SONOS, KSMC, Kingtech,
MXSMIO, Macronix vEE, RichBook, Rich TV, OctaBus, FitCAM, ArmorFlash. The names and brands of third
party referred thereto (if any) are for identification purposes only.
For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
Downloaded from Arrow.com.
128
工商网监
湘ICP备2023018690号
