ADVANCED INFORMATION
MX66UM1G45G
MX66UM1G45G
1.8V 1G-BIT [x 1/x 8]
CMOS MXSMIO® (SERIAL MULTI I/O)
OctaFlash
Key Features
• Protocol Support - Single I/O and Octa I/O
• Support DTR (Double Transfer Rate) Mode
• Support clock frequency up to 166MHz
Rev. 0.00, March 01, 2017
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ADVANCED INFORMATION
MX66UM1G45G
Contents
1. FEATURES............................................................................................................................................................... 4
2. GENERAL DESCRIPTION...................................................................................................................................... 5
Table 1. Operating Frequency Comparison.................................................................................................5
3. PIN CONFIGURATIONS .......................................................................................................................................... 6
Table 2. PIN DESCRIPTION........................................................................................................................6
4. BLOCK DIAGRAM.................................................................................................................................................... 7
5. MEMORY ORGANIZATION...................................................................................................................................... 8
6. DATA PROTECTION................................................................................................................................................. 9
6-1.
Block lock protection................................................................................................................................. 10
Table 3. Protected Area Sizes....................................................................................................................10
6-2. Additional 8K-bit secured OTP ..................................................................................................................11
Table 4. Secured OTP Definition................................................................................................................ 11
7. DEVICE OPERATION............................................................................................................................................. 12
8. COMMAND SET..................................................................................................................................................... 14
8-1. SPI Command Set.................................................................................................................................... 14
8-2. OPI Command Set.................................................................................................................................... 17
9. REGISTER DESCRIPTION..................................................................................................................................... 19
9-1.
9-2.
9-3.
9-4.
Status Register......................................................................................................................................... 19
Configuration Register.............................................................................................................................. 20
Configuration Register 2........................................................................................................................... 21
Security Register...................................................................................................................................... 24
Table 5. Security Register Definition..........................................................................................................24
10. COMMAND DESCRIPTION.................................................................................................................................. 25
10-1. Write Enable (WREN)............................................................................................................................... 25
10-2. Write Disable (WRDI)................................................................................................................................ 26
10-3. Read Identification (RDID)........................................................................................................................ 27
Table 6. ID Definitions ...............................................................................................................................27
10-4. Read Status Register (RDSR).................................................................................................................. 28
10-5. Read Configuration Register (RDCR)....................................................................................................... 31
10-6. Write Status Register (WRSR) / Write Configuration Register (WRCR)................................................... 32
10-7. Read Configuration Register 2 (RDCR2).................................................................................................. 35
10-8. Write Configuration Register 2 (WRCR2).................................................................................................. 36
10-9. Read Security Register (RDSCUR).......................................................................................................... 37
10-10. Write Security Register (WRSCUR).......................................................................................................... 38
10-11. Read Data Bytes (READ/READ3B/READ4B).......................................................................................... 39
10-12. Read Data Bytes at Higher Speed (FAST_READ/FAST_READ3B/FAST_READ4B).............................. 40
10-13. OCTA Read Mode (8READ)..................................................................................................................... 41
10-14. OCTA DTR Read Mode (8DTRD)............................................................................................................. 42
10-15. Preamble Bit............................................................................................................................................. 43
10-16. Burst Read................................................................................................................................................ 44
10-17. Fast Boot.................................................................................................................................................. 45
10-18. Sector Erase (SE/SE3B/SE4B)................................................................................................................ 50
P/N: PM2504
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MX66UM1G45G
10-19. Block Erase (BE/BE3B/BE4B).................................................................................................................. 51
10-20. Chip Erase (CE)........................................................................................................................................ 52
10-21. Page Program (PP/PP3B/PP4B).............................................................................................................. 53
10-22. Deep Power-down (DP)............................................................................................................................ 55
10-23. Release from Deep Power-down (RDP)................................................................................................... 56
10-24. Enter Secured OTP (ENSO)..................................................................................................................... 57
10-25. Exit Secured OTP (EXSO)........................................................................................................................ 57
10-26. Write Protection Selection (WPSEL)......................................................................................................... 58
10-27. Advanced Sector Protection..................................................................................................................... 59
10-28. Program Suspend and Erase Suspend.................................................................................................... 74
Table 7. Acceptable Commands During Suspend.....................................................................................75
10-29. Program Resume and Erase Resume...................................................................................................... 76
10-30. No Operation (NOP)................................................................................................................................. 77
10-31. Software Reset (Reset-Enable (RSTEN) and Reset (RST)).................................................................... 77
11. Serial Flash Discoverable Parameter (SFDP)................................................................................................... 79
11-1. Read SFDP Mode (RDSFDP)................................................................................................................... 79
Table 8. Signature and Parameter Identification Data Values (TBD).........................................................80
12. Data Integrity check............................................................................................................................................ 81
12-1. ECC (Error Checking and Correcting)...................................................................................................... 81
Table 9. 16-Byte Chunks within a Page.....................................................................................................81
12-2. ECS# (Error corrected Signal) Pin............................................................................................................ 82
12-3. Parity Check (CRC1)................................................................................................................................ 83
13. RESET.................................................................................................................................................................. 86
Table 10. Reset Timing-(Standby)..............................................................................................................86
Table 11. Reset Timing-(Other Operation).................................................................................................86
14. POWER-ON STATE.............................................................................................................................................. 87
15. ELECTRICAL SPECIFICATIONS......................................................................................................................... 88
Table 12. ABSOLUTE MAXIMUM RATINGS.............................................................................................88
Table 13. CAPACITANCE TA = 25°C, f = 1.0 MHz.....................................................................................88
Table 14. DC CHARACTERISTICS...........................................................................................................90
Table 15. AC CHARACTERISTICS............................................................................................................91
16. OPERATING CONDITIONS.................................................................................................................................. 93
Table 16. Power-Up/Down Voltage and Timing .........................................................................................95
16-1. INITIAL DELIVERY STATE....................................................................................................................... 95
17. ERASE AND PROGRAMMING PERFORMANCE............................................................................................... 96
18. DATA RETENTION............................................................................................................................................... 96
19. LATCH-UP CHARACTERISTICS......................................................................................................................... 96
20. ORDERING INFORMATION................................................................................................................................. 97
21. PART NAME DESCRIPTION................................................................................................................................ 98
22. PACKAGE INFORMATION................................................................................................................................... 99
P/N: PM2504
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Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
1.8V 1G-BIT [x 1/x 8] CMOS MXSMIO® (SERIAL MULTI I/O)
FLASH MEMORY
1. FEATURES
HARDWARE FEATURES
• SCLK Input
- Serial clock input
• SIO0 - SIO7
- Serial Data Input or Serial Data Output
• DQS
- Data strobe signal
• RESET#
- Hardware Reset pin
• PACKAGE
-24-Ball BGA (5x5 ball array)
-All devices are RoHS Compliant and Halogen
Free.
GENERAL
• Supports Serial Peripheral Interface -- Mode 0
• Single Power Supply Operation
- 1.65 to 2.0 volt for read, erase, and program
operations
• Protocol Support
- Single I/O and Octa I/O
- Support DTR (Double Transfer Rate) Mode
• Fast frequency support
- Support clock frequency up to
- Single I/O mode: 133MHz
- Octa I/O mode: 166MHz
- Configurable dummy cycle number for OPI read
operation
• Octa Peripheral Interface (OPI) available
• Equal Sectors with 4K byte each, or Equal Blocks
with 64K byte each
- Any Block can be erased individually
• Programming :
- 256byte page buffer
- Octa Input/Output page program to enhance
program performance
• Typical 100,000 erase/program cycles
• 20 years data retention
SOFTWARE FEATURES
• Input Data Format
- SPI: 1-byte command code
- OPI: 2-byte command code
• Advanced Security Features
- Block lock protection
The BP0-BP3 and T/B status bits define the size of
the area to be protected against program and erase
instructions
- Advanced Sector Protection (Solid and Password
Protect)
• Additional 8K bit security OTP
- Features unique identifier
- Factory locked identifiable, and customer lockable
• Command Reset
• Program/Erase Suspend and Resume operation
• Electronic Identification
- JEDEC 1-byte manufacturer ID and 2-byte device
ID
• Support Serial Flash Discoverable Parameters
(SFDP) mode
P/N: PM2504
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ADVANCED INFORMATION
MX66UM1G45G
2. GENERAL DESCRIPTION
MX66UM1G45G is 1Gb bits Serial NOR Flash memory, which is configured as 134,217,728 x 8 internally.
MX66UM1G45G feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire
bus while it is in single I/O mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a
serial data output (SO). Serial access to the device is enabled by CS# input.
The MX66UM1G45G MXSMIO® (Serial Multi I/O) provides sequential read operation on whole chip.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the
specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis, or word basis. Erase command is executed on sector (4K-byte), or block (64K-byte), or whole chip
basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
When the device is not in operation and CS# is high, it is put in standby mode.
The MX66UM1G45G utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after
100,000 program and erase cycles.
Table 1. Operating Frequency Comparison
Numbers of Dummy Cycle
6
8
10
12
14
16
18
20
Octa I/O STR (MHz)
66
84
104
104
133
166
166
166*
Octa I/O DTR (MHz)
66
84
104
104
133
166
166
166*
Notes: * means default status
P/N: PM2504
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MX66UM1G45G
3. PIN CONFIGURATIONS
24-BALL BGA (5x5 ball array)
1
2
3
NC
NC
Table 2. PIN DESCRIPTION
4
SYMBOL
CS#
SCLK
RESET#
ECS#
DQS
5
A
B
C
D
E
RESET#
ECS#
SI/SIO0
NC
SCLK
GND
VCC
NC
SO/SIO1
VSSQ
CS#
DQS
SIO2
NC
VCCQ
SIO1
SIO0
SIO3
SIO4
SIO7
SIO6
SIO5
VCCQ
VSSQ
SIO2-SIO7
VCC
VCCQ
GND
VSSQ
NC
DESCRIPTION
Chip Select
Clock Input
Hardware Reset Pin Active lowNote 1
ECC Correction Signal (open drain)
Data Strobe Signal
Serial Data Input (for 1 x I/O)/ Serial
Data Input & Output (for 8 x I/O read
mode)
Serial Data Output (for 1 x I/O)/ Serial
Data Input & Output (for 8 x I/O read
mode)
Serial Data Input & Output (for 8 x I/O
read mode)
1.8V Power Supply
1.8V Buffer Power Supply
Ground
IO Ground Supply
No Connection
Notes:
1. The pin of RESET# will remain internal pull up
function while this pin is not physically connected
in system configuration.
However, the internal pull up function will be disabled
if the system has physical connection to RESET#
pin.
P/N: PM2504
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ADVANCED INFORMATION
MX66UM1G45G
4. BLOCK DIAGRAM
SIO3
SIO4
SIO5
SIO6
SIO7
RESET#
CS#
DQS
ECS#
SCLK
X-Decoder
SI/SIO0
SO/SIO1
SIO2
Address
Generator
Memory Array
Y-Decoder
Data
Register
Sense
Amplifier
SRAM
Buffer
Mode
Logic
State
Machine
HV
Generator
Clock Generator
Output
Buffer
P/N: PM2504
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ADVANCED INFORMATION
MX66UM1G45G
5. MEMORY ORGANIZATION
Sector
Address Range
…
7FF8FFFh
7FF7000h
7FF7FFFh
7FF0FFFh
7FEF000h
7FEFFFFh
…
7FE8000h
7FE8FFFh
32743
7FE7000h
7FE7FFFh
…
…
32744
7FE0FFFh
7FDF000h
7FDFFFFh
…
…
7FE0000h
32735
…
32736
7FD8000h
7FD8FFFh
32727
7FD7000h
7FD7FFFh
32720
…
32728
…
2045
…
7FF0000h
32751
…
32752
…
2046
…
7FF8000h
32759
…
32760
…
2047
7FFFFFFh
…
7FFF000h
…
32767
…
Block(64K-byte)
7FD0000h
7FD0FFFh
∼
…
0028FFFh
027000h
0027FFFh
0020FFFh
001F000h
001FFFFh
…
0018000h
0018FFFh
23
0017000h
0017FFFh
…
0010000h
0010FFFh
15
000F000h
000FFFFh
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…
…
16
…
P/N: PM2504
…
24
0008FFFh
0007000h
0007FFFh
…
0008000h
7
…
8
…
0
…
0020000h
31
…
32
…
1
…
0028000h
39
…
40
…
2
002FFFFh
…
002F000h
…
47
0
0000000h
0000FFFh
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Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
6. DATA PROTECTION
During power transition, there may be some false system level signals which result in inadvertent erasure or
programming. The device is designed to protect itself from these accidental write cycles.
The state machine will be reset as standby mode automatically during power up. In addition, the control register
architecture of the device constrains that the memory contents can only be changed after specific command
sequences have completed successfully.
In the following, there are several features to protect the system from the accidental write cycles during VCC powerup and power-down or from system noise.
• Valid command length (SPI Mode) or command/command# combination (OPI Mode) will be check.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
other command to change data.
• Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from
writing all commands except Release from deep power down mode command (RDP), and softreset command.
P/N: PM2504
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MX66UM1G45G
6-1. Block lock protection
- The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0 and T/B) bits to allow part of memory to be
protected as read only. The protected area definition is shown as Table 3 Protected Area Sizes, the protected
areas are more flexible which may protect various area by setting value of BP0-BP3 bits.
Table 3. Protected Area Sizes
Protected Area Sizes (T/B bit = 0)
Status bit
BP3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
BP2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
BP1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Protect Level
BP0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1Gb
0 (none)
1 (1 block, protected block 2047th)
2 (2 blocks, protected block 2046th~2047th)
3 (4 blocks, protected block 2044th~2047th)
4 (8 blocks, protected block 2040th~2047th)
5 (16 blocks, protected block 2032nd~2047th)
6 (32 blocks, protected block 2016th~2047th)
7 (64 blocks, protected block 1984th~2047th)
8 (128 blocks, protected block 1920th~2047th)
9 (256 blocks, protected block 1792nd~2047th)
10 (512 blocks, protected block 1536th~2047th)
11 (1024 blocks, protected block 1024th~2047th)
12 (2048 blocks, protected all)
13 (2048 blocks, protected all)
14 (2048 blocks, protected all)
15 (2048 blocks, protected all)
Protected Area Sizes (T/B bit = 1)
Status bit
BP3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
P/N: PM2504
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BP2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
BP1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Protect Level
BP0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1Gb
0 (none)
1 (1 block, protected block 0th)
2 (2 blocks, protected block 0th~1st)
3 (4 blocks, protected block 0th~3rd)
4 (8 blocks, protected block 0th~7th)
5 (16 blocks, protected block 0th~15th)
6 (32 blocks, protected block 0th~31st)
7 (64 blocks, protected block 0th~63rd)
8 (128 blocks, protected block 0th~127th)
9 (256 blocks, protected block 0th~255th)
10 (512 blocks, protected block 0th~511th)
11 (1024 blocks, protected block 0th~1023rd)
12 (2048 blocks, protected all)
13 (2048 blocks, protected all)
14 (2048 blocks, protected all)
15 (2048 blocks, protected all)
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Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
6-2. Additional 8K-bit secured OTP
The secured OTP for unique identifier: to provide 8K-bit one-time program area for setting device unique serial
number. Which may be set by factory or system customer.
- Security register bit 0 indicates whether the chip is locked by factory or not.
- To program the 8K-bit secured OTP by entering secured OTP mode (with Enter Security OTP command), and
going through normal program procedure, and then exiting secured OTP mode by writing Exit Security OTP
command.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register)
command to set customer lock-down bit1 as "1". Please refer to "Table 5. Security Register Definition" for
security register bit definition and "Table 4. Secured OTP Definition" for address range definition.
- Note: Once lock-down by factory or customer, the corresponding range cannot be changed any more. While in
secured OTP mode, array access is not allowed.
Table 4. Secured OTP Definition
Address range
Size
Lock-down
xxx000~xxx1FF
4096-bit
Determined by Customer
xxx200~xxx3FF
4096-bit
Determined by Factory
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MX66UM1G45G
7. DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended
operation.
2. When incorrect command# sequence is inputted to this device, this device becomes standby mode and keeps
the standby mode until next CS# falling edge. In standby mode, SO pin of this device should be High-Z.
3. When correct command# sequence is inputted to this device, this device becomes active mode and keeps the
active mode until next CS# rising edge.
4. When device under STR mode, input data is latched on the rising edge of Serial Clock (SCLK) and data shifts
out on the falling edge of SCLK. When device under DTR mode, input data is latched on the both rising and
falling edge of Serial Clock (SCLK) and data shifts out on both rising and falling edge of SCLK.
5. While a Write Status Register, Program or Erase operation is in progress, access to the memory array is
neglected and not affect the current operation of Write Status Register, Program, Erase.
Figure 1. Input Timing (STR mode)
tSHSL
CS#
tCHSL
tSLCH
tCHSH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
tCLCH
LSB
MSB
SIO
Figure 2. Input Timing (DTR mode)
tSHSL
CS#
tCHSL
tSLCH
tSHCH
tCLSH
SCLK
tDVCH
tCHDX
SIO
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tCHCL
tCLDX
tDVCL
MSB
tCLCH
LSB
12
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ADVANCED INFORMATION
MX66UM1G45G
Figure 3. Output Timing (STR mode)
CS#
tCH
SCLK
tCLQV
tCLQX
tCL
tCLQV
tSHQZ
tCLQX
LSB
SIO
Figure 4. Output Timing (DTR mode)
SCLK
tCHQV
DQS
tCLQV
tQSV
tDQSQ
tDQSQ
tQH
tQH
SIO[7:0]
P/N: PM2504
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MX66UM1G45G
8. COMMAND SET
8-1. SPI Command Set
Address Byte
Command
Code
Total
ADD
Byte
Byte 1
Byte 2
Byte 3
Dummay
Cycle
Data
Byte
03 (hex)
3
ADD1
ADD2
ADD3
0
1- ∞
0B (hex)
3
ADD1
ADD2
ADD3
8
1- ∞
02 (hex)
3
ADD1
ADD2
ADD3
0
1-256
20 (hex)
3
ADD1
ADD2
ADD3
0
0
D8 (hex)
3
ADD1
ADD2
ADD3
0
0
13 (hex)
4
ADD1
ADD2
ADD3
ADD4
0
1- ∞
0C (hex)
4
ADD1
ADD2
ADD3
ADD4
8
1- ∞
12 (hex)
4
ADD1
ADD2
ADD3
ADD4
0
1-256
21 (hex)
4
ADD1
ADD2
ADD3
ADD4
0
0
DC (hex)
4
ADD1
ADD2
ADD3
ADD4
0
0
60 or C7
(hex)
0
0
0
06 (hex)
0
0
0
04 (hex)
0
0
0
68 (hex)
0
0
0
B0 (hex)
0
0
0
30 (hex)
0
0
0
B9 (hex)
0
0
0
AB (hex)
0
0
0
00 (hex)
0
0
0
66 (hex)
0
0
0
99 (hex)
0
0
0
7E (hex)
0
0
0
98 (hex)
0
0
0
Byte 4
Array access
READ3B
(normal read)
FAST READ3B
(fast read data)
PP3B
(page program)
SE3B
(sector erase)
BE3B
(block erase 64KB)
READ4B
(normal read)
FAST READ4B
(fast read data)
PP4B
(page program)
SE4B
(sector erase 4KB)
BE4B
(block erase 64KB)
CE
(chip erase)
Device operation
WREN
(write enable)
WRDI
(write disable)
WPSEL
(Write Protect Selection)
PGM/ERS Suspend
(Suspends Program/ Erase)
PGM/ERS Resume
(Resumes Program/ Erase)
DP
(Deep power down)
RDP
(Release from deep power
down)
NOP
(No Operation)
RSTEN
(Reset Enable)
RST
(Reset Memory)
GBLK
(gang block lock)
GBULK
(gang block unlock)
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MX66UM1G45G
Address Byte
Command
Code
Total
ADD
Byte
Dummay
Cycle
Data
Byte
9F (hex)
0
0
3
5A (hex)
3
0
0
05 (hex)
0
0
1
15 (hex)
0
0
1
01 (hex)
0
0
1-2
71 (hex)
4
ADD1
ADD2
ADD3
ADD4
0
1
72 (hex)
4
ADD1
ADD2
ADD3
ADD4
0
1
2B (hex)
0
0
0
2F (hex)
0
0
0
16 (hex)
0
0
1-4
17 (hex)
0
0
4
18 (hex)
0
0
0
C0 (hex)
0
0
1
B1 (hex)
0
0
0
C1 (hex)
0
0
0
2C (hex)
0
0
1
2D (hex)
0
0
1
E3 (hex)
4
0
0
E4 (hex)
0
0
0
E2 (hex)
4
ADD1
ADD2
ADD3
ADD4
0
1
E1 (hex)
4
ADD1
ADD2
ADD3
ADD4
0
1
E0 (hex)
4
ADD1
ADD2
ADD3
ADD4
0
1
Byte 1
Byte 2
Byte 3
Byte 4
Register Access
RDID
(read identification)
RDSFDP
(Read SFDP Table)
RDSR
(read status register)
RDCR
(read configuration register)
WRSR/WRCR
(write status/configuration
register)
RDCR2
(read configuration register2)
WRCR2
(write configuration register2)
RDSCUR
(read security register)
WRSCUR
(write security register)
RDFBR
(read fast boot register)
WRFBR
(write fast boot register)
ESFBR
(erase fast boot register)
SBL
(Set Burst Length)
ENSO
(enter secured OTP)
EXSO
(exit secured OTP)
WRLR
(write Lock register)
RDLR
(read Lock register)
WRSPB
(SPB bit program)
ESSPB
(all SPB bit erase)
RDSPB
(read SPB status)
WRDPB
(write DPB register)
RDDPB
(read DPB register)
P/N: PM2504
Downloaded from Arrow.com.
ADD1
ADD1
15
ADD2
ADD2
ADD3
ADD3
ADD4
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
RDPASS
(read password register)
WRPASS
(write password register)
PASSULK
(password unlock)
Address Byte
Command
Code
Total
ADD
Byte
Byte 1
Byte 2
Byte 3
Byte 4
Dummay
Cycle
Data
Byte
27 (hex)
4
00h
00h
00h
00h
8
8
28 (hex)
4
00h
00h
00h
00h
0
8
29 (hex)
4
00h
00h
00h
00h
0
8
Note 1: It is not recommended to adopt any other code/address not in the command definition table, which will potentially enter
the hidden mode.
Note 2: The RSTEN command must be executed before executing the RST command. If any other command is issued
in-between RSTEN and RST, the RST command will be ignored.
P/N: PM2504
Downloaded from Arrow.com.
16
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
8-2. OPI Command Set
Command Set
1'st
Byte
2'nd
Byte
8-8-8
(STR)
8-8-8
(DTR)
Address Byte
Total
ADD
Byte
Byte 1 Byte 2 Byte 3 Byte 4
Dummay
Cycle
Data
Byte
6-20
1- ∞
6-20
1- ∞
Array access
8READ
(8 I/O read )
8DTRD
(8 I/O DT Read)
PP4B
(Page Program)
SE4B
(Sector erase 4KB)
BE4B
(block erase 64KB)
CE
(chip erase)
EC (hex) 13 (hex)
4
ADD1
ADD2
ADD3
ADD4
V
4
ADD1
ADD2
ADD3
ADD4
V
EE (hex) 11 (hex)
(Note5)
(Note3)
(Note3)
12 (hex) ED (hex)
V
V
4
ADD1
ADD2
ADD3
ADD4
0
1-256
21 (hex) DE (hex)
V
V
4
ADD1
ADD2
ADD3
ADD4
0
0
DC (hex) 23 (hex)
V
V
4
ADD1
ADD2
ADD3
ADD4
0
0
60 or C7 9F or
(hex) 38 (hex)
V
V
0
0
0
06 (hex) F9 (hex)
V
V
0
0
0
04 (hex) FB (hex)
V
V
0
0
0
68 (hex) 97 (hex)
V
V
0
0
0
B0 (hex) 4F (hex)
V
V
0
0
0
30 (hex) CF (hex)
V
V
0
0
0
B9 (hex) 46 (hex)
V
V
0
0
0
AB (hex) 54 (hex)
V
V
0
0
0
00 (hex) FF (hex)
V
V
0
0
0
66 (hex) 99 (hex)
V
V
0
0
0
99 (hex) 66 (hex)
V
V
0
0
0
7E (hex) 81 (hex)
V
V
0
0
0
98 (hex) 67 (hex)
V
V
0
0
0
9F (hex) 60 (hex)
V
V
4
00h
00h
00h
00h
4
5A (hex) A5 (hex)
V
V
4
ADD1
ADD2
ADD3
ADD4
20
05 (hex) FA (hex)
V
V
4
00h
00h
00h
00h
15 (hex) EA (hex)
V
V
4
00h
00h
00h
01h
(Note5)
Device operation
WREN
(write enable)
WRDI
(write disable)
WPSEL
(Write Protect Selection)
PGM/ERS Suspend
(Suspends Program/
Erase)
PGM/ERS Resume
(Resumes Program/
Erase)
DP
(Deep power down)
RDP
(Release from
deep power down)
NOP
(No Operation)
RSTEN
(Reset Enable)
RST
(Reset Memory)
GBLK
(gang block lock)
GBULK
(gang block unlock)
(Note2)
(Note2)
Register Access
RDID
(read identification)
RDSFDP
(Read SFDP Table)
RDSR
(read status register)
RDCR
(read configuration
register)
P/N: PM2504
Downloaded from Arrow.com.
17
3
(Note6)
4
1
4
1
(Note4)
(Note4)
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
Command Set
8-8-8
(DTR)
Total
ADD
Byte
01 (hex) FE (hex)
V
V
4
00h
00h
00h
01 (hex) FE (hex)
V
V
4
00h
00h
71 (hex) 8E (hex)
V
V
4
ADD1
72 (hex) 8D (hex)
V
V
4
2B (hex) D4 (hex)
V
V
4
2F (hex) D0 (hex)
V
V
0
C0 (hex) 3F (hex)
V
V
4
00h
00h
00h
00h
16 (hex) E9 (hex)
V
V
4
00h
00h
00h
00h
17 (hex) E8 (hex)
V
V
4
00h
00h
00h
00h
18 (hex) E7 (hex)
V
V
B1 (hex) 4E (hex)
V
C1 (hex) 3E (hex)
1'st
Byte
WRSR
(write status register)
WRCR
(configuration register)
RDCR2
(read configuration
register2)
WRCR2
(write configuration
register2)
RDSCUR
(read security register)
WRSCUR
(write security register)
SBL
(Set Burst Length)
RDFBR
(read fast boot register)
WRFBR
(write fast boot register)
ESFBR
(erase fast boot register)
ENSO
(enter secured OTP)
EXSO
(exit secured OTP)
WRLR
(write Lock register)
RDLR
(read Lock register)
WRSPB
(SPB bit program)
ESSPB
(all SPB bit erase)
RDSPB
(read SPB status)
WRDPB
(write DPB register)
RDDPB
(read DPB register)
RDPASS
(read password register)
WRPASS
(write password register)
PASSULK
(password unlock)
Address Byte
8-8-8
(STR)
2'nd
Byte
Dummay
Cycle
Data
Byte
00h
0
2
00h
01h
0
2
ADD2
ADD3
ADD4
4
1
ADD1
ADD2
ADD3
ADD4
0
1
00h
00h
00h
00h
4
1
0
0
0
1
Byte 1 Byte 2 Byte 3 Byte 4
(Note4)
(Note4)
4
1-4
(Note4)
(Note6)
0
4
0
0
0
V
0
0
0
V
V
0
0
0
2C (hex) D3 (hex)
V
V
4
00h
00h
00h
00h
0
1
2D (hex) D2 (hex)
V
V
4
00h
00h
00h
00h
4
1
E3 (hex) 1C (hex)
V
V
4
ADD1
ADD2
ADD3
ADD4
0
0
E4 (hex) 1B (hex)
V
V
0
0
0
E2 (hex) 1D (hex)
V
V
4
ADD1
ADD2
ADD3
ADD4
6-20
1
E1 (hex) 1E (hex)
V
V
4
ADD1
ADD2
ADD3
ADD4
0
1
E0 (hex) 1F (hex)
V
V
4
ADD1
ADD2
ADD3
ADD4
6-20
1
27 (hex) D8 (hex)
V
V
4
00h
00h
00h
00h
20
8
28 (hex) D7 (hex)
V
V
4
00h
00h
00h
00h
0
8
29 (hex) D6 (hex)
V
V
4
00h
00h
00h
00h
0
8
(Note4)
(Note3)
(Note3)
Note 1: It is not recommended to adopt any other code/address not in the command definition table, which will potentially enter
the hidden mode.
Note 2: The RSTEN command must be executed before executing the RST command. If any other command is issued
in-between RSTEN and RST, the RST command will be ignored.
Note 3: See dummy cycle and frequency table.
Note 4: 4 dummy cycles in both STR/DTR.
Note 5: The starting address must be even byte (A0 must be 0) in DTR OPI mode.
Note 6: Data bytes are always output in STR.
P/N: PM2504
Downloaded from Arrow.com.
18
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
9. REGISTER DESCRIPTION
9-1. Status Register
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write
status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status
register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status
register cycle.
WEL bit. The Write Enable Latch (WEL) bit is a volatile bit that is set to “1” by the WREN instruction. WEL needs to be
set to “1” before the device can accept program and erase instructions, otherwise the program and erase instructions
are ignored. WEL automatically clears to “0” when a program or erase operation completes. To ensure that both WIP
and WEL are “0” and the device is ready for the next program or erase operation, it is recommended that WIP be
confirmed to be “0” before checking that WEL is also “0”. If a program or erase instruction is applied to a protected
memory area, the instruction will be ignored and WEL will clear to “0”.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area
(as defined in Table 3) of the device to against the program/erase instruction without hardware protection mode being
set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to
be executed. Those bits define the protected area of the memory to against Page Program (PP/PP3B/PP4B), Sector
Erase (SE/SE3B/SE4B), Block Erase (BE/BE3B/BE4B) and Chip Erase (CE) instructions (only if Block Protect bits
(BP3:BP0) set to 0, the CE instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as default. Which is unprotected.
Status Register
bit7
Reserved
bit6
Reserved
bit5
BP3
(level of
protected
block)
bit4
BP2
(level of
protected
block)
bit3
BP1
(level of
protected
block)
bit2
BP0
(level of
protected
block)
Reserved
Reserved
(note 1)
(note 1)
(note 1)
(note 1)
Reserved
Reserved
Non-volatile
bit
Non-volatile
bit
Non-volatile
bit
Non-volatile
bit
bit1
bit0
WEL
WIP
(write enable
(write in
latch)
progress bit)
1=write
1=write
enable
operation
0=not write 0=not in write
enable
operation
volatile bit
volatile bit
Note 1: see the Table 3 "Protected Area Size".
P/N: PM2504
Downloaded from Arrow.com.
19
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
9-2. Configuration Register
The Configuration Register is able to change the default status of Flash memory. Flash memory will be configured
after the CR bit is set.
ODS bit
The output driver strength (ODS2, ODS1, ODS0) bits are volatile bits, which indicate the output driver level (as
defined in "Output Driver Strength Table") of the device. The Output Driver Strength is defaulted as 30 Ohms when
delivered from factory. To write the ODS bits requires the Write Status Register (WRSR) instruction to be executed.
TB bit
The Top/Bottom (TB) bit is a non-volatile bit. The Top/Bottom (TB) bit is used to configure the Block Protect area by
BP bit (BP3, BP2, BP1, BP0), starting from TOP or Bottom of the memory array. The TB bit is defaulted as “0”, which
means Top area protect. When it is set as “1”, the protect area will change to Bottom area of the memory device. To
write the TB bits requires the Write Status Register (WRSR) instruction to be executed.
PBE bit
The Preamble Bit Enable (PBE) bit is a volatile bit. It is used to enable or disable the preamble bit data pattern
output on dummy cycles. The PBE bit is defaulted as “0”, which means preamble bit is disabled. When it is set as “1”,
the preamble bit will be enabled, and inputted into dummy cycles. To write the PBE bits requires the Write Status
Register (WRSR) instruction to be executed.
Configuration Register
bit7
bit6
bit5
Reserved
Reserved
Reserved
x
x
x
x
x
x
bit4
bit3
bit2
bit1
bit0
PBE
TB
ODS 2
ODS 1
ODS 0
(Preamble bit (top/bottom (output driver (output driver (output driver
Enable)
selected)
strength)
strength)
strength)
0=Top area
0=Disable
protect
1=Bottom
(Note 1)
(Note 1)
(Note 1)
1=Enable
area protect
(Default=0)
volatile bit
OTP
volatile bit
volatile bit
volatile bit
Note 1: see "Output Driver Strength Table"
Output Driver Strength Table
ODS2
0
0
0
0
1
1
1
1
P/N: PM2504
Downloaded from Arrow.com.
ODS1
0
0
1
1
0
0
1
1
ODS0
0
1
0
1
0
1
0
1
Description
146 Ohms
76 Ohms
52 Ohms
41 Ohms
34 Ohms
30 Ohms
26 Ohms
24 Ohms (Default)
20
Note
Impedance at VCC/2
(Typical)
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
9-3. Configuration Register 2
Address
00000000h
00000200h
Bit
Bit 7-2
Symbol
x
Description
Reserved
Bit 1
DOPI (3)
DTR OPI Enable
Bit 0
SOPI (3)
STR OPI Enable
Bit 7-4
Bit 3-2
x
x
Bit 1
DOS
Bit 0
00000300h
00000400h
00000500h
00000800h/
04000800h(5)
x
Bit 2-0
DC
Bit 7-2
x
Bit 1-0
ECS
Bit 7
x
Bit 6-5
CRC CYC
Downloaded from Arrow.com.
Reserved
Dummy cycle
Reserved
ECS# pin goes low
define
Reserved
CRC chunk size
configuration
CRCBEN CRC# output enable
Bit 3-1
x
Bit 0
PPTSEL
Bit 7
ECCFAVLD
Bit 6-4
ECCFS
Bit 3-0 ECCCNT(1)
P/N: PM2504
DQS on STR mode
DQSPRC DTR DQS pre-cycle
Bit 7-3
Bit 4
Reserved
Reserved
Reserved
Preamable pattern
selection
ECC fail address valid
indicator
ECC fail status
ECC failure chunk
counter
Define
Reserved
00= SPI
01= STR OPI enable
10= DTR OPI enable
11= inhibit
Reserved
Reserved
0= Disable
1= Enable
0= 0 cycle
1= 1 cycle
Reserved
Refer to "Dummy Cycle and
Frequency Table (MHz)"
Reserved
00= 2 bit error or double programmed
01= 1 or 2 bit error or double
programmed
10= 2 bit error only
11= 1 or 2 bit error
00= 16Byte
01= 32Byte
10= 64Byte
11= 128Byte
0= CRC# output Disable
1= CRC# output Enable
Reserved
refer to "9-3-2. Preamable Pattern
Select Bit Table"
0= ECC failure address invalid (no
fail address recorded)
1= ECC failure address valid (there's
fail address recorded)
000= None
xx1= 1 bit corrected
x1x= 2 bits deteced
1xx= Double programmed page
detected
21
Default
x
0
0
x
x
0
0
x
000
x
Type
x
Volatile
Bit
Volatile
Bit
x
x
Volatile
Bit
Volatile
Bit
x
Volatile
Bit
x
00
Volatile
Bit
x
x
00
Volatile
Bit
0
x
0
Volatile
Bit
x
Volatile
Bit
0
Volatile
Bit
000
Volatile
Bit
0000
Volatile
Bit
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
Address
00000C00h(2)/
04000C00h(5)
Bit
Symbol
Bit 7-4
ECCFA
Bit 3-0
x
(2)
00000D00h /
Bit 7-0
04000D00h(5)
(2)
00000E00h /
Bit 7-0
04000E00h(5)
00000F00h(2)/
04000F00h(5)
40000000h
80000000h
ECCFA
ECCFA
Bit 7-2
x
Bit 1-0
ECCFA
Bit 7-4
x
Bit 3
CRCEN#
Bit 2
x
(3,4)
Bit 1
DEFDOPI#
Bit 0
DEFSOPI# (3,4)
Bit 7-5
x
Bit 4
CRCERR
Bit 3-0
x
Description
ECC failure chunk
address
Define
ECC 1st failure chunk address
(A7:A4)
Reserved
Reserved
ECC failure chunk
address
ECC failure chunk
address
ECC 1st failure chunk address
(A15:A8)
ECC 1st failure chunk address
(A23:A16)
Reserved
Reserved
x
ECC failure chunk
address
ECC 1st failure chunk address
(A25:A24)
x
Reserved
Reserved
x
x
1
OTP
x
x
1
OTP
1
OTP
x
x
Volatile
Bit
x
0= Parity check Enable
1= Parity check Disable
Reserved
Reserved
Enable DOPI after
00= inhibit
Power on or reset
01= default DTR OPI mode
10= default STR OPI mode
Enable SOPI after
11= default SPI mode
Power on or reset
Reserved
Reserved
CMB# or Parity checked 0= CMB# or Parity check pass
fail
1= CMB# or Parity check fail
Reserved
Reserved
Enable Parity checking
Default
x
x
x
x
0
x
Type
Volatile
Bit
Volatile
Bit
Volatile
Bit
Volatile
Bit
Volatile
Bit
Volatile
Bit
Notes:
1. ECC failure chunk counter (00000800h bit[3:0]) stops counting once reach maximum value 15. The counting number increases
if user reads the failure chunk multipe times.
2. ECC fail address only records first fail chunk fail address. For both 1bit and 2bit fail. ECCFA is valid only if ECCFAVLD value is 1.
3. The default status of DOPI and SOPI reflect the DEFDOPI# and DEFSOPI# setting. For example, if DEFDOPI#/DEFSOPI#
are 01, DOPI and SOPI value will change to 10 after next Power on or reset and default status of the device will be DTR OPI.
4. The default DEFDOPI# status depends on the device model selection.
5. ECC status have seprate bits for upper/lower 512Mb memory. User could get lower 512Mb ECC status via adress 00xxxxxxh
(A26=0) while get upper 512Mb status via 04xxxxxxh (A26=1).
P/N: PM2504
Downloaded from Arrow.com.
22
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
9-3-1. Dummy Cycle and Frequency Table (MHz)
DC [2:0]
000(Default)
001
010
011
100
101
110
111
Numbers of Dummy
Cycle
20
18
16
14
12
10
8
6
9-3-2. Preamable Pattern Select Bit Table
All SIOs (Except SIO3)
Bit 0= 0
0011 0100 1001 1010
Bit 0= 1
0101 0101 0101 0101
P/N: PM2504
Downloaded from Arrow.com.
23
Octa I/O STR (MHz)
Octa I/O DTR (MHz)
166
166
166
133
104
104
84
66
166
166
166
133
104
104
84
66
SIO3
0011 0101 0001 0100
0101 0101 0101 0101
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
9-4. Security Register
The definition of the Security Register bits is as below:
Erase Fail bit. The Erase Fail bit is a status flag, which shows the status of last Erase operation. It will be set to
"1", if the erase operation fails or the erase region is protected. It will be set to "0", if the last operation is successful.
Please note that it will not interrupt or stop any operation in the flash memory.
Program Fail bit. The Program Fail bit is a status flag, which shows the status of last Program operation. It will be
set to "1", if the program operation fails or the program region is protected. It will be set to "0", if the last operation is
successful. Please note that it will not interrupt or stop any operation in the flash memory.
Erase Suspend bit. Erase Suspend Bit (ESB) indicates the status of Erase Suspend operation. Users may use
ESB to identify the state of flash memory. After the flash memory is suspended by Erase Suspend command, ESB
is set to "1". ESB is cleared to "0" after erase operation resumes.
Program Suspend bit. Program Suspend Bit (PSB) indicates the status of Program Suspend operation. Users may
use PSB to identify the state of flash memory. After the flash memory is suspended by Program Suspend command,
PSB is set to "1". PSB is cleared to "0" after program operation resumes.
Secured OTP Indicator bit. The Secured OTP indicator bit shows the secured OTP area is locked by factory or
not. When it is "0", it indicates non-factory lock; "1" indicates factory-lock.
Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for
customer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 8K-bit Secured
OTP area cannot be updated any more. While it is in 8K-bit secured OTP mode, main array access is not allowed.
Table 5. Security Register Definition
bit7
bit6
bit5
bit4
WPSEL
E_FAIL
P_FAIL
Reserved
0=normal
WP mode
1=individual
mode
(default=0)
0=normal
Erase
succeed
1=indicate
Erase failed
(default=0)
0=normal
Program
succeed
1=indicate
Program
failed
(default=0)
-
0=Erase
is not
suspended
1= Erase
suspended
(default=0)
Non-volatile
bit (OTP)
Volatile bit
Volatile bit
-
Volatile bit
P/N: PM2504
Downloaded from Arrow.com.
bit3
bit2
ESB
PSB
(Erase
(Program
Suspend bit) Suspend bit)
24
bit1
bit0
LDSO
Secured OTP
(indicate if
indicator bit
lock-down)
0 = not lock0=Program
down
0 = nonis not
1 = lock-down
factory
suspended
(cannot
lock
1= Program
program/
1 = factory
suspended
erase
lock
(default=0)
OTP)
Non-volatile
Non-volatile
Volatile bit
bit
bit (OTP)
(Read only)
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
10. COMMAND DESCRIPTION
10-1. Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP/
PP3B/PP4B, SE/SE3B/SE4B, BE/BE3B/BE4B, CE, WRSR, WRCR2, SBL, WRFBR, ESFBR, WRSCUR, WRLR,
WSPB and ESSPB which are intended to change the device content WEL bit should be set every time after the
WREN instruction setting the WEL bit.
The sequence of issuing WREN instruction is: CS# goes low→sending WREN instruction code→ CS# goes high.
Figure 5. Write Enable (WREN) Sequence (SPI Mode)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
06h
High-Z
SO
Figure 6. Write Enable (WREN) Sequence (STR-OPI Mode)
CS#
SCLK
SIO[7:0]
06h
F9h
Figure 7. Write Enable (WREN) Sequence (DTR-OPI Mode)
CS#
SCLK
SIO[7:0]
P/N: PM2504
Downloaded from Arrow.com.
06h
25
F9h
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
10-2. Write Disable (WRDI)
The Write Disable (WRDI) instruction is to reset Write Enable Latch (WEL) bit. The sequence of issuing WRDI
instruction is: CS# goes low→sending WRDI instruction code→CS# goes high.
The WEL bit is reset by following situations:
- Power-up
- Reset# pin driven low
- WRDI command completion
- WRSR/WRCR/WRCR2 command completion
- PP/PP3B/PP4B command completion
- SE/SE3B/SE4B/BE/BE3B/BE4B/CE command completion
- SBL command completion
- PGM/ERS Suspend command completion
- Softreset command completion
- WRSCUR command completion
- WRFBR/ESFBR command completion
- WRLR/WSPB/ESSPB command completion
- GBLK/GBULK command completion
Figure 8. Write Disable (WRDI) Sequence (SPI Mode)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
04h
High-Z
SO
Figure 9. Write Disable (WRDI) Sequence (STR-OPI Mode)
CS#
SCLK
SIO[7:0]
04h
FBh
Figure 10. Write Disable (WRDI) Sequence (DTR-OPI Mode)
CS#
SCLK
SIO[7:0]
P/N: PM2504
Downloaded from Arrow.com.
04h
26
FBh
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
10-3. Read Identification (RDID)
The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Macronix
Manufacturer ID and Device ID are listed as Table 6 ID Definitions.
The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code→24-bits ID data out
on SO→ to end RDID operation can drive CS# to high at any time during data out.
While Program/Erase operation is in progress, it will not decode the RDID instruction, therefore there's no effect on
the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby
stage.
Table 6. ID Definitions
RDID
9Fh
Manufacturer ID
Memory type
Memory density
C2
80
3B
Figure 11. Read Identification (RDID) Sequence (SPI mode)
CS#
0
1
2
3
4
5
6
7
8
9 10
13 14 15 16 17 18
28 29 30 31
SCLK
Command
SI
9Fh
Manufacturer Identification
High-Z
SO
7
6
5
2
1
MSB
Device Identification
0 15 14 13
3
2
1
0
MSB
Figure 12. Read Identification (RDID) Sequence (STR-OPI Mode)
CS#
SCLK
Pre-drive
SIO[7:0]
9Fh
60h
00
00
00
MID
00
Address
Type
Density
Dummy
Figure 13. Read Identification (RDID) Sequence (DTR-OPI Mode)
CS#
SCLK
DQS
Pre-drive
SIO[7:0]
9Fh
60h
00
00
00
MID
00
Address
P/N: PM2504
Downloaded from Arrow.com.
Type
Density
Dummy
27
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
10-4. Read Status Register (RDSR)
The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even
in program/erase/write status register condition). It is recommended to check the Write in Progress (WIP) bit before
sending a new instruction when a program, erase, or write status register operation is in progress.
The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register data
out on SO.
Figure 14. Read Status Register (RDSR) Sequence (SPI Mode)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
command
05h
SI
Status Register Out
High-Z
SO
7
6
5
4
3
2
1
Status Register Out
0
7
6
5
4
3
2
1
0
7
MSB
MSB
Figure 15. Read Status Register (RDSR) Sequence (STR-OPI Mode)
CS#
SCLK
Pre-drive
SIO[7:0]
05h
FAh
00
00
00
SR
00
Address
SR
Dummy
Figure 16. Read Status Register (RDSR) Sequence (DTR-OPI Mode)
CS#
SCLK
DQS
Pre-drive
SIO[7:0]
05h
FAh
00
00
00
00
SR
Address
P/N: PM2504
Downloaded from Arrow.com.
SR
Dummy
28
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
For user to check if Program/Erase operation is finished or not, RDSR instruction flow are shown as follows:
Figure 17. Program/Erase flow with read array data
start
WREN command
RDSR command*
WEL=1?
No
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
WIP=0?
No
Yes
RDSR command
Read WEL=0, BP[3:0]
Read array data
(same address of PGM/ERS)
No
Verify OK?
Yes
Program/erase successfully
Program/erase
another block?
Program/erase fail
Yes
* Issue RDSR to check BP[3:0].
No
Program/erase completed
P/N: PM2504
Downloaded from Arrow.com.
29
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
Figure 18. Program/Erase flow without read array data (read P_FAIL/E_FAIL flag)
start
WREN command
RDSR command*
WEL=1?
No
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
WIP=0?
No
Yes
RDSR command
Read WEL=0, BP[3:0]
RDSCUR command
Yes
P_FAIL/E_FAIL =1 ?
No
Program/erase fail
Program/erase successfully
Program/erase
another block?
No
Yes
* Issue RDSR to check BP[3:0].
Program/erase completed
P/N: PM2504
Downloaded from Arrow.com.
30
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
10-5. Read Configuration Register (RDCR)
The RDCR instruction is for reading Configuration Register Bits. The Read Configuration Register can be read at
any time (even in program/erase/write configuration register condition).
The sequence of issuing RDCR instruction is: CS# goes low→ sending RDCR instruction code→ Configuration
Register data out on SO.
Figure 19. Read Configuration Register (RDCR) Sequence (SPI Mode)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
command
15h
SI
Configuration register Out
High-Z
SO
7
6
5
4
3
2
1
0
Configuration register Out
7
6
5
4
3
2
1
0
7
MSB
MSB
Figure 20. Read Configuration Register (RDCR) (STR-OPI Mode)
CS#
SCLK
Pre-drive
SIO[7:0]
15h
00
EAh
00
00
01
CR
Address
CR
Dummy
Figure 21. Read Configuration Register (RDCR) (DTR-OPI Mode)
CS#
SCLK
DQS
Pre-drive
SIO[7:0]
15h
EAh
00
00
00
01
CR
Address
P/N: PM2504
Downloaded from Arrow.com.
CR
Dummy
31
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
10-6. Write Status Register (WRSR) / Write Configuration Register (WRCR)
The WRSR instruction is for changing the values of Status Register Bits and Configuration Register Bits. Before
sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write
Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1,
BP0) bits to define the protected area of memory (as shown in "Table 3. Protected Area Sizes"). The WRSR has no
effect on bit1(WEL) and bit0 (WIP) of the status register.
In SPI, CS# must go high exactly at the 8 bits or 16 bits data boundary; In DOPI, CS# must go high while clock is
low; otherwise, the instruction will be rejected and not executed. The self-timed Write Status Register cycle time (tW)
is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during
the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status
Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset.
Figure 22. Write Status Register (WRSR) Sequence (SPI Mode)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
command
SI
SO
01h
High-Z
Status
Register In
7
6
5
4
3
2
Configuration
Register In
1
0 15 14 13 12 11 10 9
8
MSB
Note : The CS# must go high exactly at 8 bits or 16 bits data boundary to completed the write register command.
P/N: PM2504
Downloaded from Arrow.com.
32
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
Figure 23. Write Status Register (WRSR) Sequence (STR-OPI Mode)
CS#
SCLK
SIO[7:0]
01h
FEh
00
00
00
00
SR
Figure 24. Write Status Register (WRSR) Sequence (DTR-OPI Mode)
CS#
SCLK
SIO[7:0]
01h
00
FEh
00
00
SR
00
Note: CS# must go high while SCLK is low.
Figure 25. Write Configuration Register (WRCR) Sequence (STR-OPI Mode)
CS#
SCLK
SIO[7:0]
01h
FEh
00
00
00
01
CR
Figure 26. Write Configuration Register (WRCR) Sequence (DTR-OPI Mode)
CS#
SCLK
SIO[7:0]
01h
FEh
00
00
00
01
CR
Note: CS# must go high while SCLK is low.
P/N: PM2504
Downloaded from Arrow.com.
33
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
Figure 27. WRSR flow
start
WREN command
RDSR command
WEL=1?
No
Yes
WRSR command
Write status register data
RDSR command
WIP=0?
No
Yes
RDSR command
Read WEL=0, BP[3:0]
Verify OK?
No
Yes
WRSR successfully
P/N: PM2504
Downloaded from Arrow.com.
WRSR fail
34
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
10-7. Read Configuration Register 2 (RDCR2)
The RDCR2 instruction is for reading Configuration Register 2. Except CRCERR bit, the Read Configuration
Register 2 command would be rejected while Internal write operation is in progress (WIP=1).
The sequence of issuing RDCR2 instruction is: CS# goes low→ sending RDCR2 instruction code→ Sending 4 byte
address → Configuration Register 2 data out on SO.
Figure 28. Read Configuration Register 2 (RDCR2) Sequence (SPI Mode)
CS#
SCLK
command
Address *
31 30 29
71h
SI
3
2
1
0
MSB
CR2
High-Z
SO
7
6
5
4
3
CR2
2
1
0
7
MSB
Note: * See "9-3. Configuration Register 2" for defining address .
Figure 29. Read Configuration Register 2 (RDCR2) Sequence (STR-OPI Mode)
CS#
SCLK
Pre-drive
SIO[7:0]
71h
8Eh
A[31:24] A[23:16]
A[15:8]
CR2
A[7:0]
Address *
CR2
Dummy
Note: * See "9-3. Configuration Register 2" for defining address .
Figure 30. Read Configuration Register 2 (RDCR2) (DTR-OPI Mode)
CS#
SCLK
DQS
Pre-drive
SIO[7:0]
71h
CR2
8Eh A[31:24] A[23:16] A[15:8] A[7:0]
Address *
CR2
Dummy
Note: * See "9-3. Configuration Register 2" for defining address .
P/N: PM2504
Downloaded from Arrow.com.
35
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
10-8. Write Configuration Register 2 (WRCR2)
The WRCR2 instruction is for changing the values of Configuration Register 2. Before sending WRCR2 instruction,
the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in
advance.
In SPI, CS# must go high exactly at the 8 bits data boundary; In DOPI, CS# must go high while clock is low;
otherwise, the instruction will be rejected and not executed, and the Write Enable Latch (WEL) bit is reset.
Figure 31. Write Configuration Register 2 (WRCR2) Sequence (SPI Mode)
CS#
SCLK
Command
31 30 29
72h
SI
CR2
Address *
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
Note 1: * See "9-3. Configuration Register 2" for defining address .
Figure 32. Write Configuration Register 2 (WRCR2) Sequence (STR-OPI Mode)
CS#
SCLK
SIO[7:0]
72h
8Dh
A[31:24]
A[23:16]
A[15:8]
A[7:0]
CR2
Address *
Note 1: * See "9-3. Configuration Register 2" for defining address .
Figure 33. Write Configuration Register 2 (WRCR2) Sequence (DTR-OPI Mode)
CS#
SCLK
SIO[7:0]
72h
8Dh
A[31:24] A[23:16] A[15:8]
A[7:0]
CR2
Address *
Note 1 : * See "9-3. Configuration Register 2" for defining address.
Note 2 : CS# must go high while SCLK is low
P/N: PM2504
Downloaded from Arrow.com.
36
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
10-9. Read Security Register (RDSCUR)
The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read
at any time (even in program/erase/write status register/write security register condition) and continuously.
The sequence of issuing RDSCUR instruction is : CS# goes low→sending RDSCUR instruction→Security Register
data out on SO→ CS# goes high.
Figure 34. Read Security Register (RDSCUR) Sequence (SPI Mode)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
command
2Bh
SI
Security register Out
High-Z
SO
7
6
5
4
3
2
1
Security register Out
0
7
6
5
4
3
2
1
0
7
MSB
MSB
Figure 35. Read Security Register (RDSCUR) Sequence (STR-OPI Mode)
CS#
SCLK
Pre-drive
SIO[7:0]
2Bh
D4h
00
00
00
Security
Register
00
Address
Security
Register
Dummy
Figure 36. Read Security Register (RDSCUR) Sequence (DTR-OPI Mode)
CS#
SCLK
DQS
Pre-drive
SIO[7:0]
2Bh
D4h
00
00
00
Security
Register
00
Address
P/N: PM2504
Downloaded from Arrow.com.
Security
Register
Dummy
37
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
10-10. Write Security Register (WRSCUR)
The WRSCUR instruction sets the LDSO bit of the Security Register. The WREN (Write Enable) instruction is
required before issuing WRSCUR instruction. The WRSCUR instruction may change the values of bit1 (LDSO bit)
for customer to lock-down the 8K-bit Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area
cannot be updated any more.
The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high.
The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
Figure 37. Write Security Register (WRSCUR) Sequence (SPI Mode)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
2Fh
High-Z
SO
Figure 38. Write Security Register (WRSCUR) Sequence (STR-OPI Mode)
CS#
SCLK
SIO[7:0]
2Fh
D0h
Figure 39. Write Security Register (WRSCUR) Sequence (DTR-OPI Mode)
CS#
SCLK
SIO[7:0]
P/N: PM2504
Downloaded from Arrow.com.
2Fh
38
D0h
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
10-11. Read Data Bytes (READ/READ3B/READ4B)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on
the falling edge of SCLK at a maximum frequency fR. The address is automatically increased to the next higher
address after each byte data is shifted out, so the whole memory can be read out at a single READ/READ3B/
READ4B instruction. The address counter rolls over to 0 when the highest address has been reached.
The sequence of issuing READ/READ3B/READ4B instruction is: CS# goes low→sending READ/READ3B/READ4B
instruction code→ 3-byte or 4-byte address on SI→ data out on SO→to end READ/READ3B/READ4B operation
can use CS# to high at any time during data out.
Figure 40. Read Data Bytes (READ/READ3B/READ4B) Sequence (SPI Mode only)
CS#
SCLK
Command
SI
03h/13h (Note)
24/32-Bit Address
(Note)
31 30 29
3
2
1
0
MSB
SO
Data Out 1
High-Z
7
6
5
4
3
2
Data Out 2
1
0
7
MSB
Note: The number of address cycles are based on different address mode. In 3-Byte command operation, it is 24-bit.
In 4-Byte command operation, it is 32-bit.
P/N: PM2504
Downloaded from Arrow.com.
39
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
10-12. Read Data Bytes at Higher Speed (FAST_READ/FAST_READ3B/FAST_READ4B)
The FAST_READ/FAST_READ3B/FAST_READ4B instruction is for quickly reading data out. The address is latched
on rising edge of SCLK, and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC.
The address is automatically increased to the next higher address after each byte data is shifted out, so the whole
memory can be read out at a single FAST_READ/FAST_READ3B/FAST_READ4B instruction. The address counter
rolls over to 0 when the highest address has been reached.
The sequence of issuing FAST_READ/FAST_READ3B/FAST_READ4B instruction is: CS# goes low→ sending
FAST_READ/FAST_READ3B/FAST_READ4B instruction code→ 3-byte or 4-byte address on SI→ 8 dummy cycles
→ data out on SO→ to end FAST_READ/FAST_READ3B/FAST_READ4B operation can use CS# to high at any
time during data out.
While Program/Erase/Write Status Register cycle is in progress, FAST_READ/FAST_READ3B/FAST_READ4B
instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle.
Figure 41. Read at Higher Speed (FAST_READ/FAST_READ3B/FAST_READ4B) Sequence (SPI Mode only)
CS#
SCLK
Command
SI
24/32-Bit Address
(Note)
0Bh/0Ch (Note)
31 30 29
3
2
1
0
High-Z
SO
CS#
SCLK
Dummy Cycle
SI
7
6
5
4
3
2
1
0
DATA OUT 2
DATA OUT 1
SO
7
6
5
4
3
2
1
0
7
MSB
MSB
6
5
4
3
2
1
0
7
MSB
Note: The number of address cycles are based on different address mode. In 3-Byte command operation, it is 24-bit.
In 4-Byte command operation, it is 32-bit.
P/N: PM2504
Downloaded from Arrow.com.
40
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
10-13. OCTA Read Mode (8READ)
The 8READ instruction enable Octa throughput of Serial NOR Flash in read mode. An OPI Enable bit of
Configuration Register 2 must be set to "1" before sending the STR Octa READ instruction.
While Program/Erase/Write Status Register cycle is in progress, 8READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
Figure 42. OCTA Read Mode Sequence (STR-OPI Mode)
≈
≈
CS#
SCLK
ECh
13h
A[31:24]
A[23:16]
A[15:8]
≈
Pre-drive
SIO[7:0]
A[7:0]
Address
P/N: PM2504
Downloaded from Arrow.com.
D0
D1
D2
D3
Dummy
41
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
10-14. OCTA DTR Read Mode (8DTRD)
The 8DTRD instruction enable DTR Octa throughput of Serial NOR Flash in read mode. An DOPI Enable bit of
Configuration Register 2 must be set to "1" before sending the DTR Octa READ instruction.
While Program/Erase/Write Status Register cycle is in progress, 8DTRD instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
In DTR Octa READ mode, the starting address must be even byte (A0=0).
Figure 43. OCTA Read Mode Sequence (DTR-OPI Mode)
≈
CS#
≈
SCLK
EEh
≈
SIO[7:0]
≈
DQS
11h A[31:24]A[23:16] A[15:8] A[7:0]
D1
D0
D3
D2
Dummy
Address
word unit word unit
Figure 44. OCTA Read Mode Sequence (DTR-OPI Mode) with DQS pre-cycle enabled (CR2 DQSPRC=1)
≈
CS#
≈
SCLK
EEh
≈
SIO[7:0]
≈
DQS
11h A[31:24]A[23:16] A[15:8] A[7:0]
D1
D0
D3
D2
Dummy
Address
word unit word unit
P/N: PM2504
Downloaded from Arrow.com.
42
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
10-15. Preamble Bit
The Preamble Bit data pattern supports system/memory controller to determine the valid windows of data output
more easily and improve data capture reliability while the flash memory is running in high frequency.
The preamble bit is designed as a 16-bit data pattern, which can be enabled or disabled by setting the bit4 of
Configuration register (Preamble bit Enable bit). Once CR is set, the preamble bit is inputted into dummy
cycles. Two different patterns are selectable by setting CR PSB (Pattern Select Bit), and please refer to "9-3.
Configuration Register 2" for details.
Once Preamble Bit feature is enabled, the preamble bit pattern will be output after a pre-driven signal. When the
device is under OPI mode, all SIO pins except SIO3 will output the same learning pattern. The signal on SIO3 will
be different from other I/O pins in case PSB=0.
In OPI, when dummy cycle number reaches 20, the complete 16 bits will start to output right after the pre-driven
signal. When dummy cycle number is not sufficient of 16 cycles, the rest of the preamble bits will be cut off.
In DOPI, when dummy cycles number reaches 12, the complete 16 bits will start to output right after the pre-driven
signal.
Figure 45. Preamble Bit data pattern Output Sequence (STR-OPI Mode)
CS#
SCLK
Preamble Bits
Pre-drive
SIO[7:0]
ECh
13h
A[31:24] A[23:16]
A[15:8]
A[7:0]
P0
Address
P1
P2
P3
D[7:0]
D[7:0]
Dummy
Note: 8 dummy cycle example.
Figure 46. Preamble Bit data pattern Output Sequence (DTR-OPI Mode)
CS#
SCLK
DQS
Preamble Bits
Pre-drive
SIO[7:0]
EEh 11h
A
A
A
[31:24] [23:16] [15:8]
A
[7:0]
P0
Address
P1
P2
P3
D[7:0] D[7:0] D[7:0] D[7:0]
Dummy
Note: 6 dummy cycle example.
P/N: PM2504
Downloaded from Arrow.com.
43
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
10-16. Burst Read
To set the Burst length, following command operation is required to issue command: “C0h” in the first Byte, following
clock defining wrap around register value.
Their definitions are as the following table:
Data
Wrap Around
Wrap Depth
00h
Reserved
Reserved
01h
Yes
16-byte
02h
Yes
32-byte
03h
Yes
64-byte
1xh
No
X
The wrap around unit is defined within the 256Byte page, with random initial address. It is defined as “wrap-around
mode disable” for the default state of the device. To exit wrap around, it is required to issue another “C0h” command
in which data=‘1xh”. Otherwise, wrap around status will be retained until power down or reset command. To change
wrap around depth, it is requried to issue another “C0h” command in which data=“0xh”. The device is default without
Burst read.
Figure 47. Set Burst Length (SPI Mode)
CS#
0
1
2
3
4
5
6
7
8
9
D7
D6
10
11
12
13
14
15
SCLK
SIO
C0h
D5
D4
D3
D2
D1
D0
Figure 48. Set Burst Length (STR-OPI Mode)
CS#
SCLK
SIO[7:0]
P/N: PM2504
Downloaded from Arrow.com.
C0h
3Fh
00
00
44
00
00
SBL
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
10-17. Fast Boot
The Fast Boot Feature provides the ability to automatically execute read operation after power on cycle or reset
without any read instruction.
A Fast Boot Register is provided on this device. It can enable the Fast Boot function and also define the number of
delay cycles and start address (where boot code being transferred). Instruction WRFBR (write fast boot register)
and ESFBR (erase fast boot register) can be used for the status configuration or alternation of the Fast Boot
Register bit. RDFBR (read fast boot register) can be used to verify the program state of the Fast Boot Register. The
default number of delay cycles is 21 cycles in OPI/DOPI; while the number of delay cycles is 13 in SPI and there is
a 16bytes boundary address for the start of boot code access.
When CS# starts to go low, data begins to output from default address after the delay cycles. After CS# returns to
go high, the device will go back to standard SPI/OPI/DOPI mode and user can start to input command. In the fast
boot data out process from CS# goes low to CS# goes high, a minimum of one byte must be output.
Once Fast Boot feature has been enabled, the device will automatically start a read operation after power on cycle,
reset command, or hardware reset operation.
Fast Boot Register (FBR)
Bits
Description
FBSA (FastBoot Start
Address)
31 to 4
3
Reserved
2 to 1
FBSD (FastBoot Start
Delay Cycle)
0
FBE (FastBoot Enable)
Bit Status
Default State
16 bytes boundary address for the start of boot
FFFFFFF
code access.
1
00: 11 delay cycles
01: 15 delay cycles
10: 17 delay cycles
11: 21 delay cycles
0=FastBoot is enabled.
1=FastBoot is not enabled.
Type
NonVolatile
NonVolatile
11
NonVolatile
1
NonVolatile
Figure 49. Fast Boot Sequence (SPI Mode)
CS#
0
-
-
-
-
-
-
n
n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11n+12n+13n+14n+15
SCLK
Delay Cycles
SI
Don’t care or High Impedance
Data Out 1
SO
High Impedance
7
6
5
4
MSB
3
2
Data Out 2
1
0
7
MSB
6
5
4
3
2
1
0
7
MSB
Note: The delay cycle is always 13 in SPI mode.
P/N: PM2504
Downloaded from Arrow.com.
45
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
Figure 50. Fast Boot Sequence (STR-OPI Mode)
≈
CS#
1
≈
0
SCLK
n-1
n
n+1
n+2
n+3
Pre-drive
≈
SIO[7:0]
D0
D1
D2
D3
Delay Cycles
Note:
If FBSD = 11, delay cycles is 21 and n is 20.
If FBSD = 10, delay cycles is 17 and n is 16.
If FBSD = 01, delay cycles is 15 and n is 14.
If FBSD = 00, delay cycles is 11 and n is 10.
0
SCLK
DQS
1
n-2
n-1
n
n+1
≈
CS#
≈ ≈
Figure 51. Fast Boot Sequence (DTR-OPI Mode)
≈
Pre-drive
SIO[7:0]
D1
D0
D3
D2
Delay Cycles
Note:
If FBSD = 11, delay cycles is 21 and n is 21.
If FBSD = 10, delay cycles is 17 and n is 17.
If FBSD = 01, delay cycles is 15 and n is 15.
If FBSD = 00, delay cycles is 11 and n is 11.
P/N: PM2504
Downloaded from Arrow.com.
46
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
Figure 52. Read Fast Boot Register (RDFBR) Sequence
CS#
0
1
2
3
4
5
6
7
8
9 10
37 38 39 40 41
SCLK
Command
SI
16h
Data Out 1
High-Z
SO
7
6
5
Data Out 2
26 25 24 7
6
MSB
MSB
Figure 53. Read Fast Boot Register (RDFBR) Sequence (STR-OPI Mode)
CS#
SCLK
Pre-drive
SIO[7:0]
16h
E9h
00
00
00
00
FBR1
Address
FBR2
Dummy
Figure 54. Read Fast Boot Register (RDFBR) Sequence (DTR-OPI Mode)
CS#
SCLK
DQS
Pre-drive
SIO[7:0]
16h
E9h
00
00
00
00
FBR1
Address
P/N: PM2504
Downloaded from Arrow.com.
FBR2
Dummy
47
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
Figure 55. Write Fast Boot Register (WRFBR) Sequence
CS#
0
1
2
3
4
5
6
7
8
37 38 39
9 10
SCLK
Command
SI
Fast Boot Register
17h
7
6
26 25 24
5
MSB
SO
High-Z
Figure 56. Write Fast Boot Register (WRFBR) Sequence (STR-OPI Mode)
SCLK
SIO[7:0]
17h
E8h
00
00
00
00
FBR1
≈ ≈ ≈
≈
CS#
FBR4
Figure 57. Write Fast Boot Register (WRFBR) Sequence (DTR-OPI Mode)
CS#
SCLK
SIO[7:0]
P/N: PM2504
Downloaded from Arrow.com.
17h
E8h
00
00
00
48
00
FBR1 FBR2 FBR3 FBR4
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
Figure 58. Erase Fast Boot Register (ESFBR) Sequence
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
18h
High-Z
SO
Figure 59. Erase Fast Boot Register (ESFBR) Sequence (STR-OPI Mode)
CS#
SCLK
SIO[7:0]
18h
E7h
Figure 60. Erase Fast Boot Register (ESFBR) Sequence (DTR-OPI Mode)
CS#
SCLK
SIO[7:0]
P/N: PM2504
Downloaded from Arrow.com.
18h
49
E7h
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
10-18. Sector Erase (SE/SE3B/SE4B)
The Sector Erase (SE/SE3B/SE4B) instruction is for erasing the data of the chosen sector to be "1". The instruction
is used for any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL)
bit before sending the Sector Erase (SE/SE3B/SE4B). Any address of the sector (Please refer to "5. MEMORY
ORGANIZATION") is a valid address for Sector Erase (SE/SE3B/SE4B) instruction. The CS# must go high exactly
at the byte boundary (the least significant bit of the address byte been latched-in); otherwise, the instruction will be
rejected and not executed.
The sequence of issuing SE/SE3B/SE4B instruction is: CS# goes low→ sending SE/SE3B/SE4B instruction code→
3-byte or 4-byte address → CS# goes high.
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets 1 during the
tSE timing, and clears when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If
the Block is protected by BP bits (Block Protect Mode), the Sector Erase (SE/SE3B/SE4B) instruction will not be
executed on the block.
Figure 61. Sector Erase (SE/SE3B/SE4B) Sequence (SPI Mode)
CS#
SCLK
24/32-Bit Address
(Note)
Command
SI
20h/21h (Note)
31 30
2
1
0
MSB
Note: The number of address cycles are based on different address mode. In 3-Byte command operation, it is 24-bit.
In 4-Byte command operation, it is 32-bit.
Figure 62. Sector Erase (SE) Sequence (STR-OPI Mode)
CS#
SCLK
SIO[7:0]
21h
DEh
A[31:24]
A[23:16]
A[15:8]
A[7:0]
Figure 63. Sector Erase (SE) Sequence (DTR-OPI Mode)
CS#
SCLK
SIO[7:0]
P/N: PM2504
Downloaded from Arrow.com.
21h
A
A
A
DEh [31:24]
[23:16] [15:8]
50
A
[7:0]
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
10-19. Block Erase (BE/BE3B/BE4B)
The Block Erase (BE/BE3B/BE4B) instruction is for erasing the data of the chosen block to be "1". The instruction
is used for 64K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write
Enable Latch (WEL) bit before sending the Block Erase (BE/BE3B/BE4B). Any address of the block (Please refer to
"5. MEMORY ORGANIZATION") is a valid address for Block Erase (BE/BE3B/BE4B) instruction. The CS# must go
high exactly at the byte boundary (the least significant bit of address byte been latched-in); otherwise, the instruction
will be rejected and not executed.
The sequence of issuing BE/BE3B/BE4B instruction is: CS# goes low→ sending BE/BE3B/BE4B instruction code→
3-byte or 4-byte address → CS# goes high.
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets during the tBE
timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the Block
is protected by BP bits (Block Protect Mode), the Block Erase (BE/BE3B/BE4B) instruction will not be executed on
the block.
Figure 64. Block Erase (BE/BE3B/BE4B) Sequence (SPI Mode)
CS#
SCLK
24/32-Bit Address
(Note)
Command
SI
D8h/DCh (Note)
31 30
2
1
0
MSB
Note: The number of address cycles are based on different address mode. In 3-Byte command operation, it is 24-bit.
In 4-Byte command operation, it is 32-bit.
Figure 65. Block Erase (BE) Sequence (STR-OPI Mode)
CS#
SCLK
SIO[7:0]
DCh
23h
A[31:24]
A[23:16]
A[15:8]
A[7:0]
Figure 66. Block Erase (BE) Sequence (DTR-OPI Mode)
CS#
SCLK
SIO[7:0]
P/N: PM2504
Downloaded from Arrow.com.
DCh
23h
A
A
A
[31:24] [23:16] [15:8]
51
A
[7:0]
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
10-20. Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN)
instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS#
must go high exactly at the byte boundary, otherwise the instruction will be rejected and not executed.
The sequence of issuing CE instruction is: CS# goes low→sending CE instruction code→CS# goes high.
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Chip Erase cycle is in progress. The WIP sets during the tCE
timing, and clears when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared.
When the chip is under "Block protect (BP) Mode". The Chip Erase (CE) instruction will not be executed, if one (or
more) sector is protected by BP3-BP0 bits. It will be only executed when BP3-BP0 all set to "0".
Figure 67. Chip Erase (CE) Sequence (SPI Mode)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
60h or C7h
Figure 68. Chip Erase (CE) Sequence (STR-OPI Mode)
CS#
SCLK
SIO[7:0]
60h or C7h 9Fh or 38h
Figure 69. Chip Erase (CE) Sequence (DTR-OPI Mode)
CS#
SCLK
SIO[7:0]
P/N: PM2504
Downloaded from Arrow.com.
60h or
C7h
52
9Fh or
38h
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
10-21. Page Program (PP/PP3B/PP4B)
The Page Program (PP/PP3B/PP4B) instruction is for programming the memory to be "0". A Write Enable (WREN)
instruction must be executed to set the Write Enable Latch (WEL) bit before sending each Page Program (PP/
PP3B/PP4B) command. The device programs only the last 256 data bytes sent to the device. The last address
byte (the 8 least significant address bits, A7-A0) should be set to 0 for 256 bytes page program. If A7-A0 are not all
zero, transmitted data that exceed page length are programmed from the starting address (32-bit address that last
8 bit are all 0) of currently selected page. If the data bytes sent to the device exceeds 256, the last 256 data byte
is programmed at the request page and previous data will be disregarded. If the data bytes sent to the device has
not exceeded 256, the data will be programmed at the request address of the page. There will be no effort on the
other data bytes of the same page. Please refer "12-1. ECC (Error Checking and Correcting)" for Partial program or
double program restriction.
In DTR OPI, the starting address given must be even address (A0=0) and data byte number must be even.
The sequence of issuing PP/PP3B/PP4B instruction is: CS# goes low→ sending PP/PP3B/PP4B instruction code→
3-byte or 4-byte address → at least 1-byte on data in SPI and STR OPI; at least two bytes in DOPI→ CS# goes
high.
The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte
boundary in SPI (the latest eighth bit of data being latched in), CS# must go high while SCLK is low in DOPI,
otherwise the instruction will be rejected and will not be executed.
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Page Program cycle is in progress. The WIP sets during the tPP
timing, and clears when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If
the page is protected by BP bits (Block Protect Mode), the Page Program (PP/PP3B/PP4B) instruction will not be
executed.
Figure 70. Page Program (PP/PP3B/PP4B) Sequence (SPI Mode)
CS#
SCLK
Command
24/32-Bit Address
(Note)
31 30 29
02h/12h (Note)
SI
3
2
Data Byte 1
1
0
7
6
5
4
3
2
0
1
MSB
MSB
CS#
SCLK
Data Byte 2
SI
7
6
MSB
5
4
3
2
Data Byte 3
1
0
7
6
5
4
MSB
3
2
Data Byte 256
1
0
7
6
5
4
3
2
1
0
MSB
Note: The number of address cycles are based on different address mode. In 3-Byte command operation, it is 24-bit.
In 4-Byte command operation, it is 32-bit.
P/N: PM2504
Downloaded from Arrow.com.
53
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
Figure 71. Page Program (PP) Sequence (STR-OPI Mode)
tCHSH
≈
CS#
tSLCH
12h
EDh
A[31:24]
A[23:16]
A[15:8]
A[7:0]
D0
D1
≈≈
SIO[7:0]
≈
SCLK
D254
D255
Figure 72. Page Program (PP) Sequence (DTR-OPI Mode)
tCLSH
tSLCH
SCLK
SIO[7:0]
12h
A
A
A
EDh [31:24]
[23:16] [15:8]
A
[7:0]
D1
D0
word unit
≈ ≈ ≈
≈
CS#
D255
D254
word unit
Note: CS# must go high while SCLK is low.
P/N: PM2504
Downloaded from Arrow.com.
54
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
10-22. Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device to minimum power consumption (the standby
current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction
to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction are
ignored. When CS# goes high, it's only in deep power-down mode not standby mode. It's different from Standby
mode.
The sequence of issuing DP instruction is: CS# goes low→sending DP instruction code→CS# goes high.
Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP)
and Read Electronic Signature (RES) instruction and softreset command. (those instructions allow the ID being
reading out). When Power-down, or software reset command the deep power-down mode automatically stops, and
when power-up, the device automatically is in standby mode. For DP instruction the CS# must go high exactly at the
byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed.
As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode.
Figure 73. Deep Power-down (DP) Sequence (SPI Mode)
CS#
0
1
2
3
4
5
6
tDP
7
SCLK
Command
B9h
SI
Stand-by Mode
Deep Power-down Mode
Figure 74. Deep Power-down (DP) Sequence (STR-OPI Mode)
CS#
tDP
SCLK
SIO[7:0]
B9h
46h
Stand-by Mode Deep Power-down Mode
Figure 75. Deep Power-down (DP) Sequence (DTR-OPI Mode)
CS#
tDP
SCLK
SIO[7:0]
B9h
46h
Stand-by Mode Deep Power-down Mode
P/N: PM2504
Downloaded from Arrow.com.
55
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
10-23. Release from Deep Power-down (RDP)
The Release from Deep Power-down (RDP) instruction is completed by driving Chip Select (CS#) High. When Chip
Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the
Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in
the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES1, and Chip
Select (CS#) must remain High for at least tRES1(max), as specified in Table 15 AC Characteristics. Once in the
Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. The
RDP instruction is only for releasing from Deep Power Down Mode. Reset# pin goes low will release the Flash from
deep power down mode.
Even in Deep power-down mode, the RDP is also allowed to be executed, only except the device is in progress of
program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress.
Figure 76. Release from Deep Power-down (RDP) Sequence (SPI Mode)
CS#
0
1
2
3
4
5
6
tRES1
7
SCLK
Command
SI
SO
ABh
High-Z
Deep Power-down Mode
Stand-by Mode
Figure 77. Release from Deep Power-down (RDP) Sequence (STR-OPI Mode)
CS#
tRES1
SCLK
SIO[7:0]
54h
ABh
Deep Power-down Mode Stand-by Mode
Figure 78. Release from Deep Power-down (RDP) Sequence (DTR-OPI Mode)
CS#
tRES1
SCLK
SIO[7:0]
ABh
54h
Deep Power-down Mode Stand-by Mode
P/N: PM2504
Downloaded from Arrow.com.
56
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
10-24. Enter Secured OTP (ENSO)
The ENSO instruction is for entering the additional 8K-bit secured OTP mode. While device is in 8K-bit secured
OTP mode, main array access is not available. The additional 8K-bit secured OTP is independent from main array
and may be used to store unique serial number for system identifier. After entering the Secured OTP mode, follow
standard read or program procedure to read out the data or update data. The Secured OTP data cannot be updated
again once it is lock-down.
The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP
mode→ CS# goes high.
Please note that after issuing ENSO command user can only access secure OTP region with standard read or
program procedure. Furthermore, once security OTP is lock down, only read related commands are valid.
10-25. Exit Secured OTP (EXSO)
The EXSO instruction is for exiting the additional 8K-bit secured OTP mode.
The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP
mode→ CS# goes high.
P/N: PM2504
Downloaded from Arrow.com.
57
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
10-26. Write Protection Selection (WPSEL)
There are two write protection methods provided on this device, (1) Block Protection (BP) mode or (2) Advanced
Sector Protection mode. The protection modes are mutually exclusive. The WPSEL bit selects which protection
mode is enabled. If WPSEL=0 (factory default), BP mode is enabled and Advanced Sector Protection mode is
disabled. If WPSEL=1, Advanced Sector Protection mode is enabled and BP mode is disabled. The WPSEL
command is used to set WPSEL=1. A WREN command must be executed to set the WEL bit before sending the
WPSEL command. Please note that the WPSEL bit is an OTP bit. Once WPSEL is set to “1”, it cannot be
programmed back to “0”.
When WPSEL = 0: Block Protection (BP) mode,
The memory array is write protected by the BP3~BP0 bits.
When WPSEL =1: Advanced Sector Protection mode,
Blocks are individually protected by their own SPB or DPB. On power-up, all blocks are write protected by the
Dynamic Protection Bits (DPB) by default. The Advanced Sector Protection instructions WRLR, RDLR, WRPASS,
RDPASS, PASSULK, WRSPB, ESSPB, WRDPB, RDDPB, GBLK, and GBULK are activated. The BP3~BP0 bits of
the Status Register are disabled and have no effect.
The sequence of issuing WPSEL instruction is: CS# goes low → send WPSEL instruction to enable the Advanced
Sector Protect mode → CS# goes high.
Write Protection Selection
Start
(Default in BP Mode)
WPSEL=1
Set
WPSEL Bit
Advanced
Sector Protection
Set
Lock Register
WPSEL=0
Block Protection
(BP)
Bit 2 =1
Bit 2 =0
Password
Protection
P/N: PM2504
Downloaded from Arrow.com.
Solid
Protection
58
Dynamic
Protection
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
10-27. Advanced Sector Protection
There are two ways to implement software Advanced Sector Protection on this device. Through these two protection
methods, user can disable or enable the programming or erasing operation to any individual sector or all sectors.
There is a non-volatile (SPB) and volatile (DPB) protection bit related to the single sector in main flash array. Each
of the sectors is protected from programming or erasing operation when the bit is set.
The figure below helps describing an overview of these methods. The device is default to the Solid mode when
shipped from factory. The detail algorithm of advanced sector protection is shown as follows:
Figure 79. Advanced Sector Protection Overview
Start
Bit 2=1
Bit 2=0
Set
Lock Register ?
Solid Protection Mode
Password Protection Mode
Set 64 bit Password
Set
SPB Lock Down Bit ?
(SPBLKDN)
Bit 6 = 0
SPB Locked
All SPB can not be changeable
Bit 6 = 1
SPB Unlocked
SPB is changeable
Solid Protection Bits
(SPB)
Dynamic Protect Bit Register
(DPB)
DPB=1 sector protect
Sector Array
SPB=1 Write Protect
SPB=0 Write Unprotect
DPB=0 sector unprotect
P/N: PM2504
Downloaded from Arrow.com.
DPB 0
SA 0
SPB 0
DPB 1
SA 1
SPB 1
DPB 2
SA 2
SPB 2
:
:
:
:
:
:
DPB N-1
SA N-1
SPB N-1
DPB N
SA N
SPB N
59
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
10-27-1. Lock Register
The Lock Register is a 8-bit register. Lock Register Bit[6] is SPB Lock Down Bit (SPBLKDN) which is assigned to
control all SPB bit status. Lock Register Bit[2] is Password Protection Mode Lock Bit. Both bits are defaulted as 1
when shipping from factory.
When SPBLKDN is 1, SPB can be changed. When it is locked as 0, all SPB can not be changed.
Users can choose their favorite sector protecting method via setting Lock Register Bit[2] using WRLR command.
The device default status was in Solid Protection Mode (Bit[2]=1), Once Bit[2] has been programmed (cleared to
"0"), the device will enable the Password Protection Mode and lock in that mode permanently.
In Solid Protection Mode (Bit[2]=1, factory default), the SPBLKDN can be programmed using the WRLR command
and permanently lock down the SPB bits. After programming SPBLKDN to 0, all SPB can not be changed anymore,
and neither Lock Register Bit[2] nor Bit[6] can be altered anymore.
In Password Protection Mode (Bit[2]=0), the SPBLKDN becomes a volatile bit with default 0 (SPB bit protected).
A correct password is required with PASSULK command to set SPBLKDN to 1. To clear SPBLKDN back to 0, a
Hardware/Software Reset or power-up cycle is required.
If user selects Password Protection mode, the password setting is required. User can set password by issuing
WRPASS command before Lock Register Bit[2] set to 0.
Lock Register
Bits
Description
7
Reserved
SPB Lock Down bit
6
(SPBLKDN)
5 to 3
Reserved
2
Bit Status
Default
Reserved
0: SPB bit Protected
1: SPB bit Unprotected
Reserved
Reserved
Solid Protection Mode: 1
Bit 2=1: OTP
Password Protection Mode: 0 Bit 2=0: Volatile
Reserved
Password Protection 0=Password Protection Mode Enable
Mode Lock Bit
1= Solid Protection Mode
1 to 0
P/N: PM2504
Downloaded from Arrow.com.
Reserved
Type
Reserved
1
OTP
Reserved
60
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
Figure 80. Read Lock Register (RDLR) Sequence
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
command
2Dh
SI
Register Out
High-Z
SO
7
6
5
4
3
2
1
0
7
MSB
Figure 81. Read Lock Register (RDLR) Sequence (STR-OPI Mode)
CS#
SCLK
Pre-drive
SIO[7:0]
2Dh
D2h
00
00
00
LR
00
Address
LR
Dummy
Figure 82. Read Lock Register (RDLR) Sequence (DTR-OPI Mode)
CS#
SCLK
DQS
Pre-drive
SIO[7:0]
2Dh
D2h
00
00
00
00
LR
Address
P/N: PM2504
Downloaded from Arrow.com.
LR
Dummy
61
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ADVANCED INFORMATION
MX66UM1G45G
Figure 83. Write Lock Register (WRLR) Sequence
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
Command
SI
Lock Register In
2Ch
7
6
5
4
3
2
1
0
MSB
High-Z
SO
Figure 84. Write Lock Register (WRLR) Sequence (STR-OPI Mode)
CS#
SCLK
SIO[7:0]
2Ch
D3h
00
00
00
00
LR
Figure 85. Write Lock Register (WRLR) Sequence (DTR-OPI Mode)
CS#
SCLK
SIO[7:0]
2Ch
D3h
00
00
00
00
LR
Note: CS# must go high while SCLK is low.
P/N: PM2504
Downloaded from Arrow.com.
62
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ADVANCED INFORMATION
MX66UM1G45G
10-27-2. Solid Protection Bits
The Solid Protection Bits (SPBs) are nonvolatile bits for enabling or disabling write-protection to sectors and blocks.
The SPB bits have the same endurance as the Flash memory. An SPB is assigned to each 4KB sector in the bottom
and top 64KB of memory and to each 64KB block in the remaining memory. The factory default state of the SPB bits
is “0”, which has the sector/block write-protection disabled.
When an SPB is set to “1”, the associated sector or block is write-protected. Program and erase operations on the
sector or block will be inhibited. SPBs can be individually set to “1” by the WRSPB command. However, the SPBs
cannot be individually cleared to “0”. Issuing the ESSPB command clears all SPBs to “0”. A WREN command must
be executed to set the WEL bit before sending the WRSPB or ESSPB command.
The RDSPB command reads the status of the SPB of a sector or block. The RDSPB command returns 00h if the
SPB is “0”, indicating write-protection is disabled. The RDSPB command returns FFh if the SPB is “1”, indicating
write-protection is enabled.
Note: If SPBLKDN=0, commands to set or clear the SPB bits will be ignored.
SPB Register
Bit
Description
7 to 0 SPB (Solid Protection Bit)
P/N: PM2504
Downloaded from Arrow.com.
Bit Status
00h = Unprotect Sector / Block
FFh = Protect Sector / Block
63
Default
Type
00h
Non-volatile
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
Figure 86. Read SPB Status (RDSPB) Sequence
CS#
0
1
2
3
4
5
6
7
8
37 38 39 40 41 42 43 44 45 46 47
9
SCLK
Command
SI
32-Bit Address
E2h
A31 A30
A2 A1 A0
MSB
Data Out
High-Z
SO
7
6
5
4
3
2
1
0
MSB
Figure 87. Read SPB Status (RDSPB) Sequence (STR-OPI Mode)
≈
CS#
≈
SCLK
E2h
1Dh
A[31:24]
A[23:16]
A[15:8]
≈
Pre-drive
SIO[7:0]
A[7:0]
Address
SPB
SPB
Dummy
Figure 88. Read SPB Status (RDSPB) Sequence (DTR-OPI Mode)
≈
CS#
≈
≈
SCLK
DQS
Pre-drive
E2h
A
A
A
1Dh [31:24] [23:16] [15:8]
A
[7:0]
≈
SIO[7:0]
Address
P/N: PM2504
Downloaded from Arrow.com.
SPB
SPB
Dummy
64
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
Figure 89. SPB Erase (ESSPB) Sequence
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
E4h
High-Z
SO
Figure 90. SPB Erase (ESSPB) Sequence (STR-OPI Mode)
CS#
SCLK
SIO[7:0]
E4h
1Bh
Figure 91. SPB Erase (ESSPB) Sequence (DTR-OPI Mode)
CS#
SCLK
E4h
SIO[7:0]
P/N: PM2504
Downloaded from Arrow.com.
65
1Bh
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
Figure 92. SPB Program (WRSPB) Sequence
CS#
0
1
2
3
4
5
6
7
8
37 38 39
9
SCLK
Command
SI
32-Bit Address
E3h
A31 A30
A2 A1 A0
MSB
Figure 93. SPB Program (WRSPB) Sequence (STR-OPI Mode)
CS#
SCLK
SIO[7:0]
E3h
1Ch
A[31:24]
A[23:16]
A[15:8]
A[7:0]
Figure 94. SPB Program (WRSPB) Sequence (DTR-OPI Mode)
CS#
SCLK
SIO[7:0]
P/N: PM2504
Downloaded from Arrow.com.
E3h
1Ch
A
A
A
[31:24] [23:16] [15:8]
66
A
[7:0]
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
10-27-3. Dynamic Write Protection Bits
The Dynamic Protection features a volatile type protection to each individual sector. It can protect sectors from
unintentional change, and is easy to disable when there are necessary changes.
All DPBs are default as protected (FFh) after reset or upon power up cycle. Via setting up Dynamic Protection bit (DPB)
by write DPB command (WRDPB), user can cancel the Dynamic Protection of associated sector.
The Dynamic Protection only works on those unprotected sectors whose SPBs are cleared. After the DPB state is
cleared to “0”, the sector can be modified if the SPB state is unprotected state.
DPB Register
Bit
Description
7 to 0
DPB (Dynamic protected Bit)
Bit Status
Default
00h= DPB for the sector address unprotected
FFh
FFh= DPB for the sector address protected
Type
Volatile
Figure 95. Read DPB Register (RDDPB) Sequence
CS#
0
1
2
3
4
5
6
7
8
37 38 39 40 41 42 43 44 45 46 47
9
SCLK
Command
SI
32-Bit Address
E0h
A31 A30
A2 A1 A0
MSB
Data Out
High-Z
SO
7
6
5
4
3
2
1
0
MSB
Figure 96. Read DPB Register (RDDPB) Sequence (STR-OPI Mode)
≈
CS#
≈
SCLK
E0h
1Fh
A[31:24]
A[23:16]
A[15:8]
A[7:0]
Address
P/N: PM2504
Downloaded from Arrow.com.
≈
Pre-drive
SIO[7:0]
DPB
DPB
Dummy
67
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
Figure 99. Read DPB Register (RDDPB) Sequence (DTR-OPI Mode)
≈
CS#
≈
≈
SCLK
DQS
Pre-drive
E0h
A
A
A
A
[7:0]
1Fh [31:24] [23:16] [15:8]
≈
SIO[7:0]
Address
DPB
DPB
Dummy
Figure 97. Write DPB Register (WRDPB) Sequence
CS#
0
1
2
3
4
5
6
7
8
37 38 39 40 41 42 43 44 45 46 47
9
SCLK
Command
SI
Data Byte 1
32-Bit Address
E1h
A31 A30
7
A2 A1 A0
MSB
6
5
4
3
2
1
0
MSB
Figure 98. Write DPB Register (WRDPB) Sequence (STR-OPI Mode)
CS#
SCLK
SIO[7:0]
E1h
1Eh
A[31:24]
A[23:16]
A[15:8]
A[7:0]
DPB
Address
Figure 100. Write DPB Register (WRDPB) Sequence (DTR-OPI Mode)
CS#
SCLK
SIO[7:0]
E1h
1Eh A[31:24] A[23:16] A[15:8] A[7:0]
DPB
Address
P/N: PM2504
Downloaded from Arrow.com.
68
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ADVANCED INFORMATION
MX66UM1G45G
10-27-4. Password Protection Mode
Password Protection mode potentially provides a higher level of security than Solid Protection mode. In Password
Protection mode, the SPBLKDN bit defaults to “0” after a power-on cycle or reset. When SPBLKDN=0, the SPBs
are locked and cannot be modified. A 64-bit password must be provided to unlock the SPBs.
The PASSULK command with the correct password will set the SPBLKDN bit to “1” and unlock the SPB bits. After
the correct password is given, a wait of 2us is necessary for the SPB bits to unlock. The Status Register WIP bit will
clear to “0” upon completion of the PASSULK command. Once unlocked, the SPB bits can be modified. A WREN
command must be executed to set the WEL bit before sending the PASSULK command.
Several steps are required to place the device in Password Protection mode. Prior to entering the Password
Protection mode, it is necessary to set the 64-bit password and verify it. The WRPASS command writes the
password and the RDPASS command reads back the password. Password verification is permitted until the
Password Protection Mode Lock Bit has been written to “0”. Password Protection mode is activated by programming
the Password Protection Mode Lock Bit to “0”. This operation is not reversible. Once the bit is programmed, it
cannot be erased. The device remains permanently in Password Protection mode and the 64-bit password can
neither be retrieved nor reprogrammed.
The password is all “1’s” when shipped from the factory. The WRPASS command can only program password bits to “0”.
The WRPASS command cannot program “0’s” back to “1’s”. All 64-bit password combinations are valid password
options. A WREN command must be executed to set the WEL bit before sending the WRPASS command.
● The unlock operation will fail if the password provided by the PASSULK command does not match the stored
password. This will set the P_FAIL bit to “1” and insert a delay before clearing the WIP bit to “0”. User has to
wait 150us before issuing another PASSULK command. This restriction makes it impractical to attempt all
combinations of a 64-bit password (such an effort would take millions of years). Monitor the WIP bit to determine
whether the device has completed the PASSULK command.
● When a valid password is provided, the PASSULK command does not insert the delay before returning the WIP
bit to zero. The SPBLKDN bit will set to “1” and the P_FAIL bit will be “0”.
● It is not possible to set the SPBLKDN bit to “1” if the password had not been set prior to the Password Protection
mode being selected.
Password Register (PASS)
Bits
Field
Function Type
Name
63 to 0 PWD
P/N: PM2504
Downloaded from Arrow.com.
Description
Default State
Non-volatile OTP storage of 64 bit password. The
Hidden
password is no longer readable after the Password
OTP FFFFFFFFFFFFFFFFh
Password
Protection mode is selected by programming Lock
Register bit 2 to zero.
69
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
Figure 101. Read Password Register (RDPASS) Sequence
CS#
0
1
2
3
4 5
6
7
8
39 40
47 48
109 110
SCLK
Command
SI
32-bit Address
27h
0
0
0
8 Dummy
0
Data Out
High-Z
SO
7
6
58 57 56
High-Z
MSB
SCLK
≈
≈ ≈
CS#
≈
Figure 102. Read Password Register (RDPASS) Sequence (STR-OPI Mode)
SIO[7:0]
D8h
00h
00h
00h
≈
Pre-drive
27h
00h
Address
D0
D7
20 Dummy
≈
CS#
≈
DQS
≈
≈
SCLK
≈ ≈
Figure 103. Read Password Register (RDPASS) Sequence (DTR-OPI Mode)
27h
D8h
00h
00h
00h
Address
P/N: PM2504
Downloaded from Arrow.com.
≈
Pre-drive
SIO[7:0]
00h
D1
D0
D7
D6
20 Dummy
70
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
Figure 104. Write Password Register (WRPASS) Sequence
CS#
0
1
2
3
4 5
6
7
39 40
8
102 103
SCLK
32-bit Address
Command
SI
28h
0
0
0
Password
7
0
6
58 57 56
MSB
High-Z
SO
Figure 105. Write Password Register (WRPASS) Sequence (STR-OPI Mode)
≈
CS#
SIO[7:0]
≈
SCLK
28h
D7h
00h
00h
00h
00h
D0
Address
D6
D7
Password
Figure 106. Write Password Register (WRPASS) Sequence (DTR-OPI Mode)
≈
≈
CS#
SCLK
SIO[7:0]
28h
D7h
00h
00h
00h
00h
Address
P/N: PM2504
Downloaded from Arrow.com.
D1
D0
D7
D6
Password
71
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
Figure 107. Password Unlock (PASSULK) Sequence
CS#
0
1
2
3
4 5
6
7
39 40
8
102 103
SCLK
32-bit Address
Command
SI
29h
0
0
0
Password
0
7
6
58 57 56
MSB
High-Z
SO
Figure 108. Password Unlock (PASSULK) (STR-OPI Mode)
≈
CS#
SIO[7:0]
≈
SCLK
29h
D6h
00h
00h
00h
00h
D0
Address
D6
D7
Password
Figure 109. Password Unlock (PASSULK) (DTR-OPI Mode)
≈
≈
CS#
SCLK
SIO[7:0]
29h
D6h
00h
00h
00h
00h
Address
P/N: PM2504
Downloaded from Arrow.com.
D1
D0
D7
D6
Password
72
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ADVANCED INFORMATION
MX66UM1G45G
10-27-5. Gang Block Lock/Unlock (GBLK/GBULK)
These instructions are only effective after WPSEL was executed. The GBLK/GBULK instruction is a chip-based
protected or unprotected operation. It can enable or disable all DPB.
The WREN (Write Enable) instruction is required before issuing GBLK/GBULK instruction.
The sequence of issuing GBLK/GBULK instruction is: CS# goes low → send GBLK/GBULK (7Eh/98h) instruction
→CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
The CS# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed.
10-27-6. Sector Protection States Summary Table
Protection Status
DPB bit
SPB bit
0
0
0
1
1
0
1
1
P/N: PM2504
Downloaded from Arrow.com.
Sector State
Unprotect
Protect
Protect
Protect
73
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ADVANCED INFORMATION
MX66UM1G45G
10-28. Program Suspend and Erase Suspend
The Suspend instruction interrupts a Program or Erase operation to allow the device conduct other operations.
After the device has entered the suspended state, the memory array can be read except for the page being
programmed or the sector being erased.
Security Register bit 2 (PSB) and bit 3 (ESB) can be read to check the suspend status. The PSB (Program Suspend
Bit) sets to “1” when a program operation is suspended. The ESB (Erase Suspend Bit) sets to “1” when an erase
operation is suspended. The PSB or ESB clears to “0” when the program or erase operation is resumed.
When the Serial NOR Flash receives the Suspend instruction, Program Suspend Latency(tPSL) or Erase Suspend
latency(tESL) is required to complete suspend operation. (Refer to "Table 15. AC CHARACTERISTICS") After the
device has entered the suspended state, the WEL bit is clears to “0” and the PSB or ESB in security register is set to “1”,
then the device is ready to acceptanother command.
However, some commands can be executed without tPSL or tESL latency during the program/erase suspend, and
can be issued at any time during the Suspend.
Please refer to "Table 7. Acceptable Commands During Suspend".
Figure 110. Suspend to Read Latency
tPSL / tESL
CS#
P/N: PM2504
Downloaded from Arrow.com.
Suspend Command
74
Read Command
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
Table 7. Acceptable Commands During Suspend
Command Name
Suspend Type
Command Code
Commands which require tPSL/tESL delay
READ
03h/13h
FAST_READ
0Bh/0Ch
8READ
ECh
8DTRD
EEh
RDSFDP
5Ah
RDID
9Fh
SBL
C0h
ENSO
B1h
EXSO
C1h
WREN
06h
RESUME
30h
RDLR
2Dh
RDSPB
E2h
RDFBR
16h
RDDPB
E0h
RDCR2 with A[31:30]=00/01
71h
WRCR2 with A[31:30]=00
WRCR2 with A[31:30]=01
72h
Program Suspend
Erase Suspend
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Commands not required tPSL/tESL delay
WRDI
04h
RDSR
05h
RDCR
15h
RDCR2 with A[31:30]=10
71h
WRCR2 with A[31:30]=10
72h
RDSCUR
2Bh
RES
ABh
RSTEN
66h
RST
99h
NOP
00h
P/N: PM2504
Downloaded from Arrow.com.
75
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
10-29. Program Resume and Erase Resume
The Resume instruction resumes a suspended Program or Erase operation. After the device receives the Resume
instruction, the WEL and WIP bits are set to “1” and the PSB or ESB is cleared to “0”.The program or erase
operation will continue until it is completed or until another Suspend instruction is received.
To issue another Suspend instruction, the minimum resume-to-suspend latency (tPRS or tERS) is required.
However, in order to finish the program or erase progress, a period equal to or longer than the typical timing is
required.
To issue other command except suspend instruction, a latency of the self-timed Page Program Cycle time (tPP) or
Sector Erase (tSE) is required. The WEL and WIP bits are cleared to “0” after the Program or Erase operation is
completed.
Figure 111. Resume to Read Latency
CS#
Resume Command
tSE / tBE / tPP
Read Command
Figure 112. Resume to Suspend Latency
CS#
P/N: PM2504
Downloaded from Arrow.com.
Resume
Command
tPRS / tERS
76
Suspend
Command
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
10-30. No Operation (NOP)
The “No Operation” command is only able to terminate the Reset Enable (RSTEN) command and will not affect any
other command.
10-31. Software Reset (Reset-Enable (RSTEN) and Reset (RST))
The Software Reset operation combines two instructions: Reset-Enable (RSTEN) command following a Reset (RST)
command. It returns the device to a standby mode. All the volatile bits and settings will be cleared then, which
makes the device return to the default status as power on.
To execute Reset command (RST), the Reset-Enable (RSTEN) command must be executed first to perform the
Reset operation. If there is any other command to interrupt after the Reset-Enable command, the Reset-Enable will
be invalid.
If the Reset command is executed during program or erase operation, the operation will be disabled, the data under
processing could be damaged or lost.
The reset time is different depending on the last operation. For details, please refer to "Table 11. Reset Timing(Other Operation)" for tREADY2.
P/N: PM2504
Downloaded from Arrow.com.
77
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
Figure 113. Software Reset Recovery
Stand-by Mode
66
CS#
99
tREADY2
Mode
Note: Refer to "Table 11. Reset Timing-(Other Operation)" for tREADY2.
Figure 114. Reset Sequence (SPI mode)
TSHSL
CS#
SCLK
Command
Command
99h
66h
SIO0
Figure 115. Reset Sequence (STR-OPI mode)
TSHSL
CS#
SCLK
SIO[7:0]
66h
99h
99h
66h
99h
66h
Figure 116. Reset Sequence (DTR-OPI mode)
TSHSL
CS#
SCLK
SIO[7:0]
P/N: PM2504
Downloaded from Arrow.com.
66h
99h
78
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
11. Serial Flash Discoverable Parameter (SFDP)
11-1. Read SFDP Mode (RDSFDP)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional
and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables
can be interrogated by host system software to enable adjustments needed to accommodate divergent features
from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on
CFI.
The sequence of issuing RDSFDP instruction in SPI is CS# goes low→send RDSFDP instruction (5Ah)→send 3
address bytes on SI pin→ send 8 dummy cycles → read SFDP code on SO→to end RDSFDP operation can use
CS# to high at any time during data out.
SFDP in SPI is a JEDEC standard, JESD216.
The sequcn of issuing RDSFDP instruction in OPI/DOPI mode:
CS# low → send RDSFDP instruction (5Ah/A5h) → send 4 address bytes on SIO pin→ send 20 dummy cycles →
read SFDP code on SIO[7:0] → to end RDSFDP operation can use CS# to high at any time during data out.
Figure 117. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
SO
24 BIT ADDRESS
23 22 21
5Ah
3
2
1
0
High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Cycle
SI
7
6
5
4
3
2
1
0
DATA OUT 2
DATA OUT 1
SO
7
6
5
P/N: PM2504
Downloaded from Arrow.com.
4
3
2
1
0
7
MSB
MSB
79
6
5
4
3
2
1
0
7
MSB
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
Figure 118. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence (STR-OPI Mode)
1
2
3
4
5
≈ ≈
CS#
6
SCLK
26
27
28
Pre-drive
A5h
A[31:24] A[23:16]
A[15:8]
A[7:0]
≈
SIO[7:0]
5Ah
Address
D0
D1
D2
20 Dummy
Figure 119. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence (DTR-OPI Mode)
≈
CS#
1
2
3
4
23
5Ah
≈
≈
DQS
SIO[7:0]
25
≈
SCLK
24
A5h A[31:24]A[23:16] A[15:8] A[7:0]
D1
D0
D3
D2
20 Dummy
Address
word unit word unit
Note: Address must be low byte (A0=0) in DTR OPI.
Table 8. Signature and Parameter Identification Data Values (TBD)
P/N: PM2504
Downloaded from Arrow.com.
80
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ADVANCED INFORMATION
MX66UM1G45G
12. Data Integrity check
The data storage and transmission errors will cause unexpected Flash device variation that makes a harmful impact
on overall system functions. To prevent these errors, this product provides advanced Data Integrity Check function.
For the data storage and data transmission in the flash device, Data Integrity Check can check errors and correct
them, allowing self-checking and preventing errors in advance.
The Data Integrity Check function includes two methods:
- ECC (Error Checking and Correcting): to prevent the data storage errors
- Parity Check (CRC1): to prevent the data transmission errors
The status register data and software signals can also be used to associate the Data Integrity Check function to fully
record the results of checking, and can also immediately feedback.
12-1. ECC (Error Checking and Correcting)
Macronix Serial Octa SPI Flash have built-in ECC. The ECC algorithm uses a Hamming code that can correct a
single bit error per 16-Byte chunk. During a page program operation, the internal state machine will create the ECC
automatically. During a read operation, the internal ECC state machine corrects bit errors automatically.
It is recommended that data be programmed in multiples of 16 bytes in the predefined 16-byte chunk address
(see "Table 9. 16-Byte Chunks within a Page") using the Page Program command instead of programming a byte
or a word at a time using the Program command. However, partial program of 16-byte chunk is allowed under the
restriction that user won't program or alter the content of partially programmed chunk without erasing the sector
first.
ECC checking of a 16-Byte chunk will be disabled if double program (rewriting without erase), or rewrite a chunk
(alternating of single bit, byte, or word) happens in that chunk. Once ECC checking of a chuck is disabled, it will not
be re-activated until the sector, containing the ECC disabled chunk, is erased.
The ECC registers show detailed information for error correction activity on the device. The ECC status registers
are placed on CR2. Which include 3-bit ECC status to identify the error type, 4-bit failure chunk counter and first
failure chunk address.
The ECC register can be reset through either of the following situations:
- Write "00" data into ECC status register
- Issuing Software Reset Command
- Hardware Reset
- Power-up cycle
Table 9. 16-Byte Chunks within a Page
Chunk#
0
1
2
3
4
5
16 Bytes
B0
~B15
B16
~B31
B32
~B47
B48
~B63
B64
~B79
B80
~B95
P/N: PM2504
Downloaded from Arrow.com.
6
7
8
9
10
11
12
13
14
15
B96
B112 B128 B144 B160 B176 B192 B208 B224 B240
~B111 ~B127 ~B143 ~B159 ~B175 ~B191 ~B207 ~B223 ~B239 ~B255
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ADVANCED INFORMATION
MX66UM1G45G
12-2. ECS# (Error corrected Signal) Pin
The ECS# pin is a real time hardware signal to feedback the ECC correction status. The ECS# pin is designed as
an open drain structure. In normal situation, the ECS# is kept on Hi-Z state. Once error correction begins, the ECS#
pin will pull low during the whole ECC chunk unit after a duration of tECSV delay timing.
The ECS# pin is default as going low when 2-bit error detection is enabled and double program detected. However,
user can select the different option for error correction by setting the ECS register in CR2 [00000400h].
Command
Address
≈
≈≈ ≈
ECC chunk (16Bytes)
ECC chunk (16Bytes)
≈
ECS#
≈≈ ≈
SIO[7:0]
≈
≈
≈
SCLK
≈
≈
CS#
≈
Figure 120. ECS# Timing
tECSV
P/N: PM2504
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82
Chunk with ECC error detected
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ADVANCED INFORMATION
MX66UM1G45G
12-3. Parity Check (CRC1)
The parity check function can only be operated at DTR OPI mode, it does not support OPI mode. The CRCEN#
bit in CR2 [address 40000000h] bit3 can enable the parity check function. CRCEN# is an OTP bit; once it is
programmed to "0", it cannot be disabled anyhow.
For write operation after the Parity check function is enabled, the CRC code needs to be set after the address
and data cycles. The starting address for the Flash device has to be issued at CRC chunk boundary, and the data
CRC bit also should be output by each CRC chunk unit. Otherwise, read CRC code might be error; and program
command would abort.
There is a bit [CR2 00000500h] that output data is CRC on both clock edges, or is CRC/CRC# on clock rising/
falling edge respectively. The CRC chunk unit is default to set as 16bytes. It can also configure the chunk unit to
32bytes, 64bytes or 128bytes by CRC register setting in CR2 [address 00000500h].
For register write, an extra DATA# cycle must be set right after data cycle as in "Figure 124. CRC Timing (Write
Register - example for 1byte data)".
For register read, an extra DATA# would be output after the data cycle as in "Figure 125. CRC Timing (Read
register - example for 1byte data)".
The address CRC byte is calculated by bitwise exclusive-OR of all the address bytes; the data CRC bytes are
calculated by bitwise exclusive-OR of all the data bytes in the CRC chunk.
≈
≈≈ ≈
≈
≈≈ ≈
CRC
CRC
Multiple of CRC chunks
Address
≈
Command
≈
ECS#
CRC
≈
SIO[7:0]
≈
SCLK
≈
CS#
≈
Figure 121. CRC Timing (Without CRC# output)
tECSV
ECC Chunk with ECC checking fail
Address
≈
≈≈ ≈
CRC CRC#
tECSV
P/N: PM2504
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CRC CRC#
Multiple of CRC chunks
≈
Command
≈
ECS#
CRC
≈
SIO[7:0]
≈
≈
SCLK
≈≈ ≈
≈
CS#
≈
Figure 122. CRC Timing (With CRC# output)
83
ECC Chunk with ECC checking fail
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ADVANCED INFORMATION
MX66UM1G45G
Figure 123. CRC Timing (Page Program)
Data (16/32/64/128B)
CRC
Command
CRC
≈ ≈ ≈
SIO[7:0]
≈≈ ≈
SCLK
≈
≈
CS#
Data (16/32/64/128B)
CRC
Address
Figure 124. CRC Timing (Write Register - example for 1byte data)
CS#
SCLK
SIO[7:0]
CRC
Command
Data
Data#
Address
Figure 125. CRC Timing (Read register - example for 1byte data)
CS#
SCLK
SIO[7:0]
Command
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Data
CRC
Data#
Address
84
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ADVANCED INFORMATION
MX66UM1G45G
≈
CS#
≈
≈
SCLK
≈ ≈
Figure 126. CRC Timing (RDPASS)
≈
DQS
CRC
Command
≈ ≈
Pre-drive
SIO[7:0]
D1 D0 D3 D2 D5 D4 D7 D6 FF FF FF FF
20 Dummy
Address
8 Bytes
FF FF FF
CRC
8/24/56/120 Bytes
16/32/64/128 Bytes
Figure 127. CRC Timing (WRPASS/PASSULK)
SCLK
SIO[7:0]
CRC
Command
D1 D0 D3 D2 D5 D4 D7 D6 FF FF FF FF
8 Bytes
Address
≈≈
≈ ≈
CS#
FF FF CRC
8/24/56/120 Bytes
16/32/64/128 Bytes
Figure 128. CRC Timing (WRFBR)
SCLK
SIO[7:0]
CRC
Command
D1 D0 D3 D2 FF FF FF FF
4 Bytes
Address
≈≈
≈ ≈
CS#
FF FF CRC
Data 12/28/60/124 Bytes
16/32/64/128 Bytes
P/N: PM2504
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MX66UM1G45G
13. RESET
Driving the RESET# pin low for a period of tRLRH or longer will reset the device. After reset cycle, the device is at
the following states:
- Standby mode
- All the volatile bits such as WEL/WIP will return to the default status as power on.
- All the volatile bits in CR2 will return to the default status as power on.
- Fastboot read will be executed on first CS# pin goes low
If the device is under programming or erasing, driving the RESET# pin low will also terminate the operation and
data could be lost. During the resetting cycle, the SIO data becomes high impedance and the current will be
reduced to minimum.
Figure 129. RESET Timing
CS#
tRHSL
SCLK
tRH tRS
RESET#
tRLRH
tREADY1 / tREADY2
Table 10. Reset Timing-(Standby)
Symbol Parameter
tRHSL Reset# high before CS# low
tRS
Reset# setup time
tRH
Reset# hold time
tRLRH Reset# low pulse width
tREADY1 Reset Recovery time
Min.
10
15
15
10
35
Typ.
Max.
Unit
us
ns
ns
us
us
Min.
10
15
15
10
40
40
310
12
25
100
40
Typ.
Max.
Unit
us
ns
ns
us
us
us
us
ms
ms
ms
ms
Table 11. Reset Timing-(Other Operation)
Symbol
tRHSL
tRS
tRH
tRLRH
Parameter
Reset# high before CS# low
Reset# setup time
Reset# hold time
Reset# low pulse width
Reset Recovery time (During instruction decoding)
Reset Recovery time (for read operation)
Reset Recovery time (for program operation)
tREADY2 Reset Recovery time(for SE4KB operation)
Reset Recovery time (for BE64K operation)
Reset Recovery time (for Chip Erase operation)
Reset Recovery time (for WRSR operation)
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MX66UM1G45G
14. POWER-ON STATE
The device is at below states when power-up:
- Standby mode (please note it is not deep power-down mode)
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage unless the VCC achieves below correct
level:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change
during power up state. When VCC is lower than VWI (POR threshold voltage value), the internal logic is reset and
the flash device has no response to any command.
For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not
guaranteed. The write, erase, and program command should be sent after the below time delay:
- tVSL after VCC reached VCC minimum level
The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.
Please refer to the ""Power-up Timing"".
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is
recommended. (generally around 0.1uF)
- At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response
to any command. The data corruption might occur during the stage while a write, program, erase cycle is in
progress.
- To stabilize the VCCQ level, the VCCQ/VSSQ rail decoupled by a suitable capacitor close to package pins is
recommended. One VCCQ pin connect to one capacitor.
- It is recommended VCC and VCCQ power are separated system supply with same supply voltage.
P/N: PM2504
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MX66UM1G45G
15. ELECTRICAL SPECIFICATIONS
Table 12. ABSOLUTE MAXIMUM RATINGS
RATING
VALUE
Ambient Operating Temperature
Industrial grade
-40°C to 85°C
Storage Temperature
-65°C to 150°C
Applied Input Voltage
-0.5V to VCC+0.5V
Applied Output Voltage
-0.5V to VCC+0.5V
VCC to Ground Potential
-0.5V to 2.5V
NOTICE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage
to the device. This is stress rating only and functional operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended period may affect reliability.
2. Specifications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot to VCC+1.0V or -1.0V for period up to 20ns.
Figure 131. Maximum Positive Overshoot Waveform
Figure 130. Maximum Negative Overshoot Waveform
20ns
0V
VCC+1.0V
-1.0V
2.0V
20ns
Table 13. CAPACITANCE TA = 25°C, f = 1.0 MHz
Symbol Parameter
CIN
COUT
P/N: PM2504
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Min.
Typ.
Max.
Unit
Input Capacitance
16
pF
VIN = 0V
Output Capacitance
16
pF
VOUT = 0V
88
Conditions
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ADVANCED INFORMATION
MX66UM1G45G
Figure 132. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL
Input timing reference level
0.8VCC
Output timing reference level
0.7VCC
AC
Measurement
Level
0.3VCC
0.2VCC
0.5VCC
Note: Input pulse rise and fall time are 133MHz
DTR ≤ 100MHz
DTR ≤ 133MHz
Data setup time (9) (10)
DTR ≤ 166MHz
STR ≤ 133MHz
(10)
Data In Hold Time
STR > 133MHz
DTR ≤ 100MHz
DTR ≤ 133MHz
Data hold time (9) (10)
DTR ≤ 166MHz
CS# Active Hold Time (relative to
STR
SCLK)
CS# active hold time
DTR
STR
CS# Not Active Setup Time
(relative to SCLK)
DTR
Output Disable Time
Clock transient to DQS valid time
Loading: 10pF
Loading: 15pF
Clock transient to Output Valid
Loading: 20pF
Loading: 30pF
Output Hold Time
Loading: 10pF(10)
Loading: 15pF(10)
SIO valid skew related to DQS
Loading: 20pF(10)
Loading: 30pF(10)
SIO hold time related to DQS
91
Unit
MHz
MHz
MHz
MHz
MHz
0.45*T
0.45*T
0.6
0.8
1
4.5
3
10
ns
ns
V/ns
V/ns
V/ns
ns
ns
ns
40
ns
2
1
1
0.8
0.6
2
1
1
0.8
0.6
ns
ns
ns
ns
3
ns
3
3
3
ns
ns
ns
ns
ns
8
Align to 30pF tCLQV
5.5
5.5
5.5
5.5
1
0.6
0.8
1.0
1.2
min(tCL,tCH)tQHS
ns
ns
ns
ns
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
Symbol
tQHS
tECSV
tDP(2)
tRES1(2)
tW
tPP(4)
tSE
tBE
tCE
tESL(6)
tPSL(6)
tPRS(7)
tERS(8)
Alt. Parameter
SIO hold skew factor
Loading: 10pF(10)
Loading: 15pF(10)
Loading: 20pF(10)
Loading: 30pF(10)
Loading: 30pF(10)
ECS go low time
CS# High to Deep Power-down Mode
CS# High to Standby Mode
Write Status/Configuration Register non-volatile bit Cycle
Time
Page Program Cycle Time
Sector Erase Cycle Time
Block Erase (64KB) Cycle Time
Chip Erase Cycle Time
Erase Suspend Latency
Program Suspend Latency
Latency between Program Resume and next Suspend
Latency between Erase Resume and next Suspend
Min.
Typ.
0.15
25
250
150
0.3
0.3
100
400
Max.
0.8
1.0
1.2
1.4
10
10
30
Unit
40
ms
0.75
400
2000
300
25
25
ms
ms
ms
s
us
us
us
us
ns
ns
us
us
Notes:
1. tCH + tCL must be greater than or equal to 1/ Frequency.
2. Typical values given for TA=25°C. Not 100% tested.
3. Test condition is shown as Figure 132 and Figure 133.
4. While programming consecutive bytes, Page Program instruction provides optimized timings by selecting to
program the whole 256 bytes or only a few bytes between 1~256 bytes.
5. By default dummy cycle value. Please refer to the "Table 1. Operating Frequency Comparison".
6. Latency time is required to complete Erase/Program Suspend operation until WIP bit is "0".
7. For tPRS, minimum timing must be observed before issuing the next program suspend command. However, a
period equal to or longer than the typical timing is required in order for the program operation to make progress.
8. For tERS, minimum timing must be observed before issuing the next erase suspend command. However, a
period equal to or longer than the typical timing is required in order for the erase operation to make progress.
9. tDVCH+tCHDX>1.5ns for each SIO; tDVCL+tCLDX>1.5ns for each SIO.
10. Sampled, not 100% tested.
P/N: PM2504
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MX66UM1G45G
16. OPERATING CONDITIONS
At Device Power-Up and Power-Down
AC timing illustrated in Figure 135 and Figure 136 are for the supply voltages and the control signals at device
power-up and power-down. If the timing in the figures is ignored, the device will not operate correctly.
During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be
selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL.
Figure 135. AC Timing at Device Power-Up
VCC
VCC(min)
GND
tVR
tSHSL
CS#
tSLCH
tCHSL
tCHSH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
LSB IN
MSB IN
SI
High Impedance
SO
Symbol
tVR
tCLCH
Parameter
VCC Rise Time
Notes
1
Min.
Max.
500000
Unit
us/V
Notes :
1. Sampled, not 100% tested.
2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to
Table 15. AC CHARACTERISTICS.
P/N: PM2504
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ADVANCED INFORMATION
MX66UM1G45G
Figure 136. Power-Down Sequence
During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.
VCC
CS#
SCLK
Figure 137. Power-up Timing
VCC
VCC(max)
Chip Selection is Not Allowed
VCC(min)
tVSL
Device is fully accessible
VWI
time
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MX66UM1G45G
Figure 138. Power Up/Down and Voltage Drop
When powering down the device, VCC must drop below VPWD for at least tPWD to ensure the device will initialize
correctly during power up. Please refer to "Figure 138. Power Up/Down and Voltage Drop" and "Table 16. PowerUp/Down Voltage and Timing" below for more details.
VCC
VCC (max.)
Chip Select is not allowed
VCC (min.)
V_keep
tVSL
Full Device
Access
Allowed
VWI
VPWD (max.)
tPWD
Time
Table 16. Power-Up/Down Voltage and Timing
Symbol
Min.
tPWD
Parameter
VCC voltage needed to below VPWD for ensuring initialization will
occur
Voltage that a re-initialization is necessary if VDD drop
below to VKEEP
The minimum duration for ensuring initialization will occur
tVSL
VPWD
V_keep
Max.
Unit
0.8
V
1.5
V
300
us
VCC(min.) to device operation
3000
us
VCC
VCC Power Supply
1.65
2.0
V
VWI
Write Inhibit Voltage
1.0
1.5
V
16-1. INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status
Register contains 00h (all Status Register bits are 0). DEFDOPI# in CR2 depends on shipping device model.
P/N: PM2504
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MX66UM1G45G
17. ERASE AND PROGRAMMING PERFORMANCE
Parameter
Min.
Typ. (1)
Max. (2)
Unit
40
ms
Write Status Register Cycle Time
Sector Erase Cycle Time (4KB)
25
400
ms
Block Erase Cycle Time (64KB)
250
2000
ms
Chip Erase Cycle Time
150
300
s
Page Program Time
0.15
0.75
ms
Erase/Program Cycle
100,000
cycles
Note:
1. Typical program and erase time assumes the following conditions: 25°C, 1.8V, and checkboard pattern.
2. Under worst conditions of 1.65V.
3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming
command.
4. The maximum chip programming time is evaluated under the worst conditions of 0°C, VCC=1.8V, and 100K
cycle with 90% confidence level.
18. DATA RETENTION
Parameter
Condition
Min.
Data retention
55˚C
20
Max.
Unit
years
19. LATCH-UP CHARACTERISTICS
Min.
Input Voltage with respect to GND on all power pins
Max.
1.5 VCCmax
Input current with respect to GND on all non-power pins
-100mA
+100mA
Test conditions are compliant to JEDEC JDESD78 standard
P/N: PM2504
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MX66UM1G45G
20. ORDERING INFORMATION
Please contact Macronix regional sales for the latest product selection and available form factors.
PART NO.
MX66UM1G45GXDI00
P/N: PM2504
Downloaded from Arrow.com.
CLOCK (MHz)
TEMPERATURE
PACKAGE
166
-40°C to 85°C
24-Ball BGA
(5x5 ball array)
97
Remark
Rev. 0.00, March 01, 2017
ADVANCED INFORMATION
MX66UM1G45G
21. PART NAME DESCRIPTION
MX 66 UM 1G45G
XD
I
00
MODEL CODE:
00: Default STR, x1 I/O enable
TEMPERATURE RANGE:
I: Industrial (-40°C to 85°C)
PACKAGE:
XD: 24-Ball BGA (5x5 ball array)
DENSITY & MODE:
1G45G: 1Gb
TYPE:
UM: 1.8V Octa I/O
DEVICE:
66: Serial NOR Flash
P/N: PM2504
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MX66UM1G45G
22. PACKAGE INFORMATION
P/N: PM2504
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MX66UM1G45G
Except for customized products which have been expressly identified in the applicable agreement, Macronix's
products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or
household applications only, and not for use in any applications which may, directly or indirectly, cause death,
personal injury, or severe property damages. In the event Macronix products are used in contradicted to their
target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its
actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or
distributors shall be released from any and all liability arisen therefrom.
Copyright© Macronix International Co., Ltd. 2017. All rights reserved, including the trademarks and tradename
thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, Nbit, Macronix NBit,
eLiteFlash, HybridNVM, HybridFlash, HybridXFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC,
Kingtech, MXSMIO, Macronix vEE, Macronix MAP, Rich Book, Rich TV, OctaRAM, OctaBus, OctaFlash and
FitCAM. The names and brands of third party referred thereto (if any) are for identification purposes only.
For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
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