MX69F164C3BT

ADVANCED INFORMATION MX69F162/164C3BT/B 16M-BIT [X16] FLASH AND 2M-BIT/4M-BIT [X16] SRAM MIXED MULTI CHIP PACKAGE MEMORY FEATURES • Supply voltage range: 2.7V to 3.6V • Fast access time: Flash memory:70/90ns SRAM memory:70/85ns • Operation temperature range: -40 ~ 85° C • Fully compatible with MX69F1602/1604C3T/B device - Word write suspend to read - Sector erase suspend to word write - Sector erase suspend to read register report Automatic sector erase, word write and sector lock/ unlock configuration 100,000 minimum erase/program cycles Boot Sector Architecture - T = Top Boot Sector - B = Bottom Boot Sector Status Register feature for detection of program or erase cycle completion Data protection performance - Sectors to be locked/unlocked Common Flash Interface (CFI) 128-bit Protection Register - 64-bit Unique Device Identifier - 64-bit User-Programmable Latch-up protected to 100mA from -1V to VCC+1V • • • FLASH • Word mode only • VCCf=VCCQ=2.7V~3.6V for read, erase and program operation • VPP=12V for fast production programming • Low power consumption - 9mA typical active read current, f=5MHz - 18mA typical program current (VPP=1.65~3.6V) - 21mA typical erase current (VPP=1.65~3.6V) - 7uA typical standby current under power saving mode • Sector architecture - Sector structure : 4Kword x 2 (boot sectors), 4Kword x 6 (parameter sectors), 32Kword x 31 (main sectors) - Top/Bottom Boot • Auto Erase and Auto Program - Automatically program and verify data at specified address - Auto sector erase at specified sector • Automatic Suspend Enhance • • • • • SRAM • • • • • • MX69F162C3BT/B: 128K wordx16 Bit MX69F164C3BT/B: 256K wordx16 Bit 70mA maximum active current 1uA typical standby current Data retention supply voltage: 2.0V~3.6V Byte data control : LBs#(Q0 to Q7) and UBs#(Q8 to Q15) P/N:PM1083 REV. 0.2, MAY 20, 2004 1 MX69F162/164C3BT/B GENERAL DESCRIPTION The MXIC's mixed multi chip memory combines Flash and SRAM into a single package. The mixed multi chip memory operates 2.7 to 3.6V power supply to allow for simple in-system operation. The Flash memory of mixed multi chip memory manufactured with MXIC's advanced nonvolatile memory technology, the flash memory of mixed multi chip memory is designed to be re-programmed and erased in system or in standard EPROM programmers. The device offers access times of 70ns/90ns, and 7uA typical standby current. Flash memories augment EPROM functionality with incircuit electrical erasure and programming and use a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility. Flash memory reliably stores memory contents even after 100,000 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produces reliable cycling. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamperes on address and data pin from -1V to VCC + 1V. The dedicated VPP pin gives complete data protection when VPP< VPPLK. The Flash contains both a Command User Interface (CUI) and a Write State Machine (WSM). A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for erase, word write and sector lock/unlock configuration operations. Flash erase automation allows sector erase operation to be executed using an industry-standard two-write command sequence to the CUI. A sector erase operation erases one of the device's 32K-word sectors typically within 1.0s, 4K-word sectors typically within 0.5s independent of other sectors. Each sector can be independently erased minimum 100,000 times. Sector erase suspend mode allows system software to suspend sector erase to read or write data from any other sector. Flash program automation allows program operation to be executed using an industry-standard two-write command sequence to the CUI. Writing memory data is performed in word increments of the device's 32K-word sectors typically within 0.8s and 4K-word sectors typically within 0.1s. Word program suspend mode enables the system to read data or execute code from any other memory array location. The Flash features with individual sectors locking by using a combination of thirty-nine sector lock-bits and WP#, to lock and unlock sectors. The Flash status register indicates the status of the WSM when the sector erase, word program or lock configuration operation is done. The Flash power saving mode feature substantially reduces active current when the device is in static mode (addresses not switching). In this mode, the typical ICCS current is 7uA (CMOS) at 3.0V VCC. As CEf# and RESET# are at VCC, ICC CMOS standby mode is enabled. When RESET# is at GND, the reset mode is enabled which minimize power consumption and provide data write protection. The Flash require a reset time (tPHQV) from RESET# switching high until outputs are valid. Similarly, the flash has a wake time (tPHEL) from RESET#-high until writes to the CUI are recognized. With RESET# at GND, the WSM is reset and the status register is cleared. The 2M-bit SRAM of MX69F162C3BT/B is organized as 128K-word by 16-bit. The 4M-bit SRAM of MX69F164C3BT/B is organized 256K-word by 16-bit. The advanced CMOS technology and circuit techniques provide both high speed and low power features of with a typical CMOS standby current of 1uA and maximum access time of 70ns/85ns in 3V operation. The mixed multi chip memory is available in 11mm x 8mm FBGA Package to suit a variety of design applications. P/N:PM1083 REV. 0.2, MAY 20, 2004 2 MX69F162/164C3BT/B Feature Summary Feature Vcc Operating Voltage Configuration MX69F162/164C3BT/B 2.7~3.6V Flash SRAM Fast Access Time Block Architecture - 70 : - 90 : Flash 16M:1M Word x16bit MX69F162C3BT/B:128K Word x16bit MX69F164C3BT/B:256K Word x16bit Flash/70ns, SRAM/70ns Flash/90ns, SRAM/85ns 2 x 4K Word Boot 6 x 4K Word Parameter 31 x 32K Word Main Address Pin Flash SRAM Manufacture Code Device ID Code Flash Flash A0~A19 MX69F162C3BT/B:A0~A16 MX69F164C3BT/B:A0~A17 00C2H MX69F162/164C3BT=88C2H MX69F162/164C3BB=88C3H P/N:PM1083 REV. 0.2, MAY 20, 2004 3 MX69F162/164C3BT/B PIN ASSIGNMENT 66-ball CSP for MX69F162/164C3BT/B (Top View Balls Down, 11 x 8 x 1.4mm, Ball Pitch=0.8mm) A B C D E F G H NC NC NC A11 A15 A14 A13 A12 GNDf VCCQ NC NC A16 A8 A10 A9 Q15 WEs# Q14 Q7 WEf# NC RESET# VPP A19 Q11 Q13 Q6 Q4 Q5 GNDs Q12 CE2s VCCs VCCf WP# Q10 Q2 Q3 8.0 mm LBs# UBs# OEs# Q9 Q8 Q0 Q1 A18 A17 A7 A6 A3 A2 A1 CE1 s# NC NC NC NC NC NC A5 A4 A0 CEf# GNDf OEf# 1 2 3 4 5 6 7 11.0 mm 8 9 10 11 12 Notes: 1.To maintain compatibility with all JEDEC Variation B options for this ball location C6, this C6 land pad should be connected directly to the land pad for ball G4 (A17). PIN DESCRIPTION SYMBOL A0 to A16 A0 to A17 A17 to A19 A18 to A19 Q0 to Q15 CEf# CE1s# CE2s OEf# OEs# PIN NAME Address Inputs (Common) for MX69F162C3BT/B Address Inputs (Common) for MX69F164C3BT/B Address Input (Flash) for MX69F162C3BT/B Address Input (Flash) for MX69F164C3BT/B Data Inputs/Outputs (Common) Chip Enable (Flash) Chip Enable (SRAM) Chip Enable (SRAM) Output Enable (Flash) Output Enable (SRAM) SYMBOL WEf# WEs# UBs# LBs# RESET# WP# N.C. GND VCCf VCCs VPP VCCQ PIN NAME Write Enable (Flash) Write Enable (SRAM) Upper Byte Control (SRAM) Lower Byte Control (SRAM) Hardware Reset Pin/Deep Power Down (Flash) Write Protect No Connection Ground Pin (Common) Power Supply (Flash, 2.7V~3.6V) Power Supply (SRAM, 2.7V~3.6V) Program/Erase Power Supply (1.65V~3.6V or 11.4V~12.6V) I/O Power Supply (Flash) tied to VCCf P/N:PM1083 REV. 0.2, MAY 20, 2004 4 MX69F162/164C3BT/B BLOCK DIAGRAM for MX69F162/164C3BT/B VCCf VPP GND VCCQ A0~A19 A0~A19 CEf# OEf# WEf# RESET# WP# 1MWx16bit (16M) Flash Memory Q0 to Q15 Q0 to Q15 Vccs GND A0~A16/A0~A17 CE1s# CE2s OEs# WEs# UBs# LBs# 2M/4M bit Static RAM Q0 to Q15 P/N:PM1083 REV. 0.2, MAY 20, 2004 5 MX69F162/164C3BT/B DEVICE BUS OPERATIONS for MX69F162/164C3BT/B Notes CEf# OEf# WEf# CE1s# CE2s OEs#WEs# LBs# (1) Full Standby 3,4 H L L L L L 5,7 3,4,6 L X X H L L L L H X X H H H H H L X (1) H X Flash Output Disable 3,4 Array Read Query from Flash Configuration Status Register Write to Flash Reset H X H X H X H X H X H X H X SRAM Output Disable Read from SRAM H X X L H 3,4 H X X L (1) X L X L X L X L X L X L X L X L H H X L H X H X H L H L Write to SRAM H X X L H H L L H L X H L L H L L H Dout High Z Dout Din X Din Dout Dout High Z Din Din X H H H H H H High Z High Z H X X X X High Z High Z L X X X X Din Din H X X X X Dout Dout H X X X X ID(2) ID(2) H X X X X Dout Dout H X X X X Dout Dout H X X X X High Z High Z H X X X X UBs# Q0~ Q7 High Z Q8~ High Z REH Q15 SET# Legend: L=VIL, H=VIH, X at control pins=VIL or VIH. See "ELECTRIAL CHARACTERISTICS 1.DC Characteristics" for voltage levels. Notes: 1. Do not apply CEf#=VIL, CE1s#=VIL and CE2s=VIH at a time. 2. ID=Device Identifier Code. See "Table 3. Configuration Code" 3. Outputs are dependent on a seperate device controlling bus output. 4. Modes of the flash and SRAM can be interleaved so that while one is disabled the other controls outputs. 5. To program or erase the lockable sectors hold WP# at VIH. 6. RESET# at GND ± 0.2V to ensure the lowest power consumption. 7. Refer to Table 2 for valid Din during a write operation. P/N:PM1083 REV. 0.2, MAY 20, 2004 6 MX69F162/164C3BT/B ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Operating Temperature During Read, Sector Erase, Word Write . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC Storage Temperature . . . . . . . . . . . . . .-65oC to +125oC Voltage on Any Ball (except VCCf, VCCs, VCCQ and VPP) with respect to GND . . . . . . . . .-0.5 V to VCC+0.5(1) VPP Supply Voltage (for Sector Erase and Word Write) with respect to GND . . . . . . . . . .-0.5V to +13.5V(1,2,4) VCCf, VCCs and VCCQ Supply Voltage with respect to GND. . . . . . . . . . . . . . . . .-0.2V to +4.0V(1) Output Short Circuit Voltage . . . . . . . . . . . . .100mA(3) WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operation Conditions" may affect device reliability. 1. Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods