MX93000

MX93000 MX93000 FEATURES • • • • • • • • • • • • • Single +5V power supply Sigma-Delta A/D D/A with digital filters Support u/A Law and 16-bit linear format On-chip automatic level control On-chip differential line driver On-chip digital volume control Programmable transmit/receive gain control Support switch paths for DAM (Digital Answering Machine) applications Easy interface to general purpose DSPs Easy read/write of control register by microprocessors Programmable power-down Support power-low/battery-low detection 28-pin DIP/SOP package PRODUCT OVERVIEW The MX93000 Special Codec integrates key functions of the analog-front-end of Digital Answering Machine (DAM) into a single integrated circuit. The MX93000 is intended to provide a complete, low cost, and single chip solution for telephone applications requiring a single +5V power supply. The MX93000 Special Codec is especially powerful when applied to some DAM models which are intended to meet different countries' specifications in the same system hardware. User can achieve this goal by simply setting control firmware. This benifit will help DAM system makers to save developing time and R/D resources. The A/D D/A converters are implemented with 2ndorder sigma-Delta modulators. The on-chip digital filters, which are carried out with 16-bit and 2's complement format, are used to get the required frequency response of a PCM Codec. The Codec can support 8-bit u/A law and linear format. For the latter, it is 16-bit format with 14-bit resolution . Before the A/D digitizing the voice-band analog signal into digital format, the analog signal can be processed by a built-in Automatic Level Control (ALC) and programmable Gain Amplifier (PGA). The ALC circuit controls the input level of A/D converter to about 1.5 Volt, so as to get a better signal to noise ratio during a low-level input. The PGA circuit is used to control the gain of different sources : microphone, aux or line input. After the digital data is converted into analog signal by the D/A converter, a fully differential line driver is supported to drive the telephone line directly without the need of external amplifier. On the other hand, the analog signal can be monitored by passing the analog signal to the on-chip volume control circuit, which can drive an external driver like LM386. In addition, the MX93000 supports switches and control registers so that users can program the Special Codec to be under line operations and all other specific operations of DAM. To enhance an easy read/write of control registers by microprocessors, the control data is clocked by the 8 kHz sampling clock and synchronized by SDEN\, where SDEN\ is coming from the output port of microprocessor by detecting one of the rising edge of 8 kHz clock. PIN CONFIGURATION 28PIN SOP/DIP SDATA SDEN\ DX DR FS MCLK VDD GND PRST BAT\ VBAT PDN\ VPOW LIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 SPK VR VREF FILT ALCC ALCRC PGAC AUX MIC AG AGND AVDD LOUT2 LOUT1 MX93000 P/N: PM0306 1 REV. 3.0, JUL 15, 1996 MX93000 SPECIAL DIAGRAM CODEC BLOCK 2 MX93000 FUNCTIONAL DESCRIPTION PCM CODEC : This block includes A/D & D/A converters and all of the digital filters. A/D & D/A converters: which are implemented with 2nd-order sigma-delta modulation. Output formats are A-Law/u-Law/16-bit linear, where u/A laws are of CCITT specifications and the 16-bit linear data can get 14-bit resolution and higher linearity than that of u/A law. Digital filters : For the purpose of A/D out-of-band noise filtering and D/A image attenuation, digital filters are implemented on the same chip. The digital input applied to D/A converter can not be a dc signal other than idle (bits all zero), as limit cycles in the digital modulator at a level of -70 dBm will present at the analog output. POWER MANAGEMENT : The MX93000 supports the automatic power-down control and power supply detection. This function will work well even under 3V power supply. Regarding the power_down procedure please refer to register 4 description for details. POWER_LOW/BATTERY_LOW detectors : active low 2 comparators and references are used to check whether POWER_LOW/BATTERY_LOW or not. The relationship between POWER_ON_RESET and POWER_LOW/BATTERY_LOW is as the following table: (I) POWER_LOW (PDN\) (I) BATTERY_LOW (BAT\) (0)POWER_ON_RESET (PRST) 0 0 0 0 1 1 1 0 1 1 1 1 LINE DRIVER : Not only support the programmable gain from 0 to 22.5 dB with 16 steps and 1.5 dB/step, but also fully differentially drive -5 dBm power over 300 ohms. If switches SWE , SWJ , and SWK are opened, then the line driver will be muted to -70dB automatically. In addition, when SWJ or SWK are turned on, there are loss at the line driver output due to single-ended to fully-differential transform. LINE_IN BUFFER : Buffer stage with selection of echo cancellation path or not. For the echo cancellation path, 3-6 dB cancellation can get it. PROGRAMABLE GAIN CONTROL (PGA) : It supports 0 to 22.5 dB gain with 16 steps and 1.5dB/step. The gain value is controlled separately by 3 registers, where different input signal paths will have a different gain value, and when the input path is changed, the respective register value will keep no change. 3 MX93000 AUTOMATIC LEVEL CONTROL (ALC) : The ALC can support 36 dB gain with the attack time and release time controlled by C6 and R3 * C6, respectively. SPK ATTENUATOR : Speaker output signal can be attenuated either by internal register or external resister. For the former, the attenuation is from 0 to -45 dB with 16 steps and -3.0dB/step. For the later, 10K ohms variable resistor is suggested. If switches SWF and SWH are open, then attenuator will be muted to -70dB automatically. SERIAL_CONTROL_INTERFACE : To read/write the internal registers. SDEN\ (serial data enable) is used to start receiving control signal. 8kHz frame sync.is used to transmit/receive the serial data (SDATA). CODEC_SERIAL_PORT : 4-pin signal will complete the data trasmitting/receiving. MCLK is not only the data rate but also the chip master clock. Currently, it is fixed at 1.536 MHz and the frame synchronization clock, Fs, is 8 kHz. For simplicity, the A/D and D/A are synchronous so that MCLK and Fs are enough. Data transfer of DX/DR are MSB first in both 8-bit and 16-bit formats. VOLTAGE REFERENCE : Two 2.25V voltage references are on-chip generated . VREF is for external and AG is for internal uses. Both two pins need the decoupling capacitors AGND at all times. VREF can be used to bias the microphone, the level shift circuits, or others. SWITCHES : There are 2 registers which are used to control all of the switches so that user can direct many different signal paths, of which 3 of them are : a) Path of normal operation MIC input --> SWA --> PGA/ALC --> SWC --> SWD --> PCM Codec Ain LOUT1/LOUT2 SWC --> SWJ --> Line Driver LINE IN --> Line Buffer --> SWI --> PCM Codec Ain c) Path of line play LINE IN --> SWA --> PGA/ALC --> SWC --> SWD --> PCM Codec Ain LOUT1/LOUT2 ATTENUATOR CHANNEL-b SPK-OUT ATTENUATOR ==> ATTENUATOR CHANNEL-a (adjusted by VR1 10Ký) 15 MX93000 REGISTER 4 : ADDRESS BIT DATA DATA BIT POWER_ON DESCRIPTION (PDN) A2 1 D7 0 A1 0 D6 0 PDN A0 0 D5 0 ECHO D4 0 D3 0 D2 0 D1 0 D0 0 MASTER CLOCK CODEC FORMAT D(6)=1 : POWER DOWN MODE. a.When D(6) is set to 1, the MX93000 will enter power down mode after 5 MCLKS. The 5_MCLK period is for the initialization of digital circuits in the MX93000. b.When the MX93000 enters power down mode, it will clear all registers after 20us. c.When system power recovers and MCLK is enabled, the MX93000 will wake up after 30ms and then user can restore all registers. up set PDN = 1 MCLK Keep Hi or Low CKTs power_on MCLK (pin 6) PDN\ (pin12) REG4 PDN bit CODEC power-consumption > 5 MCLKs 20 us 30 ms (ECHO) D(5) = (1):ECHO CANCELLER ON (3-6dB) (0):ECHO CANCELLER OFF (MASTER CLOCK) D(3,2) = (0,0): 1.536 MHz (CODEC FORMAT) D(1,0) = = = = (1,1): (1,0): (0,1): (0,0): LINEAR CODER & DECODER (16 BITS FORMAT) LINEAR CODER & DECODER (16 BITS FORMAT) A-LAW CODER & DECODER (8 BITS FORMAT) u-LAW CODER & DECODER (8 BITS FORMAT) LINEAER 16 BITS FORMAT : 14 BITS RESOLUTION with 2LSB=0 SIGN\SCALE POSITIVE NEGATIVE MIN 0000 0000 0000 0000 1111 1111 1111 1100 MAX 0111 1111 1111 1100 1000 0000 0000 0000 16 MX93000 REGISTER 5 : ADDRESS BIT DATA DATA BIT POWER-ON DESCRIPTION (ALC) D(1) = 1 : ALC loop gain attenuate 6dB D(1) = 0 : ALC loop gain attenuate 0dB @@ reserve for internal use REGISTER 6 : ADDRESS BIT DATA DATA BIT POWER-ON DESCRIPTION @@ reserve for future use REGISTER 7 : ADDRESS BIT DATA DATA BIT POWER-ON DESCRIPTION (READ) D(3) = 1 : read data from register 0-6 = 0 : write data to register 0-7 (REGISTER ADDRESS) D(2-0) : 1.When READ = 1, READ will be cleared automatically. 2.When READ = 1, next uP/DSP SDEN\ signal active low, CODEC will change CODEC SDATA interface into output and following the last time REGISTER ADDRESS to output the content of register. Note 1. :When using SWK or SWH, the path between AUX and SWA will disconnect. Oppositely, if using the path between AUX and SWA, then SWK and SWH will be invalid. A2 1 D7 0 A1 1 D6 0 A0 1 D5 0 D4 0 D3 0 READ D2 0 D1 0 D0 0 A2 1 D7 0 A1 1 D6 0 A0 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 A2 1 D7 0 A1 0 D6 0 A0 1 D5 0 D4 0 D3 0 D2 0 D1 0 ALC D0 0 REGISTER ADDRESS 17 MX93000 THE FOLLOWING LIST IS BASIC COMPONENT REQUIRED : REFERANCE R1 R2 R3 R4,R5 PART 620 ý 2 Ký 75 Ký DESCRIPTION matching resistor; to reflect 600ý at the transformer primary current-limit resistor; to limit MIC bias current ; please follow MIC specification time constant ; ALC release time constant = R3 * C6 to scale down SYSTEM power supply (VPOW) and compare with 1.25V to do power-down check to scale down BATTERY (VBAT) and compare with 1.25V to do power-down check 10Ký 10 Ký 330 Ký 200 Ký 0.1 uF 10 uF 10 uF 47 uF 1uF 1000 pF 0.1 uF 0.1 uF 10 uF 10Ký the time constant for power-on-reset circuits ; where RC=R8 * C11 current-limit resistor for Q1 discharge path for ALC circuit when Q1 turns off to attenuate line-in signal DC blocking capacitor to decouple analog virtual ground ; where AG = VREF = 2.25v DC blocking capacitor time constant ; ALC Attack time contant > 2ký ± 10% * C6 DC offset cancellation decouple capacitor anti-aliasing capacitor decoupling capacitor for power supply of Codec digital circuit decoupling capacitor for power supply of Codec analog circuit the time constant for power-on-reset circuits ; where RC = R8 * C11 to attenuate the input signal from SWH or SWF ; if using digital volume control, connecting pin-27 VR to VREF ALC feedback component ; all NPN (ß > 100) transistor can play this role to protect reset circuits from spike R6,R7 R8 R9 R10 R11 C1,C4 C2,C3 C5 C6 C7 C8 C9 C10 C11 VR1 then Q1 D1 2N3904 1N4148 18 MX93000 PIN DESCRIPTIONS : SYMBOL SDATA PIN TYPE I/O(D) PIN NUMBER 1 DESCRIPTION Bidirectional serial port ; It's an interface for microprocessor serial data transfer Serial data enable ; active low ; for starting to receive/transmit serial data (A2-D0) Transmit data pin (Codec serial data) Receive data pin (Codec serial data) Codec frame sync ; 8KHz frame synchronization clock for the transmit/receive channel Master clock input (MCLK=1.536 MHz) When this pin is continuously high or low and set register4/bit6 "PDN=1", then the MX93000 will enter power-down mode Digital power ; 5V power supply for all internal digital logic Digital ground ; ground reference (0V) for all internal digital logic Power on reset (active high) ; Determined by PDN\ and BATT\ input signal Battery detector output (active low); referenced to 1.25V Battery detector input ; the voltage is divided from battery power for reference to 1.25V Power down detector output (active low) ; referenced to 1.25V Power down detector input ; System DC power is divided and then connected so as to compare with reference voltage (1.25v) Telephone signal line input , can be switched to PGA. Telephone line output (postive) with PGA ; where PGA gain is from 0 to 22.5dB Telephone line output (negative) with PGA ; where PGA gain is from 0 to 22.5dB SDEN\ I (D) 2 DX DR FS O (D) I (D) I (D) 3 4 5 MCLK I (D) 6 VDD GND (D) (D) 7 8 PRST O (D) 9 BAT\ VBAT O (A) I (A) 10 11 PDN\ VPOW O (A) I (A) 12 13 LIN LOUT1 I (A) O (A) 14 15 LOUT2 O (A) 16 Note : "D" means digital "A" means analog 19 MX93000 SYMBOL AVDD AGND PIN TYPE (A) (A) PIN NUMBER 17 18 DESCRIPTION Analog power supply ; 5V power for all internal analog circuitry Analog ground ; ground reference(0V) for all internal analog circuitry Internal analog ground ; nominal 2.25V and must not be used to sink or source current Microphone signal input, can be switched to PGA, where PGA gain is from 0 to 22.5dB 1.Auxiliary signal input, can be switched to PGA, where PGA gain is from 0 to 22.5dB 2.As an output port for Aout or an input port for attenuator or line driver Programmable Gain Amplifier output port Auto level control time constant ; where RC=2K±10%*C6 Offset cancellation capacitor (positive) ; normally add a 1 uF capacitor 1.Anti-aliasing filter; normally add a 1000pF capacitor 2.As an input port for Codec or an output port for SWD or SWI Voltage reference ; normal 2.25V and can sink 500uA Speaker volume control ; use a variable resistor 10ký Speaker output ; it can be attenuated by VR or control register from 0 to -45dB AG O (A) 19 MIC I (A) 20 AUX I/O (A) 21 PGAC ALCRC ALCC O (A) O (A) O (A) 22 23 24 FILT I/O (A) 25 VREF VR SPK O (A) 0 (A) O (A) 26 27 28 20 MX93000 APPENDIX : MX93000 Buglist 1.A/D Full Swing : Full Swing of A/D is 3.4 Volt in stead of the original target 3.0 Volt. 2.Maximum External Attenuation of SPK through VR pin is only 27 dB. 3.Line Drive Gain: Line driver will behave as a gain loss rather than a gain loss rather than a gain stage whenever line driver inputs are come from SWK and/or SWJ. Line Driver gain if input from SWE 0.0 dB 1.5 dB 3.0 dB 4.5 dB 6.0 dB 7.5 dB 9.0 dB 10.5 dB 12.0 13.5 15.0 16.5 18.0 19.5 21.0 22.5 dB dB dB dB dB dB dB dB SWK/SWJ -9.0 dB -8.7 dB -7.6 dB -6.8 dB -6.0 dB -5.3 dB -4.6 dB -4.0 dB -3.5 -3.0 -2.6 -2.2 -1.9 -1.6 -1.4 -1.2 dB dB dB dB dB dB dB dB 4.The larger of VREF's bypass capacitor, the better of D/A idle channel noise. 100 uF rather than 10uF can get a good performance. 21 MX93000 28-PIN PLASTIC SOP (300 mil) ITEM A B C D E F G H I J K L NOTE: MILLIMETERS 17.83 max. 1.194 max. 1.27 [TP] .41 [Typ.] .20 min. 2.54 max. 2.34 ± .13 10.31 ± .31 7.60 ± .13 1.37 ± .20 .25 [Typ.] .91 ± .20 INCHES .702 max. .026 max. .047 [TP] .016 [Typ.] .008 min. .100 max. .092 ± .005 .406 ± .012 .299 ±.005 .054 ± .008 .010 [Typ.] .036 ± .008 28 15 1 A 14 H I G F K J Each lead centerline is located within .25 mm[.01 inch] of its true position [TP] at a maximum material condition. D C B E L 28-PIN PLASTIC DIP (300 mil) ITEM A B C D E F G H I J K L M NOTE: MILLIMETERS 34.29 max .64 [REF] 2.54 [TP] .46 [Typ.] 32.99 1.52 [Typ.] 3.30 ± .25 .51 [REF] 3.30 ± 2.5 3.81 max. 7.87 ± 2.5 7.32 ± 2.5 .25 [Typ.] INCHES 1.350 max .025 [REF] .100 [TP] .018 [Typ.] 1.300 .060 [Typ.] .130 ± .010 .020 [REF] .130±.098 .150 max. .310±.098 .288±.098 .010 [Typ.] F D E C B M 2~8° H G I J 1 A 14 K L 28 15 Each lead centerline is located within .25 mm[.01 inch] of its true position [TP] at a maximum material condition. 22 MX93000 ORDERING INFORMATION MX MXIC COMPONY PREFIX 93 000 K C COMMERICIAL 0 ~ 70 × C FAMILY PREFIX PACKAGE TYPE K:PDIP S:SOP PRODUCT NUMBER 23 MX93000 MACRONIX INTERNATIONAL CO., LTD HEADQUARTERS : TEL : +886-3-578-8888 FAX : +886-3-578-8887 EUROPE OFFICE : TEL : +32-2-456-8020 FAX : +32-2-456-8021 JAPAN OFFICE : TEL : +81-44-246-9100 FAX : +81-44-246-9105 SINGAPORE OFFICE : TEL : +65-747-2309 FAX : +65-748-4090 TAIPEI OFFICE : TEL : +886-2-2509-3300 FAX : +886-2-2509-2200 MACRONIX AMERICA INC. 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