MX97102

MX97102 ISDN S/T CONTROLLER FEATURES • Pin-to-Pin and Register-to-Register compatible with Siemens 2186 • Full duplex 2B+D ISDN S/T Transceiver according to CCITT I.430 • GCI digital interface • 3 types of 8-bit CPU interface • Receive timing recovery with adaptively switched thresholds • E-channel Monitoring • • • • • • • • Programmable SDS1,SDS2 D-channel access control LAPD(HDLC) support with FIFO(2x64) buffers Activation/Deactivation Multiframing with S and Q bit access CPU access to B and IC channels Watchdog timer Package types : P-LCC-44, P-LQFP-64 GENERAL DESCRIPTIONS MX97102 implements the 4-wire S/T interface used to link voice/data terminals to an ISDN. It is designed for the user site of the ISDN-basic access, two 64kbit/s B channels and a 16kbit/s D channel. MX97102 can be mainly divided into three portions according to their interfaces. Except these three interface functions, it also provides the LAPD controller which handles the HDLC packets of the ISDN D-channel for the associated microprocessor. The first, S/T interface controller, provides all electrical and logical functions of the S/T interface, such as S/T transceiver, activation/deactivation, timing recovery, multiframe S and Q channels, and D-channel access and priority control for communicating with remote equipments. The Second is the microprocessor interface controller which offers the registers compatible with Siemens PSB2186, provides three types of microprocessor interface, such as Motorola bus mode, Intel multiplexed mode and Intel non-multiplexed mode. The last portion is the GCI interface controller which is used to connect different voice/data application modules for local digital data exchangements. PIN CONFIGURATION 44-PLCC PAD7 PAD6 PAD5 PAD4 PAD3 PAD2 PAD1 PAD0 64-PLQFP PAD7 PAD6 PAD5 PAD4 PAD3 PAD2 PAD1 PAD0 NC NC NC NC NC NC 35 NC 34 NC 33 PA1 PA2 PA0 48 47 46 45 44 43 42 41 40 39 38 37 PSDS1 PSDS2 PRST PA5(EAW) VSSD PDCL PFSC1 NC VSSD ECHO PA4 7 6 1 44 40 39 PRDN(DS) PWRN(R/W) PCSN PALE PIDP1 NC PA2 PA1 PSDS1 PSDS2 PRST PA5(EAW) NC VSSD PDCL PFSC1 NC VSSD ECHO PA4 PA3 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 36 32 31 30 29 28 27 26 25 NC NC PA0 PRDN(D5) PWRN(R/W) PCSN PALE PIDP1 PIDP0 PSX2 PSX1 VDD NC NC NC NC 12 MX97102 34 PIDP0 PSX2 PSX1 VDD NC MX97102 24 23 22 21 20 19 18 17 17 18 PA3 VSSD PBCL NC NC 23 VSSA PXTAL2 PXTAL1 PSR2 PINTN 29 28 PSR1 NC 10 11 12 13 14 PSR2 15 NC NC NC NC NC NC VSSD PINTN NC PBCL VSSA PXTAL2 PXTAL1 NC P/N:PM0473 REV. 2.5, SEP. 05, 2000 1 PSR1 16 1 2 3 4 5 6 7 8 9 MX97102 BLOCK DIAGRAM Control and Data Interface signals PIDP0 PIDP1 S/T Interface LAP-D Transmitter Multiframe Activation/ control Deactivation Receiver DPLL 7.68MHZ OSC ECHO PDCL PFSC1 GCI Interface B-channel Switching FIFO WATCH DOG RESET SOURCE uP Interface PINTN microprocessor interface PRST FIGURE 2: FUNCTIONAL BLOCK DIAGRAM P/N:PM0473 REV. 2.5, SEP. 05, 2000 2 MX97102 PIN DESCRIPTION (44-PIN) TABLE 1: MX97102 PIN DESCRIPTIONS LQFP PAD# 37 38 39 40 41 42 43 44 27 28 PLCC PAD# 41 42 43 44 1 2 3 4 37 38 PIN NAME PAD0(D0) PAD1(D1) PAD2(D2) PAD3(D3) PAD4(D4) PAD5(D5) PAD6(D6) PAD7(D7) I/O DESCRIPTION Multiplexed Bus Mode:Address/data bus from the CPU system to this devic ,and data between the CPU system and this device. Non-Multiplexed Bus Mode:Data bus between the CPU system and this I/O device. PCSN I PWRN(R/W) I 29 39 PRDN(DS) I 8 1~5, 9,13,15 17~20 31~36 45~49 56,60 26 23 PINTN ChipSelect:A logic "LOW" enable this device for a read/write operation. Read/Write:A logic "HIGH" indicates a valid read operation by CPU. A logic "LOW" indicates a valid write operation by CPU.(Motorola bus mode) Write:A logic "LOW" indicates a write operation.(Intel bus mode) Data Strobe: The rising edge marks the end of a valid read or write operation (Motorola bus mode). Read:A logic "LOW" indicates a read operation.(Intel bus mode) Open Interrupt Request:The signal is a logic "LOW" when this device requests an Drain interrupt. It is an open drain output. No used. 14 NC 19,20 29,30 36 PALE 54 9 PRST 59 13 PFSC1 Address Latch Enable:A logic "HIGH" indicates an address on the address/ data bus(Multiplexed bus type only). ALE also selects the micro-processor interface type (multiplexed or non-multiplexed). I/O Reset:A logic "HIGH" on this input forces this device into reset state. The minimum pulse length is four DCL-clock periods or four ms. If the terminal specific functions are enabled,this device may also output a reset signal. O(I) Frame Sync 1:Frame sync output. Logic "HIGH" during channel 0 on the GCI interface. This pin becomes Input if Test Mode is programmed (register ADF1). O(I) Data Clock:Clock of frequency, 1536kHz output, equals to twice the GCI data rate. This pin becomes Input if Test Mode is programmed (register ADF1) O This pin output the Echo bit from the receiving line. REV. 2.5, SEP. 05, 2000 I 58 12 PDCL 62 P/N:PM0473 16 ECHO 3 MX97102 TABLE 1: MX97102 PIN DESCRIPTIONS(Continued) LQFP PAD# 30 51 50 64 63 55 PLCC PAD# 40 6 5 18 17 10 PIN NAME I/O PA0 PA1 PA2 PA3 PA4 PA5(EAW) I I I I I I 7 52,53 22 7,8 PBCL PSDS1,2 O O DESCRIPTION (non-multiplexed bus mode) Address Bit 0 Address Bit 1 Address Bit 2 Address Bit 3 Address Bit 4 Address Bit 5; External Awake, when terminal specific function en abled, this pin is used as an external awake line. If a falling edge on this input is detected, it generates an interrupt and a reset pulse. Bit Clock:Clock of frequency 768kHz equal to the GCI data rate. Serial Data Strobe 1&2 : programmable strobe signals, selecting either one or two B or IC channels on GCI interface, is supplied via this line. (registers ADF2,4) Digital ground Analog ground Power supply (5V±5%) Connection for crystal or external clock input. Connection for external crystal. Left unconnected if external clock is used. S-Bus Receiver Input S-Bus Transmitter Output(positive) S-Bus Transmitter Output(negative) GCI-Data Port 0 (DD) GCI-Data Port 1 (DU) Open drain without internal pull-up resister or push-pull. 6,57,61 10 21 12 11 14 16 22 23 24 25 11, 15 21 24 31 26 25 27 28 32 33 34 35 VSSD VSSA VDD PXTAL1 PXTAL2 I O PSR2 PSR1 I PSX1 PSX2 O PIDP0(DD) PIDP1(DU) I/O ABSOLUTE MAXIMUM RATINGS TABLE 2: ABSOLUTE MAXIMUM RATINGS RATING Maximum Supply Voltage (VDD) DC Input Voltage on any pin Storage Temperature Range VALUE 6V -0.4Vto VDD+0.4V -55° to 150° C C Operating Free Air Temperature Range 0° to 70° C C P/N:PM0473 REV. 2.5, SEP. 05, 2000 4 MX97102 DC CHARACTERISTICS TABLE 3: DC CHARACTERISTICS Temperature from 0 to 70°C; VDD = 5V±5%, VSSA = 0V, VSSD = 0V Symbol Parameter Conditions Min. Value VIL L-input voltage -0.4 VIH H-input voltage 2.0 VOL L-output voltage IOL= 2mA VOL1 L-output voltage (IDP0) IOL= 7mA VOH H-output voltage IOH= -400uA 2.4 VOH H-output voltage IOH= -100uA VDD-0.75 ILI Input leakage current 0