MX98726EC

MX98726EC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER WITH uP INTERFACE 1.0 Features • Direct interface to 80188/186 up to 40Mhz. • Integrated 10/100 TP tranceiver on chip to reduce overall cost • Optional MII interface for external tranceiver. • Fully comply to IEEE 802.3u spec. • Best fit in network printer and hub/switch management application • A local DMA channel between on-chip FIFOs and packet memory • Shared memory architecture allow host and MX98726EC to use only one single SRAM • Host DMA can share packet memory with local DMA with simple hand shake protocol for x188/186 type of processor • Supports proprietary local DMA channel to share packet memory • Support bus size configuration: - CPU : 8 bits, SRAM: 8 bits - CPU : 16 bits, SRAM: 8/16 bits • Flexible packet buffer partition and addressing space for 32k, 64k up to 512K bytes • NWAY autonegotiation function to automatically set up network speed and protocol • 3 loop back modes for system level diagnostics • Rich on-chip register set to support a wide variety of network management functions • Support 64 bits hash table for multicast addressing • Support software EEPROM interface for easy upgrade of EEPROM content • Support 1K bits and 4K bits EEPROM interface • 5V CMOS in 128 PQFP package for minimum board size application 1.1 Introduction MX98726EC ( Generic MAC , or GMAC ) is a cost effective solution as a generic single chip 10/100 Fast Ethernet controller. It is designed to directly interface 80188, 80186 ( host ) without glue logic. Two types of memory sharing schemes are supported, i.e. interleaved and shared mode to support a variety of applications. Single chip solution will help reduce system cost not only on the components but also the board size. Full NWAY function with 10/100 tranceiver will ease the field installation, simply plug the chip in and it will connect itself with the best protocol available. The interleaved mode allow uP to access SRAM ( packet/host buffer ) through MX98726EC's local DMA channel. This way, no extra SRAM interface logic is needed on the host side. If high performance is desired, then shared memory mode is another alternative which allow host to access SRAM on its own by denying SRAM bus grant to MX98726EC using simple hand shake protocol. Without SRAM bus grant, MX98726EC will float its interface connected to the SRAM, therefore host can utilize its own memory subsystem to conduct its own SRAM access. A intelligent built-in SRAM bus arbitor will manage all the SRAM access requests from host, on-chip transmit channel and on-chip receive channel. The throughput of these network channels and MX98726EC's DMA burst length can be easily adjusted by option bits on the chip. These options can help system developers to "fine tune" a best cost/performance ratio. MX98726EC is also equipped with fast back-to-back transmit capability which allow software to "fire" as many transmit packets as needed in a single command. Receive FIFO also allow back-to-back reception. Optional EEPROM can be used to stored network network address and other information. In case cost is really a concern, most configuration options including network address can be programmed through uP. P/N:PM0729 REV. 1.1, MAY. 28, 2001 1 MX98726EC 1.2 Internal Block Diagram Packet Buffer (SRAM) EPROM SRAMIU Serial ROM port Host BIU RX FIFO RX SM TX FIFO TX SM MII Interface PCS NWAY CTRL & REGS 100 TX PHY 100TX PMD interface 10Mbps MCC+TP interface Architecture and Interface overview 1.3 Typical Applications Packet buffer EPROM C46/C66 local DMA uP with dedicate bus Host side CSB decode Customer Application MX98726EC RJ45 Xformer TP cable Interleaved memory Architecture P/N:PM0729 REV. 1.1, MAY. 28, 2001 2 MX98726EC Host Memory Subsystem SRAM Bus Packet buffer EPROM C46/C66 HOLD uP with shared bus HLDA RJ45 Xformer MX98726EC TP cable CSB Decode Customer Application Shared memory Architecture 1.4 Combo Application Host Memory Subsystem Packet buffer Local DMA EPROM C46/C66 1M 8PHY or 10M 8PHY Customer Application Host CSB Decode MX98726EC RJ11 Phone Line Xformer TP Cable or RJ45 Xformer COMBO APPLICATION P/N:PM0729 REV. 1.1, MAY. 28, 2001 3 P/N:PM0729 GND MA1(EEDI) MD15 MD14 MD13 MD12 MD11 MD10 VDD MA7 MA6 MA5 MA4 MA3 EECS MA9 MA8 MA0(EECK) MA2(EEDO) MA14 GND 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 MA13 MA12 MA11 MA10 GND 128 MA15 1 102 MD9 MD8 MD7 MD6 MD5 VDD MD4 MD3 MD2 GND VDD MD1 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 MD0 MWE1B MWE0B MOEB MCSB GND LED0(TXC) LED1(TXEN) CLKIN INTB SRDY RDB WRB PSENB ALE BHEB RSTB A16(COL) A17(CRS) A18(RXDV) A19(RXC) AD8 AD9 AD10 AD11 GND 101 100 99 98 97 96 95 94 93 92 91 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 GND VDD (RXD3)MA16 (RXD2)MA17 (RXD1)MA18 (RXD0)MA19 TXD3 TXD2 TXD1 TXD0 VDDA GNDA RDA VDDA X2 CKREF(X1) GNDA GNDA VDDA GNDR VDDR RXIN RXIP VDDR GNDR GNDR VDDA TXON TXOP GNDA CPK RXT2EQ RTX VDDA GNDA GNDA VDDA 2.0 Pin Configuration and Description MX98726EC 4 MIO AD7 AD6 AD5 AD4 AD3 AD2 AD1 CSB GND HLDA VDDA HOLD GNDA GNDA C46/C66 UPTYPE1(MDC) UPTYPE0(MDIO) AD0 VDD VDD GND AD15 AD14 AD13 AD12 MX98726EC REV. 1.1, MAY. 28, 2001 MX98726EC 2.1 Pin Description : PIN# 82 49-54, 59-62, 76 70 Pin Name CLKIN AD[7:0] AD[15:8] ALE A19(RXC) Type I, TTL I/O, 4ma 56,57 I/O, 4ma 66-69 I,TTL I, TTL Description Host Clock Input : 8M to 40 Mhz. Multiplexed Address/Data Bit [7:0] : Internal pull-down Multiplexed Address/Data Bit [15:8] : Internal pull-down Address Latch Enable : Active high Host Bus Address Bit19, when on-chip tranceiver is used,it is used in A[19:16], when in MII mode, it is defined as receive clock RXC (25MHz or 2.5MHz) When this pin is used as address bit, it is internally grounded until Reg50.6 (A19A16EN bit) is set to enable decoding of this pin as address bit. Internal pull-up Host Bus Address Bit18, when on-chip tranceiver is used,it is used in A[19:16], when in MII mode, it is defined as receive data valid RXDV signal. When this pin is used as address bit, it is internally grounded until Reg50.6 (A19A16EN bit) is set to enable decoding of this pin as address bit. Internal pull-up. Host Bus Address Bit17, when on-chip tranceiver is used, it is used in A[19:16], when in MII mode, it is defined as carrier same CRS signal. When this pin isused as address bit, it is internally grounded until Reg50.6 (A19A16EN bit) is set to enable decoding of this pin as address bit. Internal pull-up. Host Bus Address Bit16, when on-chip tranceiver is used, it is used in A[19:16], when in MII mode, it is defined as collision COL signal. When this pin is used as address bit, it is internally grounded until Reg50.6 (A19A16EN bit) is set to enable decoding of this pin as address bit. Internal pull-up. Host Read Strobe: Active low. Internal pull-up Host Write Strobe : Active low. Internal pull-up Host Interrupt Output : Polarity can be programmed, default is active low. For active Low interrupt application, external pull-up is reguired. For active high interrupt application, external pull-down is required. Host Byte High Enable : Internal pull-up. BHEB A0 Function 0 0 Word Transfer 0 1 Upper Byte Transfer 1 0 Lower Byte Transfer 1 1 Lower Byte Transfer Synchronous Host Ready Output : Active high synchronized to CLKIN to indicate data is ready to be transferred. Initially low at the beginning of a host cycle. Chip Select : Active low, used to enable GMAC to decode host address. When high, no host cycle is recognized by MAC. Host Memory/IO cycle indicator : Set for memory access and reset for IO access. Internal pull-up. Decode of MIO can be disable by DISMIO register bit. Default is enabled. REV. 1.1, MAY. 28, 2001 71 A18(RXDV) I,TTL 72 A17(CRS) I,TTL 73 A16(COL) I,TTL 79 78 81 RDB WRB INTB I, TTL I, TTL O/D, 4ma 75 BHEB I,TTL 80 SRDY O, 4ma 47 48 CSB MIO I, TTL I, TTL P/N:PM0729 5 MX98726EC 45 HOLD O, 4ma Packet Memory Bus Hold Request : Active high to request Host to "float" its interface of the packet memory. Host grants the packet buffer bus to MX98726EC by asserting HLDA = 1. Packet Memory Bus Hold Acknowledge: Packet buffer bus is granted to MX98726EC. If HLDA=0 then MX98726EC will float its interface on the packet buffer. Internal pull-up. Host Program Strobe Enable : Active low to indicate current cycle is a ROM access and MX98726EC will not decode this ROM cycle. PSENB must high for packet memory access. Internal pull-up. Host Reset Input : Active low, Schmitt trigger input, Internal pull-up. 46 HLDA I, TTL 77 PSENB I, TTL 74 RSTB I,TTL Packet Buffer Interface : PIN# Pin Name Type O,4ma I/O, 4ma I/O, 4ma I/O, 4ma I/O, 4ma I/O,4ma Description Memory Address Bit 19-0: If HLDA = 0 then all these address lines are tristated. Memory Address Bit19, when on-chip tranceiver is used, it is defined as MA19, while in MII mode, it is used as receive data bit RXD0 pin. Memory Address Bit18, when on-chip tranceiver is used, it is defined as MA18, while in MII mode, it is used as receive data bit RXD1 pin. Memory Address Bit17, when on-chip tranceiver is used, it is defined as MA17, while in MII mode, it is used as receive data bit RXD2 pin. Memory Address Bit16, when on-chip tranceiver is used, it is defined as MA16, while in MII mode, it is used as receive data bit RXD3 pin. Memory Data Bit 15-0 : Internal pull-down. 1, MA[19:3] 115-119 7 MA19(RXD0) 6 5 4 MA18(RXD1) MA17(RXD2) MA16(RXD3) 90-96, MD[15:0] 98-104, 106-109 114 MA2(EEDO) 1/O,4ma 113 MA1(EEDI) 1/O,4ma 111 MA0(EECK) 1/O,4ma 87 86 88, 89 P/N:PM0729 MOEB MCSB MWEB[1:0] O,4ma O,4ma O,4ma Memory Address Bit 2 or EEPROM Data Out bit: Right after host reset, GMAC automatically load configuration information from external EEPROM. During this period, MA2 pin acts as a EEDO pin that read in output data stream from EEPROM. After EEPROM auto load sequence is done, this pin becomes MA2 together with MA[19:3] forms packet buffer address line 19 - 0. Internally pull-down. Memory Address Bit 1 or EEPROM Data In bit: During EEPROM auto load sequence, MA1 pin acts as EEDI pin that write data stream into EEPROM. After EEPROM auto load sequence is done, this pin becomes MA1, together with MA[19:2] forms packet buffer address lines. Memory Address Bit 0 or EEPROM Clock Input : During EEPROM auto load sequence, MA0 pin acts as EECK pin that provides clock to EEPROM. After EEPROM auto load sequence is done, this pin becomes MA0, together with MA[19:1] forms packet buffer address lines. Memory Output Enable: Active low during packet buffer read access. Memory Chip Select: Active low during packet buffer accesses. Byte Write Enable: Active low during packet buffer write cycle. MWEB1 for high byte and MWEB0 for low byte. REV. 1.1, MAY. 28, 2001 6 MX98726EC 10/100 Tranceiver interface : PIN# 14 17 16 23 24 29 30 32 33 34 Pin Name RDA CKREF(X1) X2 RXIN RXIP TXON TXOP CPK RTX2EQ RTX Type O I, TTL O I I O O O O O Description RDA external resistor to ground: 10K ohm, 5% 25Mhz , 30 PPM external osc./crystal input : 25Mhz , 30 PPM external crystal output : Twisted pair receive differential input: support both 10/100 Mbps speed Twisted pair receive differential input: support both 10/100 Mbps speed Twisted pair transmit differential output: support both 10/100 Mbps speed, meet 802.3/802.3u spec. Twisted pair transmit differential output: support both 10/100 Mbps speed, meet 802.3/802.3u spec. NC pin : used in test mode only RTX2EQ external resistor to ground: 1.4K ohm, 5% RTX external resistor to ground: 560 ohm, 5% Miscellaneous : PIN# 110 44 84 Pin Name EECS C46/C66 LED0(TXC) Type O,2ma I,TTL I/O,16ma Description EEPROM Chip Select Signal : Active high EEPROM Size Select : Set for C46, reset for C66. Internal pull-up. LED0 (TXC in MII mode) : When on-chip tranceiver is used, it is defined as SPEED LED. When the light is on, it indicates the 100 Mbps speed. When off, it indicates the 10 Mbps speed. When both LED0 and LED1 are flashing identically, it means the bus integrity error. (Internal pull-up). When in MII mode, this pin is defined as transmit clock TXC (25 MHz or 2.5 MHz) input. LED1 (TXEN in MII mode) :When on-chip tranceiver is used, it is defined as Link/Activity LED. When the light is stable and on, it indicates a good link. When flashing, it indicates TX and RX activities. When off, it means a bad link. (Internal pull-up). When in MII mode, this pin is defined as transmit enable TXEN pin. uP type select control bit 1-0: UPTYPE1 and UPTYPE0 must be externally pull-up or down through < 4.7K ohm resistors to configure the bus interface for different uP. UPTYPE1 UPTYPE0 uP selected 0 0 reserved 0 0 1 80x1 1 0 80188 1 1 80186 uP type select control bit 0 ( MDIO in MII mode ): UPTYPE0 is internally pull-down and used as uP type selection during host reset ( RSTB=0 ). After host reset sequence is completed, this pin become MDIO pin if MII mode is selected. uP type select control bit 1 ( MDC in MII mode ) : UPTYPE1 is internally pull-down, after host reset sequence is completed , this pin become MDC clock output pin if MII mode is selected. REV. 1.1, MAY. 28, 2001 83 LED1(TXEN) O,16ma 42,43 UPTYPE0, I,TTL 42 UPTYPE0( MDIO) I/O,TTL 43 UPTYPE1(MDC) I/O, TTL P/N:PM0729 7 MX98726EC Vdd/Gnd Pins : PIN# 12,15,20,28,35,38,40 13,18,19,31,36,37,39,41 22,25 21,26,27 3,58,63,92,97,120 2,55,64,65,85,93,105,112,128 Pin Name VDDA GNDA VDDR GNDR VDD GND Description Analog Vdd Pins : Must be carefully isolated in a separted vdd plane. Analog Ground Pins : Must be carefully isolated in a separted ground plane. RX Vdd Pins : Must be carefully isolated in a separted Vdd plane. RX Ground Pins : Must be carefully isolated in a separted ground plane. Digital Vdd Pins : Must be carefully isolated in a separted Vdd plane. Digital Ground Pins : Must be carefully isolated in a separted ground plane. P/N:PM0729 REV. 1.1, MAY. 28, 2001 8 MX98726EC 3.0 Register (Default value is defined after hardware/power-up reset) Reset logic : All register bits are cleared by hardware reset, while register bit with an "*" in its symbol name is also cleared by software reset. Network Control Register A : NCRA (Reg00h),R/W, default=00h Bit 0.0 0.1 0.2 Symbol RESET ST0* ST1* Description Software reset. Start Transmit Command/Status : Write to issue commands. When done, both bits are cleared automatically. Transmit command : ST1 IDLE state 0 TX DMA Poll 0 TX FIFO Send 1 TX DMA Poll 1 ST0 0 Read to indicate TX DMA idle state, write has no effect. 1 Start TX DMA, send packets stored in packet memory. 0 Immediately send the packet stored in the TX FIFO. 1 Start TX DMA, send packets stored in packet memory. All transmit commands are cleared to 00 when the operation is done to indicate idle state. When the TX DMA poll and the TX FIFO Send can not be used at the same time. New packet can be written to the FIFO directly only when ST1, ST0=IDLE and TXDMA[3:0]=1h. The TX DMA poll and the TX FIFO Send commands can be issued only when ST1, ST0=IDLE and TXDMA[3:0]=1h, regardless of any error status in previous transmission. 0.3 0.4, 0.5 SR* LB0*,LB1* Start Receive: Enable the MAC receive packets. Default is disabled. Loopback Mode: LB1 LB0 Mode0 0 0 Normal mode Mode1 0 1 Internal FIFO Loopback Mode2 1 0 Internal NWAY Loopback Mode3 1 1 Internal PMD Loopback Mode 2 and 3 are reserved for IC test purpose. Only mode 1 can be used on bench. External loopback for bench can be done by full duplex normal mode with real cable hooked up from TX port to RX port. Interrupt Mode: Set for active high interrupt, reset for active low interrupt case. Clock Select : Set to use internal 40MHz clock for all internal DMA, default is reset to use internal 50MHz clock for all internal DMA. 0.6 0.7 INTMODE CLKSEL P/N:PM0729 REV. 1.1, MAY. 28, 2001 9 MX98726EC Network Control Register : NCRB (Reg01h),R/W, default=01h Bit 1.0 1.1 1.2 Symbol PR* CA* PM* Description Promiscuous mode: Set to receive any incoming valid frames received, regardless of its destination address. Default is set. Capture Effect Mode: Set to enable an enhanced backoff algorithm to avoid network capture effect. Pass Multicast: Set to accept all multicast packets including broadcast address ( 1st bit in destination address is 1 ), default is reset Pass Bad Frame: Enable GMAC to accept Runt frame. Default is reset. Accept Broadcast: Default is reset. Set to accept all broadcast packets. Reserved for test purpose. Default is 0. Must be 00. 1.3 PB* 1.4 AB* 1.5 HBD* Reserved P/N:PM0729 REV. 1.1, MAY. 28, 2001 10 MX98726EC GMAC Test Register A : TRA (Reg02h),R/W, default=00h Bit 2.0 2.1-2.3 Symbol TEST TMODE[2:0] Description Test mode enable: Set to enable test modes defined by TMODE[2:0], default is reset for normal operation. Test Mode Select bits[2:0]: Reserved for GMAC's internal tests, only meaningful when the TEST bit is set, except when TMODE [2:0] = "110" which is also used as normal mode with EEPROM interface disabled. When TMODE [2:0] = "110" & Test =0, then MA19~MA16 are still SRAM address bit19~16, while Test = 1, MA19~MA16 are defined as test pins reserved for debug purpose. Receive Watchdog Release : When set, the receive watchdog is released 40 to 48 bit times from the last carrier deassertion. When reset, the receive watchdog is released 16 to 24 bits times from the last carrier deassertion. Receive Watchdog Disable : When set, the receive watchdog is disabled. When reset, receive carriers longer than 2560 bytes are guaranteed to cause the watchdog timeout. Packets shorted than 2048 bytes are guaranteed to pass. Forced Collision : Set to force collision at every transmit packet, this bit works only in internal FIFO loopback mode, i.e. LB0=1, LB1=0, to test excessive collision. Default is reset. Start/Stop Backoff counter: When set, indicates internal backoff counter stops counting when any carrier is detected. Counter resumed when carrier drops. When reset, the internal backoff counter is not affected by carrier activity. Default is reset. 2.4 RWR 2.5 RWD 2.6 FC 2.7 SB GMAC Test Register : TRB (Reg03h),R/W, default=00h Bit 3.0 Symbol FKD* Description Flaky Oscillator Disable: When set, indicates that the internal flaky oscillator is disabled. Pseudo random numbers are chosen instead of fully random numbers, used for the internal diagnostic purpose. Set to disable the normal clocking scheme in the timer's test. Reset to enable the timer test. Default is reset. Reserved for test Reserved for test Reserved for test Normally used as BFS0 pin for test purpose, while in MII mode, it is defined as MII management clock signal (MDC) to be used as a timing reference of MDIO pin. Normally used as BKCNTLB pin for test purpose, while in MII mode, it is used to control the direction of MDIO pin. Set MDIOEN = 1 will make MDIO pin as input pin, the value can be read from MDI bit. Set MDIOEN = 0 will make MDIO pin as output pin, the value of MDO bit is driven out to MDIO pin. Normally used as BFS1 pin for test purpose, while in MII mode, it is used as MII management write data (MDO) for MDIO pin's output data. Normally used as BFSTATUS pin for test purpose, while in MII mode, it is used as MII management read data (MDI) for MDIO pin's input data. REV. 1.1, MAY. 28, 2001 3.1 3.2 3.3 3.4 RDNCNTCB* RDNCNTSB* COLCNTCB* BFS0*(MDC) 3.5 BKCNTLB*(MDIOEN) 3.6 3.7 BFS1*(MDO) BFSTATUS*(MDI) P/N:PM0729 11 MX98726EC Last Transmitted Packet Status: LTPS ( Reg04h), RO, default=00h Bit 4.0 4.1 4.2 4.3 Symbol CC0* CC1* CC2* CC3* Description Collision Count Bit 0 : Collision Count Bit 1 : Collision Count Bit 2 : Collision Count Bit 3 : when CC[3:0] = 1111 and a new collision is detected, then it is called excessive collision error which will abort the current packet, TEI interrupt bit will be set. Carrier Sense Lost : Set to indicate CRS was lost during the transmission, default is reset for normal packet transmission. TX FIFO underflow : Set to indicate a underflow problem in TX FIFO an FIFOEI interrupt is generated for driver to resolve this problem. Out of Window Collision : Set to indicate an collision occured after 64 bytes of data has been transmitted, no retransmission will be issued Transmit Error: Set to indicate packet transmitted with error, reset for normal packet transmission. 4.4 4.5 4.6 4.7 CRSLOST* UF* OWC* TERR* Last Received Packet Status: LRPS ( Reg05h), RO, default=00h Bit 5.0 5.1 5.2 5.3 5.4 5.5 5.6 5.7 Symbol BF* CRC* FAE* FO* RW* MF* RF* RERR* Description RX Packet Buffer Full Error : 1 indicates RX packet buffer is full. CRC error : Calculation is based on integer multiple of bytes, set to indicate CRC error for received packet. Frame Alignment Error : Set to indicate extra nibble is received which is not at octet boundary. This error is independent of CRC detection. FIFO overrun : When set, an interrupt is generated, driver must resolve this error. Receive Watchdog : Set to indicate the frame length exceeds 2048 bytes. An interrupt will be generated to driver. Multicast address : Set to indicate current frame has multicast address. Runt Frame : Set to indicate a frame length less than 64 bytes, only meaningful when Reg01h.3 PB bit =1 is set. Receive Error : Set to indicate a packet received with errors including CRC, FAE, FO, RW, ( RF and PB=1 ). Notes : This LRPS register contains the same status byte as in the description field of the last received packet in the packet memory. Missed Packet Counter: MPC (Reg07/06h), R/W, default=0000h Bit 6.7-0 7.7-0 Symbol MISSCNT[7:0]* MISSCNT[15:8]* Description Miss Packet Counter Bit [7:0]: Lower byte of Miss packet counter Miss Packet Counter Bit [15:8]: Upper byte of Miss packet counter P/N:PM0729 REV. 1.1, MAY. 28, 2001 12 MX98726EC Interrupt Mask Register: IMR (Reg08h), R/W, default=00h Bit 8.0 Symbol CNTOFIM Description Miss Counter Over Flow Interrupt Mask : Set to enable Miss counter overflow interrupt, default is reset. When Overflow condition of the miss packet counter occures, counter is halt and driver need to resolve this condition in order to reset the counter if counter is ever used. Received Interrupt Mask: Set to enable Packet Received Interrupt, default is reset which disable RI interrupt. Transmit Interrupt Mask: Set to enable Packet transmit OK interrupt, default is reset which disable TI interrupt. Receive Error Mask: Set to enable Receive Error interrupt, default is reset which disable RXEI interrupt. Transmit Error Mask: Set to enable transmit error interrupt, default is reset which disable TXEI interrupt. FIFO Error Interrupt Mask: Set to enable FIFO Error interrupt, default is reset which disable FIFOEI interrupt. Bus Error Interrupt Mask: Set to enable Bus Error interrupt, default is reset which disable BUSEI interrupt. RX Buffer Full Interrupt Mask: Set to enable RX Buffer full interrupt, default is reset which disable BFI interrupt. 8.1 8.2 8.3 8.4 8.5 8.6 8.7 RIM TIM RXEIM TXEIM FIFOEIM BUSEIM RBFIM Interrupt Register: IR (Reg09h), R/W, default=00h Bit 9.0 9.1 9.2 9.3 9.4 9.5 9.6 9.7 Symbol CNTOFI* RI* TI* REI* TEI* FIFOEI* BUSEI* RBFI* Description Miss Counter Over Flow Interrupt : Set to assert interrupt when Miss packet counter is overflow, write 1 to this bit will clear the bit and interrupt, write 0 has no effect. Receive OK interrupt : Set to assert interrupt, write 1 to this bit will clear the bit and interrupt, write 0 has no effect Transmit OK interrupt: Set to assert interrupt, write 1 to this bit will clear the bit and interrupt, write 0 has no effect Receive Error Interrupt: Set to assert interrupt when packet is received with error , write 1 to this bit will clear the bit and interrupt, write 0 has no effect Transmit Error Interrupt : Set to assert interrupt when packet is transmitted with error, write 1 to this bit will clear the bit and interrupt, write 0 has no effect FIFO Error Interrupt: Set to assert interrupt when either TX FIFO is overrun or RX FIFO is overrun, write 1 to this bit will clear the bit and interrupt, write 0 has no effect Bus Error Interrupt: Set to assert interrupt when Bus integrity check is enabled and failed. Write 1 to this bit will clear the bit and interrupt, write 0 has no effect RX Buffer Full Interrupt: Set to assert interrupt when RX buffer area is being overwritten by new received packets, write 1 to this bit will clear the bit and interrupt, write 0 has no effect Note : All page pointer bit [11:0] are mapped to MA[19:8] in the same bit ordering. P/N:PM0729 REV. 1.1, MAY. 28, 2001 13 MX98726EC Boundary Page Pointer Register: BP (Reg0Bh/0Ah), R/W, default=x000h Bit 0A.7-0, 0B.3-0 Symbol BP[11:0] Description Boundary Page Pointer between tx/rx buffer: page TLBP[11:0] to page BP[11:0] is tx buffer. page BP[11:0] to RHBP[11:0] is rx buffer. BP[11:0] is mapped to MA[19:8]. MSB bit is Reg0BH.3 bit. LSB is Reg0AH.0 bit. TX Low Boundary Page Pointer Register: TLBP (Reg0Dh/0Ch), R/W, default=x000h Bit 0C.7-0, 0D.3-0 Symbol TLBP[11:0] Description TX Low Boundary Page Pointer : Points to the first page of transmit buffer ring. It's a static pointer that is used by GmAC to link to the last page pointed by boundary pointer. TLBP[11:0] MSB bit is Reg0Fh.3 bit. LSB is Reg0Ch.0 bit. Transmit Buffer Write Page Pointer : TWP (Reg.0Fh/0Eh), R/W, default=x000h Bit 0E.7-0, 0F.3-0 Symbol TWP[11:0] Description Transmit Buffer Write Page Pointer: TWP[11:0] are mapped to MA[19:8] with the same bit ordering. The MSB is the Reg0Fh.3 bit. The LSB is the Reg0Eh.0 bit. TWP is normally controlled by the device driver. An internal Byte Counter (TWPBC) is associated with this page register. IO Base Page Register: IOB (Reg11h/10h), R/W, default=x000h Bit 10.7-0, 11.3-0 Symbol IOB[11:0] Description IO Base Address Register: On-chip register IO base address register. This page address register defines the base page address of all on-chip registers in a IO address space.(00h-FFh). MIO=0 and CSB=0 will force GMAC to decode IO address for on chip register access. if MIO=1 and CSB=0, then all on chip registers are localed in memory page 0. IOB register is mapped to physical address [19:8] during decoding. IOB is 0000h after Reset, software can assign new base address by writing new page number to this register. Transmit Buffer Read Page Pointer Register: TRP (Reg13h/12h), R/W, default=x000h Bit 12.7-0, 13.0-3 Symbol TRP[11:0] Description The Page Index of transmit buffer read pointer: Current transmit read page pointer. MSB bit is Reg13h.3 bit. LSB is Reg12h.0 bit. TRP is controlled by GMAC only. An internal Byte Counter (TRPBC) is associated with this page register. P/N:PM0729 REV. 1.1, MAY. 28, 2001 14 MX98726EC Receive Interrupt Timer: RXINTT (Reg15h/14h), R/W Bit 14.7-0, 15.7-0, Symbol RXINTT[7:0], RXINTT[15:8] Description Receive Interrupt Timer: Default is 0000h "not used". Receive Buffer Write Page Pointer Register: RWP (Reg17h/16h), R/W, default=x000h Bit 16.7-0, 17.0-3 Symbol RWP[11:0] Description Receive Buffer Write Page Pointer: Current receive write page pointer. MSB bit is Reg17h.3 bit. LSB is Reg16h.0 bit. This register is controlled by GMAC only. An internal Byte Counter (RWPBC) is associated with this page register. Receive Buffer Read Page Pointer Register: RRP ( Reg19h/18h), R/W, default=000h Bit 18.7-0, 19.0-3 Symbol RRP[11:0] Description Receive Buffer Read Page Pointer: MAC current receive read page pointer. RRP[11:0] is mapped to MA[19:8]. MSB bit is Reg19h.3 bit. LSB is Reg18h.0 bit. This register is normally controlled by device driver. An internal byte Counter (RRPBC) is associated with this page register. 64K Memory Bank Address : Reg19h (R/W), default=0h Bit 19.7-4 Symbol BANK[3:0] Description Reserved : Default is 0000 RX High Boundary Page Pointer Register: RHBP ( Reg1Bh/1Ah), R/W, default=x000h Bit 1A.7-0. 1B.0-3 Symbol Description RHBP[11:0] Receive High Boundary Page Pointer : RX packet buffer is defined as between RHBP [11:0] and BP[11:0]. MSB bit is Reg1Bh.3 bit. LSB is Reg1Ah.0 bit. P/N:PM0729 REV. 1.1, MAY. 28, 2001 15 MX98726EC EEPROM Interface Register: Reg1Ch, R/W, default=00h Bit 1C.0 1C.1 1C.2 1C.3 1C.4 1C.5 1C.6 1C.7 Symbol EECS* EECK* EEDI* EEDO* EESEL* EELD* HOLDREQ HLDAACK Description Chip select output to external EEPROM clock device Serial clock output to external EEPROM clock device,