EVB83100-01

MLX83100 Automotive 2-Phase DC Pre-Driver Datasheet 1. Features and Benefits   2-phase DC gate driver  Level shifting between MCU PWM outputs and 2 external half-bridges  Compatible with 3.3V-5V microcontrollers  Supported supply voltage range       Absolute maximum rating: 45V Operating range: 4.5V-28V 12V-28V Battery systems Automotive qualified for 12V Sleep mode with current 150˚C the extended temperature range is only allowed for limited period of time. The application mission profile has to be agreed by Melexis. Some analog parameters may drift out of limits, but chip functionality is guaranteed. REVISION 5.11 – OCTOBER 2021 3901083100 Page 7 of 42 MLX83100 Automotive 2-Phase DC Pre-Driver Datasheet 10. General Electrical Specifications General electrical specifications valid for TJ = [-40, 150]°C and VSUP = [7, 18]V, unless otherwise specified Parameter Symbol Condition Min. Typ. Max. Unit No.1 Supply voltage range VSUP  Functional 7 - 18 V No.2 Supply voltage extended range low VSUP_ERL  Functional w. decreased gate drive voltage 4.5 - 7 V Supply voltage extended range high VSUP_ERH 18 - 28 V No.4 Quiescent current from VSUP ISUP_SLEEP  VDD = Low - - No.5 Operating current from VSUP ISUP_INT  Pre-driver operation 25kHz PWM, no load - - 5 mA No.6 Supply over voltage high VSUP_OVH  Warning on ICOM - - 35 V No.7 Supply over voltage low VSUP_OVL  ICOM released 30 - - V 0.4 - 1 V - - 2 µs Power Supply VSUP No.3 No.8 Supply over voltage hysteresis VSUP_OVHY 30 100 (TJ>150C) µA No.9 Supply over voltage debounce time VSUP_OV_DEB No.10 Supply under voltage high VSUP_UVH  ICOM released - - 6 V No.11 Supply under voltage low VSUP_UVL  Warning on ICOM 5 - - V No.12 Supply under voltage hysteresis VSUP_UVHY 0.2 - 0.5 V - - 10 µs No.13 Supply under voltage debounce time VSUP_UV_DEB VPOR  Reset released on rising edge VSUP when VDD=high 2.6 - 4.5 V No.15 Current from VBATF IVBATF  Pre-driver not in sleep  Max. value for 2VVDSMON - - 1002 µA No.104Quiescent current from VBATF IVBATF_SLEEP  Pre-driver in sleep mode  VSUP, VBATF ≤ 16V `- - 12 µA No.14 Power on reset level VVBATF 2 From DDA-version only. Preliminary, safe specification, to be confirmed by product verification during safe launch. REVISION 5.11 – OCTOBER 2021 3901083100 Page 8 of 42 MLX83100 Automotive 2-Phase DC Pre-Driver Datasheet Temperature Warning No.16 Over temperature high OVTH  Warning on ICOM - 185 - C No.17 Over temperature low OVTL  ICOM released - 168 - C fOSC  Internal Oscillator 6.8 8 9.2 MHz On-Chip Oscillator No.18 Oscillator frequency Charge Pump CP, VBOOST No.19 Output slew rate VCP - 100 - V/µs No.20 Charge pump frequency fCP 170 200 230 kHz 5 12 13 V 6 8 - MOhm VBOOST_UVH ICOM released  CP Mode 0 (V BOOST)  CP Mode 1 (V BOOST-VSUP) 6.1 - 7.2 V VBOOST_UVL Warning on ICOM  CP Mode 0 (V BOOST)  CP Mode 1 (V BOOST-VSUP) 5.6 - 6.7 V No.25 VBOOST discharge stop VBOOST_DISST  CP Mode 1 (V BOOST-VSUP)  Discharge activated by VSUP_OV and topped by VBOOST_DIS_STOP VSUP -0.2 - VSUP +0.8 V No.26 VBOOST discharge current IBOOST_DIS - 90 mA No.21 Reverse polarity N-FET gatesource voltage (VBOOST-VSUP) Resistive load from VBOOST to No.22 GND No.23 VBOOST under voltage high No.24 VBOOST under voltage low REVISION 5.11 – OCTOBER 2021 3901083100 VGS_RPFET  CP Mode 1  VSUP > 7V  IREG < 20mA  RTyp at room temperature RBOOST_LEAK  RMin at 150C TJ  (excl. RVREG_LEAK) OP  CP Mode 1 (V BOOST-VSUP)  From VBOOST to DGND 25 20 (TJ>150C) Page 9 of 42 MLX83100 Automotive 2-Phase DC Pre-Driver Datasheet Driver Supply VREG IREG_CPMODE0  VREG > 11V  CP Mode 0, EN_CP = 1 - - 40 mA IREG_CPMODE1  VREG > 11V  CP Mode 1, EN_CP = 1 - - 20 mA  CP Mode 0, EN_CP = 1  VSUP > 8V  IREG < 40mA 11 12 13 V  CP Mode 0, EN_CP = 1  7V< VSUP < 8V  IREG < 40mA 10 - 13 V  CP Mode 1, EN_CP = 1  VSUP > 8V  IREG < 20mA 11 12 13 V  RMin at 150C TJ 0.3 0.4 - MOhm No.27 Load current on VREG No.28 Output voltage VREG VREG  RTyp at room temperature No.29 Internal resistive load from VREG to GND RVREG_LEAK No.30 VREG over voltage high VREG_OVH  Warning on ICOM 14.2 - 16.5 V No.31 VREG over voltage low VREG_OVL  ICOM released 13.5 - 15.8 V No.32 VREG over voltage hysteresis VREG_OVHY 0.65 - 1.5 V No.33 VREG under voltage high VREG_UVH  ICOM released 7.2 - 8.1 V No.34 VREG under voltage low VREG_UVL  Warning on ICOM 6.9 - 7.8 V 0.3 - 0.7 V 4 - 7 mA 200 300 370 kOhm 3 - 5.5 V No.35 VREG under voltage hysteresis VREG_UVHY Digital Supply VDD  Incl. ICOM current sourcing No.36 VDD operating current IDD No.37 VDD pull down resistance VDD_RPD No.38 VDD input voltage VDD  VDD = 3.3V or 5V No.39 VDD under voltage high VDD_UVH  ICOM released 2.55 - 2.95 V No.40 VDD under voltage low VDD_UVL  Warning on ICOM 2.45 - 2.85 V No.41 VDD under voltage hysteresis VDD_UVHY 0.08 0.10 0.14 V No.42 VDD sleep voltage high VDD_SLEEPH  Out of sleep 2.1 - 2.7 V No.43 VDD sleep voltage low VDD_SLEEPL  Go to sleep 1.6 - 2.1 V No.44 VDD sleep voltage hysteresis VDD_SLEEPHY 0.45 0.58 0.80 V REVISION 5.11 – OCTOBER 2021 3901083100 Page 10 of 42 MLX83100 Automotive 2-Phase DC Pre-Driver Datasheet Gate Drivers No.45 Rise time No.46 Fall time Pull-up ON resistance low-side pre-driver No.47 Pull-up ON resistance high-side pre-driver No.48 RON_UP Pull-down ON resistance high-side pre-driver Turn-off gate drive peak current (sinking)  CLOAD = 1nF, 20% to 80%  CLOAD = 1nF, 80% to 20%  VSUP > 7V  -10mA, T J = -40C  -10mA, TJ = 175C  VSUP > 7V Pull-down ON resistance low-side pre-driver No.49 Turn-on gate drive peak current (sourcing) No.50 tr tf RON_DN IGON IGOFF  10mA, TJ = -40C  10mA, TJ = 175C 6 4 7 7 15 15 ns ns 10 - 30 Ohm 15 - 30 Ohm 10 - 15 - 30 Ohm - -0.45 A - 0.45 A  VGS = 0V, VSUP > 7V  VGS = 12V, VSUP > 7V 30 Ohm 40 (TJ>150C) tPDDRV  From logic input threshold to 2V V GS drive output at no load 20 - 150 ( TJ>150C) ns tPDDRVM  Transitions at the different phases at no load condition -20 - 20 ns Programmable dead time : asynchronous internal delay No.53 between high-side and lowside pre-driver of one half bridge tDEAD  DEAD_TIME [ 2:0] = 000 001 010 011 100 101 110 111 -25% 0.00 0.51 0.80 1.10 1.67 2.30 3.40 6.90 +25% µs No.54 Dead time matching between different channels tDEAD_TOL -15 - 15 % 0.40 0.60 0.85 1.05 1.25 1.50 Disabled 0.50 0.75 1.00 1.25 1.50 1.75 0.60 0.90 1.15 1.45 1.75 2.00 No.51 Propagation delay No.52 Propagation delay matching Programmable drain-source No.55 voltage for monitoring of external N-FETs 3 VVDS_MON  VDSMON[2:0] = 001 010 011 100 101 110 1203 000 V For bare die it is specified to 200ns max due measurement accuracy at wafer level REVISION 5.11 – OCTOBER 2021 3901083100 Page 11 of 42 MLX83100 Automotive 2-Phase DC Pre-Driver Datasheet 111 1.70 2.00 2.30 Programmable drain-source monitor blanking time: Delay No.56 between gate high and tVDS_BL enabling corresponding VDS monitor VDS_BLANK_TIME[1:0] = 00 01 10 11 5.10 2.55 1.28 0.60 6.80 3.40 1.70 0.80 8.50 4.25 2.13 1.00 µs No.57 Sleep gate discharge resistor Rsgd  Internal resistance between FET gate-source pins to switch-off FET. VDD = 0V (sleep mode)  VGS = 0.5V - - 1 kOhm No.58 Trickle charge pump current capability ITCP      - - No.59 VGS under voltage threshold high VGS_UVH  ICOM released 42 - 70 %VREG No.60 VGS under voltage threshold low VGS_UVL  Warning on ICOM 36 - 63 %VREG No.61 PWM frequency fDR_PWM - 20 100 kHz No.62 Leakage from CPx - PHASEx RCP_LEAK 0.5 1 - MOhm No.63 VCPx discharge current IBOOST_DIS  Activated by VSUP_OVH  From VCPx to VPHASEx 8 - 40 mA No.64 Digital input high voltage VIN_DIG_H  Min. voltage logical high  FETBx & FETTx-pins 80 - - %VDD No.65 Digital input low voltage VIN_DIG_L  Max. voltage logical low  FETBx & FETTx-pins - - 20 %VDD No.66 Input pull-up resistance RIN_DIG_PU  FETBx-pins  MISO-pin, in normal mode 90 - 410 kOhm No.67 Input pull-down resistance RIN_DIG_PD  FETTx-pins 90 - 410 kOhm No.104 MISO RDSon pull-down RON_PD_MISO  MISO-pin, in SPI mode 0.5 1.1 3.4 kOhm No.105 MISO RDSon pull-up RON_PU_MISO  MISO-pin, in SPI mode 1.3 2.0 3.2 kOhm No.106 MISO source current IMISO_SOURCE  MISO-pin, in SPI mode - 3 6 mA No.107 MISO sink current IMISO_SINK  MISO-pin, in SPI mode - 3 6 mA VSUP > 12V PHASEx = VSUP VGSx = VPHASEx + 6.5V ITCP,max @ TJ = 150C See performance graphs  RTyp at room temperature  RMin at 150C TJ -25 -20 (TJ>150C) µA Logic IO’s - FET inputs, MISO REVISION 5.11 – OCTOBER 2021 3901083100 Page 12 of 42 MLX83100 Automotive 2-Phase DC Pre-Driver Datasheet Logic IO’s - EN input R_EN_PD  EN ENPR_DEL  From bridge disable EN VREG + 2xVf, diode. An alternative mode of operation for the charge pump supports the use of an external low drop N-FET for reverse polarity protection. In this mode the charge pump boosts the output voltage relative to the supply voltage instead of relative to ground, see application diagram in Figure 4-2. The disadvantage is an additional amount of dissipation inside the driver to regulate VREG. The charge pump architecture is a supply voltage doubler with feedback loop for stable output voltage generation, as shown in Figure 12-2. It can be configured in EEPROM to either regulate the boosted output voltage VBOOST relative to ground or relative to the supply voltage, see Figure 12-3 for the typical output voltage. Furthermore the EEPROM configuration allows disabling the charge pump for applications not requiring the low voltage operation, in order to reduce the overall power consumption. REVISION 5.11 – OCTOBER 2021 3901083100 Page 18 of 42 MLX83100 Automotive 2-Phase DC Pre-Driver Datasheet For safety reasons the pre-driver provides integrated under voltage detection on VBOOST. In addition the charge pump comprises a discharge switch in order to keep VBOOST output voltage in a safe operating area in case of over voltage on the supply input pin. The discharge switch is activated as soon as the supply voltage VSUP exceeds the V SUP_OVH threshold level and is deactivated when it drops below the V SUP_OVL threshold. At the same time the charge pump is deactivated. EN_CP CPMODE Charge pump configuration 0 x Charge pump disabled 1 0 Charge pump configured to regulate VBOOST relative to ground, to support low voltage operation 1 1 Charge pump configured to regulate VBOOST relative to the supply, to support the use of a reverse polarity N-FET Table 12-1 Charge pump configuration options CPMODE VSUP EN_CP Control CP Level shift with dead time & slope fCP CP_FB VBOOST VSUP CPMODE CP_DSCHG VSUP COMP OPA VBOOST_UV COMP Figure 12-2 Charge pump principle schematic Voltage [V] Charge Pump and Voltage Regulator Output vs Power Supply Input 25 V 23 V 20 V 18 V 15 V 13 V 10 V 8V 5V 3V 0V 4.0 V CP Mode 0 - VBOOST CP Mode 1 - VBOOST VREG CPx-GATETx 6.0 V 8.0 V 10.0 V 12.0 V VSUP [V] Figure 12-3 Charge pump output and driver supply REVISION 5.11 – OCTOBER 2021 3901083100 Page 19 of 42 MLX83100 Automotive 2-Phase DC Pre-Driver Datasheet 12.1.3. Voltage Regulator - VREG The voltage regulator regulates the power supply down to 12V, in order to supply the low -side gate drivers and switch the external low-side N-FETs without gate-source over voltage at high battery voltages. The regulated output voltage VREG further provides the bootstrap voltage for driving the high -side N-FETs. For safety reasons the pre-driver provides integrated under voltage and over voltage detection on VREG. 12V regulator VREG VBATF Trickle TopDRV Charge Pump Top Driver TopDRV Bottom BotDRV Driver CPx 2 GATETx 2 PHASEx 2 GATEBx 2 Ccpx Rshunt Figure 12-4 Voltage regulator for driver supply – VREG 12.1.4. Digital Supply - VDD The MLX83100 comprises a current sense amplifier. The current sense amplifier and IO’s are supplied from the digital supply VDD. For safety reasons the pre-driver provides integrated under voltage detection on VDD. Note: When supplying VDD with a limited output impedance (e.g. from a microcontroller IO) the performance of the amplifier may be affected. 12.1.5. Sleep Mode Sleep mode is activated when the digital supply input VDD is pulled below “ VVDD sleep voltage threshold low”. In sleep mode the charge pump is disabled and the current consumption on VSUP is reduced. All gate drivers are switched off via sleep gate discharge resistors RSGD. The pre-driver will wake-up as soon as the voltage level on VDD rises above “VVDD sleep voltage threshold high”. REVISION 5.11 – OCTOBER 2021 3901083100 Page 20 of 42 MLX83100 Automotive 2-Phase DC Pre-Driver Datasheet Pin Name State in sleep mode CP The charge pump is disabled. VBOOST Since the charge pump is disabled VBOOST is pulled to the supply voltage via the external charge pump diodes. GATEBx In sleep mode, gate-discharge resistors (RSGD) between GATEBx and DGND are activated, ensuring all low-side gate drivers are switched off GATETx In sleep mode, gate-discharge resistors (RSGD) between GATETx and PHASEx are activated, ensuring all high-side gate drivers are switched off PHASEx Phases are kept low with GATETx through the internal body diode of the pre-driver VREG Voltage regulator is disabled CPx Any charge that remains after VREG is disabled will leak to ground ISENSE Current sense amplifier is supplied from VDD, and thus not active FETBx, FETTx EN, ICOM, MISO All IO’s are supplied from VDD, and thus not active Table 12-2 Drivers in Sleep Mode Notes: 1. In case any of the digital input pins are externally pulled high while VDD is low, current will flow into VDD via internal ESD protection diodes. This condition is not allowed. 2. When VDD is pulled low, also ICOM will go low. This should not be interpreted as a diagnostic interrupt. CPx GATETx RSGD PHASEx VREG GATEBx RSGD Figure 13-1-5 Drivers in Sleep Mode REVISION 5.11 – OCTOBER 2021 3901083100 Page 21 of 42 MLX83100 Automotive 2-Phase DC Pre-Driver Datasheet 12.2. Gate Drivers 12.2.1. PWM Input Control Logic – FETBx & FETTx Each of the 4 external N-FETs can be controlled independently via the 4 digital PWM input pins: FETBx and FETTx. However, the digital logic provides the option to control the 2 external half bridges with only 2 control signals, by shorting high-side and low-side PWM input pins for each half bridge. The IC provides internal shoot through protection since the digital logic prevents simultaneous activation of both high-side and low-side driver of one half bridge. A configurable dead time ensures the high-side (lowside) N-FET is fully switched off, before switching on the complementary low-side (high-side) N-FET. For safety reasons the pre-driver provides integrated drain-source and gate-source monitoring for each of the 4 external N-FETs. FETTx Dead Time GATETx PHASEx EN Dead Time FETBx GATEBx Figure 12-5 Input control logic of the driver stage 12.2.2. Enable Input EN The enable input pin EN enables the gate driver outputs when set high. When reset, all gate driver outputs are switched to the low state, switching off all external N-FETs. This is performed by pulling all gate drivers to ground via the pull-down on-resistances. The enable pin can be used by the microcontroller to disable all drivers in case of any fault detection. While EN is low, the programming of the EEPROM via SPI can be initiated by pulling ICOM low for the SPI start-up time specified by tSPI_SU. 12.2.3. Gate Driver Supply and Bootstrap Architecture – VREG & CPx The voltage regulator regulates the power supply voltage down to 12V. The regulated voltage is used to directly supply the low-side drivers. To provide sufficient supply voltage for the high-side drivers a bootstrap architecture is used. When the low-side N-FET is switched on, the phase voltage will be pulled low and the bootstrap capacitor is charged from the VREG buffer capacitor through the bootstrap diode. Afterwards, if the low-side N-FET is switched off and the high-side N-FET is switched on, the charge of the bootstrap capacitor is used to supply sufficient gate drive voltage to the high-side N-FET. The integrated trickle charge pump assures the bootstrap capacitor will not be discharged, and allows 100% PWM operation. REVISION 5.11 – OCTOBER 2021 3901083100 Page 22 of 42 MLX83100 Automotive 2-Phase DC Pre-Driver Datasheet 12.3. Integrated Current Sense Amplifier The IC comprises an integrated fast, high-bandwidth, low offset current sense amplifier. The current sense amplifier is supplied from the digital supply. It senses the voltage over the low -side shunt, amplifies it with the gain programmed in EEPROM and adds the offset provided on VREF. The output of the amplifier is available on ISENSE. VDD 1 VREF IBP ISENSE OPA OPA IBM Figure 12-6 Current Sense Amplifier REVISION 5.11 – OCTOBER 2021 3901083100 Page 23 of 42 MLX83100 Automotive 2-Phase DC Pre-Driver Datasheet 12.4. Protection and Diagnostic Functions 12.4.1. Power Supply Over Voltage Shutdown (VSUP_OV) The pre-driver has an integrated VSUP over voltage shut down to prevent destruction of the IC at high supply voltages. 12.4.2. Power Supply Under Voltage Warning (VSUP_UV) The pre-driver has an integrated VSUP under voltage detection. The diagnostics interface will give a warning to the microcontroller. It is the responsibility of the microcontroller to take action in order to ensure reliable operation. 12.4.3. Digital Supply Under Voltage Warning (VDD_UV) The pre-driver has an integrated VDD under voltage detection. The diagnostics interface will give a warning to the microcontroller. It is the responsibility of the microcontroller to take action in order to ensure reliable communication between microcontroller and pre-driver. 12.4.4. VBOOST Under Voltage Warning (VBOOST_UV) The integrated charge pump boosts the supply voltage in low voltage operation on the VBOOST output. There is an under voltage detection on VBOOST to warn the microcontroller the charge pump is not ready. It is the responsibility of the microcontroller to take action in order to ensure reliable motor operation. 12.4.5. Gate Driver Supply Over Voltage Warning/Shutdown (VREG_OV) The MLX83100 comprises an integrated VREG over voltage detection. The reaction of the pre-driver on this VREG_OV event depends on the status of the Bridge Feedback bit in EEPROM. If this VREG_OV_BF_EN bit is set the pre-driver will disable all gate drivers, switching off all external N-FETs. If the bit is reset it will just give a warning to the microcontroller. VREG_OV_BF_EN Pre-driver reaction VREG_OV event 0 VREG_OV is reported on ICOM, but the drivers remain active 1 VREG_OV is reported on ICOM and the drivers are disabled Table 12-3 EEPROM Configuration for VREG over voltage detection 12.4.6. Gate Driver Supply Under Voltage Warning (VREG_UV) The pre-driver detects when the regulated voltage drops below the under voltage threshold. The diagnostics interface will give a warning to the microcontroller. It is the responsibility of the microcontroller to take action in order to ensure reliable switching of the external N-FETs, since the VREG voltage directly supplies the low-side gate drivers. REVISION 5.11 – OCTOBER 2021 3901083100 Page 24 of 42 MLX83100 Automotive 2-Phase DC Pre-Driver Datasheet 12.4.7. Gate Source Voltage Monitoring Warning (VGS_UV) In order to ensure reliable switching of the high-side N-FETs, the MLX83100 comprises gate-source monitors for each of the high-side N-FETs. In case of an under voltage, the diagnostics interface will give a warning to the microcontroller, if the gate-source comparators are enabled in EEPROM. It is the responsibility of the microcontroller to take action in order to ensure reliable switching of the high-side gate drivers. 12.4.8. Over Temperature Warning (OVT) If the junction temperature exceeds the specified threshold, a warning will be communicated to the microcontroller. The pre-driver will continue in normal operation. It is the responsibility of the microcontroller to protect the IC against over temperature destruction. 12.4.9. Shoot Through Protection and Dead Time The pre-drivers’ internal implementation guarantees that low-side and high-side N-FET of the same external half bridge cannot be conducting at the same time, preventing a short between the supply and ground. In addition the pre-driver provides a programmable dead time in EEPROM. The dead time sets the delay between the moment when the high-side (low-side) N-FET is switched off, and the moment when the complementary low-side (high-side) N-FET can be switched on. 12.4.10. Drain-Source Voltage Monitoring Warning/Shutdown (VDS_ERR) The MLX83100 provides a drain-source voltage monitoring feature for each external N-FET to protect against short circuits to ground or supply. For the high-sides the drain-source voltage are sensed via the VBATF –and PHASEx-pins. For the low-sides the PHASEx –and IBP-pins are used. The drain-source voltage comparator can be enabled or disabled in EEPROM. The drain-source voltage monitor for a certain external N-FET is activated when the corresponding input is switched on and the dead time has passed. An additional blanking time can be programmed in EEPROM. If the drain-source voltage remains higher than the VDS monitor threshold voltage, the VDS error is raised. The threshold voltage is configurable in EEPROM. The reaction of the pre-driver on a VDS error can be configured in EEPROM with the Bridge Feedback bit. If this bit is set the pre-driver automatically disables the drivers when a VDS error is detected. If the bit is reset, the drivers remain active. In both cases the VDS error will be reported to the microcontroller. VDS_COMP_EN VDS_BF_EN Pre-driver reaction on VDS-error event 0 x Any VDS error is ignored and no error is reported on ICOM 1 0 VDS_ERR is reported on ICOM, but the drivers remain active 1 1 VDS_ERR is reported on ICOM and the drivers are disabled Table 12-4 EEPROM Configuration for drain-source error detection REVISION 5.11 – OCTOBER 2021 3901083100 Page 25 of 42 MLX83100 Automotive 2-Phase DC Pre-Driver Datasheet 12.4.11. EEPROM Error Warning (EEP_ERR) To ensure reliable communication with EEPROM the pre-driver provides an automatic single bit error correction and double error detection. If two bits in the addressed word are bad the EEPROM gives the EEP_ERR warning, indicating a double error was detected. 12.4.12. Diagnostics Interface – ICOM All diagnostic events described above are reported to the microcontroller via a single pin, ICOM. In normal operation, when no error is detected, ICOM is default high. The ICOM interface acts as a serial interface that feeds back detailed diagnostics information. If an error is detected, ICOM goes from default high to communicating a PWM-signal. The speed of this PWM signal depends on the EEPROM configuration of bit PWM_SPEED. Each error corresponds to a duty cycle with a 5bit resolution. Thus the microcontroller can distinguish different errors by reading the duty cycle, see Table 12-7. PWM_SPEED Description 0 Slow mode: for slow microcontrollers 1 Fast mode : for fastest response of microcontroller Table 12-5 EEPROM Configuration for diagnostics communication speed The duty cycle is transmitted until the microcontroller sends the acknowledgement. This is done by pulling ICOM low for more than a PWM-period, tAck > tICOM. At each ICOM falling edge the pre-driver checks the actual voltage on ICOM in order to detect an acknowledgement. After acknowledgement the duty cycle of the next error is transmitted, if multiple errors were detected. All errors have been reported when the endof-frame duty cycle is send. When all errors are physically removed, and the end-of-frame message is acknowledged by the microcontroller, ICOM returns to its default high state. Physical Error ICOM Default high Error Information End-of-Frame Default high MCU Acknowledge Figure 12-7 ICOM Diagnostics Communication REVISION 5.11 – OCTOBER 2021 3901083100 Page 26 of 42 MLX83100 Automotive 2-Phase DC Pre-Driver Datasheet Notes: 1. When VDD is pulled low to put the pre-driver in sleep mode, ICOM will go low as well. This should not be interpreted as a diagnostic interrupt. As soon as VDD goes high, the pre-driver wakes-up and ICOM will return to its default high state. 2. At POR it is possible that the voltages on VSUP and VREG were not above the under voltage thresholds (e.g. due to charging of external capacitors). It is possible that ICOM reports these under voltage errors after POR. This implies that the microcontroller has to acknowledge these errors before ICOM will be in its default high state and the pre-driver is ready for normal operation. The drivers are disabled when The drivers are enabled again as soon as An error condition is detected for which the hardware protection is activated VSUP_OV VREG_OV VDS_ERR The microcontroller acknowledges the error VDD = Low (sleep mode) VDD = High (wake-up) EN = Low EN = High Table 12-6 Pre-Driver Output State Summary VDD VDD Microcontroller Pre-Driver