MLX75030 Universal ActiveLight Sensor Interface
Datasheet
Features & Benefits
Two independent simultaneously
operating active light measurement
channels
Integrated DC light cancellation circuitry
for active light channel DC light
suppression
Two logarithmic ambient light channels
High input capacitance tolerant input
current terminals
Extremely high degree of adaptability
for different optical systems
Stand-by and sleep modes
Integrated 16bit ADC
Integrated temperature sensor
Digital communication interface via SPI
Integrated watchdog timer
High safety design by comprehensive
diagnostic and monitoring functions
Minimum amount of external
components
Small-size SMD package QFN24 4x4 mm
Ordering Information
Temperature Code
R
C
20
21
GNDA
GNDAMB
DIAGAMB
15
14
13
75030
A
12345
1025
12
Ambient PDD
11
Ambient PDC
10
ActiveLight PDB
`
CEXT
22
VCCD
23
GNDD
24
1
2
3
4
5
6
\CS
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Drive LED B
Drive LED A
16
MOSI
Touch Screen Wake-up on Proximity
19
17
MISO
Driver/passenger discrimination
Shunt R-
18
AOUT
Touch-less gesture recognition
VCCA
SCLK
Optical proximity sensing & display dimming
Pin Description
Shunt R GND
Packing Form Code
RE or TU
RE or TU
R = -40 to 105°C, C = 0°C to 70°C
LW = = Quad Flat Package (QFN) with wettable flanks
BAA-000 = Design Revision
RE = Reel, TU = Tube
MLX75030RLW-BAA-000-RE
Application Examples
Option Code
BAA-000
BAA-000
\WT
Legend:
Temperature Code:
Package Code:
Option Code:
Packing Form:
Ordering example:
Package Code
LW
LW
\MR
Product Code
MLX75030
MLX75030
9
ActiveLight PDA
8
\WAKE-UP
7
DR
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MLX75030 Universal ActiveLight Sensor Interface
Datasheet
1. General Description
The MLX75030 Universal ActiveLight Sensor Interface has been designed to allow easy and robust dual-channel optical
reflection and dual channel ambient light measurement. Therefore it is ideally suited for the design of responsive
human-machine interfaces (HMI) that require proximity or gesture detection in environments subject to wide
background light level variations, possibly in combination with display dimming.
The MLX75030 IC consists of two optical sensor interface parts. Part one is optimized for active light measurements
and is designed to control up to 2 external LEDs and to sense modulated light current from up to 2 external
photodiodes on independent channels A and B. The ActiveLight detection is virtually independent from background
light by means of integrated hardware-level ambient light suppression. Part two consists of two logarithmic current
sensors C and D, which measure the photocurrent of externally connected photodiodes. Simple and programmable
operation is ensured by internal control logic, configurable user registers and SPI communication.
2. Functional Block Diagram
Figure 1 : MLX75030 Functional Block Diagram
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Datasheet
3. Application Diagram
Beam shaping
optics
SUN
NIR LED A
Photodiode A
scene
NIR LED B
MLX75030
or
MLX75031
Photodiode B
NIR
transparent
face place
Figure 2 : Application diagram of a dual channel active reflection detector with 2 photodiodes and 2 LEDs.
The measured signal is virtually independent of background light from the sun or other sources.
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Datasheet
Table of Contents
1. General Description ............................................................................................................................... 2
2. Functional Block Diagram ...................................................................................................................... 2
3. Application Diagram .............................................................................................................................. 3
Table of Contents ...................................................................................................................................... 4
4. Glossary of Terms .................................................................................................................................. 6
5. Absolute Maximum Ratings ................................................................................................................... 7
6. Pin Definitions & Descriptions ............................................................................................................... 8
7. General Electrical Specifications .......................................................................................................... 10
8. Sensor Specific Specifications .............................................................................................................. 11
9. Detailed Description ............................................................................................................................ 16
9.1. Analog Sensor Functions .................................................................................................................. 16
9.1.1. Active Light Sensor ..................................................................................................................... 16
9.1.1.1. Active Light Channel DC Light Measurement.................................................................... 17
9.1.2. ActiveLight Channel DC Light compensation ............................................................................ 17
9.1.3. Ambient Light Sensor ................................................................................................................. 19
9.1.3.1. Normal Operation ............................................................................................................... 19
9.1.3.2. Calibration and temperature compensation .................................................................... 20
9.1.3.3. Diagnostics Mode Operation ............................................................................................. 21
9.1.4. Temperature Sensor ................................................................................................................... 21
9.1.5. DAC .............................................................................................................................................. 22
9.1.6. LED Driver.................................................................................................................................... 23
9.1.7. POR .............................................................................................................................................. 23
9.2. SPI ...................................................................................................................................................... 23
9.2.1. General Description of SPI Interface ......................................................................................... 23
9.2.2. Detailed Explanation of SPI Instruction Words ......................................................................... 27
9.2.2.1. NOP – Idle Command ......................................................................................................... 27
9.2.2.2. CR – Chip Reset Command ................................................................................................. 27
9.2.2.3. RSLP/CSLP – Request Sleep/Confirm Sleep ....................................................................... 27
9.2.2.4. RSTBY/CSTBY - Request Standby/Confirm Standby .......................................................... 28
9.2.2.5. NRM – Normal Running Mode ........................................................................................... 28
9.2.2.6. SM – Start Measurement ................................................................................................... 28
9.2.2.7. RO – Start Read-Out ........................................................................................................... 30
9.2.2.8. SM+RO - Start Measurement combined with Read-Out .................................................. 33
9.2.2.9. WR/RR – Write/Read Register ........................................................................................... 34
9.2.2.10. SD – Start Diagnostics....................................................................................................... 35
9.3. Internal Status Flags ......................................................................................................................... 37
9.4. User Registers Overview................................................................................................................... 39
9.4.1. SetAna register ........................................................................................................................... 40
9.4.2. SetAH register ............................................................................................................................. 41
9.4.3. SetAL register .............................................................................................................................. 41
9.4.4. SetBH register ............................................................................................................................. 42
9.4.5. SetBL register .............................................................................................................................. 42
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9.4.6. SetPF register .............................................................................................................................. 43
9.4.7. Err register .................................................................................................................................. 44
9.4.8. Rst register .................................................................................................................................. 45
9.4.9. DCComp register ......................................................................................................................... 45
9.4.10. GainBuf register ........................................................................................................................ 46
9.4.11. Calib1/Calib2 register ............................................................................................................... 47
9.4.12. EnChan register ........................................................................................................................ 51
9.4.13. Tamb register ............................................................................................................................ 52
9.5. Window Watchdog Timer ................................................................................................................ 53
9.6. Reset Behaviour ................................................................................................................................ 55
9.7. Wake-up from Sleep or Standby ...................................................................................................... 56
9.8. CRC Calculation ................................................................................................................................. 57
9.9. Global Timing Diagrams.................................................................................................................... 58
10. Performance Graphs.......................................................................................................................... 59
10.1. ActiveLight Channel DC Measurement .......................................................................................... 59
10.2. Temperature Sensor Characteristics ............................................................................................. 59
10.3. Ambient Light Channel C ................................................................................................................ 59
10.4. Ambient Light Channel D................................................................................................................ 59
11. Application Information..................................................................................................................... 60
11.1. Application circuit for 2 ActiveLight channels and 2 ambient light channels .............................. 60
12. Application Comments ...................................................................................................................... 61
13. Tape and Reel Specification ............................................................................................................... 62
14. Standard information regarding manufacturability of Melexis products with different soldering
processes............................................................................................................................................ 65
15. ESD Precautions................................................................................................................................. 66
16. Package Information.......................................................................................................................... 66
17. Marking Information ......................................................................................................................... 67
18. Disclaimer .......................................................................................................................................... 68
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4. Glossary of Terms
ADC
CR
CRC
CS
CSLP
CSTBY
CTRL
DAC
DC
DR
EMC
GNDA
GNDD
IR
LED
LPF
LSB
MISO
MOSI
MR
MSB
MUX
NOP
NP
NRM
OSC
OTP
OTR
PD
POR
RCO
RO
RR
RSLP
RSTBY
S&H
SCLK
SC-LPF
SM
SNR
SPI
TIA
VBATT_30
VCCA
VCCD
VDD_30
VSENSE
WDT
WR
WT
uC
Analog-Digital converter
Chip Reset
Cyclic Redundancy Check
Chip Select
Confirm Sleep
Confirm Standby
Control Signal
Digital to Analog Converter
Direct Current
Device Ready
Electromagnetic Compatibility
Ground for analog Blocks of MLX7530
Ground for digital Blocks of MLX75030
Infrared
Light emitting diode
Low-pass filter
Least Significant Bit
Master In Slave Out
Master Out Slave In
Master Reset
Most Significant Bit
Multiplexer
No Operation
Number of Pulses
Normal Running Mode
Oscillator
One time programmable
Optical transfer ratio
Photodiode
Power on reset
RC-Oscillator
Read-Out
Read Register
Request Sleep
Request Standby
Sample and Hold
SPI Shift Clock
Switched Capacitor biquad Low-pass filter
Start Measurement
Signal-to-Noise Ratio
Serial Peripheral Interface
Transimpedance Amplifier
VBATT which is supplied from connection 30 of the car
Supply Voltage for the analog blocks
Supply Voltage for the digital blocks
VDD which is supplied from connection 30 of the car
Voltage across the shunt resistor
Watchdog Timer
Write Register
Watchdog Trigger
Microcontroller
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5. Absolute Maximum Ratings
Exceeding the absolute maximum ratings may cause permanent damage.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Parameter
Symbol Condition
Supply voltage range
VDD
-0.3
5.0
V
Terminal current
Iterminal
per bondpad
-20
+20
mA
Vterminal
Pins 1-8, 14-24
-0.3
VDD+0.3
V
-0.3
VDD+0.3
V
-40
+150
°C
+150
°C
320
mW
Terminal voltage
1
Pins 9-13
Storage temperature
Tstg
Junction temperature
Tj
Power dissipation
2
Min
Max
Units
Ptot
For max ambient temperature of
100°C and
Teta_ja = 154K/W
ESDHBM
Human body model,
acc. to AEC-Q100-002
-2
2
kV
Pins 9-13
-1
1
kV
ESD capability of any pin
(Human Body Model)
ESD capability of any pin
(Charge device model)
ESDCDM
Charge device model
acc. to AEC- Q100-011
-750
+750
V
Maximum latch–up free current at any pin
ILATCH
JEDEC- Standard EIA / JESD78
-100
+100
mA
Table 1 : Absolute Maximum Ratings
1
Pins 9-13 require special care with regard to the used ESD protection devices, since these nodes of the design are
very sensitive to substrate noise and/or leakage currents.
2
The Power dissipation is valid for JA values for the 24 Pin QFN 4x4 package according to Table 27.
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6. Pin Definitions & Descriptions
Pin
№
Name
Functional
Schematic
Type
Function
VCCD
PAD
1
\MR
Digital Output
Master Reset
VCCD
2
PAD
\WT
Digital Input
Watchdog Trigger
Digital Input
SPI Shift Clock
VCCD
3
PAD
SCLK
VCCD
EN
4
PAD
MISO
Digital Output
SPI Data Output
VCCD
5
PAD
MOSI
Digital Input
SPI Data Input
Digital Input
Chip Select
VCCD
PAD
6
\CS
VCCD
PAD
7
DR
Digital Output
Device Ready
Digital Input
Normal Mode
Analog Input
IR Photo Diode A
Analog Input
IR Photo Diode B
Analog Input
Ambient Light Photo Diode C
Analog Input
Ambient Light Photo Diode D
VCCD
PAD
8
\WAKE-UP
9
ActiveLight
Detect PDA
10
ActiveLight
Detect PDB
11
Ambient PDC
VCCA
PAD
VCCA
PAD
VCCA
PAD
VCCA
12
Ambient PDD
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PAD
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Datasheet
VCCA
13
DIAGAMB
PAD
Analog Input
Ambient channel diagnostic
VCCA
PAD
14
GNDAMB
Analog I/O
Ground Ambient Light Channels
15
GNDA
Ground
Ground
16
VCCA
Supply
Regulated Power Supply
17
AOUT
Analog I/O
Analog Test Output, connect to VCCA
VCCA
18
Shunt R GND
PAD
Shunt R-
PAD
Analog Input
Shunt resistor feedback to Ground
Analog Input
Shunt resistor feedback
VCCA
19
VCCA
20
PAD
Drive LED B
Analog Output
Drives FET gate for IR LED Emitter B
Analog Output
Drives FET gate for IR LED Emitter A
VCCA
PAD
21
Drive LED A
22
CEXT
23
VCCD
Supply
Regulated external power supply
24
GNDD
Ground
Ground
VCCA
PAD
Analog Input
External blocking Cap, connected to GNDA
Table 2 : Pin definitions and descriptions
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Datasheet
7. General Electrical Specifications
DC Operating Parameters TA = -40°C to 105°C (R version), TA = 0°C to 70°C (C version),
VDD = 3.0V to 3.6V (unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
Supply Voltage range
VDD
3.0
3.3
3.6
V
Supply Current (active Mode)
IDD
without photodiode dc current
6
mA
Standby Current
ISBY
@ Vcc=3.6V, T=30°C
500
uA
Sleep Current
ISleep
@ Vcc=3.6V, T=30°C
Operation Temperature Range
Pull-up resistor
Pull-down resistor
TA
Rpu
Rpd
50
uA
105
°C
High-level Input Voltage
VIH
0.7 VDD
VDD
V
Low-level Input Voltage
VIL
0
0.3 VDD
V
Hysteresis on Digital Inputs
VHYST
High Output Voltage (not on pin MR)
VOH
CL=30pF
0.8 VDD
VDD
V
Low Output Voltage (not on pin MR)
VOL
CL=30pF
0
0.2 VDD
V
Input leakage
ILK
-10
10
µA
Tri-state Output Leakage Current
IOZ
-10
10
µA
Input Capacitance, per Pin
CIN
Output voltage Low, Pin MR
VOutL
-40
for SCLK and \CS
for MOSI
50k
50k
Ohm
Ohm
0.28
V
10
IODC=2mA
pF
0.1
Table 3 : Electrical specifications
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V
MLX75030 Universal ActiveLight Sensor Interface
Datasheet
8. Sensor Specific Specifications
DC Operating Parameters TA = -40°C to 105°C, TA = 0°C to 70°C (C version),
VDD = 3.0V to 3.6V (unless otherwise specified)
ActiveLight Channels (Detectors A & B)
Parameter
Symbol
Active light signal optical
transfer ratio
OTR
dc sunlight signal
fast full scale transition at Isunmax
Test Conditions
I LED
I PDAB
Min
Typ
Max
30
80000
ISun
140
900
tsunrise
3.5
min. relative active light
modulation
(referred to received IR signal)
I PDAB
Carrier frequency range for
ActiveLight measurement
signal
Input capacitance PDA, PDB
f0
selectable via “SetPF”
register, see also 9.4.6
CPDA,B
At 1.0 V reverse bias
DC light measurement range
DC light measurement offset
DC light measurement slope
DC light measurement
linearity
error
DC
light measurement
word
length
DC light measurement
resolution
TIA
Test pulse
IDC range
IDC offset
IDC sens
At IDC = 0uA
Temperature coefficient of
TIA Test pulse
TC ADCTIA_test_00
TIA Test pulse step width
ADCTIA_test_step
Temperature coefficient of
TIA Test pulse step width
TIA Test pulse step width
variation
TC ADCTIA_test_step
Idc range: 0uA -> 275uA
ADCTIA_test_00
ADC _ TIA _ TEST _ STEP
for averaging of 8
measurements
T=27°C,
DACA6=0, DACA7=0
Gain Anti-alias Filter=2
ADC Buffer bypassed
DACA6=0, DACA7=0
Gain Anti-alias Filter=2
ADC Buffer bypassed
T=27°C,
Gain Anti-alias Filter=2
ADC Buffer bypassed
Gain Anti-alias Filter=2
ADC Buffer bypassed
Gain Anitalias Filter=2
ADC Buffer bypassed
uA
ms
- 400Hz BW,
- max LED current of 1000mA
- 25°C
- dc sun constant
- ActiveLight response time
per channel 2.5ms
I PDAB _ min
Units
0.3
45.7
0
4096
115
7168
150
5
16
13
35035 36182
109.4
kHz
10
pF
275
10240
184
12
uA
LSB
LSB/uA
%
Bit
Bit
LSB
37570
-2.78
4458
5932
LSB/K
7770
-4.8
5
%
LSB
LSB/K
10
%
Error condition Err6
Critical error detected on TIA output, is TIA output outside 1.1V+/- (0.65 … 0.75V)
Note:
Critical error may occur if the referring active light Channel is disabled and the according diagnostic function is
enabled (see EnChan register).
Critical error may occur after enabling of the referring active light Channel due to analog settling time.
Table 4 : ActiveLight sensor channels specifications
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ActiveLight Channel DC-Light Compensation
Parameter
Symbol
Test Conditions
Maximum ActiveLight Signal DC-Light
compensation range
RSCOMP_max
in percent of LED current
DC_COMP_IC1,2,3,4,5=15
DAC=255
ActiveLight Signal Compensation
Offset
RSCOMP_Offset
in percent of LED current
@ Idc = 0uA
Range of segment 1
Range of segment 2
Range of segment 3
Range of segment 4
Full compensation level @ segment 1
Iamb_1
Iamb_2
Iamb_3
Iamb_4
Icomp_1
Full compensation level @ segment 2
Icomp_2
Full compensation level @ segment 3
Icomp_3
Full compensation level @ segment 4
rst
1 corner dc current
nd
2 corner dc current
rd
3 corner dc current
th
4 corner dc current
DC_COMP_IC1,2,3,4,5 = 15
DAC=255
in percent of LED current
Min
Typ
15
20
Max Units
%
0.8
%
7.2
10.0 12.0 uA
40.0
45.0 50.0 uA
135.0 150.0 165.0 uA
440.0 500.0 560.0 uA
1.5
3.5
4.7 %
5.1
7.7
10.3
%
9.5
13.7
17.9
%
Icomp_4
13.6
18.8
24.0
%
Full compensation level @ 900uA
(max DC sunlight)
Icomp_5
15.0
20.7
25.8
%
Full compensation level @ segment 1
Full compensation level @ segment 2
Full compensation level @ segment 3
Full compensation level @ segment 4
Full compensation level @ 900uA
(max DC sunlight)
DC_COMP_IC1 = 15, other =0
DC_COMP_IC2 = 15, other =0
DC_COMP_IC3 = 15, other =0
DC_COMP_IC4 = 15, other =0
DC_COMP_IC5 = 15, other =0
Icomp_1
Icomp_2
Icomp_3
Icomp_4
Icomp_5
DC_COMP_IC1,2,3,4,5 = 7
DAC=255
in percent of LED current
0.65
2.4
4.4
6.3
7.1
1.6
3.6
6.4
8.85
9.6
2.2
4.8
8.4
11.4
12.1
%
%
%
%
%
IC_1
IC_2
IC_3
IC_4
IC_5
in percent of LED current
in percent of LED current
in percent of LED current
in percent of LED current
in percent of LED current
1.4
2.1
5.0
4.4
2.0
2.3
2.9
6.6
5.9
3.0
2.8
3.6
8.2
7.3
4.1
%
%
%
%
%
Table 5: DC light compensation specifications
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Ambient Light Channels (detectors C, D)
Parameter
Input current range for
detectors C
Input current range for
detectors D
input current threshold level
C
input
current threshold level
D
Input capacity on ambient
PDC
Input capacity on ambient
PDD
Transfer function logarithmic
Symbol Test Conditions
Min
Iambc
Typ
Max
Units
0.01
1040
uA
Iambd
0.0005
20
uA
Iambc_detect
Iambd_detect
Cambc
Cambd
333
5.5
1
100
nA
nA
nF
pF
at 0.6V
at 0.6V
See section 10.3 and 10.4
Vamb
Output Ambient Channel C
At VCC=3,3V, Iin=100uA 29464
32768 36072
LSB
Output Ambient Channel D
At VCC=3,3V, Iin=10uA
32768 36072
LSB
Slope Ambient Channel C
At VCC=3,3V and 105°C 5300
5900
6500
LSB/dec
Slope Ambient Channel D
At VCC=3,3V and 105°C 5300
5900
6500
LSB/dec
Ambient Channels Linearity
Error
for Iin ≥ Iambx_detect
including temperature
compensation
3
5
%
29464
Ambient light word length
Ambient light channel
resolution
for averaging of 16
measurements
See section 9.1.3 for a
detailed explanation of
this parameter.
for Iin ≥ Iambx_detect
Ambient light response time
Ambient PDC voltage
Ambient PDD voltage
Vambc
Vambd
At VCC=3,3V, Iin=100uA 0.4
At VCC=3,3V, Iin=10uA 0.4
16
bits
13
bits
0.6
0.6
3
ms
0.9
0.9
V
V
Error condition Err3
Note:
Err3 is set if output voltage OUTN or OUTP of the ambient channel SC filter is out of range (meaning: 60% of VCCA). Critical error may occur after enabling of the referring Ambient Light Channel due to analog
settling time.
Table 6 : Ambient light channel specifications
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Temperature Sensor
Parameter
Symbol
Temp. sensor range
Test Conditions
Temp. sensor transfer
3
function
V
@ VDD=3,3V
Temp. sensor error
error@0…105°C
@ VDD=3,3V,
o
Tamb = 0…105 C
Temp. response time
tresp_
Min
Typ
-40
-82
-67
Max
Units
105
°C
-51
LSB/K
±5
°C
1
Temp. sensor word length
for averaging of 16
measurements
Temp. sensor resolution
s
16
bits
13
bits
Table 7 : Temperature sensor specifications
LED Driver
Parameter
Symbol
Test Conditions
Min
Max
Units
Shunt = 1 Ω
1.05
993
mA
Shunt resistor values
1
10
Ohm
Shunt voltage
1.05
993
mV
420
us
mV
us
LED current
Rising and falling time
DC offset level
Time before pulse
Typ
3
1
See section 9.4.1
Tdc_pulse
47.5
External important transistor parameter
Max gate source voltage
VGS
VDD=3V
2
V
Max Gate/Basis current
IG/B
VDD=3V
400
uA
Error condition Err5
Err5 difference between Vdac and Vsense. Detection level larger 100mV
Table 8 : LED driver specifications
POR
Parameter
Symbol
POR on threshold voltage
POR off threshold voltage
VPOR-ON
VPOR-OFF
POR hysteresis voltage
VHYS
Test Conditions
Min
Typ
Max
Units
1.58
1.68
2.75
2.85
V
V
60
130
mV
Table 9: Power on Reset specifications
3
This value is stored in the Calib1 Register
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SPI and Timing
Parameter
Symbol
Test Conditions
Min
Typ
8
bit
0.5
1
5
MHz
2.5
±7.5%
MHz
SPI word length
Max
Units
SPI Clock Frequency
fSCLK = 1/tSCLK
Frequency of Internal RC Oscillator
fRCO = 1/TRCO
CS low prior to first SCLK edge
tcs_sclk
50
CS high after last SCLK edge
tsclk_cs
50
ns
CS high time between transmissions
tcs_inter
50
ns
Time between CS high and DR low
tcs_dr
0
Min low time on WAKE_UP pin
twu_l
100
µs
Min low time on WT pin
twt_l
10
µs
WDT initial active window time
twdt_init
WDT open window time
WDT closed window time
MR low time during reset
tMR
Start-up time after power-on
tstartup
Start-up time after power-on for SPI
tstartup_SPI
Start-up time after wake-up from sleep
Start-up time after wake-up from standby
After POR, Watchdog
Reset and Wake-Up
ns
21.84
4
(232us)
µs
140
±7.5%
ms
twdt_open
70
±7.5%
ms
twdt_closed
70
±7.5%
ms
2
±7.5%
ms
50
±7.5%
ms
15
µs
twakeup_slp
50
±7.5%
ms
twakeup_stby
50
±7.5%
ms
After Watchdog Reset
Error condition Err2
RCO stuck at High or Low
Error condition Err4
Internal voltage regulator : err4 is set if the regulator does not start (detection threshold in the range [1V;2V]
Table 10 : Serial peripheral interface specifications
4
with random measurement start, the max time can be up to 232us, if an autozeroing phase of the IC is executed.
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9. Detailed Description
9.1. Analog Sensor Functions
9.1.1. Active Light Sensor
The MLX75030 works with two separate transmit- and receive-channels A and B. In order to perform an active light
measurement, carrier modulated light signal bursts are transmitted by the LED(s) and received by the ActiveLight channel
detectors connected to the pins 9 and 10. Both receive-channels can work separate or in parallel.
The measured ActiveLight signal current is amplified and converted to digital numbers by the on-board ADC by following
formula:
AActiveLightADC I ActiveLightPD
4.10 4 * K DEMOD * GAIN _ ADJ _ AA * GAIN _ BUF
215
V
50,3
LSB
Where
is the ActiveLight signal value in DN
is the ActiveLight signal current in uA
is a correlation gain value between 0.25 and 0.5, depending on the setting of Tdem bits in register SetAna
is the Anti-aliasing filter gain, set by SetAL and SetBL registers, defaulting to value 2
is the ADC input buffer gain, set by SetAna and GainBuf registers, defaulting to value 1
It is recommended to use the default values of
.
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. It is recommended to optimize the value of
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9.1.1.1. Active Light Channel DC Light Measurement
The input DC current compensation circuitry of the transimpedance amplifier is able to supply and measure the dc current
supplied to the photodetector. Both active light channels are identical in structure. In order to reach a feasible resolution in
the current range of interest (low currents in the range up to 275uA), the measurement characteristic will saturate for
currents above the IDC current range, however the compensation circuit is nevertheless able to supply the specified current
levels up to 900uA to the detector. The given ADC word length for the active light channel dc light data is 16Bit.
The DC light measurement can be used to estimate ambient light conditions and compensate DC light dependent
parameters (see next section).
MLX75308BA DC light measurement at rain channels
60000
55000
50000
45000
PDA
ADC out [LSB]
40000
PDB
35000
30000
25000
20000
15000
10000
5000
0
0
50
100
150
200
250
300
350
400
450
500
Idc [uA]
Figure 3: Typical ActiveLight channel DC measurement characteristics for both channels A and B
9.1.2. ActiveLight Channel DC Light compensation
Under certain operating conditions, the spectral sensitivity of some photodiodes is not constant and varies with the
amount of (infrared) dc-light received. For the ActiveLight measurements this means that the ActiveLight signal can change
rapidly if the sensor experiences highly changing sunlight conditions, even if all other conditions are constant. This results
in reduced ActiveLight signal sensitivity of the system under changing dc-light conditions.
The variation of the ActiveLight signals as a function of DC-light can be partially compensated by automatically adapting the
amplitude
of
the
sensors’
transmitted
infrared
light
pulses
for
ActiveLight
measurement.
In order to make the system as flexible as possible, the compensation can be adapted to different photodiode types by
definition of the compensation characteristics as a piecewise linear curve like described in Figure 4. The values of the 5
corner points of the curve can be defined by the corresponding 4-Bit words PD_COMP_ICx (x = 1..5) in the register
maps, see section 9.4. The PD light compensation can be enabled by setting the EN_PDCOMP bit to “1”.
In order to calculate the decimal values PD_COMP_ICx (x = 1..5) for a certain photodiode, one has to measure the
relative ActiveLight signal levels px at 5 different DC light levels Iamb_x while the EN_PDCOMP is set to "0" (a calculation
example is given below, where
is the measured ActiveLight signal at DC light signal
):
p0 = pulse level at (Iamb_0 = 0) = 1 (this is the 100% reference)
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p1 = pulse level at (Iamb_1 = 10uA) = e.g. 0.97440 =
A @ Iamb _ 0 215
A @ Iamb _ 1 215
p2 = pulse level at (Iamb_2 = 45uA) = e.g. 0.94224 =
A @ Iamb _ 0 215
A @ Iamb _ 2 215
p3 = pulse level at (Iamb_3 = 150uA) = e.g. 0.91556 = …
p4 = pulse level at (Iamb_4 = 500uA) = e.g. 0.89858 = …
p5 = pulse level at (Iamb_5 = 900uA) = e.g. 0.89477 = …
Based on these relative ActiveLight pulse levels, one can calculate the following parameters (x = 1..5):
rcomp _ i 3 105 1 px
ycomp_1
ycomp_2
ycomp_3
ycomp_4
ycomp_5
=
1.285714
-0.28571
0
0
0
-1.28571
1.714286
-0.42857
-1.8E-17
1.78E-17
0
-1.42857
1.857143
-0.42857
-7.9E-17
0
0
-1.42857
2.678571
-1.25
0
0
0
-2.25
2.25
•
rcomp_1
rcomp_2
rcomp_3
rcomp_4
rcomp_5
For the calculation example, we get the following values:
rcomp_1
rcomp_2
rcomp_3
rcomp_4
rcomp_5
=
7.68E-07
1.73E-06
2.53E-06
3.04E-06
3.16E-06
The settings PD_COMP_ICx (x = 1..5) can be derived from the y comp_x (x = 1..5) as follows:
PD_COMP_IC1[3:0] = round (
PD_COMP_IC2[3:0] = round (
PD_COMP_IC3[3:0] = round (
PD_COMP_IC4[3:0] = round (
PD_COMP_IC5[3:0] = round (
ycomp _ 1
0.4 0.132 10 6
ycomp _ 2
0.4 0.165 10 6
ycomp _ 3
0.4 0.334 10 6
ycomp _ 4
0.4 0.334 10 6
ycomp _ 5
0.4 0.180 10 6
, 0)
, 0)
, 0)
, 0)
, 0)
For the calculation example, this means:
PD_COMP_IC1[3:0] = 9dec
PD_COMP_IC2[3:0] = 14dec
PD_COMP_IC3[3:0] = 7dec
PD_COMP_IC4[3:0] = 5dec
PD_COMP_IC5[3:0] = 3dec
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These values can be written inside the corresponding registers, see section 9.4. When the PD compensation is enabled
(EN_PDCOMP = "1"), the compensation will modulate the LED current of the ActiveLight channels.
ICOMP
[in % of LED current]
For IC_5 = 0 -> Icomp_4 = Icomp_5
Icomp_4
Icomp_3
Icomp_2
Icomp_1
IC_1
IC_2
IC_3
IC_4
Iamb_0
Iamb_1
Iamb_2
Iamb_3
Iamb_4
Iamb_5
Idc
Figure 4: Example of a compensation curve I COMP for IC_5=0. The dc-currents of the corner points are fixed in the design and cannot
be influenced. The compensation components I C_1…IC_5 are defined by the registers DC_COMP_IC1…5 with 4 bits each. The
resulting compensation characteristics are shown in the black graph.
9.1.3. Ambient Light Sensor
9.1.3.1. Normal Operation
The ambient light detection system of the MLX75030 consists of two independent channels C and D and an on-chip
controllable dedicated ground pin GNDAMB. GNDAMB should not be directly connected to GND. An external photodiode is
connected in between each channel and GNDAMB.
The ambient light signal is low pass filtered on chip.
The signal of a 1ms switched-capacitor filters is sampled by the ADC (on request by an SPI command, each 2.5ms), where it
is converted into a 16bit digital word.
The total input stage, this means from the external diode up to the 1ms filter, has a cut-off frequency at ~160Hz. Sampling
this output every 2.5ms, commanded by SPI, would make a sample rate of 400Hz, which well above the Nyquist frequency
of the present frequency content of 160Hz.
Within the specified input current range the ambient input stages bias the external photodiodes with > 0V in normal
operation.
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9.1.3.2. Calibration and temperature compensation
The output of each ambient channel has a strong temperature dependence and a slight process dependence that can be
compensated at run time. This is shown in following equation (channel x, where x = C or D):
O
I x 1 TCIref T 1 x 2 T
300
Ix:
amboutx:
TCIref:
Ox:
αx, βx:
ambout x 215
T
e
(1)
calculated input light value
16-bit ADC converted value of the ambient channel
temperature coefficient of the reference current (typ. Value = +375ppm/K)
offset of the measurement (digital value)
calibration values for channel x (see below)
During calibration at least 2 light levels (Ix1 and Ix2) have to be supplied to the target ambient channel (x) with its
photodiode at the same known temperature T. The closer these values are chosen to the range used in application, the
more accurate the final result will be. During the setting of these light levels, the output of ambient channel x: ambout x1
and amboutx2 are measured. This results in 2 equations and 2 unknowns: αx and βx. Both unknowns can be calculated from
following formulas:
I
T ln 1
ambout1 215
I
I2
and ln 1
ambout1 ambout 2
T
1
(2)
Note that these 2 values automatically correct any gain error of the connected photodiode and used lens system.
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9.1.3.3. Diagnostics Mode Operation
In diagnostics mode, the status of the external photodiodes is checked. The following checks are performed for each
ambient light channel X where X is C or D:
X disconnected
GNDAMB disconnected
X shorted to GNDA/GNDD/GNDAMB
X shorted to VCCA/VCCD
GNDAMB shorted to GNDA/GNDD
GNDAMB shorted to VCCA/VCCD
X shorted to other ambient light channel
Note that in spite of the ability to detect any error by the ambient diagnostics, an error on an ambient pin might still have
other unwanted effects.
Shorting any channel to GNDA/GNDD/GNDAMB will make the readout of the whole ambient block useless. At this
time a maximum current of 14mA might be constantly pulled from the supply, independent of the amount of
channels that is shorted to GNDA/GNDD/GNDAMB.
During normal operation, node GNDAMB should be considered a ground pin. Shorting this pin to any other voltage
might result in a short current of max 800mA!
Because of such unwanted effects, a detection of an error in diagnostics mode should be followed by a disabling of
the ambient channels in order to avoid disturbing the operation of other blocks in the system.
Note that unused channels should be connected with an external resistance (~60kOhm) to GNDAMB. Doing so will
avoid disturbing the other channels, but will give a constant error on the channel connected to GNDAMB.
9.1.4. Temperature Sensor
The on-chip temperature sensor measures the IC temperature. The output voltage of the sensor is converted by the 16-bit
ADC. The sensor will be trimmed for the best result during the production. This trimming value is not applied to the
temperature sensor internally, but is available to the customer through two on-chip registers Calib1 and Calib2, see 9.4.11.
The Calib1 register contains the slope of the temperature curve in LSB/K. The Calib2 register contains the offset of the
curve at a defined temperature at which the chip is tested in production.
The temperature is calculated from the temperature readout (tempout) and the gain and offset calibration data (calibration
data measured at 30°C) according to the formula:
TK 303.15K
11775 67 (calib2 32) tempout
67 (calib1 16)
K
or in °C:
T 30C
11775 67 (calib2 32) tempout
67 (calib1 16)
°C
Where:
tempout: digital temperature readout (16 Bit)
calib1: contents of calib1 register (5 Bit)
calib2: contents of calib2 register (6 Bit)
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9.1.5. DAC
For active light sensor applications, the MLX75030 DAC has been designed to have the following features:
To generate a pulse voltage signal from 1mV to 1V, so that LED current driven by LED driver can be 1mA to 1A if a 1Ω shunt
resistor is used between pins 18 and 19. After controlling and slewing circuitry, the final output voltage over external shunt
resistor is like in Figure 6.
DAC piece (2MSBs
B[7:6] )
00
01
10
11
Steps each piece
(6LSBs B[5:0] )
64
64
64
64
step size for
1 bit (V)
1.00E-04
5.00E-04
2.50E-03
1.25E-02
Range covered
(V)
6.40E-03
3.20E-02
1.60E-01
8.00E-01
Range start (V)
Range end (V)
1.05E-03
7.65E-03
4.07E-02
2.06E-01
7.35E-03
3.92E-02
1.98E-01
9.93E-01
Table 11 : The DAC voltage values based DAC codes (B[7:6]) can refer to the following table
1.20E+00
1.00E+00
8.00E-01
6.00E-01
4.00E-01
2.00E-01
0.00E+00
0
50
100
150
200
250
300
Figure 5 : Piece Wise Linear DAC voltage VS DAC codes
Trising = 3u
1mV...1V
1mV
Tdc_pulse
( max 400us)
tpulse_on
Figure 6: Vshunt waveform
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9.1.6. LED Driver
LED driver will set the DAC voltage on external shunt resistor by a closed regulation loop.
9.1.7. POR
The Power On Reset (POR) is connected to voltage supply.
The POR cell generates a reset signal (high level) before the supply voltage exceeds a level from 2.7V.
The cell contains a hysteresis of 100mV.
Figure 7: POR sequence
9.2. SPI
9.2.1. General Description of SPI Interface
After power-on, the sensor enters a reset state (invoked by the internal power-on-reset circuit). A start-up time tstartup after
power-on, the internal reference voltages have become stable and a first measurement cycle can start. To indicate that the
start-up phase is complete, the DR pin will go high (DR is low during the start-up phase).
The control of this sensor is completely SPI driven. For each task to be executed, the proper command must be uploaded
via the SPI. The SPI uses a four-wire communication protocol. The following pins are used:
CS: when CS pin is low, transmission and reception are enabled and the MISO pin is driven. When the CS pin goes
high, the MISO pin is no longer driven and becomes a floating output. This makes it possible that one micro -processor
takes control over multiple sensors by setting the CS pin of the appropriate sensor low while sending commands. The
idle state of the chip select is high.
SCLK: clock input for the sensor. The clock input must be running only during the upload of a new command or during
a read-out cycle. The idle state of the clock input is high.
MOSI: data input for uploading the different commands and the data that needs to be written into some regi sters.
The idle state of the data input is low.
MISO: data output of the sensor.
A SPI timing diagram is given in Figure 8. This is the general format for sending a command. First the CS pin must be set low
so that the sensor can accept data. The low level on the CS pin in combination with the first rising clock edge is used to
start an internal synchronization counter that counts the incoming bits. Data on the MOSI pin is clocked in at the rising
clock edge. Data on the MISO pin is shifted out during the falling clock edge. Note that the tri-state of the MISO pin is
controlled by the state of CS.
After uploading a command, the CS pin must be set high for a minimum time of t cs_inter in order to reset the internal
synchronization counter and to allow new commands to be interpreted.
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tcs_sclk
tsclk_cs
tcs_inter
CS
SCLK
7
MOSI
6
5
4
3
2
1
0
7
6
5
4
3
2
Control1 Byte
Control2 Byte
Data1 Byte
Data2 Byte
1
0
MISO
Tri state
Tri state
Figure 8 : SPI Timing Diagram for 2 byte instructions
The basic structure of a command consists of 2 bytes: the Control1 Byte and the Control2 Byte that are uploaded to the
device and the Data1 Byte and the Data2 Byte that are downloaded to the micro-controller. Exceptions are the commands
needed to read and write the user registers (WR/RR). These commands need 3 bytes.
The timing diagram is given in Figure 9.
All data transfer happens with MSB first, LSB last. Referring to Figure 8 and Figure 9 : within a byte, bit 7 is always defined
as the MSB, bit 0 is the LSB. This applies to all data transfers from master to slave and vice versa.
tcs_sclk
tsclk_cs
tcs_inter
CS
SCLK
MOSI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
Control1 Byte
Control2 Byte
Control3 Byte
Data1 Byte
Data2 Byte
Data3 Byte
1
0
MISO
Tri state
Tri state
Figure 9 : SPI Timing Diagram for 3 byte instructions
The MSB of the Control1 Byte (bit 7) is a command token: setting this bit to 1 means that the Control1 Byte will be
interpreted as a new command. If the MSB is 0, the next bits are ignored and no command will be accepted. The idle
command has a Control1 Byte of 0x00. The command type (chip reset, power mode change, start measurements, start
read-out, read/write register) is selected with the next bits 6..0 of the Control1 Byte.
The Control2 Byte consists of 0x00, to allow clocking out the Data2 Byte. The Data2 Byte contains always the Ctrl1 Byte that
was uploaded. Thus the micro-controller can check that the Data2 Byte is an exact replica of the Ctrl1 Byte, to verify that
the right command is uploaded to the device.
The Data1 Byte contains some internal status flags to allow checking the internal state of the device.
The internal status flags are defined in the table below.
See section 9.3 for more information concerning the operation of the status flags.
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Status flag
Status when bit is set
Status when bit is clear
Bit 7 (MSB)
Previous Command was valid
Bit 4
Previous Command was invalid
Power State:
11 = (reserved)
10 = Normal Running Mode
01 = Stand-by State
00 = Sleep State
Sleep Request was sent
Bit 3
Standby Request was sent
No Standby Request available
Bit 2
Device is in TestMode
Internal Oscillator is enabled (Standby Mode or
Normal Running Mode)
Critical Error occurred
Device is not in TestMode
Internal Oscillator is shut down (Sleep
Mode)
No Error is detected
Bit 6..5
Bit 1
Bit 0 (LSB)
No Sleep Request available
Table 12 : Internal Status Flags as given in the Data1 Byte
Table 13 : Instruction set of the Active light sensor summarizes the instruction set of the sensor.
A detailed explanation of these different commands is given in Section 9.2.2.
Symbol Command Description Control1 Byte
Control2 Byte
Control3 Byte
NOP
Idle Command
0000 0000
0000 0000
N/A
CR
Chip Reset
1111 0000
0000 0000
N/A
RSLP
Request Sleep
1110 0001
0000 0000
N/A
CSLP
Confirm Sleep
1010 0011
0000 0000
N/A
RSTBY
Request Standby
1110 0010
0000 0000
N/A
CSTBY
Confirm Standby
1010 0110
0000 0000
N/A
NRM
Normal Running Mode
1110 0100
0000 0000
N/A
SM
Start Measurement
1101 R2R1R0T
M6..M3 M2M1M0P
N/A
SD
Start Diagnostics
1011 0000
M6..M3 M2M1M0P
N/A
RO
Start Read-Out
1100 0011
0000 0000
N/A
WR
Write Register
1000 0111
D7..D0
A3..A0 P1P000
RR
Read Register
1000 1110
A3..A0 0000
0000 0000
Table 13 : Instruction set of the Active light sensor
Besides the above instruction set, there are some test commands available for production test purposes.
To prevent unintentional access into these test modes, it requires multiple commands before the actual test mode is
entered.
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State
Diagram
MLX75308BA
An overview of modes in which the device
can operate
is shown
in Figure 10 : State Diagram of the MLX75030below.
It also indicates which commands are available in the different operation modes.
Set
Flag 7
Set
Flag 7
RSTBY, RSLP,
CSTBY, CSLP,
RO only
Clear
Flag 7
RSTBY, RSLP,
CSTBY, CSLP,
RO only
NOP, WR, RR,
SM, SD, RO after
SM or SD
WD Disable
Clear Flag 4
Clear Flag 7
Standby Mode
Flag 2+6 = 0
Flag 1+5 = 1
Sleep Mode
Flag 1+2+5+6 = 0
CSLP & Flag 4=1
CR
NOP, WR, RR,
SM, SD, RO after
SM or SD
Low level on
WAKE_UP pin
Low level on
WAKE_UP pin
NRM
WD
Initialized
Clear Flag 3
Clear Flag 7
Set
Flag 7
NRM
RO only, RO
when DR=0
CSTBY & Flag 3=1
Clear
Flag 7
CR
WD
Initialized
POR
Clear Flag 3
Clear Flag 4
Clear Flag 7
Low level on
WAKE_UP pin
Clear
Flag 7
CR
DR low for
50ms
NOP, WR, RR, RO after
SM or SD when DR=1,
CSTBY & Flag 3=0,
CSLP & Flag 4=0
Test Mode
Flag 2 = 1
Normal Running Mode
(Idle State)
Flag 2+5 = 0
Flag 1+6 = 1
NRM
CR
Clear Flag 3
Clear Flag 4
Clear Flag 7
RSLP
RSTBY
Set Flag 3
Clear Flag 7
SM, SD,
SM+RO,
SD+RO
Clear
Flag 7
Set Flag 4
Clear Flag 7
CR
DR = 1
DR = 0
Measurement Sequence or
Diagnostic Measurement
Sequence
Figure 10 : State Diagram of the MLX75030
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9.2.2. Detailed Explanation of SPI Instruction Words
9.2.2.1. NOP – Idle Command
The Idle Command can be used to read back the internal status flags that appear in the Data1 Byte.
The state of the device is not changed after the NOP command is uploaded.
9.2.2.2. CR – Chip Reset Command
After upload of a Chip Reset command, the sensor returns to a state as it is after power-up (Normal Running Mode) except
for the watchdog counter, the state of the MR line and the contents of the 'Rst' register. The watchdog counter, the 'Rst'
register and the state of the MR line will not be influenced by a CR command.
The CR command can be uploaded at any time, even during a measurement or a read-out cycle, provided that the internal
synchronization counter is reset. This is done by setting the CS pin high for at least a time tcs_inter.
When a CR command is uploaded during sleep mode resp. standby mode, the device goes automatically into normal
running mode. Note that this requires a time t wakeup_slp resp. twakeup_stby before the internal analog circuitry is fully set up
again.
Right after upload of a CR command, the DR pin will go low during a time tstartup. Once the wake-up/reset phase is
complete, the DR pin will go high.
9.2.2.3. RSLP/CSLP – Request Sleep/Confirm Sleep
To avoid that the slave device goes unintentionally into sleep mode, the master has to upload two commands. First a RSLP
(Request Sleep) shall be uploaded, then the slave sets bit 4 of the internal status flag byte high. The master has to confirm
the sleep request by uploading a CSLP (Confirm Sleep). Afterwards the slave will go into Sleep Mode, hereby reducing the
current consumption.
The status flag can be cleared by uploading a CR command or a NRM command.
Note that uploading a Chip Reset makes the device switching into normal running mode.
When the device is operating in Sleep Mode, the WAKE_UP pin will be monitored. A falling edge on WAKE_UP will wake up
the device and will switch it into Normal Running Mode.
When the device is operating in Sleep Mode, the WT pin will be monitored. If a falling edge is detected, the Critical Error
flag in the Internal Status Flag Byte will be set high and the corresponding bit in the 'Err' register will be set high (refer also
to Sections 9.3 and 9.4.7).
Note that no pull-up or pull-down resistor is foreseen on the WAKE_UP pin. To avoid that parasitic spikes can wake up the
device, the WAKE_UP input is debounced (typical debounce time is in the range of 2µs). The low time on the WAKE_UP pin
should be at least a time twu_l.
The state of the DR pin will not be changed when going into Sleep Mode. However, after a wake-up event the DR pin is set
low during a time twakeup_slp.
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9.2.2.4. RSTBY/CSTBY - Request Standby/Confirm Standby
To put the device in Standby Mode, a similar system is used: the master shall send the RSTBY command, requesting the
slave to go into Standby Mode. The slave device sets bit 3 of the internal status flag byte high, indicating that it wants to go
into standby. The master has to confirm this by sending the CSTBY byte.
The status flag can be cleared by uploading a CR command or a NRM command.
Uploading a Chip Reset makes the device switching into normal running mode.
When the device is operating in Standby Mode, the WAKE_UP pin will be monitored. A falling edge on WAKE_UP will wake
up the device and will switch it into Normal Running Mode.
Note that no pull-up or pull-down resistor is foreseen on the WAKE_UP pin. To avoid that parasitic spikes can wake up the
device, the WAKE_UP input is debounced (typical debounce time is in the range of 2µs). The low time on the WAKE_UP pin
should be at least a time twu_l.
The state of the DR pin will not be changed when going into Standby Mode. However, after a wake-up event the DR pin is
set low during a time twakeup_stby.
9.2.2.5. NRM – Normal Running Mode
The NRM command shall be used to wake up the device from Sleep Mode, or to go from Standby into Normal Running
Mode. This requires a time twakeup_slp resp. twakeup_stby before the internal analog circuitry is fully set up again. The NRM will
also clear the Sleep Request or Standby Request flag.
When the NRM command is uploaded during normal running mode, the state of the device will not be influenced, except
when the Sleep Request or Standby Request flag was set high due to a RSLP or RSTBY command. In this case, the Sleep
Request or Standby Request flag will be cleared; the state of the DR pin will not change.
9.2.2.6. SM – Start Measurement
The SM command is used to start up measurement cycles. Several types of measurements can be selected with the
measurement selection bits M6..M0 in the Control2 Byte:
M6: setting this bit high enables the temperature measurement
M5: setting this bit high enables the read-out of the two ambient light channels
M4: setting this bit high enables the DC light measurement in the active light channel(s)
M3: setting this bit high fires LED A
M2: setting this bit high fires LED B
M1: setting this bit high enables the active light measurement in channel A
M0: setting this bit high enables the active light measurement in channel B
A typical timing diagram is given in Figure 11. After uploading the SM command, the measurement cycle is started as soon
as the CS pin is set high. The ADC starts converting all the needed analog voltages and stores the digital values in registers.
A time tcs_dr after CS is set high, the state of the DR pin goes low. A time tdr after DR was set low, the state of the DR pin
becomes high, indicating that all measurements are completed and that the resulted data is available for read-out (readback of the stored data in the registers). This time can be up to 231.84us, if an internal autozeroing process is under
execution and needs to be finished.
Table 14 : Example measurement execution times tdr gives an overview of some execution times t dr for the basic types of
measurements.
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Measurement Type
Temperature measurement
Ambient light measurements on all channels C and D
Active light measurements on channels A & B, with 32 pulses, pulse frequency of 48.1kHz,
Tdem=6us, Tdc_pulse=400us
DC + Active light measurements on channels A & B, with 32 pulses, pulse frequency of
48.1kHz, Tdem=6us, Tdc_pulse=400us
Temperature measurement + Ambient light measurements on all channels C & D + DC +
Active light measurements on channels A & B, with 32 pulses, pulse frequency of 48.1kHz,
Tdem=6us, Tdc_pulse=400us
Min. tdr
(µs)
Max. tdr
(µs)
269
388
298
430
1513
1673
1811
2002
2079
2299
Table 14 : Example measurement execution times t dr
Note that the DR pin can be used as an interrupt for the master device as it indicates when a read-out cycle can be
started.
Note that measurement execution of ActiveLight measurement only is not allowed. ActiveLight measurements must
always be done with Ambient Light measurements.
CS
SCLK
tcs_dr
MOSI
MISO
tdr
SM/SD Command
Tri state
Status Flags/Ctrl 1
Tri state
DR
Internal State
Idle State
Measurement Cycle SM/SD
Idle State
Figure 11 : Timing Diagram of a Measurement Cycle
The SM command contains 3 option bits R2R1R0. These bits set the polarity of the anti-aliasing filters, the switched
capacitors low pass filters and the ADC input buffer in active light channels A & B:
R2: this bit inverts the op-amp in the anti-aliasing filter. The output will change from (Signal + Offset_opamp_aa)
to (Signal - offset_opamp_aa). In this way, by processing 2 measurements with inverted R2 bits, the offset of the
AA filter can be cancelled.
R1: Inversion of the offset of active light_sclp_filter. The output will change from (Signal + Offset_opamp_sclp) to
(Signal - offset_opamp_sclp). In this way, by processing 2 measurements with inverted R1 bits, the offset of the
SCLP filter can be cancelled.
R0: Inversion of the offset of the ADC_buffer. The output will change from (Signal + Offset_opamp_buf) to (Signal offset_opamp_buf). In this way, by processing 2 measurements with inverted R0 bits, the offset of the SCLP filter
can be cancelled.
T: this bit replaces the light pulses by internal current pulses during the active light measurements.
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The SM command contains an option bit T. If this bit is set to 0, normal active light measurements are performed (i.e. the
external LEDs are fired and the active light channels A and/or B are measured). If this bit is set to 1, no LEDs are fired, but
internal test pulses are applied to channels A and/or B. The internal test pulses can be influenced in amplitude by the bits
DACA7 and DACA6. Limits for ADC outputs of the TIA test pulses are shown in Table 15 : Current levels for active light test
mode.
DACA7
DACA6
I_Testpulse [uA]
0
0
1
1
0
1
0
1
5
13
21
29
Table 15 : Current levels for active light test mode
In the Control2 byte an even parity bit P is foreseen. The parity bits calculation is based on the measurement selection bits
M6..M0. If the number of ones in the given data set [M6..M0] is odd, the even parity bit P shall be set to 1, making the total
number of ones in the set [M6..M0, P] even.
The SPI invalid flag will be set when the parity bit does not correspond to the calculated parity bit.
After upload of a SM/SD command, no other commands will be accepted till DR is high. This is done to avoid too much
disturbances in the analog part. Once DR is high, the next command will be accepted. An exception however is the Chip
Reset command. This will always be accepted.
Note that none of the SM/SD commands are available in Standby Mode.
9.2.2.7. RO – Start Read-Out
When the state of the DR pin changed into a high state, the measurement data is available for read-out. The RO command
shall be uploaded to start a read-out cycle and to start reading out the data that was stored in the internal registers.
To make sure that no memory effects can occur, all data registers are cleared at the end of each read-out cycle.
A typical timing diagram is given in Figure 12 below:
CS
tcs_dr
8tsclk
8tsclk
RO-Ctrl1
RO-Ctrl2
X*8tsclk
SCLK
tdr
MOSI
MISO
SM1x/SM2/SM3x
Command
Tri state
Status Flags
1 byte
Ctrl1
1 byte
Output Data Frame
Tri state
X bytes
DR
Figure 12 : Timing diagram for Read-Out
The data that appears on the MISO pin depends on the type of measurement that was done (i.e. it depends on the
command that was uploaded: SM/SD and the selected measurement bits M 6..M0).
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The table below shows the Output Data Frame when all measurements are selected :
Data
Byte
Number
Output Data Frame Contents
Comments
Byte 3
Byte 4
Temperature (8 MSB)
Temperature (8 LSB)
Byte 5
Ambient light channel C measurement (8 MSB)
Byte 6
Ambient light channel C measurement (8 LSB)
Byte 7
Ambient light channel D measurement (8 MSB)
Byte 8
Ambient light channel D measurement (8 LSB)
Depends on M6
Depends on M6
Depends on M5
+ on EN_CH_C
Depends on M5
+ on EN_CH_C
Depends on M5
+ on EN_CH_D
Depends on M5
+ on EN_CH_D
Byte 9
Byte 10
not used
not used
DC measurement of IR channel A, before the active light burst measurement
(8 MSB)
DC measurement of IR channel A, before the active light burst measurement
(8 LSB)
DC measurement of IR channel B, before the active light burst measurement
(8 MSB)
DC measurement of IR channel B, before the active light burst measurement
(8 LSB)
Byte 11
Byte 12
Byte 13
Byte 14
Byte 15
Active light burst measurement of IR channel A (8 MSB)
Byte 16
Active light burst measurement of IR channel A (8 LSB)
Byte 17
Active light burst measurement of IR channel B (8 MSB)
Byte 18
Active light burst measurement of IR channel B (8 LSB)
Byte 19
Byte 20
Byte 21
Byte 22
Byte 23
DC measurement of IR channel A, after the active light burst measurement (8
MSB)
DC measurement of IR channel A, after the active light burst measurement (8
LSB)
DC measurement of IR channel B, after the active light burst measurement (8
MSB)
DC measurement of IR channel B, after the active light burst measurement (8
LSB)
CRC (8 bit)
Depends on M4
Depends on M4
Depends on M4
Depends on M4
Depends on M1
+ LED selection
depends on M3/M2
Depends on M1
+ LED selection
depends on M3/M2
Depends on M0
+ LED selection
depends on M3/M2
Depends on M0
+ LED selection
depends on M3/M2
Depends on M4
Depends on M4
Depends on M4
Depends on M4
Output always
Table 16 : SM Output Data Frame
Note : When certain measurements are disabled, the corresponding data bytes are omitted from the Output Data Frame.
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Cyclic Redundancy Check Calculation
In all Output Data Frames, a CRC byte is included as last byte. This byte provides a way to detect transmission errors
between slave and master. An easy method to check if there were no transmission errors is to calculate the CRC of the
whole read-out frame as defined in previous tables. When the calculated CRC results in 0x00, the transmission was error
free. If the resulting CRC is not equal to zero, then an error occurred in the transmission and all the data should be ignored.
For more information regarding the CRC calculation, please refer to section 9.8.
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9.2.2.8. SM+RO - Start Measurement combined with Read-Out
If after upload of the SM command, extra clocks are given (without putting CS high!), the data stored in the internal
registers will appear on the MISO pin. At the end of the read-out phase the internal registers will be cleared to avoid
memory effects in the next read-outs.
The newly uploaded SM command will be executed after the read-out, when the CS pin goes high.
The two figures below show the difference between the two modes of operation :
- Figure 13 : Separated SM - RO (X value is defined in Figure 6)shows the operation with separate SM and RO commands.
After upload of a SM command, the measurement cycle will start and the internal registers will be filled. Once the DR pin is
high, the RO command can be uploaded to start the read-out cycle. All data of the internal registers will be transferred and
at the end of the read-out the registers will be cleared.
- Figure 14 : Combined SM - RO (X value is defined in Figure 6) shows the operation with the combined SM and RO. First
one has to upload a SM command to start a measurement. The data is available for read-out when the DR pin goes high.
Instead of uploading a RO command, a SM command can be uploaded again to combine read-out and the start of the next
measurement cycle. If extra clocks are given after upload of the SM command, the data of the internal registers becomes
available on the MISO pin. Note that the CS pin shall not be set high until the read-out is finished. Once CS pin goes high,
the DR pin is set low and a new measurement cycle will be started. A time t dr later the DR pin goes high to indicate that the
data is available.
CS
8tsclk
8tsclk
SM/SD
0x00
tcs_dr
8tsclk
8tsclk
RO-Ctrl1
RO-Ctrl2
X*8tsclk
SCLK
MOSI
MISO
Tri state
Status Flags
1 byte
Tri state
Ctrl1
Status Flags
tdr
1 byte
1 byte
Ctrl1
1 byte
Tri state
Output Data Frame
X bytes
DR
Device State
Idle
Measurement Cycle
Idle
Internal Registers
0x00
Filling up
Data Available
Read-out
Idle
Emptying
0x00
Figure 13 : Separated SM - RO (X value is defined in Figure 6)
CS
8tsclk
8tsclk
SM/SD
0x00
tcs_dr
8tsclk
8tsclk
tcs_dr
X*8tsclk
SCLK
MOSI
MISO
Tri state
Status Flags
1 byte
SM/SD
Tri state
Ctrl1
1 byte
tdr
Status Flags
1 byte
0x00
Ctrl1
1 byte
Tri state
Output Data Frame
tdr
X bytes
DR
Device State
Internal Registers
Idle
0x00
Measurement Cycle
Filling up
Idle
Data Available
Read-out
Emptying
0x
00
Measurement Cycle
Idle
Filling up
Data Available
Figure 14 : Combined SM - RO (X value is defined in Figure 6)
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9.2.2.9. WR/RR – Write/Read Register
The slave contains several user registers that can be read and written by the master.
The WR and RR commands are used for that.
The WR command writes the contents of an 8-bit register addressed by bits A3..0 with data D7..0. Data is sent to the device
over the MOSI pin. Control2 Byte contains the 8 bit data that shall be written into the target register. Control3 Byte
contains the address of the target register.
The WR command is defined in the table below:
Control1 Byte
Control2 Byte
Control3 Byte
1000 0111
D7D6D5D4 D3D2D1D0
A3A2A1A0 P1P000
D7D6D5D4 D3D2D1D0
A3A2A1A0
P1P0
Data contents of register to be written
Address of target register
Parity bits (P1 = odd parity bit, P0 = even parity bit)
Data1 Byte
Data2 Byte
Data3 Byte
Status Flag Byte
1000 0111
0000 0000
Table 17 : Write Register command
In order to detect some transmission errors while writing data towards the slave device, the micro-controller has to
compute an odd and an even parity bit of the Control2 and the 4 MSB's of the Control3 byte and send these parity bits to
the slave. The slave will check if the parity bits are valid. The data will only be written into the registers if the parity bits are
correct. If the parity bits are not correct, bit 7 of the internal Status Flag Byte will be set high, indicating that the command
was invalid. This can be seen when uploading a NOP command (when one is only interested in reading back the internal
status flags) or during upload of the next command.
In case the parity bits were not correct, the data of the registers will not be changed.
The parity bits calculation is based on the data D7..D0 and A3..A0. If the number of ones in the given data set [D 7..D0, A3..A0]
is odd, the even parity bit P0 shall be set to 1, making the total number of ones in the set [D 7..D0, A3..A0, P0] even.
Similar: if the number of ones in the given data set [D7..D0, A3..A0] is even, the odd parity bit P1 shall be set to 1, making the
total number of ones in the set [D7..D0, A3..A0, P1] odd.
Note that the parity bits can be generated with XOR instructions: P1 = XNOR(D7..D0, A3..A0) and P0 = XOR(D7..D0, A3..A0). The
odd parity bit P1 should always be the inverse of the even parity bit P0.
The RR command returns the contents of an 8-bit register addressed by bits A3..0. Data is read back over the MISO pin. The
Data1 Byte contains the Internal Status Flag byte. Data2 Byte contains the copy of the Control1 Byte. Data3 Byte contains
the 8 bits of the target register.
The RR command is defined in the table below:
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Control1 Byte
Control2 Byte
Control3 Byte
1000 1110
A3A2A1A0 0000
0000 0000
A3A2A1A0
Address of target register
Data1 Byte
Data2 Byte
Data3 Byte
Status Flag Byte
1000 1110
D7D6D5D4 D3D2D1D0
D7..0
Data contents of register read
Table 18 : Read Register command
Note that the WR and RR commands are commands that require 3 bytes instead of 2 bytes.
An overview of the user registers that can be accessed with WR/RR commands and more general information concerning
the user registers can be found in section 9.4
9.2.2.10. SD – Start Diagnostics
The SD command will start a measurement cycle in which internal signals will be measured and converted. With this
command it is possible to test some circuits in the chip and check if they are functioning as expected.
The SD command behaves in much the same way as the SM commands: instead of uploading a SM command, a SD
command can be uploaded. This starts the measurement cycle and conversion of some internal signals. The pin DR goes
high when the cycle is completed, indicating that a read-out can be started. With the RO command it is possible to read out
the data and check if all the data values are within certain ranges.
After upload of a SD command, no other commands will be accepted till DR is high. This is done to avoid too much
disturbances in the analog part. Once DR is high, the next command will be accepted. An exception however is the Chip
Reset command. This will always be accepted. The SD command is not available in Standby Mode.
Similar to the SM command, the SD command has some measurement selection bits M 6..M0 in the Control2 Byte. Different
measurements can be selected with these bits:
M6: setting this bit high enables the ADC diagnostics
M5: setting this bit high enables the DAC-ADC diagnostics
M4: setting this bit high enables the Ambient Diode checks
M3..M0: (reserved)
Table 19 gives an overview of some execution times tdr for the basic types of measurements.
Measurement Type
ADC Diagnostics
DAC-ADC Diagnostics
Ambient Diode checks
ADC + DAC-ADC + Ambient Diode Diagnostics
Min. tdr (µs)
Max. tdr (µs)
224
91
370
680
249
102
410
752
Table 19: Basic Measurement Execution Times t dr
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If all possible measurements are selected, the Output Data Frame is defined in the table below:
Data Byte Number
Data Byte Contents after SD command
Comments
Byte 3
ADCtest0 (8 MSB)
Depends on M6
Byte 4
ADCtest0 (8 LSB)
Depends on M6
Byte 5
ADCtest1 (8 MSB)
Depends on M6
Byte 6
ADCtest1 (8 LSB)
Depends on M6
Byte 7
ADCtest2 (8 MSB)
Depends on M6
Byte 8
ADCtest2 (8 LSB)
Depends on M6
Byte 9
ADCtest3 (8 MSB)
Depends on M6
Byte 10
ADCtest3 (8 LSB)
Depends on M6
Byte 11
ADCtest4 (8 MSB)
Depends on M6
Byte 12
ADCtest4 (8 LSB)
Depends on M6
Byte 13
DAC-ADC Test (8 MSB)
Depends on M5
Byte 14
DAC-ADC Test (8 LSB)
Depends on M5
Byte 15
00000 + CDx Ambient Diodes Detection (3 bit)
Depends on M4
Byte 16
CRC (8 bit)
Output always
Table 20 : SD Output Data Frame
When certain measurements are disabled, the corresponding data bytes are omitted from the Output Data Frame.
ADCtest0/1/2/3/4
These measurements are AD conversions of some internal reference voltages:
ADCtest0 is typically at 1/16 of the ADC range: ADCtest0 = 0x0E00 .. 0x1200.
ADCtest1 is typically at 1/4=4/16 of the ADC range: ADCtest1 = 0x3E00 .. 0x4200.
ADCtest2 is typically at 3/4=12/16 of the ADC range: ADCtest2 = 0xBE00 .. 0xC200.
ADCtest3 is typically at 15/16 of the ADC range: ADCtest3 = 0xEE00 .. 0xF200.
ADCtest4 is similar to ADCtest0/1/2/3: an AD conversion of an internal reference voltage is made. However, an
independent voltage reference is used as input for the ADC in case of ADCtest4. In the case of ADCtest0/1/2/3, the
reference voltages are generated from the references used for the ADC.
The typical output for ADCtest4 will be as listed in below table:
ADCtest4 values
@ Vs=3.0V
@ Vs=3.3V
@ Vs=3.6V
min
33400
30400
27400
typ
35400
32400
29400
max
37400
34400
31400
LSB
LSB
LSB
DAC-ADC test
A DAC-ADC test measurement is performed in the following way: the DAC output is connected to the ADC input. The DAC
input will be DACA from register 'SetAH'. This DAC-input will be converted to an analog output voltage that will be
converted again by the ADC to give a digital value. This digital value is given in the bytes DAC-ADC Test.
Ambient Diodes Detection
During the Diagnostics measurement, the status of the external photo diodes connected to the ambient light channel
inputs is checked.
Three bits CDx are output: when the bit C is set high, an error on the photo diode channel C is present.
In a similar way, bit D indicate if errors on ambient light channels D is present or not.
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9.3. Internal Status Flags
Bit 7: Previous Command invalid/valid
When an uploaded command is considered invalid, bit 7 will be set high. This bit can be read out when the next command
will be uploaded. If the next command is valid, bit 7 will be cleared again.
A command is considered invalid in case:
- a command is unknown (i.e. all commands that are not mentioned in Table 13)
- the parity bit in the SM or SD command is not correct
- the parity bits in a WR command are not correct
- when a command (except the CR command) was sent during a measurement cycle (i.e. after uploading a SM/SD
command, when DR is still low)
- when a RO command was sent when DR is low (at any time, i.e. not only after uploading a SM/SD command)
- if a '1' is written into one of the bits of the 'Err' register
- if an ambient measurement is requested in case all bits EN_CH_C/EN_CH_D/EN_DIAGAMB are zero
Bit 6..5: Power State, Bit 4: Sleep request, Bit 3: Standby request
The behaviour of the power state and the sleep request bits is explained in Figure 15 : Power State and Sleep Request bits.
First a RSLP command is uploaded to the sensor. As a result of that, the sensor will put the status flag bit 4 (sleep request
flag) high. The master can read out that flag by uploading a NOP command, or when uploading other commands.
The master can confirm to go into sleep mode by uploading a CSLP command. The request flag will be reset and the sensor
will switch into sleep state. The status flag bits 6 and 5 will be set accordingly.
CS
SCLK
MOSI
RSLP
(NOP)
CSLP
(NOP)
NRM
MISO
Status Flag Bit 4
(Sleep Request)
Status Flag Bits 6..5
(Power State)
Device State
10
00
10
Normal Running Mode
Sleep State
Normal Running Mode
Figure 15 : Power State and Sleep Request bits
To go into standby mode, the same procedure shall be applied: uploading a RSTBY command makes the request standby
flag going high. Uploading a CSTBY will make the device going into standby mode, whereby the request standby flag will be
cleared and the power state bits will be set accordingly.
Bit 2: Device in TestMode/Normal Mode
To make the sensor efficiently testable in production, several test modes are foreseen to get easy access to different
blocks. The status flag bit 2 indicates if the device is operating in Test Mode or Normal Mode.
If the device enters test mode by accident, the application will still work like normal. However, the status flag bit 2 will be
set high. The master can take actions to get out of test mode by uploading a CR command.
Bit 1: Internal Oscillator is enabled/disabled
This bit is high when the internal oscillator is enabled. Once the RCO is shut down the bit will be set low.
Bit 0: Critical Error is detected/not detected
During each measurement cycle there is a monitoring of the voltage on critical nodes along the analog paths. When the
voltage of one of these controlled nodes goes out of its normal operating range, the Critical Error Flag will be set high.
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The Critical Error Flag will also be set high when a falling edge on the WT pin will be detected while the device is in Sleep
Mode.
Following nodes are monitored:
- TIA output: when the output is clipped (either high or low), the Critical Error Flag will be set high
- Difference between DAC output and shunt-feedback
- An internal reference voltage
- Output of the common mode SC-amplifiers of the Ambient Light/Temperature Channels
- Frequency on RCO output
In case the Critical Error Flag was set high, the 'Err' register indicates which node voltages got out of their normal operating
range. More info about the 'Err' register can be found in Section 9.4.7.
The Critical Error Flag remains high as long as the 'Err' register is not cleared. Once the 'Err' register is cleared, the Critical
Error Flag will be cleared as well.
Note: after POR, or after wake-up from Sleep/Standby, some bits in the 'Err' register might be set. As such the Critical Error
Flag might be set as well.
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9.4. User Registers Overview
Name
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SetAna
0x0
Tdem3
Tdem2
Tdem1
Tdem0
LEDDRV_HG
Tdc_pulse1
Tdc_pulse0
Unity_Gain
SetAH
0x1
DACA7
DACA6
DACA5
DACA4
DACA3
DACA2
DACA1
DACA0
SetAL
0x2
GAIN_ADJ_
AA_A2
GAIN_ADJ_
AA_A1
GAIN_ADJ_
AA_A0
BW_ADJ_
AA_A2
BW_ADJ_
AA_A1
BW_ADJ_
AA_A0
BW_SEL_
LP_A1
BW_SEL_
LP_A0
SetBH
0x3
DACB7
DACB6
DACB5
DACB4
DACB3
DACB2
DACB1
DACB0
SetBL
0x4
GAIN_ADJ_
AA_B2
GAIN_ADJ_
AA_B1
GAIN_ADJ_
AA_B0
BW_ADJ_
AA_B2
BW_ADJ_
AA_B1
BW_ADJ_
AA_B0
BW_SEL_
LP_B1
BW_SEL_
LP_B0
SetPF
0x5
NP3
NP2
NP1
NP0
EN_DCCOMP
RPF2
RPF1
RPF0
Err
0x6
-
Err6
Err5
Err4
Err3
Err2
Err1
-
0x7
DC_COMP_
IC13
DC_COMP_
IC12
DC_COMP_
IC11
DC_COMP_
IC10
Rst
TO
POR
DC_COMP_
IC21
DC_COMP_
IC41
DC_COMP_
IC20
DC_COMP_
IC40
GAIN_BUF2
GAIN_BUF1
GAIN_BUF0
DC_COMP_
IC30
-
-
GAIN_BUF4
GAIN_BUF3
TRIM_
TC_BGI3
TRIM_
TC_BGI2
TRIM_
TEMP5
TRIM_
TC_BGI1
TRIM_
TEMP4
TRIM_
TC_BGI0
TRIM_
TEMP3
-
-
-
TRIM_
TEMP2
TRIM_
TEMP1
EN_DIAG_B
EN_CH_A
EN_CH_B
EN_CH_C
EN_CH_D
TRIM_
TEMP0
EN_
DIAGAMB
DC_COMP_
IC51
DC_COMP_
IC50
-
-
Tamb1
0x8
DCComp2
0x9
GainBuf
0xA
-
Calib1
0xB
TRIM_
TC_BGI4
Calib2
0xC
-
-
EnChan
0xD
EN_TEMP
EN_DIAG_A
0xE
DC_COMP_
IC53
DC_COMP_
IC52
Tamb
DC_COMP_
IC22
DC_COMP_
IC42
DC_COMP_
IC31
DCComp1
DC_COMP_
IC33
DC_COMP_
IC23
DC_COMP_
IC43
DC_COMP_
IC32
Tamb0
Table 21. User registers overview
In the next sections, all the bits of these registers are described. The value of the register at Power-On is indicated in the
line 'Init' (0 or 1 or x=unknown) and the read/write access ability is indicated in the line 'Read/Write' (R indicates Read
access, W indicates Write access).
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9.4.1. SetAna register
This register contains some settings of the analog chain.
Bit
SetAna
0x0
Read/Write
Init
7
6
5
4
3
Tdem3
Tdem2
Tdem1
Tdem0
LEDDRV_HG
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
2
Tdc_
pulse1
1
Tdc_
pulse0
R/W
1
R/W
0
0
Unity_Gain
R/W
1
Tdem: changes the demodulator delay time in the active light channel
Tdem3 Tdem2 Tdem1 Tdem0 Delay time (in µs, +/-5%)
0
0
0
0
0
0
0
0
1
0.4
0
0
1
0
0.8
0
0
1
1
1.2
0
1
0
0
1.6
0
1
0
1
2
0
1
1
0
2.4
0
1
1
1
2.8
1
0
0
0
3.2
1
0
0
1
3.6
1
0
1
0
4
1
0
1
1
4.4
1
1
0
0
4.8
1
1
0
1
5.2
1
1
1
0
5.6
1
1
1
1
6
LEDDRV_HG: 1 = selects high gain mode of LED driver, 0 = selects low gain mode
Tdc_pulse: defines the time that the DC component in the active light pulse signal is
enabled before the actual active light pulses start
Tdc_
pulse1
Tdc_
pulse0
Delay time
(in µs, +/-5%)
0
0
50
0
1
100
1
0
200
1
1
400
Unity_Gain: only during active light measurements: 1=ADC buffer is bypassed, 0=ADC gain stage
is used (gain is set with bits GAIN_BUF in register 'GainBuf')
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Datasheet
9.4.2. SetAH register
This register defines the DAC level for IR channel A.
SetAH
0x1
Bit
7
DACA7
6
DACA6
5
DACA5
4
DACA4
3
DACA3
2
DACA2
1
DACA1
0
DACA0
Read/Write
Init
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DACA: the 8 bits of the DAC level for IR channel A
9.4.3. SetAL register
This register defines the gain and cut-off frequency adjustments for IR channel A.
Bit
SetAL
0x2
Read/Write
Init
7
6
5
4
3
2
1
0
GAIN_
ADJ_
AA_A2
GAIN_
ADJ_
AA_A1
GAIN_
ADJ_
AA_A0
BW_
ADJ_
AA_A2
BW_
ADJ_
AA_A1
BW_
ADJ_
AA_A0
BW_
SEL_
LP_A1
BW_
SEL_
LP_A0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
1
R/W
0
R/W
1
GAIN_ADJ_AA_A: gain adjustment of anti-aliasing filter of channel A
GAIN_ADJ_
AA_A2
GAIN_ADJ_
AA_A1
GAIN_ADJ_
AA_A0
Gain
Gain (dB)
0
0
0
2.00
6.02
0
0
1
4.29
12.64
0
1
0
6.57
16.35
0
1
1
8.86
18.95
1
0
0
11.14
20.94
1
0
1
13.43
22.56
1
1
0
15.71
23.93
1
1
1
18.00
25.11
BW_ADJ_AA_A: cut-off frequency adjustment of anti-aliasing filter of channel A
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BW_ADJ_
AA_A2
BW_ADJ_
AA_A1
BW_ADJ_
AA_A0
3dB Cut-off
Frequency (kHz)
0
0
0
18
0
0
1
20
0
1
0
22.5
0
1
1
25
1
0
0
30
1
0
1
35
1
1
0
43
1
1
1
55
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Datasheet
BW_SEL_LP_A: cut-off frequency selection of low-pass filter of channel A
BW_SEL_
BW_SEL_
Cut-off Frequency
Cut-off Frequency
LP_A1
LP_A0
(%f0)
(kHz @ f0=70kHz)
0
0
23.5
16.5
0
1
12
7.8
1
0
5.9
4.2
1
1
3
2.1
9.4.4. SetBH register
This register defines the DAC level for IR channel B.
SetBH
0x3
Bit
7
DACB7
6
DACB6
5
DACB5
4
DACB4
3
DACB3
2
DACB2
1
DACB1
0
DACB0
Read/Write
Init
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DACB: the 8 bits of the DAC level for IR channel B
9.4.5. SetBL register
This register defines the gain and cut-off frequency adjustments for IR channel B.
Bit
SetBL
0x4
Read/Write
Init
7
6
5
4
3
2
1
0
GAIN_
ADJ_
AA_B2
GAIN_
ADJ_
AA_B1
GAIN_
ADJ_
AA_B0
BW_
ADJ_
AA_B2
BW_
ADJ_
AA_B1
BW_
ADJ_
AA_B0
BW_
SEL_
LP_B1
BW_
SEL_
LP_B0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
1
R/W
0
R/W
1
GAIN_ADJ_AA_B: gain adjustment of anti-aliasing filter of channel B
GAIN_ADJ_
GAIN_ADJ_ GAIN_ADJ_
Gain
Gain (dB)
AA_B2
AA_B1
AA_B0
0
0
0
2.00
6.02
0
0
1
4.29
12.64
0
1
0
6.57
16.35
0
1
1
8.86
18.95
1
0
0
11.14
20.94
1
0
1
13.43
22.56
1
1
0
15.71
23.93
1
1
1
18.00
25.11
BW_ADJ_AA_B: cut-off frequency adjustment of anti-aliasing filter of channel B
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BW_ADJ_
AA_B2
BW_ADJ_
AA_B1
BW_ADJ_
AA_B0
3dB Cut-off
Frequency (kHz)
0
0
0
18
0
0
1
20
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Datasheet
0
1
0
22.5
0
1
1
25
1
0
0
30
1
0
1
35
1
1
0
43
1
1
1
55
BW_SEL_LP_B: cut-off frequency selection of low-pass filter of channel B
BW_SEL_
BW_SEL_
Cut-off Freuency
Cut-off Frequency
LP_B1
LP_B0
(%f0)
(kHz @ f0=70kHz)
0
0
23.5
16.5
0
1
12
7.8
1
0
5.9
4.2
1
1
3
2.1
9.4.6. SetPF register
This register defines the frequency settings and the number of pulses for the active light measurements.
Bit
SetPF
0x5
Read/Write
Init
7
6
5
4
NP3
NP2
NP1
NP0
R/W
0
R/W
1
R/W
0
R/W
0
3
EN_DC
COMP
R/W
0
2
1
0
RPF2
RPF1
RPF0
R/W
1
R/W
0
R/W
0
NP: number of pulses for the active light measurements, as defined in the table
below:
Bit 3 - NP3 Bit 2 - NP2 Bit 1 - NP1 Bit 0 - NP0
Number of Pulses
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0
0
0
0
2
0
0
0
1
4
0
0
1
0
6
0
0
1
1
8
0
1
0
0
10
0
1
0
1
12
0
1
1
0
14
0
1
1
1
16
1
0
0
0
18
1
0
0
1
20
1
0
1
0
22
1
0
1
1
24
1
1
0
0
26
1
1
0
1
28
1
1
1
0
30
1
1
1
1
32
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EN_DCCOMP: 1 = enables the DC light compensation, 0 = disables the DC light
compensation
RPF: frequency selection of pulses for the active light measurements, as defined
below:
Bit 2 - RPF2
Bit 1 - RPF1
Bit 0 - RPF0
0
0
0
Frequency of Pulses
(in kHz, +/-5%)
48.1
0
0
1
52.1
0
1
0
56.8
0
1
1
62.5
1
0
0
69.4
1
0
1
78.1
1
1
0
89.3
1
1
1
104.2
9.4.7. Err register
As described in Section 9.3 (under section 'Bit 0: Critical Error is detected/not detected'), the voltages on critical nodes are
monitored continuously. When a voltage on such a critical node goes outside its operating range, the Critical Error Flag and
the appropriate error bit in the 'Err' register will be set high. As such, the source of the error can be found in the 'Err'
register.
The error bit remains high as long as the error condition is present, or as long as the error bit is not cleared (in case the
error condition is not present anymore).
Err
0x6
Bit
7
-
6
Err6
5
Err5
4
Err4
3
Err3
2
Err2
1
Err1
0
-
Read/Write
Init
R
0
R/W*
0
R/W*
0
R/W*
x**
R/W*
x**
R/W*
x**
R/W*
0
R
0
The following bits are defined (0= no error detected; 1=error is detected):
Err: not implemented, read as '0'
Err6: critical error detected on TIA output
Err5: critical error detected on the difference between DAC output and shunt-feedback
Err4: critical error detected on internal voltage reference: when the internal voltage
reference is below 1V.
Err3: critical error detected on one of the common mode SC-filters of the ambient
light/temperature channels
Err2: critical error detected on RCO: either a stuck-at-high or a stuck-at-low condition
occurred at the output of the RCO. Note that in SLP, the error flag on the RCO will be set
high.
Err1: set to '1' when a falling edge on the WT pin is detected while the device is in Sleep
Mode
Err: not implemented, read as '0'
*: only writing '0' is allowed. If a '1' is written, the bit value in the register will not be changed, but Bit 7 of the Internal
Status Flags will be set high (Previous Command Invalid).
**: 'x' indicates that the value after POR is unknown. If the voltages of the nodes are out of range right after POR, it will be
immediately reflected in the 'Err' register and the Critical Error Flag will be set. The same is valid after wake-up from
Sleep/Standby.
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Datasheet
9.4.8. Rst register
This register allows differentiation of either a POR or a reset due to a watchdog time-out + settings for the DC light
compensation circuitry.
Bit
Rst
0x7
Read/Write
Init
7
DC_
COMP_
IC13
6
DC_
COMP_
IC12
5
DC_
COMP_
IC11
4
DC_
COMP_
IC10
3
2
1
0
-
-
TO
POR
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R/W
1
DC_COMP_IC1: setting of the amplitude of the 1st PWL slope
Rst: not implemented, read as '0'
TO: 1=a Watchdog time-out and a master reset occurred. 0=no Watchdog time-out
occurred, or after Power-On, or after a falling edge at the WT pin
POR: 1=a POR occurred, 0=a POR has not occurred. To detect subsequent Power-On-Resets,
the POR-bit shall be cleared right after Power-On.
9.4.9. DCComp register
This register contains settings for the DC light compensation circuitry. These settings have to be calculated for the
individual application (ActiveLight-channel photodiode used).
Bit
7
6
5
4
3
DC_
COMP_
IC23
2
DC_
COMP_
IC22
1
DC_
COMP_
IC21
0
DC_
COMP_
IC20
R
R
R
R
R/W
R/W
R/W
R/W
X
X
X
X
0
0
0
0
DCComp1
0x8
Read/
Write
Init
DC_COMP_IC2: setting of the amplitude of the 2nd PWL slope
Bit
DCComp2
0x9
Read/
Write
Init
7
DC_
COMP_
IC33
6
DC_
COMP_
IC32
5
DC_
COMP_
IC31
4
DC_
COMP_
IC30
3
DC_
COMP_
IC43
2
DC_
COMP_
IC42
1
DC_
COMP_
IC41
0
DC_
COMP_
IC40
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
DC_COMP_IC3: setting of the amplitude of the 3rd PWL slope
DC_COMP_IC4: setting of the amplitude of the 4th PWL slope
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Datasheet
9.4.10. GainBuf register
This register contains the gain settings of the ADC input buffer. The use of this buffer is depending on bit 'Unity_Gain' in the
register 'SetAna'.
Bit
GainBuf
0xA
Read/Write
Init
7
6
5
-
-
-
R
0
R
0
R
0
4
GAIN_B
UF4
3
GAIN_B
UF3
2
GAIN_B
UF2
1
GAIN_B
UF1
0
GAIN_
BUF0
R/W
1
R/W
1
R/W
0
R/W
1
R/W
0
GainBuf: not implemented, read as '0'
GAIN_BUF: defines the gain setting of the ADC input buffer
REVISION 008 - AUG 2018
3901075030
GAIN_
BUF4
GAIN_
BUF3
GAIN_
BUF2
GAIN_
BUF1
GAIN_
BUF0
Gain
0
0
0
0
1
2
0
0
0
1
0
1
0
0
0
1
1
0.67
0
0
1
0
0
0.5
0
0
1
0
1
0.4
0
0
1
1
0
0.33
0
0
1
1
1
0.29
0
1
0
0
0
0.25
0
1
0
0
1
0.22
0
1
0
1
0
0.2
1
0
0
0
1
10
1
0
0
1
0
5
1
0
0
1
1
3.33
1
0
1
0
0
2.5
1
0
1
0
1
2
1
0
1
1
0
1.67
1
0
1
1
1
1.43
1
1
0
0
0
1.25
1
1
0
0
1
1.11
1
1
0
1
0
1
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Datasheet
9.4.11. Calib1/Calib2 register
These registers contain the gain settings of the bandgap temperature coefficient correction and the temperature sensor.
Bit
Calib1
0xB
Read/Write
Init
7
TRIM_
TC_BGI4
6
TRIM_
TC_BGI3
5
TRIM_
TC_BGI2
4
TRIM_
TC_BGI1
3
TRIM_
TC_BGI0
2
1
0
-
-
-
R
x
R
x
R
x
R
x
R
x
R
0
R
0
R
0
TRIM_TC_BGI: defines the TC correction of the bandgap current
Calib1: not implemented, read as '0'
The Calib1 register is used to indicate the slope of the temperature sensor curve in LSB/Kelvin. The slope is calculated out of a 2point measurement of the temperature curve and is permanently programmed in the OTP by means of a 5 -Bit word and
accessible via the Calib1 register, see Table 22.
Calib1 - TRIM_TC_BGI
Dec
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Bin
0
1
10
11
100
101
110
111
1000
1001
1010
1011
1100
1101
1110
1111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Slope (LSB/Kelvin)
-51
-52
-53
-54
-55
-56
-57
-58
-59
-60
-61
-62
-63
-64
-65
-66
-67
-68
-69
-70
-71
-72
-73
-74
-75
-76
-77
-78
-79
-80
-81
-82
Table 22 : 5-Bit temperature sensor slope information as it is stored in the calib1 register.
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MLX75030 Universal ActiveLight Sensor Interface
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Bit
Calib2
0xC
Read/Write
Init
7
6
-
-
R
0
R
0
5
TRIM_T
EMP5
4
TRIM_T
EMP4
3
TRIM_T
EMP3
2
TRIM_T
EMP2
1
TRIM_T
EMP1
0
TRIM_T
EMP0
R
x
R
x
R
x
R
x
R
x
R
x
Calib2: not implemented, read as '0'
TRIM_TEMP: defines the calibration settings of the temperature sensor
The offset of the temperature curve is measured at one temperature (preferably 30deg. C) and permanently stored in the
zenerzap OTP with 6 bit word length.
This information is accessible via the Calib2 register, see Table 23.
Slope: -67 LSB/K
Calib2 - TRIM_TEMP
25degC
30degC
Dec
Bin
Offset (degC)
LSL
expected
USL
LSL
expected
USL
1
2
1
10
-31
-30
10003.07
10069.95
10036.51
10103.39
10069.95
10136.83
9668.67
9735.55
9702.11
9768.99
9735.55
9802.43
3
4
11
100
-29
-28
10136.83
10203.71
10170.27
10237.15
10203.71
10270.59
9802.43
9869.31
9835.87
9902.75
9869.31
9936.19
5
6
101
110
-27
-26
10270.59
10337.47
10304.03
10370.91
10337.47
10404.35
9936.19
10003.07
9969.63
10036.51
10003.07
10069.95
7
8
111
1000
-25
-24
10404.35
10471.23
10437.79
10504.67
10471.23
10538.11
10069.95
10136.83
10103.39
10170.27
10136.83
10203.71
9
10
1001
1010
-23
-22
10538.11
10604.99
10571.55
10638.43
10604.99
10671.87
10203.71
10270.59
10237.15
10304.03
10270.59
10337.47
11
12
1011
1100
-21
-20
10671.87
10738.75
10705.31
10772.19
10738.75
10805.63
10337.47
10404.35
10370.91
10437.79
10404.35
10471.23
13
14
1101
1110
-19
-18
10805.63
10872.51
10839.07
10905.95
10872.51
10939.39
10471.23
10538.11
10504.67
10571.55
10538.11
10604.99
15
16
1111
10000
-17
-16
10939.39
11006.27
10972.83
11039.71
11006.27
11073.15
10604.99
10671.87
10638.43
10705.31
10671.87
10738.75
17
18
10001
10010
-15
-14
11073.15
11140.03
11106.59
11173.47
11140.03
11206.91
10738.75
10805.63
10772.19
10839.07
10805.63
10872.51
19
20
10011
10100
-13
-12
11206.91
11273.79
11240.35
11307.23
11273.79
11340.67
10872.51
10939.39
10905.95
10972.83
10939.39
11006.27
21
22
10101
10110
-11
-10
11340.67
11407.55
11374.11
11440.99
11407.55
11474.43
11006.27
11073.15
11039.71
11106.59
11073.15
11140.03
23
24
10111
11000
-9
-8
11474.43
11541.31
11507.87
11574.75
11541.31
11608.19
11140.03
11206.91
11173.47
11240.35
11206.91
11273.79
25
26
11001
11010
-7
-6
11608.19
11675.07
11641.63
11708.51
11675.07
11741.95
11273.79
11340.67
11307.23
11374.11
11340.67
11407.55
27
28
11011
11100
-5
-4
11741.95
11808.83
11775.39
11842.27
11808.83
11875.71
11407.55
11474.43
11440.99
11507.87
11474.43
11541.31
29
30
11101
11110
-3
-2
11875.71
11942.59
11909.15
11976.03
11942.59
12009.47
11541.31
11608.19
11574.75
11641.63
11608.19
11675.07
31
32
33
34
11111
100000
100001
100010
-1
0
1
2
12009.47
12076.35
12143.23
12210.11
12042.91
12109.79
12176.67
12243.55
12076.35
12143.23
12210.11
12276.99
11675.07
11741.95
11808.83
11875.71
11708.51
11775.39
11842.27
11909.15
11741.95
11808.83
11875.71
11942.59
35
36
100011
100100
3
4
12276.99
12343.87
12310.43
12377.31
12343.87
12410.75
11942.59
12009.47
11976.03
12042.91
12009.47
12076.35
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37
38
100101
100110
5
6
12410.75
12477.63
12444.19
12511.07
12477.63
12544.51
12076.35
12143.23
12109.79
12176.67
12143.23
12210.11
39
40
100111
101000
7
8
12544.51
12611.39
12577.95
12644.83
12611.39
12678.27
12210.11
12276.99
12243.55
12310.43
12276.99
12343.87
41
42
101001
101010
9
10
12678.27
12745.15
12711.71
12778.59
12745.15
12812.03
12343.87
12410.75
12377.31
12444.19
12410.75
12477.63
43
44
101011
101100
11
12
12812.03
12878.91
12845.47
12912.35
12878.91
12945.79
12477.63
12544.51
12511.07
12577.95
12544.51
12611.39
45
46
101101
101110
13
14
12945.79
13012.67
12979.23
13046.11
13012.67
13079.55
12611.39
12678.27
12644.83
12711.71
12678.27
12745.15
47
48
101111
110000
15
16
13079.55
13146.43
13112.99
13179.87
13146.43
13213.31
12745.15
12812.03
12778.59
12845.47
12812.03
12878.91
49
50
110001
110010
17
18
13213.31
13280.19
13246.75
13313.63
13280.19
13347.07
12878.91
12945.79
12912.35
12979.23
12945.79
13012.67
51
52
110011
110100
19
20
13347.07
13413.95
13380.51
13447.39
13413.95
13480.83
13012.67
13079.55
13046.11
13112.99
13079.55
13146.43
53
54
110101
110110
21
22
13480.83
13547.71
13514.27
13581.15
13547.71
13614.59
13146.43
13213.31
13179.87
13246.75
13213.31
13280.19
55
56
110111
111000
23
24
13614.59
13681.47
13648.03
13714.91
13681.47
13748.35
13280.19
13347.07
13313.63
13380.51
13347.07
13413.95
57
58
111001
111010
25
26
13748.35
13815.23
13781.79
13848.67
13815.23
13882.11
13413.95
13480.83
13447.39
13514.27
13480.83
13547.71
59
60
111011
111100
27
28
13882.11
13948.99
13915.55
13982.43
13948.99
14015.87
13547.71
13614.59
13581.15
13648.03
13614.59
13681.47
61
62
111101
111110
29
30
14015.87
14082.75
14049.31
14116.19
14082.75
14149.63
13681.47
13748.35
13714.91
13781.79
13748.35
13815.23
63
111111
31
14149.63
14183.07
14216.51
13815.23
13848.67
13882.11
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Datasheet
Slope: -67 LSB/K
Calib2 - TRIM_TEMP
85degC
105degC
Dec
Bin
Offset (degC)
LSL
expected
USL
LSL
expected
USL
1
2
1
10
-31
-30
5990.27
6057.15
6023.71
6090.59
6057.15
6124.03
4652.67
4719.55
4686.11
4752.99
4719.55
4786.43
3
4
11
100
-29
-28
6124.03
6190.91
6157.47
6224.35
6190.91
6257.79
4786.43
4853.31
4819.87
4886.75
4853.31
4920.19
5
6
101
110
-27
-26
6257.79
6324.67
6291.23
6358.11
6324.67
6391.55
4920.19
4987.07
4953.63
5020.51
4987.07
5053.95
7
8
111
1000
-25
-24
6391.55
6458.43
6424.99
6491.87
6458.43
6525.31
5053.95
5120.83
5087.39
5154.27
5120.83
5187.71
9
10
1001
1010
-23
-22
6525.31
6592.19
6558.75
6625.63
6592.19
6659.07
5187.71
5254.59
5221.15
5288.03
5254.59
5321.47
11
12
1011
1100
-21
-20
6659.07
6725.95
6692.51
6759.39
6725.95
6792.83
5321.47
5388.35
5354.91
5421.79
5388.35
5455.23
13
14
1101
1110
-19
-18
6792.83
6859.71
6826.27
6893.15
6859.71
6926.59
5455.23
5522.11
5488.67
5555.55
5522.11
5588.99
15
16
1111
10000
-17
-16
6926.59
6993.47
6960.03
7026.91
6993.47
7060.35
5588.99
5655.87
5622.43
5689.31
5655.87
5722.75
17
18
10001
10010
-15
-14
7060.35
7127.23
7093.79
7160.67
7127.23
7194.11
5722.75
5789.63
5756.19
5823.07
5789.63
5856.51
19
20
10011
10100
-13
-12
7194.11
7260.99
7227.55
7294.43
7260.99
7327.87
5856.51
5923.39
5889.95
5956.83
5923.39
5990.27
21
22
10101
10110
-11
-10
7327.87
7394.75
7361.31
7428.19
7394.75
7461.63
5990.27
6057.15
6023.71
6090.59
6057.15
6124.03
23
24
10111
11000
-9
-8
7461.63
7528.51
7495.07
7561.95
7528.51
7595.39
6124.03
6190.91
6157.47
6224.35
6190.91
6257.79
25
26
11001
11010
-7
-6
7595.39
7662.27
7628.83
7695.71
7662.27
7729.15
6257.79
6324.67
6291.23
6358.11
6324.67
6391.55
27
28
11011
11100
-5
-4
7729.15
7796.03
7762.59
7829.47
7796.03
7862.91
6391.55
6458.43
6424.99
6491.87
6458.43
6525.31
29
30
11101
11110
-3
-2
7862.91
7929.79
7896.35
7963.23
7929.79
7996.67
6525.31
6592.19
6558.75
6625.63
6592.19
6659.07
31
11111
-1
7996.67
8030.11
8063.55
6659.07
6692.51
6725.95
32
100000
0
8063.55
8096.99
8130.43
6725.95
6759.39
6792.83
33
100001
1
8130.43
8163.87
8197.31
6792.83
6826.27
6859.71
34
35
100010
100011
2
3
8197.31
8264.19
8230.75
8297.63
8264.19
8331.07
6859.71
6926.59
6893.15
6960.03
6926.59
6993.47
36
37
100100
100101
4
5
8331.07
8397.95
8364.51
8431.39
8397.95
8464.83
6993.47
7060.35
7026.91
7093.79
7060.35
7127.23
38
39
100110
100111
6
7
8464.83
8531.71
8498.27
8565.15
8531.71
8598.59
7127.23
7194.11
7160.67
7227.55
7194.11
7260.99
40
41
101000
101001
8
9
8598.59
8665.47
8632.03
8698.91
8665.47
8732.35
7260.99
7327.87
7294.43
7361.31
7327.87
7394.75
42
43
101010
101011
10
11
8732.35
8799.23
8765.79
8832.67
8799.23
8866.11
7394.75
7461.63
7428.19
7495.07
7461.63
7528.51
44
45
101100
101101
12
13
8866.11
8932.99
8899.55
8966.43
8932.99
8999.87
7528.51
7595.39
7561.95
7628.83
7595.39
7662.27
46
47
101110
101111
14
15
8999.87
9066.75
9033.31
9100.19
9066.75
9133.63
7662.27
7729.15
7695.71
7762.59
7729.15
7796.03
48
110000
16
9133.63
9167.07
9200.51
7796.03
7829.47
7862.91
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Datasheet
49
50
110001
110010
17
18
9200.51
9267.39
9233.95
9300.83
9267.39
9334.27
7862.91
7929.79
7896.35
7963.23
7929.79
7996.67
51
52
110011
110100
19
20
9334.27
9401.15
9367.71
9434.59
9401.15
9468.03
7996.67
8063.55
8030.11
8096.99
8063.55
8130.43
53
54
110101
110110
21
22
9468.03
9534.91
9501.47
9568.35
9534.91
9601.79
8130.43
8197.31
8163.87
8230.75
8197.31
8264.19
55
56
110111
111000
23
24
9601.79
9668.67
9635.23
9702.11
9668.67
9735.55
8264.19
8331.07
8297.63
8364.51
8331.07
8397.95
57
58
111001
111010
25
26
9735.55
9802.43
9768.99
9835.87
9802.43
9869.31
8397.95
8464.83
8431.39
8498.27
8464.83
8531.71
59
60
111011
111100
27
28
9869.31
9936.19
9902.75
9969.63
9936.19
10003.07
8531.71
8598.59
8565.15
8632.03
8598.59
8665.47
61
62
111101
111110
29
30
10003.07
10069.95
10036.51
10103.39
10069.95
10136.83
8665.47
8732.35
8698.91
8765.79
8732.35
8799.23
63
111111
31
10136.83
10170.27
10203.71
8799.23
8832.67
8866.11
Table 23: 6-Bit Temperature curve offset information for a typical slope of -67 LSB/K.
9.4.12. EnChan register
This register contains bit to enable/disable active light and ambient light channels.
Bit
EnChan
0xD
Read/Write
Init
7
6
5
4
3
2
1
EN_
TEMP
EN_
DIAG_A
EN_
DIAG_B
EN_
CH_A
EN_
CH_B
EN_
CH_C
EN_
CH_D
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
0
EN_
DIAGA
MB
R/W
1
EN_TEMP: 1 = temperature channel is in use, 0 = temperature channel is not in use
EN_DIAG_A: 1 = enables diagnostics on active light channel A, 0 = disables the diagnostics
EN_DIAG_B: 1 = enables diagnostics on active light channel B, 0 = disables the diagnostics
EN_CH_A: 1 = active light channel A is enabled (TIA + Demodulator + Anti-Aliasing Filter +
SC-LPF), 0 = active light channel A is completely switched off to reduce current consumption
EN_CH_B: 1 = active light channel B is enabled (TIA + Demodulator + Anti-Aliasing Filter +
SC-LPF), 0 = active light channel B is completely switched off to reduce current consumption
EN_CH_C: 1 = ambient light channel C is in use, 0 = ambient light channel C is not in use
EN_CH_D: 1 = ambient light channel D is in use, 0 = ambient light channel D is not in use
EN_DIAGAMB: 1= ambient diagnosis is possible, 0= ambient diagnosis is not possible
The bits EN_CH_A/EN_CH_B/EN_DIAGAMB can be used to switch off channels that are not needed, and thus reducing the
current consumption.
When going into Sleep or Standby the setting of these bits is ignored, all channels will be switched off independently of
EN_CH register contents.
The bits EN_TEMP/EN_CH_C/EN_CH_D/EN_DIAGAMB are used to indicate which channels are in use and which channels
are not in use. Terminals, which are not connected, must be disabled in the ENChan register. Otherwise error flags might
occur.
In case all EN_CH_C/D/DIAGAMB bits are set to zero, but an ambient measurement is requested, then the Command
Invalid status flag will be set high. The measurement itself will not be executed.
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Datasheet
9.4.13. Tamb register
This register contains settings for the DC light compensation circuitry + controls the repetition rate of the auto-zero timer.
Bit
Tamb
0xE
Read/Write
Init
7
DC_
COMP_
IC53
6
DC_
COMP_
IC52
5
DC_
COMP_
IC51
4
DC_
COMP_
IC50
3
2
1
0
-
-
Tamb1
Tamb0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R/W
1
R/W
0
DC_COMP_IC5: setting of the amplitude of the 5th PWL slope
Tamb: not implemented, read as '0'
Tamb: controls the repetition rate of the auto-zero timer
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Tamb1
Tamb0
Repetition Rate (ms +/-5%)
0
0
0
1
1.25
2.5
1
0
5
1
1
10
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Datasheet
9.5. Window Watchdog Timer
The internal watchdog timer is a watchdog based on two different windows: an open and a closed window. During the
open window the master can restart the watchdog timer. During the closed window, no restarts are accepted.
The restart (re-initialisation) of the watchdog timer happens via the WT (Watchdog Trigger) pin: when a falling edge is
detected on the WT pin, the watchdog will be restarted.
The low time on the WT pin should be at least a time twt_l.
After a POR or a reset issued by the watchdog and after a wake-up from Sleep Mode (either by uploading the NRM
command, or by using the WAKE_UP pin), the window watchdog will open an active window of a time t wdt_init, during which
a watchdog restart must be issued by the µC. If no watchdog restart is received by the end of the open window, the µC will
be reset.
After this initial period, the window watchdog is programmed to wait a time t wdt_closed during which no watchdog restarts
are allowed. If a watchdog restart is sent during the closed window time, the watchdog will reset the master via the MR
(Master Reset) pin.
After a closed window, an open window of a time twdt_open will follow during which a watchdog restart is expected. If no
watchdog restart is received till the end of the open window, the µC will be reset via the MR pin.
Changing mode between Normal Running Mode and Standby Mode will not influence the watchdog timing or state. Also a
CR command will not change the used window times. The watchdog counter will not be influenced when changing mode
between NRM and STBY or when uploading a CR command.
The Watch Dog Timer is disabled in Sleep Mode. A falling edge on the WT pin in the Sleep Mode will set an error flag in the
register ‘Err’. Coming back from Sleep Mode to Normal Running Mode always restarts the watchdog with the initial timing
window.
This figure shows what timing windows are used in the different operating modes:
POR
Device State
NRM
STBY
NRM
SLP
NRM
twdt_init
twdt_closed
twdt_open
twdt_closed
twdt_open
twdt_closed
twdt_open
twdt_init
twdt_closed
twdt_open
WDT Window
Figure 16 : Window times during different operating modes
The two diagrams below show the functionality of the watchdog timer:
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Datasheet
twdt_closed
WatchdogWindow
twdt_open
twdt_open
High = Active Window
Missing WT
WT (Watchdog Trigger)
MR (Master Reset)
Initial Period
t ms
twdt_init
twdt_closed
WatchdogWindow
twdt_open
High = Active Window
WT (Watchdog Trigger)
Premature WT
MR (Master Reset)
Initial Period
t ms
twdt_init
Figure 17 : Functionality of the window watchdog timer
A reset of the µC due to time-out of the watchdog is achieved by setting the MR pin low during a time tMR (default state of
the MR pin is high).
When the device is operating in Sleep or Standby Mode, the WAKE_UP pin will be monitored. When a falling edge is
detected on that pin, the device will switch to Normal Running Mode and, when waking up from Sleep Mode, the
Watchdog Timer will be started (with an initial window time of t wdt_init).
Note that no pull-up or pull-down resistor is foreseen on the WAKE_UP pin. To avoid that parasitic spikes can wake up the
device, the WAKE_UP input is debounced (typical debounce time is in the range of 2µs). The low time on the WAKE_UP pin
should be at least a time twu_l.
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Datasheet
9.6. Reset Behaviour
Power-On Reset
After a Power-On Reset, the device is operating in Normal Running Mode. All internal data registers are set to their initial
state:
the device state is Normal Running Mode
the Watchdog counter is initialized to generate the initial window time
all registers containing (diagnostic) measurement data are initialized to 0x00
bits 7, 4, 3 of the Internal Status Flags are cleared
the user settings registers are set to their initial values (see Section 9.4)
the 'Err' register will initialize to 0x00. However, as some voltages are continuously measured, it will reflect
immediately if an error is detected or not.
The MR pin will be initialized to '1'. The DR pin will be initialized to '0', but after the time tstartup it will switch to '1' to
indicate that the device is ready to accept the first command (see also Section 9.9).
The output of the MISO pin is depending on the CS state: if CS is high, the MISO pin is in tri-state. If CS is low, the output of
the MISO pin is undefined.
CR Command
At every upload of the CR command, the device returns to the state like it is after a Power-On-Reset, except for the
Watchdog counter and the state of the MR line. The Watchdog counter and the state of the MR line will not be influenced
by uploading a CR command. Also, the CR command will not change the contents of the 'Rst' register.
After a CR command the DR pin will be kept low during a time t startup.
Read-out
At the end of each read-out, all registers containing (diagnostic) measurement data are cleared to 0x00.
Watchdog time-out
When a reset occurs due to a watchdog time-out, the MR pin will go low for a time tMR. The Watchdog counter will be
initialized with the window time twdt_init. All other states, lines and registers of the ASIC will not be affected.
Changing operation mode
When changing operation mode (RSLP, CSLP, RSTBY, CSTBY, NRM) the right status flags are set.
Changing operation mode will not affect the user settings registers and the (diagnostic) measurement data registers.
The DR pin will be set to '0' and after the time twakeup_slp resp. twakeup_stby it will be set to '1', when waking up from Sleep resp.
Standby Mode.
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MLX75030 Universal ActiveLight Sensor Interface
Datasheet
9.7. Wake-up from Sleep or Standby
The figure below shows what happens when switching operation mode, and the behaviour of the DR pin and the watchdog
timer.
The WAKE_UP pin is only monitored during Sleep and Standby. When a falling edge is detected during Sleep or Standby,
the following will happen:
- the DR pin goes low for a time twakeup_stby or twakeup_slp
- the watchdog timer is initialised and starts counting, when waking up from Sleep
- the device changes to Normal Running Mode, enabling the appropriate blocks
POR
WAKE-UP
NRM Mode
STBY Mode
SLP Mode
Level
depending on
CR/SM/SD
Level depending
on CR/SM/SD
Watchdog
Init
tstartup
Level depending
on CR/SM/SD
twakeup_stby
Active
twakeup_slp
Init
DR
Active
Figure 18 : Behaviour of DR and Watchdog when switching mode
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Datasheet
9.8. CRC Calculation
8
2
1
0
The 8-bit CRC calculation will be based on the polynomial x + x + x + x . This polynomial is widely used in the industry, it is
e.g. used for generating:
the Header Error Correction field in ATM (Asynchronous Transfer Mode) cells
the Packet Error Code in SMBus data packets
Some probabilities of detecting errors when using this polynomial:
100% detection of one bit errors
100% detection of double bit errors (adjacent bits)
100% detection of two single-bit errors for frames less than 128 bits in length
100% detection of any odd number of bits in error
100% detection of burst errors up to 8 bits
99.61% detection of any random error
A possible hardware implementation using a Linear Feedback Shift Register (LFSR) is shown in the figure below:
Figure 14: 8-bit CRC implementation using a LFSR
The generation of the CRC requires the following steps:
Reset all flip-flops
0x00 is the initial value, shifting in all zeroes does not affect the CRC
Shift in the read-out data bytes. First byte is Data Byte 1 (= Internal Status Flags), last byte is Data Byte (X+1) (with X
defined in Figure 12).
When the last byte has been shifted in, the flip-flops contain the CRC: CRC=FF[8..1].
An easy method to check if there were no transmission errors is to calculate the CRC of the whole read-out data stream
including the CRC Byte. When the calculated CRC results in 0x00, the transmission was most likely error free. If the resulting
CRC is not equal to zero, then an error occurred in the transmission and the complete data stream should be ignored.
Some CRC results for example messages are given in Table 24.
ASCII String messages
-None"A"
"123456789"
a string of 256 upper case
"A" characters with no line breaks
CRC result
0x00
0xC0
0xF4
0x8E
Table 24: CRC examples
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9.9. Global Timing Diagrams
A global timing diagram with separate SM-RO cycles is given in Figure 19. After power-up there is a Power-On-Reset phase
(POR) to initialize the sensor into a reset state. When the device is ready to accept the first command, the DR pin goes high.
In Figure 19 the first command is the WR command to define the contents of the user registers (optionally). The first
measurement cycle is e.g. initiated by uploading a SM command. After completion of the measurement cycle, the DR goes
high. This indicates that the read-out cycle can be started. A RO command has to be uploaded to bring the data on the
MISO pin. When the read-out is completed, a new measurement cycle can be started. In Figure 19 a SM command is used.
This starts a next measurement cycle. Once DR is high, a read-out can be done again.
In between different Measurement/Read-Out cycles, the user registers can be changed with WR commands. Optionally
those registers can be read back with the RR command to check if the right values were uploaded.
POR
CS
SCLK
MOSI
(WR)
SM
RO
MISO
(WR)
SM
RO
Output Data
Output Data
DR
Device State
POR
Idle
Internal Registers
SM Measurement
Idle
Filling up
Data
Available
0
Read-out
Idle
Emptying
SM Measurement
Idle
Filling up
Data
Available
0
Read-out
Idle
Emptying
0
Figure 19: Global timing diagram with separate SM-RO
Figure 20 shows a timing diagram wherein separate SM-RO cycles are mixed with combined SM-RO cycles. After the PowerOn-Reset phase, a SM measurement cycle is started. Once the DR pin is high, the data can be read out. A SM command
with extra clocks is used to combine the read-out and the start of the next measurement cycle. With the extra clocks, the
data of the internal registers is transferred to the MISO pin. When the CS pin goes high, the next measurement cycle (SM)
will be started.
Once the DR pin is high, a normal RO command is uploaded to bring the data to the MISO pin. If needed, the settings in the
user registers can be changed with the WR command and optionally the RR command can be used to check if the right
values were uploaded.
A new measurement cycle can be started with e.g. a normal SM command. When the DR pin is high, the data can be
transferred by uploading e.g. a SM command that combines the read-out and the start of a new measurement cycle.
POR
CS
SCLK
MOSI
(WR)
SM
SM
MISO
RO
Output Data
(WR)
SM
SM
Output Data
Output Data
DR
Device State
Internal Registers
POR
Idle
0
SM Measurement
Idle
Filling up
Data
Available
Read-out
Emptying
SM Measurement
0
Filling up
Idle
Data
Available
Read-out
Emptying
Idle
0
SM Measurement
Idle
Filling up
Data
Available
Read-out
Emptying
SM Measurement
0
Filling up
Figure 20: Global timing diagram with separate SM-RO and combined SM-RO together
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Idle
Data
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MLX75030 Universal ActiveLight Sensor Interface
Datasheet
10. Performance Graphs
10.1. ActiveLight Channel DC Measurement
10.2. Temperature Sensor
Characteristics
MLX75030
lightmeasurement
measurementatatrain
active
light channels
MLX75308BA
DCDClight
channels
60000
55000
MLX75030 temperatures [deg.C] vs. ADC out of temperature sensor
MLX75308BA
(slope and offset depends on Calib1 and Calib2)
50000
45000
PDA
00
0 16
0 32
90
40000
0 48
PDB
80
35000
0 63
70
80
30000
8 16
60
25000
temperature [deg. C]
8 32
20000
15000
10000
50
8 48
40
8 63
30
bold green Calib1 = 16 / Calib2 = 32:
no offset at 30 deg. C and slope is -67 LSB/K
20
5000
24 16
24 32
24 48
2800
3300
3800
4300
4800
5300
5800
6300
6800
7300
7800
8300
8800
9300
9800
10300
10800
11300
11800
12250
12750
13250
13750
14250
500
14750
450
15250
400
15750
350
16250
300
16750
250
17250
200
17750
150
18250
100
18750
50
19250
0
-10
19750
0
0
31 48
-40
31 63
ADC output of temperature sensor [LSB]
10.3. Ambient Light Channel C
16 32
10.4. Ambient Light Channel D
50000
detection range channel PDC
40000
max offset (2304LSB) @ 100uA and
min slope (5300 LSB/dec)
20000
min offset (-2304LSB) @ 100uA and
max slope (6500 LSB/dec)
10000
0
-10000
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
Ambient Current Channel C [A]
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31 0
31 32
-30
30000
24 63
31 16
-20
Idc [uA]
ADC out [LSB]
24 0
10
20250
ADC out [LSB]
Calib1 Calib2
100
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11. Application Information
11.1. Application circuit for 2 ActiveLight channels and 2 ambient light
channels
Component
Type
Value
Description
C1
SMD capacitor
47nF
Blocking capacitor, connected to analog GND
C2
SMD capacitor
68nF
Blocking capacitor for int. voltage regulator,
connected to analog GND
R1
SMD resistor
6.4 Ohms
Shunt Resistor
R2
SMD resistor
56k Ohms
Ambient Light Diagnostic termination resistor
M1
LED driver MOSFET
M2
LED driver MOSFET
LED1/2
Active light channel Infrared LED
PDA / PDB
Active light channel infrared photodiode,
daylight blocking mold
PDC
V-lambda photodiode
PDD
Photodiode
Table 25: Application circuit components for 2 ActiveLight and 2 ambient light channels
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12. Application Comments
The MLX75030 is featuring very sensitive current inputs on the pins 9 and 10 for active light detection and on the pins 11
and 12 for ambient light measurements in a range over several orders of magnitude. In order to achive optimum results in
the application it is recommended to consider the following hints for the design of the PCB:
1.
The both supply voltage pins 16 (VDDA for analog circuit parts) and 23 (VDDD for digital circuit parts) shall be starconnected to the local (external) regulator output (3.0V-3.6V) in order to avoid digital disturbance injection into the
analog supply.
2.
Note that the device works with two separate ground connections: Pin 15 works as analog ground for the sensitive
input circuitry whereas pin 24 works as digital ground and as ground connection of the LED path, which carries high
pulse currents.
3.
The Exposed Pad of the package should be star-connected to the local (external) ground pin of the regulator.
4.
The external blocking capacitors C1 and C2 shall be placed as close as possible to the corresponding pins of the device.
5.
The external photodiodes on the active light channel inputs as well as on the ambient light inputs shall be placed as
close as possible to the corresponding pins of the device. If this is not possible due to constructive reasons, the
connections shall be shielded by a noise-free analog ground plane in order to avoid performance-loss due to
disturbance coupling.
6.
Notice that GNDAMB must not be connected to any GND line on the PCB. This terminal is actively switched to supply
voltage during diagnosis mode.
7.
Note that not connected input channels (ActiveLight, ambient light) must be disabled in the EnChan register.
8.
For diagnosis purposes on pin DIAGAMB a current of 10uA is recommended. For a current in this range the diagnosis
result is least sensitive to temperature.
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13. Tape and Reel Specification
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14. Standard information regarding manufacturability
of Melexis products with different soldering processes
Our products are classified and qualified regarding soldering technology, solderability and moisture sensitivity level
according to following test methods:
Reflow Soldering SMD’s (Surface Mount Devices)
IPC/JEDEC J-STD-020
Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices
(classification reflow profiles according to table 5-2)
EIA/JEDEC JESD22-A113
Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability Testing
(reflow profiles according to table 2)
Wave Soldering SMD’s (Surface Mount Devices) and THD’s (Through Hole Devices)
EN60749-20
Resistance of plastic- encapsulated SMD’s to combined effect of moisture and soldering heat
EIA/JEDEC JESD22-B106 and EN60749-15
Resistance to soldering temperature for through-hole mounted devices
Iron Soldering THD’s (Through Hole Devices)
EN60749-15
Resistance to soldering temperature for through-hole mounted devices
Solderability SMD’s (Surface Mount Devices) and THD’s (Through Hole Devices)
EIA/JEDEC JESD22-B102 and EN60749-21
Solderability
For all soldering technologies deviating from above mentioned standard conditions (regarding peak temperature,
temperature gradient, temperature profile etc) additional classification and qualification tests have to be agreed upon with
Melexis.
The application of Wave Soldering for SMD’s is allowed only after consulting Melexis regarding assurance of adhesive
strength between device and board.
Melexis is contributing to global environmental conservation by promoting lead free solutions. For more information on
qualifications of RoHS compliant products (RoHS = European directive on the Restriction Of the use of certain Hazardous
Substances) please visit the quality page on our website: http://www.melexis.com/quality.asp
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15. ESD Precautions
Electronic semiconductor products are sensitive to Electro Static Discharge (ESD).
Always observe Electro Static Discharge control procedures whenever handling semiconductor products.
16. Package Information
DxE
Quad
4x4
N
24
e
0.50 ±0.05
A
min
max
0.80
1.00
A1
A3
All dimensions in mm
0.00
0.20
REF
0.05
D2
E2
L
K
b
2.50
2.70
2.50
2.70
0.35
0.45
0.20
–
0.18
0.30
Table 26: Package dimensions
Package
Θjc [°C/W]
Θja [°C/W]
(JEDEC 1s0p board)
Θja [°C/W]
(JEDEC 1s2p board)
QFN 4x4
16
154
50
Table 27: JA values
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17. Marking Information
Part Number
18
17
16
15
14
13
75030
A
12345
1025
19
20
21
12
5-digit Lot Number
11
10
`
22
23
24
1
2
3
4
5
9
8
7
4-digit Date Code
Format: YYWW
6
Figure 21: Package marking of the MLX75030 device in QFN24 4x4 SMD package
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18. Disclaimer
The information furnished by Melexis herein (“Information”) is believed to be correct and accurate. Melexis disclaims (i) any and all liability in connection with or arising out of
the furnishing, performance or use of the technical data or use of the product(s) as described herein (“Product”) (ii) any and all liability, including with out limitation, special,
consequential or incidental damages, and (iii) any and all warranties, express, statutory, implied, or by description, including warranties of fitness for particular purpose, noninfringement and merchantability. No obligation or liability shall arise or flow out of Melexis’ rendering of technical or other services.
The Information is provided "as is” and Melexis reserves the right to change the Information at any time and without notice. Therefore, before placing orders and/or prio r to
designing the Product into a system, users or any third party should obtain the latest version of the relevant information to verify that the information being relied upon is
current.
Users or any third party must further determine the suitability of the Product for its application, including the level of re liability required and determine whether it is fit for a
particular purpose.
The Information is proprietary and/or confidential information of Melexis and the use thereof or anything described by the In formation does not grant, explicitly or implicitly, to
any party any patent rights, licenses, or any other intellectual property rights.
This document as well as the Product(s) may be subject to export control regulations. Please be aware that export might require a prior authorization from competent
authorities.
The Product(s) are intended for use in normal commercial applications. Unless otherwise agreed upon in writing, the Product(s) are not designed, authorized or warranted to be
suitable in applications requiring extended temperature range and/or unusual environmental requirements. High reliability app lications, such as medical life-support or lifesustaining equipment are specifically not recommended by Melexis.
The Product(s) may not be used for the following applications subject to export control regulations: the development, production, processing, operation, maintenance, storage,
recognition or proliferation of 1) chemical, biological or nuclear weapons, or for the development, production, maintenance o r storage of missiles for such weapons: 2) civil
firearms, including spare parts or ammunition for such arms; 3) defense related products, or other material for military use or for law enforcement; 4) any applications that,
alone or in combination with other goods, substances or organisms could cause serious harm to persons or goods and that can b e used as a means of violence in an armed
conflict or any similar violent situation.
The Products sold by Melexis are subject to the terms and conditions as specified in the Terms of Sale, which can be found at https://www.melexis.com/en/legal/terms-andconditions.
This document supersedes and replaces all prior information regarding the Product(s) and/or previous versions of this document.
Melexis NV © - No part of this document may be reproduced without the prior written consent of Melexis. (2016)
ISO/TS 16949 and ISO14001 Certified
For the latest version of this document, go to our website at
www.melexis.com
Or for additional information contact Melexis Direct:
Europe, Africa, Asia:
Phone: +32 1367 0495
E-mail: sales_europe@melexis.com
America:
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E-mail: sales_usa@melexis.com
ISO/TS 16949 and ISO14001 Certified
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