MLX80105KLQ-EAA-000-RE

MLX80104/5 LIN Slave Controller for Switches IO4 IO6 SW6 SW7 VS SW8 27 26 25 24 23 22 GNDA 1 21 AWD IREF 2 20 SW9 SW5 3 19 IO7 SW4 4 18 IO0 SW3 5 17 GNDD TO 6 16 GNDL TI1 7 15 LIN 11 12 13 14 SW1 SW0 IO1 LIN Transceiver according to LIN 2.x and SAE J2602 SW2 TI0 8 o Baud rate up to 19.2 kBaud o Frame processing o Low interrupt load to the application 9 LIN Protocol Controller according to LIN 2.x and SAE J2602 MLX80104/5 QFN 5x5 28 10 Byte EEPROM with ECC IO2 o Internal 12 MHz RC-Oscillator o 16-bit MULAN MCU with 16kB ROM or OTP, 512 Byte RAM, 192 IO5 Application Controller IO3 Features 28 Datasheet o Slew rate control for best EME behaviour o High EMI immunity IO Configuration o o o o o o o o o o 18 fully configurable high current/high voltage inputs/outputs (7mA/26.5V) Ground shift tolerant I/Os All IOs configurable pull up or pull down characteristics Eight PWM outputs (8-bit, 80Hz to 30kHz) Ten 10-bit ADC channels Eight Interrupt capable Inputs Configurable Wake up sources (LIN, IOs, ADC) Constant current output (2mA) for external low voltage loads via bipolar transistor IOs fully diagnosable Integrated window watchdog and additional independent analogue watchdog Voltage Regulator o Low standby current consumption of typ 25µA in sleep mode o Over-temperature shutdown, 45V load dump protected Other Features o Automotive Temperature Range of –40°C to 125°C o Small MLF 5x5 28pin package o Ready-to-use firmware available (UniROM) Order Code Temp. Range Package Delivery Remark MLX80104 KLQ-DAG-000-RE MLX80104 KLW-DAG-000-RE MLX80105 KLQ-EAA-000-RE MLX80105 KLW-EAA-000-RE -40 - 125 °C -40 - 125 °C -40 - 125 °C -40 - 125 °C Reel Reel Reel Reel ROM, See 22 Marking ROM, See 22 Marking OTP, See 22 Marking OTP, See 22 Marking QFN 5x5 QFN 5x5 WF QFN 5x5 QFN 5x5 WF Short Description This IC is a fully integrated LIN Slave for matrix switch or single switch Applications in automotive environment. It is suitable for bus systems according to LIN 2.x as well as SAE J2602. The combination of physical layer LIN transceiver and LIN protocol controller along with easy to configure switch inputs and PWM outputs make it possible to develop in a short timeframe simple, but powerful and cheap switch slave nodes for LIN Bus systems. MLX80104/5 – Datasheet 390108010400 Page 1 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet Contents 1. General Overview .............................................................................................................................................. 7 1.1 2. 3. 4. Electrical Characteristics .................................................................................................................................... 8 2.1 Absolute Maximum Ratings ............................................................................................................................. 8 2.2 Operating Conditions ....................................................................................................................................... 9 2.3 Static Characteristics ....................................................................................................................................... 9 2.4 Dynamic Characteristics ................................................................................................................................ 12 MULAN – MULtiple CPU with Analog and Network support .............................................................................13 3.1 General .......................................................................................................................................................... 13 3.2 MULAN Block Diagram .................................................................................................................................. 13 3.3 CPU Timing .................................................................................................................................................... 14 3.4 MLX16-8 ......................................................................................................................................................... 14 Address Space ..................................................................................................................................................15 4.1 Memory Mapping .......................................................................................................................................... 15 4.2 RAM Sharing .................................................................................................................................................. 16 4.3 ROM/OTP Sharing .......................................................................................................................................... 16 4.4 EEPROM ......................................................................................................................................................... 17 4.4.1. 4.4.2. 4.4.3. 4.4.4. 4.4.5. 4.5 5. 6. Block Diagram.................................................................................................................................................. 7 Static/dynamic Characteristics ...............................................................................................................................17 Write Timing ..........................................................................................................................................................17 Read timing ............................................................................................................................................................17 Read .......................................................................................................................................................................18 Write/Erase ............................................................................................................................................................19 OTP (MLX80105 only) .................................................................................................................................... 21 IO Registers ......................................................................................................................................................22 5.1 General .......................................................................................................................................................... 22 5.2 System Protected ports .................................................................................................................................. 22 5.3 Standard ports ............................................................................................................................................... 24 IO Ports ............................................................................................................................................................25 6.1 6.1.1. 6.1.2. 6.1.3. 6.1.4. 6.1.5. 6.1.6. 6.1.7. 6.1.8. Common Features of Pin SWx and IOx .......................................................................................................... 25 Pin structure ..........................................................................................................................................................26 Configuration Register Central Current Source ......................................................................................................27 Configuration Register SWx ...................................................................................................................................28 Configuration Register IOx .....................................................................................................................................29 Switch current generation .....................................................................................................................................30 The switch detection thresholds ............................................................................................................................31 Switch diagnosis .....................................................................................................................................................33 Switch Configuration in sleep mode ......................................................................................................................36 6.2 Additional Operation Modes SWx Ports ........................................................................................................ 37 6.3 Additional Operation Modes IOx Ports .......................................................................................................... 40 6.4 The IREF pin ................................................................................................................................................... 42 MLX80104/5 – Datasheet 390108010400 Page 2 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 7. Clock System ....................................................................................................................................................43 7.1 RC-Oscillator .................................................................................................................................................. 43 7.2 Crystal Oscillator ............................................................................................................................................ 43 8. Watchdog System .............................................................................................................................................44 8.1 Analogue Watchdog ...................................................................................................................................... 44 8.1.1. 8.1.2. Using the analogue WDOG ....................................................................................................................................45 Timing definition ....................................................................................................................................................45 8.2 Digital Window Watchdog............................................................................................................................. 46 8.3 Watchdog Register ........................................................................................................................................ 47 9. Analogue to digital converter ...........................................................................................................................48 9.1 General Description ....................................................................................................................................... 48 9.2 Input divider ................................................................................................................................................... 49 9.3 Accuracy of the reference .............................................................................................................................. 49 9.4 ADC Register .................................................................................................................................................. 50 10. Interrupts .........................................................................................................................................................51 10.1 Interrupt vectors ............................................................................................................................................ 52 10.2 Priority port .................................................................................................................................................... 52 10.3 Interrupt mask and pending ports ................................................................................................................. 52 10.4 High level system interrupts .......................................................................................................................... 53 10.4.1. 10.4.2. 10.4.3. 10.4.4. 10.4.5. 10.4.6. Reset interrupt and watchdogs ..............................................................................................................................53 Stack error..............................................................................................................................................................53 Exception error ......................................................................................................................................................54 Protection error .....................................................................................................................................................54 Invalid address .......................................................................................................................................................54 Program error ........................................................................................................................................................54 10.5 Debugger interrupt ........................................................................................................................................ 55 10.6 Pin change Interrupt ...................................................................................................................................... 55 10.7 External Watchdog interrupt ......................................................................................................................... 55 10.8 Software interrupt ......................................................................................................................................... 55 11. PWM Unit.........................................................................................................................................................56 11.1 General .......................................................................................................................................................... 56 11.2 Block Diagram................................................................................................................................................ 56 11.3 PWM frequency calculation ........................................................................................................................... 57 11.4 PWM Control Register ................................................................................................................................... 57 11.5 Available PWM Frequencies .......................................................................................................................... 59 12. Timer ................................................................................................................................................................60 12.1 13. Timer Calculation ........................................................................................................................................... 60 LIN Interface .....................................................................................................................................................61 13.1 The Concept ................................................................................................................................................... 61 13.2 LIN Physical Layer .......................................................................................................................................... 62 14. Sleep Mode and Wake up System ....................................................................................................................65 MLX80104/5 – Datasheet 390108010400 Page 3 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 14.1 Entering Sleep Mode by API ........................................................................................................................... 65 14.2 Wake Up System ............................................................................................................................................ 65 14.2.1. 14.2.2. 14.2.3. LIN Bus ...................................................................................................................................................................65 Local Wake-up .......................................................................................................................................................65 Internal Wake-up ...................................................................................................................................................65 15. Thermal Shutdown ...........................................................................................................................................66 16. System behaviour .............................................................................................................................................67 16.1 Reset behaviour ............................................................................................................................................. 67 16.2 Initialising the System .................................................................................................................................... 67 17. ROM Patches ....................................................................................................................................................69 17.1 Principle of operation .................................................................................................................................... 69 17.2 Patch start address ........................................................................................................................................ 70 17.3 Patch jump instruction ................................................................................................................................... 70 18. Application Hints ..............................................................................................................................................72 18.1 Application Examples ..................................................................................................................................... 72 18.1.1. 19. Software Development ....................................................................................................................................75 19.1 20. Switch Matrix Hints ................................................................................................................................................73 UniROM (80104 only) .................................................................................................................................... 75 Programming Interface.....................................................................................................................................77 20.1 Characteristics for the interface pins ............................................................................................................. 78 20.2 Melexis Mini E-Mlx emulator ......................................................................................................................... 79 20.3 Melexis Mini E-Mlx emulator and Melexis interface adapter ........................................................................ 81 20.4 Melexis Programmer PTC-04 ......................................................................................................................... 83 20.4.1. 20.5 21. PTC04 DB 15 Female Connector ............................................................................................................................84 Third party programmer ................................................................................................................................ 86 Operating under Disturbance ...........................................................................................................................87 21.1 Loss of battery ............................................................................................................................................... 87 21.2 Loss of Ground ............................................................................................................................................... 87 21.3 Short circuit to battery ................................................................................................................................... 87 21.4 Short circuit to ground ................................................................................................................................... 87 21.5 Thermal overload ........................................................................................................................................... 87 21.6 Undervoltage Vs ............................................................................................................................................ 87 22. Marking/Order Code ........................................................................................................................................88 22.1 Marking MLX80104 ....................................................................................................................................... 88 22.2 Order Code MLX80104 ................................................................................................................................... 88 22.3 Marking MLX80105 ....................................................................................................................................... 89 22.4 Order Code MLX80105 ................................................................................................................................... 89 23. Pin Description .................................................................................................................................................90 24. Mechanical Specification ..................................................................................................................................92 MLX80104/5 – Datasheet 390108010400 Page 4 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 25. Land Pattern Recommendations ......................................................................................................................93 26. ESD/EMC Remarks ............................................................................................................................................94 26.1 ESD/EMC Recommendations for the MLX80104/5 ........................................................................................ 94 26.2 Automotive Qualification Test Pulses ............................................................................................................ 94 26.3 EMC Test pulse definition .............................................................................................................................. 95 27. References .......................................................................................................................................................96 28. List of Abbreviations .........................................................................................................................................96 29. Revision History ...............................................................................................................................................97 30. Standard information regarding manufacturability of Melexis products with different soldering processes ....99 31. Disclaimer ......................................................................................................................................................100 List of Figures FIGURE 1 - BLOCK DIAGRAM ............................................................................................................................................... 7 FIGURE 2 - BLOCK DIAGRAM OF MULAN CPU ................................................................................................................ 13 FIGURE 3 - CPU INTERLEAVING ........................................................................................................................................ 14 FIGURE 4 - EEPROM READ ............................................................................................................................................... 18 FIGURE 5 - COMMON PIN STRUCTURE SWX AND IOX........................................................................................................ 26 FIGURE 6 - VOLTAGE DEPENDENCY OF THE SWITCH CURRENT........................................................................................... 30 FIGURE 7 - VOLTAGE DROPS EXTERNAL LS SWITCH .......................................................................................................... 31 FIGURE 8 - VOLTAGE DROPS SWITCH MATRIX.................................................................................................................... 31 FIGURE 9 - VOLTAGE DROPS EXTERNAL HS SWITCH ......................................................................................................... 32 FIGURE 10 - WAKE UP DETECTION FOR SWITCH INPUTS ..................................................................................................... 37 FIGURE 11 - STRUCTURE OF SWX PINS .............................................................................................................................. 38 FIGURE 12 - STRUCTURE OF IOX PINS ................................................................................................................................ 40 FIGURE 13 - SAMPLE CIRCUITRY FOR IREF PIN ................................................................................................................. 42 FIGURE 14 - ANALOGUE WATCHDOG BEHAVIOUR ............................................................................................................. 44 FIGURE 15 - ADC COMPONENTS ........................................................................................................................................ 48 FIGURE 16 - PWM UNIT..................................................................................................................................................... 56 FIGURE 17 - BLOCK DIAGRAM OF TIMER........................................................................................................................... 60 FIGURE 18 - LIN OSI-REFERENCE MODEL......................................................................................................................... 61 FIGURE 19 - RECEIVER DEBOUNCING & PROPAGATION DELAY .......................................................................................... 62 FIGURE 20 - RESET BEHAVIOUR ......................................................................................................................................... 67 FIGURE 21 - PATCH HARDWARE ........................................................................................................................................ 69 FIGURE 22 - PATCH CODE IN EEPROM ............................................................................................................................. 70 FIGURE 23 - PATCH CODE IN RAM .................................................................................................................................... 70 FIGURE 24 - APPLICATION SCHEMATIC SAMPLE ................................................................................................................. 73 FIGURE 25 - READING THE SWITCH MATRIX ...................................................................................................................... 74 FIGURE 26 - PIN OUT MLX80104/05 – TOP VIEW .............................................................................................................. 77 FIGURE 27 - MLX80104/05 PROGRAMMING INTERFACE WITH THE MELEXIS MINI E-MLX EMULATOR ............................. 80 FIGURE 28 - MELEXIS MLX80104/05 PROGRAMMING INTERFACE ADAPTER ..................................................................... 81 FIGURE 29 - MLX80104/05 PROGRAMMING INTERFACE WITH THE MELEXIS MINI E-MLX EMULATOR AND MELEXIS INTERFACE ADAPTER ................................................................................................................................................. 82 FIGURE 30 - CONNECTION DIAGRAM BETWEEN PTC-04 AND MLX80104/5 ...................................................................... 83 FIGURE 31 - MLX80104/05 PROGRAMMING INTERFACE WITH THE MELEXIS PTC-04 ....................................................... 85 FIGURE 32 - PIN OUT MLX80104/5 – TOP VIEW ................................................................................................................ 90 FIGURE 33 - QFN28 DRAWING .......................................................................................................................................... 92 MLX80104/5 – Datasheet 390108010400 Page 5 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet List of Tables TABLE 1 - ABSOLUTE MAXIMUM RATINGS.......................................................................................................................... 8 TABLE 2 - OPERATING CONDITIONS .................................................................................................................................... 9 TABLE 3 - STATIC CHARACTERISTICS ................................................................................................................................ 11 TABLE 4 - DYNAMIC CHARACTERISTICS ............................................................................................................................ 12 TABLE 5 - UNIFIED MEMORY MAPPING .............................................................................................................................. 15 TABLE 6 - MLX16 PRE-DEFINED PAGES ............................................................................................................................ 16 TABLE 7 - SYSTEM PROTECTED PORTS OVERVIEW ............................................................................................................ 23 TABLE 8 - STANDARD PORTS OVERVIEW .......................................................................................................................... 24 TABLE 9 - LOGIC TABLE FOR DETECTION OF LS INPUT SWITCHES ...................................................................................... 33 TABLE 10 - LOGIC TABLE FOR DIAGNOSIS OF LS INPUT SWITCHES SHORT VS. BATTERY .................................................... 33 TABLE 11 - LOGIC TABLE FOR DIAGNOSIS OF ALL INPUT SWITCHES SHORT VS. OTHER SWITCHES BY I1............................. 33 TABLE 12 - LOGIC TABLE FOR DIAGNOSIS OF ALL INPUT SWITCHES SHORT VS. OTHER SWITCHES BY I2............................. 34 TABLE 13 - LOGIC TABLE FOR BREAK DETECTION OF LS INPUT SWITCHES ........................................................................ 34 TABLE 14 - LOGIC TABLE FOR DETECTION OF HS INPUT SWITCHES ................................................................................... 34 TABLE 15 - LOGIC TABLE FOR DIAGNOSIS OF HS INPUT SWITCHES SHORT VS. GND .......................................................... 34 TABLE 16 - LOGIC TABLE FOR BREAK DETECTION OF HS INPUT SWITCHES ........................................................................ 35 TABLE 17 - SLEEP MODE CONFIGURATION OVERVIEW (SWITCH DETECTION) ..................................................................... 37 TABLE 18 - ACTIVE MODE CONFIGURATION OVERVIEW SWX PINS .................................................................................... 39 TABLE 19 - ACTIVE MODE CONFIGURATION OVERVIEW IOX PINS ...................................................................................... 41 TABLE 20 - ADC INPUT DIVIDER ....................................................................................................................................... 49 TABLE 21 - INTERRUPT INPUTS .......................................................................................................................................... 51 TABLE 22 - INTERRUPT VECTORS ....................................................................................................................................... 52 TABLE 23 - PRIO PORT ENCODING .................................................................................................................................... 52 TABLE 24 - CONFIGURABLE PWM FREQUENCIES.............................................................................................................. 59 TABLE 25 - DUTY CYCLE MEASUREMENT AND CALCULATION IN ACCORDANCE TO LIN PHYSICAL LAYER SPECIFICATION 2.X FOR BAUD RATES UP TO 20KBPS .......................................................................................................................... 63 TABLE 26 - DUTY CYCLE MEASUREMENT AND CALCULATION IN ACCORDANCE TO LIN PHYSICAL LAYER SPECIFICATION 2.X FOR BAUD RATES OF 10.4KBPS OR BELOW ........................................................................................................... 64 TABLE 27 - PIN DESCRIPTION 9 PIN MINI CIRCULAR CONNECTOR ....................................................................................... 79 TABLE 28 - PIN DESCRIPTION 10 PIN HEADER CONNECTOR ................................................................................................ 81 TABLE 29 - CONNECTIONS FOR THIRD PARTY PROGRAMMER ............................................................................................. 86 MLX80104/5 – Datasheet 390108010400 Page 6 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 1. General Overview 1.1 Block Diagram Figure 1 shows the principle block diagram of MLX80104/5. Power Supply VS VDDD VDDA ADC_VS VS VAUX 8mA In high ... SW1 SW2 ... ... Auxiliary Supply + WakeUp Logic ADC_MUX ADC_IO1 In IO_IN IO1 In IO Mux SW1 ... SW4 SW5 IO Mux IO6 10-bit ADC Window WD Timer IREF ADC_IREF RC- GNDA Oscillator 12 MHz GNDD GNDL Dual Task MULAN LIN MCU 16kbyte ROM/OTP 512byte RAM TI0 TO VS 2mA IO4 TI1 Test/Debug Interface MUX SW9 In IO3 IO6 IO7 ADC_IOx ADC_VS ADC_IREF ... SW9 IO2 IO5 IO6 Out PWMx Out IO Mux SW9 IO1 IO6 In IO Mux SW5 SW5 In IO0 ADC_IO6 In PWM SW6 SW7 SW8 IO1 Out PWMx Out PWM0 ... PWM7 SW0 In SW3 WD WakeUp SWx 8mA SW2 POR/WD WakeUp LIN IO0 IO1 ... In low SW0 UVLO LIN Transceiver LIN 192byte EEPROM Figure 1 - Block Diagram MLX80104/5 – Datasheet 390108010400 Page 7 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 2. Electrical Characteristics All voltages are referenced to ground (GND). Positive currents flow into the IC. 2.1 Absolute Maximum Ratings In accordance with the Maximum Rating System (IEC 60134). The absolute maximum ratings given in the table below are limiting values that do not lead to a permanent damage of the device but exceeding any of these limits may do so. Long term exposure to limiting values may affect the reliability of the device. Parameter Symbol Battery Supply Voltage Short term supply voltage Transients at supply voltage Transients at supply voltage Transients at high voltage signal pins Transients at high voltage signal pins Transient at high voltage signal and power supply pins VS VS_ld VS_tr1 VS_tr2 VLINx_tr1 VLINx_tr2 VHV_tr3 DC voltage on LIN, SWx, IOx pins VLIN_DC DC voltage on IREF, AWD pin Vlogic_DC VESDIEC ESD capability Maximum latch – up free current at any pin VESDHBM VESDCDM ILATCH Maximum power dissipation Ptot Thermal impedance JA Tstg Tvj Storage temperature Junction temperature Condition ISO 7637/2 pulse 5; t < 400 ms ISO 7637/2 pulse 1[1] ISO 7637/2 pulses 2 [1] ISO 7637/3 pulse 1 [2] ISO 7637/3 pulses 2 [2] ISO 7637/2 pulses 3A, 3B [3] T2uF blocking capacitor. ISO 7637/3 test pulses are applied to LIN via a coupling capacitance of 100nF. ISO 7637/3 test pulses are applied to LIN via a coupling capacitance of 1nF. ISO 7637/2 test pulses are applied to VS via a reverse polarity diode and >2uF blocking capacitor. Equivalent to discharging a 100pF capacitor through a 1.5Kohm resistor conforms to AEC-Q100-002 MLX80104/5 – Datasheet 390108010400 Page 8 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 2.2 Operating Conditions Parameter Battery supply voltage [1] Short time battery supply voltage [2] Operating ambient temperature Symbol Min Max Unit VS VS_S Tamb 5 18 -40 18 27 +125 V V °C Table 2 - Operating Conditions [1] [2] Vs is the IC supply voltage including voltage drop of reverse battery protection diode, V DROP = 0.4…1V, VBAT_ECU = 6…27V. Short time: t < 1 min 2.3 Static Characteristics (VS = 5 to 27V, TA = -40 to +125°C, unless otherwise specified) Parameter Symbol Condition Min Typ Max Unit 6 20 mA 5 V 50 µA 90 µA Pin VS 3.00 Supply current, active without switch current 3.01 Undervoltage lockout VS_UV 3.02 Supply current, sleep mode ISsl_typ VS = 12V 3.03 Supply current, sleep mode ISsl VS = 18V IS 25 PIN LIN 3.10 Short circuit bus current IBUS_LIM VLIN= VS = 18V, TxD = 0 40 120 200 mA 3.11 Pull up resistor LIN RSLAVE VLIN=0, TxD open 20 30 60 k 3.12 Pull up current LIN, Sleep mode IBUS_PU_Sleep VLIN=0, VS=12V, sleep mode -100 -75 3.13 LIN reverse current, recessive IBUS_PAS_rec Receiver input leakage current IBUS_PAS_dom VS = 12V, VLIN=0 3.14 LIN reverse current loss of battery IBUS_NO_BAT VS=0V, 0V < VLIN < 18V 3.15 LIN current during loss of Ground [3] IBUS_NO_GND VS=VGND=12V, 0V Vref_h Figure 7 - Voltage drops external LS switch These conditions will be met by Vref_h = 0.9*VS VS MLX80104 Switch matrix Vbat 14V Vbat 7V Metal wire resistance Vdrop_I1 Vref_h I1 Injection current (calibrated) 8mA 3.5mA Drop S3(175Ώ) 1.4V 0.6V 8V 3.5V 2.4V 1.05V 1V 0.5V Drop switch (1kΏ) Drop S1(300Ώ) Drop current source I1 Supply voltage Vs 13V 6V Vin_h COMP Swin_PU ON resistanceS1x Vdrop_S1 S1x Rswitch + Vin_h Vdrop_sw Rprot Rleak >500KO Switch closed: (maximum input low voltage) (1) Vin_h = Vdrop_S3 + Vdrop_sw + Vdrop_S1 (2) Vin_h < VS – Vdrop_I1 < Vref_h Matrix row S3x Vdrop_S3 ON – resistanceS3x Switch open: (minimum input high voltage) ECU_GND (3) Vs > Vin_h = I1 * Rleak > Vref_h These conditions will be met by Vref_h = 0.9*VS MLX80104/5 – Datasheet 390108010400 Page 31 of 100 Figure 8 - Voltage drops switch matrix June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet Vbat_ECU HS – switch Vbat 14V Vbat 7V Injection current (calibrated) 8mA 3.5mA Vbat shift(0.1*Vbat) 1.4V 0.7V Vbat_ chassis Vbat_shift Rleak >500KO Drop switch (1kΏ) 8V 3.5V 2.4V 1.05V Rswitch Drop current source I2 1V 0.5V Rprot Supply voltage Vs 13V 6V Drop S2(300Ώ) Vin_l Vdrop_sw + VS S2x MLX80104 Vdrop_S2 ON resistanceS1x Switch closed: (minimum input high voltage) Vin_l (1) Vbat-Vin_l = Vdrop_S2 + Vdrop_sw + Vbat_shift (2) Vbat-Vin_l < Vdrop_I2 > Vref_l COMP I2 Swin_PD Vdrop_I2 Switch open: (maximum input low voltage) Vref_l Metal wire resistance (3) 0< Vbat-Vin_l = Vbat –(I2 * Rleak) < Vref_l ECU_GND These conditions will be met by Vref_l = 0.1*VS Figure 9 - Voltage drops external HS switch Parameters of input switches Closed switch threshold resistance (including optional protection resistor) Rin_max < 1175Ώ Rin_max_ext < 1000Ώ Protection resistor for external switches Rprot >100 Ώ Protection capacitor for external switches Cprot 0…10nF Closed switch threshold resistance (including optional protection resistor and maximum battery or GND shift) MLX80104/5 – Datasheet 390108010400 Page 32 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 6.1.7. Switch diagnosis If switches are connected via a wiring harness outside the ECU some failure states has to be considered:     Short circuit to battery Short circuit to GND Short circuit to other switches Break of wires in the harness For diagnosis the current sources I1 as well as I2 can be configured to 10..20% of the normal current value. Assuming the same worst case conditions as used for the switch detection level calculation, the diagnosis current allows the detection of up to 7.5kΩ resistance in the switch path. Low side switch Table 9 - Logic table for detection of LS input switches Error Condition Closed Switch Open Switch Broken Wire Short to battery Short to GND Short to 2nd switch SWx_S1 IOx_S1 SWx_S2 IOx_S2 SWIN_PU 1 0 0 0 1 1/0 1 0 0 0 SWIN_PD 0 0 0 0 0 0 1 0 0 0 DIAG_S1 DIAG_S2 As shown in the Table 9, a closed switch cannot be differentiated from a short vs. GND by the logic level of SWIN_PU, but if the value is stable after a certain number of cycles, a faulty closed or shorted switch can be identified. A short to battery can be detected by using the complementary diagnosis current 10..20% * I2: Table 10 - Logic table for diagnosis of LS input switches short vs. battery Error Condition Closed Switch Open Switch Broken Wire Short to battery Short to GND Short to 2nd switch SWx_S1 IOx_S1 SWx_S2 IOx_S2 SWIN_PU 0 0 0 0 0 0 0 1 0 1 SWIN_PD 0 0 0 1 0 1/0 0 1 0 1 DIAG_S1 DIAG_S2 If a switch Sx is shorted to another switch Sy, a diagnosis is possible by applying the injection current I1 to the first switch and a sequential scan of the other switches Sy with the diagnosis current 10..20% * I2: Table 11 - Logic table for diagnosis of all input switches short vs. other switches by I1 Error Condition No short Short to 2nd Switch + Short to GND Switch x Switch x Switch y Switch y + Short to SWx_S1/ SWx_S2/ SWy_S1/ SWy_S2/ DIAG_S1 DIAG_S2 Vbat IOx_S1 IOx_S2 IOy_S1 IOy_S2 SWIN_PU 0 0 1 0 0 1 1 0 0 1 SWIN_PD 0 1 0 1 0 1 1 0 0 1 This diagnosis additionally allows the detection of double fault conditions (short to other switch pin & short to battery or GND). For separation of double fault condition with short vs. battery the diagnosis scan has to be repeated by the opposite current configuration applying the injection current I2 to the first switch and a sequential scan of the other switches Sy with the diagnosis current 10..20% * I1: MLX80104/5 – Datasheet 390108010400 Page 33 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet Table 12 - Logic table for diagnosis of all input switches short vs. other switches by I2 Error Condition SWIN_PU SWIN_PD No short Short to 2nd Switch + Short to GND + Short to Vbat Switch x SWx_S1/ IOx_S1 Switch x SWx_S2/ IOx_S2 Switch y SWy_S1/ IOy_S1 0 0 1 0 1 0 0 1 0 0 1 1 1 1 Switch y SWy_S2/ DIAG_S1 DIAG_S2 IOy_S2 0 0 1 1 0 0 The last possible fault condition of the wiring harness is a break(s) of wire(s).This fault cannot be detected by using the scan methods as described in the above tables. By adding a resistor of 7.5kΩ±1% in parallel to the switch, an open switch can be differentiated from a switch break. nd For diagnosis the scan result has to be compared to a 2 scan with the diagnosis injection current 10..20% * I1: Table 13 - Logic table for break detection of LS input switches Error Condition Short to SWx_S1/ 2nd IOx_S1 switch Closed Open Break Short to Vbat Short to GND SWx_S2/ DIAG_S1 DIAG_S2 IOx_S2 SWIN_PU 1 1 0 0 1 1/0 1 0 1 0 SWIN_PD 0 0 0 0 0 0 1 0 1 0 High side switch For the diagnosis of the HS – input switches the complementary configuration has to be applied: Table 14 - Logic table for detection of HS input switches Short to SWx_S1/ SWx_S2/ 2nd DIAG_S1 DIAG_S2 IOx_S1 IOx_S2 switch Error Condition Closed Open Break Short to Vbat Short to GND SWIN_PD 1 0 0 1 0 1/0 0 0 0 0 SWIN_PU 0 0 0 0 0 0 0 0 0 0 As shown in the Table 14, a closed switch cannot be differentiated from a short to battery by the logic level of SWIN_PD, but if the value is stable after a certain number of cycles, a faulty closed or shorted switch can be identified. A short to GND can be distinguished from an open switch by using the complementary diagnosis current 10..20% * I1: Table 15 - Logic table for diagnosis of HS input switches short vs. GND Error Condition Short to SWx_S1/ SWx_S2/ 2nd DIAG_S1 DIAG_S2 IOx_S1 IOx_S2 switch Closed Open Break Short to Vbat Short to GND SWIN_PD 0 0 0 0 0 0 1 0 1 0 SWIN_PU 0 0 0 0 1 1/0 1 0 1 0 By adding a resistor of 7.5kΩ±1% in parallel to the switch, an open switch can be distinguished from a broken wire. For nd diagnosis the scan result has to be compared to a 2 scan with the diagnosis injection current 10..20% * I2: MLX80104/5 – Datasheet 390108010400 Page 34 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet Table 16 - Logic table for break detection of HS input switches Error Condition Short to SWx_S1/ SWx_S2/ 2nd DIAG_S1 DIAG_S2 IOx_S1 IOx_S2 switch Closed Open Break Short to Vbat Short to GND SWIN_PD 1 1 0 0 1 1/0 0 1 0 1 SWIN_PU 0 0 0 0 0 0 0 1 0 1 The short circuits vs. other switch input pins are covered by the method described in Table 14 and Table 15. MLX80104/5 – Datasheet 390108010400 Page 35 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 6.1.8. Switch Configuration in sleep mode In case of a valid go to sleep condition, the following procedure must be initiated:  All ports requesting a wake up capability will be connected in parallel by the closed switches S1x or S2x to the shared sleep comparators and the shared pull up/down resistors.  Any permanently closed pushbutton or switch as well as ports with short circuits to battery or GND have to be excluded from the wake up capability, because a permanent current would be applied in sleep mode and no wake up edge detection would be possible (OR interconnection). This makes switch diagnosis mandatory before GO TO SLEEP  Switches with parallel resistor for break diagnosis have to be excluded from the wake up capability because of a permanent current flow in sleep mode and an undefined shift of the wake up threshold.  After the GO TO SLEEP command any local wake up condition will be suppressed by a sleep counter in order to insure stable conditions at any port and prevent an invalid wake up. The status of S1x, S2x as well as S3x (matrix rows) will be stored with the rising edge of the GO TO SLEEP command.  In case of a changed switch status after the GO TO SLEEP timeout period the system will wake up immediately and a ‘wake up error flag’ will be set.  A local wake up will be detected after a change of a switch position(s) for longer than the specified wake up filter time, the local wake up flag will be set.  This described procedure allows a change into power saving modes even in case of failures MLX80104/5 – Datasheet 390108010400 Page 36 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet Vs MLX80104 Vs Pin SW1 nSBY Rswitch + I1 ESD Rprot LS-switch Vrefh 10K Sleep COMP SW_in COM P Falling edge detect SBY 25µs Wu_error Vref_CMOS S1x EN_GND S3x config’ 18x switch Vbat GoToSlee p counter Pad SW3 HS-switch Rswitch Vs + SBY WU 18x switch config’ Pin SW2 Rprot FF Rising edge detect S2x ESD COM P SW_in Vref_CMOS Sleep COMP I2 10K 25µs Vrefl EN_GND S3x nSBY SBY Figure 10 - Wake up detection for switch inputs As shown in Table 17, the following sleep mode configurations are possible: Table 17 - Sleep mode configuration overview (switch detection) Mode 6.2 S1x S2x S3x Comment No wake up required 0 0 0 Port tristate Wake up for LS switch 1 0 0 Internal wake up current source to Vs Wake up fur HS switch 0 1 0 Internal wake up current source to GND Wake up matrix columns 1 0 0 Internal wake up current source to Vs Wake up matrix rows 0 0 1 Path to GND Additional Operation Modes SWx Ports Open drain output mode The SWx pins can also be used as normal open drain outputs. This mode can be switched on via the configuration register bits. In this mode the central current source (S1x and S3x) should not be applied to the open drain configured pin. MLX80104/5 – Datasheet 390108010400 Page 37 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet Because of the high voltage capability of the pin the current capability can be easy extended via an external pnptransistor. S1x/S2x Vs Pin SW_x HV_clamp ESD 1.25V +/-2% EN_GND LS/ latch COMP SW_IN S3x SBY MLX80104 Figure 11 - Structure of SWx pins MLX80104/5 – Datasheet 390108010400 Page 38 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet Table 18 - Active mode configuration overview SWx pins Register SW_Sxy Mode Reg. SW_CONFIG Central current source value Input result Remark SWx_S1 SWx_S2 SWx_S3 DIAG_S1 DIAG_S2 I1 I2 Tristate 0 0 0 x x x x - Central pull up current 1 0 0 0 X 100% X SWIN_PU Low side switch or matrix columns Central pull down current 0 1 0 x 0 x 100% SWIN_PD High side switch Matrix row connection 0 0 1 x x x x SWIN_PU Diagnosis 1 1/0 1/0 0 1 0 10..20% 100% SWIN_PU/ SWIN_PD Switch Diagnosis Diagnosis 2 1/0 1/0 0 0 1 100% 10..20% SWIN_PU/ SWIN_PD Switch Diagnosis Digital Input 0 0 0 x x x x SW_Inx Open drain output 0 0 1/0 x x x x SW_Inx MLX80104/5 – Datasheet 390108010400 Page 39 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 6.3 Additional Operation Modes IOx Ports Open drain output mode The IOx pin can also be used as normal open drain outputs. This mode can be switched on via the configuration register bits. In this mode the central current source (S1x and S3x) should not be applied to the open drain configured pin. Because of the high voltage capability of the pin the current capability can be easy extended via an external pnptransistor. ADC input mode Every IOx pin can also be used as analogue input signal for the integrated 10-bit ADC. Via the ADC_CTL register the IOx pins can be selected to be used as ADC channel. See chapter 9 Analogue to digital converter for detailed description. Interrupt capable input In case external events should generate an interrupt the IOx pins can also be configured as an interrupt source. The interrupt sensitivity can be configured either for the falling or for the rising or for both edges. See chapter 10 Interrupts for a detailed description. PWM Output The eight available PWM channels can be applied to the corresponding IOx pin via the register PWM_AD. For output of the PWM channels the pin must be configured in open drain configuration. See chapter 11 PWM Unit for a detailed description. IO_IN S1x/S2x VDDD Vs IO_WU Pin IO_x HV_clamp Level shift WU filter both edge detect ESD 25µs COMP 1.25V EN_GND LS/ latch S3x LS/ latch IO_WAKE_EN SBY SBY ADC_EN ADC_IN HV_clamp MLX80104 Figure 12 - Structure of IOx pins MLX80104/5 – Datasheet 390108010400 Page 40 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet Mode IOx_S1 1 IOx_S2 1 IOx_S3 2 IOx_EN 3 IOx_IRQ 4 ADCMUXx 5 PWMx_y 6 DIAG_S1 7 DIAG_S2 7 Table 19 - Active mode configuration overview IOx pins Input result Tristate 0 0 0 0 x 0 0 x x - Central pull up current 1 0 0 0 x 0 0 x x SWIN_PU Low side switch or matrix columns Central pull down current 0 1 0 0 x 0 0 x x SWIN_PD High side switch Matrix row connection 0 0 1 0 x 0 0 x x SWIN_PU Diagnosis 1 1/0 1/0 0 0 x 0 0 1 0 SWIN_PU/ SWIN_PD Switch diagnosis Diagnosis 2 1/0 1/0 0 0 x 0 0 0 1 SWIN_PU/ SWIN_PD Switch diagnosis Digital Input 0 0 0 1 0 0 0 x x IO_INx Interrupt Input 0 0 0 1 1 0 0 x x IO_IRQx IO_INx ADC Input 0 0 0 0 x 1 0 x x ADC result Open drain output 0 0 1 1/0 x 0 0 x x IO_INx Open drain PWM Output 0 0 1 0 x 0 1 x x - Remark 1 Central current source enable register Open drain output configuration register IOx 3 Input comparator register IOx 4 Interrupt register IOx 5 ADC channel selection register 6 PWM channel selection register 7 Central current source configuration register 2 MLX80104/5 – Datasheet 390108010400 Page 41 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 6.4 The IREF pin This pin provides a calibrated pull up current from the VS supply. This output current can be used for generation of an external reference or supply voltage by using an external bipolar transistor. An Application Note “External supply regulator using the IREF pin” is available at Softdist. Vs IREF_EN VBat LS/ latch SBY Vs 2mA +/- 5% ESD VB VBE BZV55/ C5V6 PAD IREF_OUT MLX80104 V_ext +/- 1% Figure 13 - Sample circuitry for IREF pin For increasing the accuracy of the V_ext voltage at higher loads a zener diode can be placed at the base of the transistor. V_ext = VB - VBE Via the central current source diagnose register the IREF current can be switched on/off. The voltage at this pin can be monitored via the internal ADC channel IREF Central current source configuration register Address Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0xC01E SW_CONFIG - - - - IREF_EN DIAG_S2 DIAG_S1 - IREF_EN DIAG_S2 DIAG_S1 Switch IREF PIN on/ff (0=off) Configure central pull down current source to 10..20% of nominal value for switch diagnosis Configure central pull up current source to 10..20% of nominal value for switch diagnosis MLX80104/5 – Datasheet 390108010400 Page 42 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 7. Clock System 7.1 RC-Oscillator The main oscillator is a 12MHz RC oscillator, which will be trimmed under software control according to the stored calibration value in the EEPROM. The frequency can be trimmed from 8MHz up to 14MHz. After Reset the RC oscillator is calibrated with the default reset value 0x00. The RC oscillator will be calibrated during production process to 12MHz 5. The calibration value will be stored in the EEPROM and the software initialisation routine must set this value in the system configuration register (See 16.2 Initialising the System) after start up. 7.2 Crystal Oscillator In case an external 12MHz resonator or crystal is connected, it is possible to select this oscillator as system clock by setting the XTAL_ON bit in the external clock source register. The loading capacitors are not a part of the IC and must be added externally. The start-up of the IC will always be done with the internal RC Oscillator. The XTAL oscillator can be switched on and off via the SEL_XTAL register. The settling time has to be taken into account, before under software control the XTAL oscillator will be selected as system clock for the IC. External clock source register – system protected register Address Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0xE02E SEL_XTAL - - - - - - - XTAL_ON XTAL_ON Selection of external clock source 0 = Use internal RC oscillator (reset value) 1 = Use external clock source The clock switching will be done fully synchronous and therefore the switching doesn’t generate spikes or disturbances to the CPU. The external XTAL oscillator must be connected to IO2 and IO5. In this case, the IO2 and IO5 must be configured as tristate and can’t be used for any other function. MLX80104/5 – Datasheet 390108010400 Page 43 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 8. Watchdog System The MLX80104/5 is equipped with two different watchdog systems. One digital programmable window watchdog and one completely independent operating analogue Watchdog are available. 8.1 Analogue Watchdog The analogue Watchdog is intended to fulfil application requirements where a completely independent clock source from the CPU is demanded for the watchdog system. Therefore an analogue system is used for this function. This system is based on charging/discharging an external capacity. For definition of the watchdog time an external capacitor must be connected to the pin AWD. Together with a fixed loading current source inside of the IC, the Watchdog time can be adjusted to any application needs. The Watchdog will be started automatically after reset. Once this has been done after the power on, the Watchdog cannot be stopped anymore. The Watchdog is stopped during sleep mode and is enabled again after every return from wakeup or power on reset. Watchdog acknowledge register – system protected register Address Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0xE028 IO_AWD - - - - - - AWD_ACK - AWD_ACK Writing “1” Acknowledge the analogue watchdog Writing a “1” to the AWD_ACK bit loads the external capacitor to the upper threshold and restarts the unloading time. This bit will be cleared automatically after charging of the watchdog capacity is done. Software cannot read back the value. POR t WDt_R AWD_IRQ AWD_ACK CWD_H CWD_M CWD_L t WD_R AWD_RST Figure 14 - Analogue watchdog behaviour MLX80104/5 – Datasheet 390108010400 Page 44 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 8.1.1. Using the analogue WDOG If the Watchdog has been started by power on reset, the capacitor voltage on AWD pin ramps up until the upper voltage level is reached. After that, the current source of WDOG reverts to unload the capacitor. On half of the Watchdog time it generates precondition status information via an external watchdog interrupt request to the CPU. This request can be used to store sensitive data into non-volatile memory and to continue without restarting WDOG. It is not allowed to use this interrupt to trigger the watchdog! The Watchdog must be acknowledged before the CWD_L voltage is reached, otherwise a system shutdown will be performed. This system shutdown ends with a POR. 8.1.2. Timing definition The watchdog time is defined by the external capacitor connected to the AWD pin. The value of this capacitor can be calculated as follows: tWDt_R [ms] = WD[nF] and tWD_R [ms] = 0.1*WD [nF] Example: WD = 10nF -> tWDt_R =10ms und tWD_R = 1ms The complete watchdog period will be for this example: 10ms+1ms=11ms MLX80104/5 – Datasheet 390108010400 Page 45 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 8.2 Digital Window Watchdog The Mulan digital watchdog has 3 possible behaviors and is running on a 12MHz clock. It is described in the next chapters. Important: After reset the intelligent watchdog is disabled. Bootstrap code should enable it as needed. Timer watchdog description In this mode, the watchdog is a free-running up counter that can be reset by software. When it reaches a predefined timeout value, a watchdog reset is generated (RST_WD_IT). Software must therefore periodically clear this counter to avoid a CPU reset. As interrupt RST_WD_IT is also generated at power on reset, reading bit WD_BOOT of register CONTROL can be used to find out which source has generated it (WD_BOOT = 1 in case it is the watchdog). Window watchdog description In the window mode clearing the counter is only authorized within a time window starting at half the predefined timeout value. In case a clear is done outside the window (e.g. before half the timeout delay), a RST_WD_IT interrupt is generated (WD_BOOT = 1). At the end of the window an interrupt is generated (not a reset). That interrupt also starts a new waiting sequence which is stopped when the software clears the free-running up counter. If the software has not cleared the counter after a given time, a RST_WD_IT interrupt is generated. Intelligent watchdog description This watchdog operates in a completely different way. It supposes the software allocates for a given task a given provision of time and a tag. This amount of time is programmable and can be changed. The tag can represent a state of the software. Once this time is elapsed, it generates an interrupt (not a reset). The software must check if the new state of the program is coherent with the tag saved, and then reload a new couple of time and tag. The interrupt generated also starts a new waiting sequence that is cleared when the software updates the couple time and tag (i.e. when the interrupt is serviced). If the software has not updated the couple time and tag after a given time, a RST_WD_IT interrupt is generated. MLX80104/5 – Datasheet 390108010400 Page 46 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 8.3 Watchdog Register Watchdog Tag Register Address Name 0xC004 WD_TAG WD_TAG[7:0] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 WD_TAG[7:0] Tag value to be used for intelligent Watchdog mode Watchdog Control Register Address Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0xC003 WDCTRL ERR WND MODE1 MODE0 - - DIV1 DIV0 Bit3 Bit2 Bit1 Bit0 ERR WND MODE[1:0] DIV[1:0] Watchdog access error (read only, clear on read) Window Watchdog Value (read only) Definition of Watchdog behaviour 00 Disabled 01 Timer Watchdog 10 Window Watchdoog 11 Intelligent Watchdog Watchdoog clock divider, definition of watchdog clock (OSC=187kHz) 00 OSC/8 01 OSC/32 10 OSC/128 11 OSC/512 Watchdog Timer Register Address Name 0xC002 WDT WDT[7:0] Bit7 Bit6 Bit5 Bit4 WDT[7:0] Watchdog timeout value, function depends on selected mode MLX80104/5 – Datasheet 390108010400 Page 47 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 9. Analogue to digital converter 9.1 General Description The ADC10 is a 10-bit analogue-to-digital converter, which utilizes successive approximation technique with an internal sample and hold circuit. The pins IO0 … IO7 can be used as ADC input. In addition the voltage on pin IREF and VS can be monitored via ADC. Please have a look to section 9.2 for information about the input divider. MLX80104 ADC control register ADC_CTL_L ADC_CTL_H VS Reference voltage VREFH 0.75V 1.5V 2.5V 0 .. 5V IO0 ADC interrupt ADC_INT ADC result ADC_IN_L ADC_IN_H 10-Bit ADC MUX IO7 IREF VS Figure 15 - ADC components The reference voltage VREFH is based on the internal bandgap reference and is applied to the DAC after power on. In accordance to the linear input voltage range of the analogue input pins the default value of VREFH is 2.5V. To improve the maximum resolution of the measurement, the reference voltage can be adapted to VREFH=1.5V as well as 750mV. The maximum theoretical resolution (1LSB) can be calculated by VREFHmin / 1024 = 0.75V /1024 = 732V. MLX80104/5 – Datasheet 390108010400 Page 48 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 9.2 Input divider The following table illustrates the input divider on the pins, the possible maximal input voltage and resolution for the different ADC reference voltages. Ref 0.75V Ref 1.5V Ref 2.5V Pin Divider Max input voltage Resolution Max input voltage Resolution Max input voltage Resolution IO0..IO7 2 1.5V 732µV 3V 1.46mV 5V 2.44mV IREF 4 3V 2.93mV 6V 5.86mV 10V 9.77mV VS 14 10.5V 10.25mV 21V 20.51mV 35V 34.18mV Table 20 - ADC Input divider 9.3 Accuracy of the reference The maximum reference voltage VREFH is generated by an amplified bandgap voltage. This voltage is divided by a resistor divider with a dividing error better than 1% to generate 1.5V or 750mV as reference voltage. The value of the reference voltage can be selected by the ADC_CTL register. The best accuracy can be calculated by: VREFHmin +/- (MinStepsize / divider factor) = 750mV +/- 1mV This value contains the gain and offset failure of the amplifier chain and the deviation of the resistor network. The overall deviation of the output voltage is defined by the accuracy at room temperature, the temperature gradients of the bandgap reference and the offset voltage of the amplifier (approximately +/- 1.5% from – 40…150C.) This results in a total deviation of VREFHmin +/- (minStepsize + (1.5%*VREFHmax)) / divider factor = 750mV +/- 16mV The absolute error of the measured input voltage additionally depends on the distance of the maximum input voltage to VREFHmax. Example: VREFH = 750mV Vin_max = 100mV (e.g. shunt measurement) Maximum absolute error: Vin_err_max = ((VREFH / Vin_max) x VREFHTol_max ) +/- 1LSB = +/- 2.5mV MLX80104/5 – Datasheet 390108010400 Page 49 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 9.4 ADC Register ADC result register Address Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 0xC00B ADC_IN_H - - - - - - 0xC00A ADC_IN_L ADC_R Bit1 Bit0 ADC_R [9..8] ADC_R [7..0] Result of ADC conversion ADC selection register Address Name 0xC009 ADC_CTL_H VREF ADCMUX Bit7 Bit6 Bit5 VREF Bit4 Bit3 Bit2 - ADC reference voltage selection 000b off 010b 1.5V 001b 2.5V 100b 750V ADC channel selection 0000b off 0001b IO0, divided by 2, 3µs sampling time 0010b IO1, divided by 2, 3µs sampling time 0011b IO2, divided by 2, 3µs sampling time 0100b IO3, divided by 2, 3µs sampling time 0101b 0110b 0111b 1000b 1001b 1010b Bit1 Bit0 ADCMUX IO4, divided by 2, 3µs sampling time IO5, divided by 2, 3µs sampling time IO6, divided by 2, 3µs sampling time IO7, divided by 2, 3µs sampling time Vs, divided by 14, 10µs sampling time, 500mV error, Switched off during standby IREF, voltage at IREF pin, divided by 4, 3µs sampling time ADC configuration register Address Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0xC008 ADC_CTL_L BUSY - - - - - FAST START START FAST BUSY If set it starts the ADC conversion Selection of conversion clock 0 slow clock - conversion time 10µs 1 fast clock – conversion time 5µs ADC conversion in progress MLX80104/5 – Datasheet 390108010400 Page 50 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 10. Interrupts Table 21 - shows all available interrupts in the MLX80104/5. Column “Pos” represents the interrupt input position in the interrupt controller. Column “Abs” represents the absolute priority of the input. Column “Rel” represents the relative priority for inputs having an identical absolute priority. Column “type” defines which instruction will be issued by the interrupt controller in case of interrupt. Priority Description Pos Abs Rel Reset + Watchdogs Reset 0 0 0 Stack error 1 0 1 Protection error 2 0 2 Invalid address 3 0 3 Program error 4 0 4 Exchange request 5 1 0 Task reset 6 1 1 Watchdog attention 7 1 2 Mutex 8 2 0 Signal, Handshake, Event, [Mutex] 9 5 0 Timer 10 3-6 0 ADC end of conversion 11 3-6 1 End of EEPROM Write/Erase 12 3-6 2 Pin change interrupt IOx 13 3-6 3 External Watchdog interrupt 14 3-6 4 Software interrupt 15 7 0 Notes: 1: Abort current instruction 2: Abort current instruction ►Return is NOT possible 3: No disable possible 4: Priority 0 can only be reached in system mode 5: For conformance test Type Jump Jump Call Call Call Call Call Call Call Call Call Call Call Call Call Call Notes 1,3,4 1,3,4 2,3,4 2,3,4 2,3,4 3,5 3 PRIO PRIO[1:0] PRIO[3:2] PRIO[5:4] PRIO[7:6] PRIO[9:8] Ports MASK PEND MASK[0] MASK[1] MASK[2] MASK[3] MASK[4] MASK[5] MASK[6] MASK[7] MASK[8] MASK[9] MASK[10] PEND[0] PEND[1] PEND[2] PEND[3] PEND[4] PEND[5] PEND[6] PEND[7] PEND[8] PEND[9] PEND[10] Table 21 - Interrupt inputs Reminder: The highest priority is 0 and the lowest is 7. The absolute priority is compared to Mlx16 priority to trigger an interrupt The relative priority is used by interrupt controller to decide between identical absolute priority interrupts fired at the same time: Lowest is issued first. Note: The level 0 of priority is not reachable in user mode. When Mlx16-8 sets priority to 0 in user mode, it is interpreted as priority 1 by the interrupt controller. MLX80104/5 – Datasheet 390108010400 Page 51 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 10.1 Interrupt vectors Table 22 - Interrupt vectors shows the interrupt vectors table as well as the type of interrupt generated (call or jump). They all use Far Page 0 (e.g. top of the ROM). See example of Fp0 in Table 6. Priority Pos Abs Rel 0 0 0 1 0 1 2 0 2 3 0 3 4 0 4 5 1 0 6 1 1 7 1 2 8 2 0 9 5 0 10 3-6 0 11 3-6 1 12 3-6 2 13 3-6 3 14 3-6 4 15 7 0 Description Reset + Watchdogs Reset Stack error Protection error Invalid address Program error Exchange request Task reset Watchdog attention Mutex Signal, Handshake, Event, [Mutex] Timer ADC end of conversion End of EEPROM Write/Erase Pin change interrupt External watchdog interrupt Software interrupt Type Jump Jump Call Call Call Call Call Call Call Call Call Call Call Call Call Call Interrupt vector Addr Name Fp0:80 RST_WD_IT Fp0:88 STACK_IT Fp0:90 PROT_ERR_IT Fp0:98 INV_AD_IT Fp0:A0 PROG_ERR_IT Fp0:A8 EXCHANGE_IT Fp0:B0 TASK_RST_IT Fp0:B8 WD_ATT_IT Fp0:C0 M4_MUTEX_IT Fp0:C8 M4_SHE_IT Fp0:D0 TIMER_IT Fp0:D8 ADC_IT Fp0:E0 EE_IT Fp0:E8 EXT0_IT Fp0:F0 EXT1_IT Fp0:F8 SOFT_IT Table 22 - Interrupt vectors 10.2 Priority port The port PRIO defines the priority level of 4 interrupt inputs. It is divided in 4 be fields of 2 bits. The correspondence between each field value is shown on Table 23. Priority Absolute field Priority 00 3 01 4 10 5 11 6 Table 23 - PRIO port encoding 10.3 Interrupt mask and pending ports A mask bit at 0 (value at reset) masks an interrupt input, while a mask bit at 1 makes it visible to the Mlx16. Note that with a mask at 0 it is still possible to check if the interrupt input is set by reading the corresponding pending bit. The interrupt pending bit is set when the interrupt occurs, the Mlx16 cannot write into this port to simulate an interrupt. Writing in this port is used for clearing the pending bit, which discards the corresponding interrupt. As writing a 1 in any pending bit clears it while writing a 0 does nothing, you can clear one or more interrupt bits in one shot, by example writing 0x0001 in PEND port clear the interrupt 5, while writing 0x7FF clear all interrupts from 5 to 15. MLX80104/5 – Datasheet 390108010400 Page 52 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet Pending interrupt register Address Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0xE009 PEND_H - - - - - SOFT_IT EXT1_IT EXT0_IT 0xE008 PEND_L EE_IT ADC_IT TIMER_IT M4_SHE_IT M4_MUTEX_ IT WD_ATT_IT TASK_RST_ EXCHANGE_ IT IT For abbreviation please see Table 22. Interrupt mask register Address Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0xE007 MASK_H - - - - - SOFT_IT EXT1_IT EXT0_IT 0xE006 MASK_L EE_IT ADC_IT TIMER_IT M4_SHE_IT M4_MUTEX_ IT WD_ATT_IT TASK_RST_ EXCHANGE_ IT IT For abbreviation please see Table 22. Interrupt priority register Address Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0xE005 PRIO_H - - - - - - EXT1[1] EXT1[0] 0xE004 PRIO_L EXT0[1] EXT0[0] EE[1] EE[0] ADC[1] ADC[0] TMR[1] TMR[0] Further information can be found in Table 21. EXT1[1:0] Priority of external watchdog interrupt EXT0[7:0] Priority of pin change interrupt EE[1:0] Priority of end of EEPROM Write/Erase interrupt ADC[1:0] Priority of ADC end of conversion interrupt TMR[1:0] Priority of Timer interrupt 10.4 High level system interrupts 10.4.1. Reset interrupt and watchdogs This interrupt is generated at power on reset or if the intelligent watchdog asks for a reset. Take care that the priority is not reset in the Mlx16, so this interrupt routine must start with instruction “MOV UPR, #0”. 10.4.2. Stack error A stack error occurs when the Mlx16 uses the stack pointer to access an invalid or an unauthorized area. No protection error or invalid address interrupt is generated. Obviously this interrupt uses a jump and does not push the program counter into the stack. MLX80104/5 – Datasheet 390108010400 Page 53 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 10.4.3. Exception error There are 3 interrupts due to software errors on the Mlx16: a protection error, an invalid address or a program error. These interrupts are at level 0, therefore you cannot return to the interrupted program. The program counter value pushed on the stack can only be used for debugging purpose. The device reaction after this failure condition must be done in the ISR and depends on the application requirements. It is possible to release a RESET, switch to sleep mode or program and endless loop to keep stable behaviour of the device. 10.4.4. Protection error A protection error interrupt happens when the Mlx16 attempts an unauthorized access or to clear the user bit (Mlx16 M register). Here is an exhaustive list of possible causes:  Write in user mode in the EEPROM.  Access to EEPROM while it is busy (EE_BUSY=1).  Write in port EEPROM while it is busy (EE_BUSY=1).  Write in system mode in EEPROM while EN_EEPROM_WE is 0  ADC conversion request while ADC is busy (ADC_BUSY=1)  Write in ANA_OUTx ports while corresponding OUTx_WE bit of port CONTROL is 0.  Write in the Mlx4 RAM private area.  Write in user mode into a system port.  Access error in the Intelligent Watchdog  Clear the user bit (try to enter system mode) not after a jump or call far page. 10.4.5. Invalid address An invalid address interrupt occurs when the Mlx16 does an invalid memory access. Here is an exhaustive list of possible causes:  Read, write or fetch a word at an odd address  Read, write or fetch into an unused area  Write a byte or a bit in EEPROM  Write a bit in a digital port supporting only word or byte.  Fetch into port area 10.4.6. Program error A program error occurs when the Mlx16 tries to execute an invalid Mlx16 instruction. Typically, it means that Mlx16 has an invalid value in its program counter (PC). MLX80104/5 – Datasheet 390108010400 Page 54 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 10.5 Debugger interrupt This interrupt is intended to be used together with the Emulator. 10.6 Pin change Interrupt This interrupt will be used to react on change pin IOx status. The edge sensitivity can be programmed in the interrupt register (See 6.1.4 Configuration Register IOx). For the interrupt generation, the IOx will be debounced with 3us. After the debouncing the interrupt will be generated and the interrupt request is stored for every channel in the IRQ register. 10.7 External Watchdog interrupt This interrupt is requested if the analogue watchdog has reached half of the Watchdog time period. See chapter 8 Watchdog System for details. 10.8 Software interrupt It is possible to trigger a low priority interrupt by software setting bit SWI of port SWI to 1 the port bit is automatically reset after one clock period, so it will always be re-read as a 0. MLX80104/5 – Datasheet 390108010400 Page 55 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 11. PWM Unit 11.1 General There are 8 PWM channels available. They share a common 8 bits free running counter with an input clock being either a 750kHz clock or a 12MHz divided by a programmable divider from 1 to 64. The duty cycle for each PWM channel can be set separately via PWM data register. The available PWM channels can be output to an IOx pin in low side configuration. The selection must be done via the PWM_AD register. To calculate the correct initialisation value for the PWM control register Equation 1 to Equation 4 are valid. Additionally, in Table 24 you will find all possible PWM frequencies and the corresponding parameters for the PWM control register. Every IOx pin has its own PWM duty cycle register. To address this register 1st the channel must be selected via PWM channel register (0xC011). After this selection the duty cycle can be written to the PWM duty cycle register (0xC012). After this procedure, the programmed cycle will be output on IOx pin if the pin is configured as open drain output and the PWM block is enabled (Bit PWM_EN in the PWM control register 0xC010). Because the PWM is running with the CPU frequency, the accuracy is better than ±5% of the nominal PWM frequency. 11.2 Block Diagram 750 k Hz Programmable prescaler by 1 to 64 1 2 MHz PWM _ FSB PWM _ EN 1 8 bits counter PWM _ DIV 1 6 Zero Port PWM _ CFG 8 Load 8 8 > IO0 Duty cycle IO0 3 Port PWM_AD Port PWM_DATA 64 bits Buffer ... 8 > 8 Duty cycle IO7 8 > IO7 PWM _ EN Figure 16 - PWM unit MLX80104/5 – Datasheet 390108010400 Page 56 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 11.3 PWM frequency calculation Depending on the needed PWM frequency you have to choose the right equation. In case the frequency is in the range of 45Hz to 2.9kHz, Equation 3 is valid. And in case the frequency is in the range of 0.72kHz to 46kHz, Equation 4 is the right one. FPWM kHz  FPWM MHz  750kHz PWM _ DIV  1 256 Equation 1 - PWM frequency for PWM_FSB=0 PWM _ DIV  12MHz PWM _ DIV  1 256 Equation 2 - PWM frequency for PWM_FSB=1 750kHz 1 FPWM kHz 256 PWM _ DIV  Equation 3 - Parameter PWM_DIV for frequencies in the range of 45.1 .. 2929.7Hz (PWM_FSB=0) 12MHz 1 FPWM MHz 256 Equation 4 - Parameter PWM_DIV for frequencies in the range of 721.2 .. 46875Hz (PWM_FSB=1) 11.4 PWM Control Register PWM channel selection Address Name Bit7 Bit6 Bit5 Bit4 0xC011 PWM_AD - - - - Bit5 Bit4 PWMSEL 000b 001b 010b 011b 100b 101b 110b 111b Bit3 Bit2 Bit1 Bit0 PWMSEL Address duty cycle register for IO0 Address duty cycle register for IO1 Address duty cycle register for IO2 Address duty cycle register for IO3 Address duty cycle register for IO4 Address duty cycle register for IO5 Address duty cycle register for IO6 Address duty cycle register for IO7 Duty cycle register Address Name 0xC012 PWM_DATA_ WRITE PWM_DATA_WRITE 0xC013 PWM_DATA_ READ PWM_DATA_READ PWM_DATA_WRITE PWM_DATA_READ MLX80104/5 – Datasheet 390108010400 Bit7 Bit6 Bit3 Bit2 Bit1 Bit0 8-bit duty cycle value for selected PWM channel (for writing new duty cycle value) For reading the current duty cycle Page 57 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet PWM control register Address Name 0xC010 PWM_CTL PWM_EN PWM_FSB PWM_DIV Bit7 Bit6 Bit5 PWM_EN PWM_FSB Bit4 Bit3 Bit2 Bit1 Bit0 PWM_DIV Enable/Disable PWM generation 1 = Enable 0 = Disable Selection between input clock of 750kHz or 12MHz 0 = 750kHz 1 = 12MHz Programmable pre-divider 1 to 64 MLX80104/5 – Datasheet 390108010400 Page 58 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 11.5 Available PWM Frequencies Following PWM frequencies are configurable via the PWM Control Register PWM_CTL on page 58. PWM Frequency in Hz PWM_CTL [5:0] FSB DIV PWM Frequency in Hz PWM_CTL [5:0] FSB DIV PWM Frequency in Hz PWM_CTL [5:0] FSB DIV 45.8 0x3F 0 63 139.5 0x14 0 20 1171.9 0x28 1 39 46.5 0x3E 0 62 146.5 0x13 0 19 1201.9 0x27 1 38 47.3 0x3D 0 61 154.2 0x12 0 18 1233.6 0x26 1 37 48.0 0x3C 0 60 162.8 0x11 0 17 1266.9 0x25 1 36 48.8 0x3B 0 59 172.3 0x10 0 16 1302.1 0x24 1 35 49.7 0x3A 0 58 183.1 0x0F 0 15 1339.3 0x23 1 34 50.5 0x39 0 57 195.3 0x0E 0 14 1378.7 0x22 1 33 51.4 0x38 0 56 209.3 0x0D 0 13 1420.5 0x21 1 32 52.3 0x37 0 55 225.4 0x0C 0 12 1464.8 0x01 0 1 53.3 0x36 0 54 244.1 0x0B 0 11 1464.8 0x20 1 31 54.3 0x35 0 53 266.3 0x0A 0 10 1512.1 0x1F 1 30 55.3 0x34 0 52 293.0 0x09 0 9 1562.5 0x1E 1 29 56.3 0x33 0 51 325.5 0x08 0 8 1616.4 0x1D 1 28 57.4 0x32 0 50 366.2 0x07 0 7 1674.1 0x1C 1 27 58.6 0x31 0 49 418.5 0x06 0 6 1736.1 0x1B 1 26 59.8 0x30 0 48 488.3 0x05 0 5 1802.9 0x1A 1 25 61.0 0x2F 0 47 585.9 0x04 0 4 1875.0 0x19 1 24 62.3 0x2E 0 46 732.4 0x03 0 3 1953.1 0x18 1 23 63.7 0x2D 0 45 732.4 0x40 1 63 2038.0 0x17 1 22 65.1 0x2C 0 44 744.0 0x3F 1 62 2130.7 0x16 1 21 66.6 0x2B 0 43 756.0 0x3E 1 61 2232.1 0x15 1 20 68.1 0x2A 0 42 768.4 0x3D 1 60 2343.8 0x14 1 19 69.8 0x29 0 41 781.3 0x3C 1 59 2467.1 0x13 1 18 71.5 0x28 0 40 794.5 0x3B 1 58 2604.2 0x12 1 17 73.2 0x27 0 39 808.2 0x3A 1 57 2757.4 0x11 1 16 75.1 0x26 0 38 822.4 0x39 1 56 2929.7 0x00 0 0 77.1 0x25 0 37 837.1 0x38 1 55 2929.7 0x10 1 15 79.2 0x24 0 36 852.3 0x37 1 54 3125.0 0x0F 1 14 81.4 0x23 0 35 868.1 0x36 1 53 3348.2 0x0E 1 13 83.7 0x22 0 34 884.4 0x35 1 52 3605.8 0x0D 1 12 86.2 0x21 0 33 901.4 0x34 1 51 3906.3 0x0C 1 11 88.8 0x20 0 32 919.1 0x33 1 50 4261.4 0x0B 1 10 91.6 0x1F 0 31 937.5 0x32 1 49 4687.5 0x0A 1 9 94.5 0x1E 0 30 956.6 0x31 1 48 5208.3 0x09 1 8 97.7 0x1D 0 29 976.6 0x02 0 2 5859.4 0x08 1 7 101.0 0x1C 0 28 976.6 0x30 1 47 6696.4 0x07 1 6 104.6 0x1B 0 27 997.3 0x2F 1 46 7812.5 0x06 1 5 108.5 0x1A 0 26 1019.0 0x2E 1 45 9375.0 0x05 1 4 112.7 0x19 0 25 1041.7 0x2D 1 44 11718.8 0x04 1 3 117.2 0x18 0 24 1065.3 0x2C 1 43 15625.0 0x03 1 2 122.1 0x17 0 23 1090.1 0x2B 1 42 23437.5 0x02 1 1 127.4 133.2 0x16 0x15 0 0 22 21 1116.1 1143.3 0x2A 0x29 1 1 41 40 46875.0 0x01 1 0 Table 24 - Configurable PWM Frequencies MLX80104/5 – Datasheet 390108010400 Page 59 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 12. Timer The timing generation principle is shown on Figure 17. 12MHz Div by 16 Programmable Divider 1 to 32767 750kHz TIMER_IT Interrupt 1 15 TMR Register Figure 17 - Block Diagram of Timer A 15 bits free running counter clocked by 750kHz is available to generate TIMER_IT interrupt at a rate varying from 1.33µs (TIMER [14:0] = 0) to 43.689ms (TIMER [14:0] = 32767). The timer is made of a down counting loadable binary counter. It is enabled by TMR_EN (bit 15) of TMR register. Once enabled each time it reaches 0x0000; it is reloaded by the value of TMR register TMR [14:0] and generates a TIMER_IT interrupt. Reading register TMR reads the current value of the counter when TMR_EN = 1 or an unknown value when TMR_EN = 0. Because the timer is running with the CPU frequency, the accuracy is better than ±5% of the nominal value. Timer Register Address Name Bit7 0xC007 TIMER_H TMR_EN 0xC006 TIMER_L TMR_EN TMR Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TMR [14:8] TMR[7:0] Enable/Disable Timer 1 = Enable 0 = Disable 15-bit Timer value 12.1 Timer Calculation The TMR value for the TIMER register can be calculated with Equation 5, where Timer_Period is the time between the timer interrupts in µs. TMR14 : 0  Timer_Period μs 12MHz 16 Equation 5 - Calculation of the TMR parameter MLX80104/5 – Datasheet 390108010400 Page 60 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 13. LIN Interface 13.1 The Concept The LIN protocol is implemented on a MULAN core on the MLX4 part. The complete MLX16 part is free for the application. With this dual core architecture the bus communication is decoupled from the application. The complete LIN driver running on the MLX4 is part of the software development system and will be supported by Melexis. The communication between both CPUs is done via an API. This API uses the common RAM area for data exchange. The application task (running on MLX16) transmits all necessary LIN configuration data via the API to the LIN task (running on MLX4) during the initialization process. Further information can be found in the document “MelexCM LIN Firmware API - Programmer’s Reference Manual”. Supervisor Task 1 Task 0 LIN SBIF Application software Fault confinement Bus failure management Data Link Layer Api Mlx4- Dual Inter-task port of the Mlx4 System synchronization Lin software Timer (Compare/ Capture) Bit level bus interface (digital) Logical Link Layer Acceptance filtering Recovery Management Message validation Time- base synchronozation Medium Acces Control Data Encapsulation/Decapsul. Error detection/Signaling Serialization/De serialization OSI Model Physical Layer Bit timing Bit synchronization Line driver/receiver Bus interface Figure 18 - LIN OSI-Reference model MLX80104/5 – Datasheet 390108010400 Page 61 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 13.2 LIN Physical Layer The MLX80104/5 contains an integrated physical layer for applications of low speed vehicle serial data network communication using the Local Interconnect Network (LIN) protocol. The device is designed in accordance to the physical layer definition of the LIN Protocol Specification Package 2.x and the SAE J2602 standard. The corresponding baudrate and slew rate can be set via API commands. The sleep mode capability allows a shutdown of the whole application. The included wake-up function detects incoming dominant bus messages and wakes up the IC. Because of the good symmetry parameter of the transceiver the communication with RC based synchronization accuracy is possible under all worst case conditions in Vbat - or Ground shift, even in case of recessive bus voltages down to 5V. RxD debounce The RxD debouncing circuit and the integrated low pass filter in the receiver path prevent RxD spikes in case of RF interferences and schaffner pulses to guarantee a correct sampling of the master request. TxD timeout A special feature is the TxD timeout. In case of a faulty blocked TxD (MLX or LIN controller crash) the Bus output is switched off automatically after the specified TxD timeout reaction time to prevent a dominant bus. The transmission is continued by next TxD L to H transition without delay. Undervoltage lockout An undervoltage lockout comparator detects an unspecified decrease of the regulated supply voltage VAUX. This measurement covers both, unspecified overload on VAUX and unspecified decrease of VS. It’s an additional factor of safety against undefined bus behaviour. To prevent a transmission interrupt due to Schaffner or RF modulation a debounce filter is used for spike suppression. t < trec_deb t < trec_deb VLINx t tREC_PDF tREC_PDR VRxDx 50% t Figure 19 - Receiver debouncing & propagation delay MLX80104/5 – Datasheet 390108010400 Page 62 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet Duty cycle calculation LIN 2.x With the timing parameters shown in the picture below two duty cycles , based on trec(min) and trec(max) can be calculated as follows : tBit =50µs D1 = trec(min) / (2 x tBit) D2 = trec(max) / (2 x tBit) Table 25 - Duty cycle measurement and calculation in accordance to LIN physical layer specification 2.x for baud rates up to 20Kbps Duty cycle calculation J2602: With the timing parameters shown in the table below two duty cycles , based on trec(min) and trec(max) can be calculated as follows : tBit =96µs D3 = trec(min) / (2 x tBit) D4 = trec(max) / (2 x tBit) MLX80104/5 – Datasheet 390108010400 Page 63 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet Table 26 - Duty cycle measurement and calculation in accordance to LIN physical layer specification 2.x for baud rates of 10.4Kbps or below MLX80104/5 – Datasheet 390108010400 Page 64 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 14. Sleep Mode and Wake up System 14.1 Entering Sleep Mode by API A valid MLX80104/5 sleep command is used to switch into the most power saving mode under software control. In this mode all unnecessary function blocks are switched off to save the maximum possible current, keeping only some minimum parts alive, which will watch events or conditions for possible wakeup requests. To enter Sleep Mode the following sequence has to be performed: Application software first takes care of saving any needed data into non-volatile memory, because Sleep Mode will force the system to switch off power supplies. Any register content of the CPU, the content of volatile memories, etc. will be lost. Finally a HALTED command (set “EN_HALTED” bit) has to be performed, which gives a signal to enter the sleep mode. Make sure that MLX4 is already halted otherwise the system cannot finish the power down procedure. This request starts the system shutdown process. This has to be the last action from the CPU. After sending this request the CPU has to stay in an infinite loop, waiting for system shutdown. This shutdown will be performed, even if incoming wakeup conditions should occur – which will be ignored as long as the system is not in sleep mode. This ensures that the system first shuts down and clears all CPU registers completely, to secure a defined restart into Power On state. By receiving a HALTED Signal from the CPU the following sequence is performed from the MLX80104/5 itself:  Analogue Watchdog is disabled  All registers not required in sleep mode are cleared and contain their reset values.  All registers containing configuration needed in sleep mode (i.e. enable bits for Wake Up sources etc.) keep their values  The internal auxiliary supply is switched on to supply the wake-up comparators as well as the wake-up enable register Any trimming value gets lost and must be restored within the software initialisation routine after wake-up. The digital supply as well as the analogue supply is switched off. In Sleep Mode all IOs will be switched to tri-state (high-impedance). 14.2 Wake Up System There are three possible ways to wake-up the MLX80104/5: 14.2.1. LIN Bus The LIN standby receiver detects any changing edge on the bus exceeding the wake up debouncing time of minimum 50us. The integrated filter prevents a wake up via EMC interferences. 14.2.2. Local Wake-up The second way to wake up the slave node is a local wake up condition. The input comparators detect any changing edge exceeding the wake up thresholds and the local wake up debouncing time of minimum 20us. Every wake up detection set a wake up flag, the bandgap reference and the voltage regulators are switched on and the power on procedure starts. The information about a local wake up is stored in the status register. 14.2.3. Internal Wake-up The third way to wake-up is the configurable internal wake timer. After a configured time the MLX80104/5 is switched on. This mode is foreseen for observing applications with a very slow current consumption in user mode. If local wake up capabilities are used, the leakage currents of the connected switches will increase the current consumption of the whole slave node. MLX80104/5 – Datasheet 390108010400 Page 65 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 15. Thermal Shutdown A thermal overload of the MLX80104/5 may occur due to an increased power dissipation and high ambient temperature. Causes for the unspecific power dissipation may be: - Short LIN to Vbat/Vs Shorted load at IO Pins IO loads too high In case the chip temperature exceeds the specified limit, the THERMAL bit in the XIN register (see below) will be set to 1. This bit can be used for triggering the software to find the reason of the thermal problem. This can be done by disable SWx/IOx pins to check if the external circuitry causes the problem. Thermal Error Bit Address Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0xC005 XIN - - - - - - - THERMAL THERMAL Thermal error bit 0 = no thermal error 1 = Thermal error MLX80104/5 – Datasheet 390108010400 Page 66 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 16. System behaviour 16.1 Reset behaviour After connecting power to the VS pin the system will start operation. The on-chip supplies start after the defined minimum voltage level is reached on the VS pin. The system is in the RESET state as long as the supply voltage is below its minimum voltage level. VS VAUX VDDA VDDD VAUX_PORN VDDD_PORN VDDA_PORN RESETN Figure 20 - Reset behaviour The reset signal keeps the complete IC in reset state if the supply voltage is below the specified value. After reaching the minimum voltage level of the supply, the reset signal becomes inactive and the initialisation sequence is started. The RC-Oscillator is switched on with the lowest frequency and the CPU starts the initialisation. 16.2 Initialising the System For correct system start-up some registers in the IO part must be restored after every RESET or WAKEUP by writing the values from reserved EEPROM addresses. These trim values have been stored during chip test. Overwriting these EEPROM memory addresses is prohibited otherwise the data for application needs is lost and the correct IC behaviour cannot be guaranteed in the specified range. Start-up steps: 1. Trim the bandgap to the expected value (3bit), 2. Trim the RC to the expected frequency (7bit), 3. Trim the internal biasing to the expected current, 4. Trim the ADC reference to the expected voltage for every input range (7bit), 5. Trim the switch current (4bit), 6. Set the EEPROM delay time (4bit). MLX80104/5 – Datasheet 390108010400 Page 67 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet System configuration register Address Name Bit7 0xE021 ANA_OUTC_H reserved ADC-REF * 0xE020 ANA_OUTC_L EN_XTAL RC_CALI * 0xE01F ANA_OUTB_H CU_TRIM * 0xE01E ANA_OUTB_L reserved SW_TRIM * 0xE01D ANA_OUTA_H EE_DELAY * reserved 0xE01C ANA_OUTA_L EE_DELAY INT_WAKE BG_TRIM CU_TRIM SW_TRIM ADC_REF RC-CALI EN_XTAL Bit6 Bit5 Bit4 Bit3 reserved reserved Bit2 Bit1 Bit0 BG_TRIM * INT_WAKE Set the EEPROM programming time Control of internal timer controlled wake up 00 off 01 wake up after 0.5s 02 wake up after 1s 03 wake up after 2s Adjust bandgap Adjust current references Adjust switch current source Adjust reference voltage of ADC VREFH RC-Oscillator calibration Enable use of external Quartz or Resonator as clock source for the MCU 0 internal RC-Clock is used 1 Switch from RC to external Attention: All values marked with “*” are trimming values for analogue IC parameter. Those values must be kept after initialisation of the IC! Otherwise the IC will not operate correctly. MLX80104/5 – Datasheet 390108010400 Page 68 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 17. ROM Patches In order to rapidly correct minor bugs in ROM a specific hardware has been added to replace up to four ROM spaces by EEPROM code. The principle is shown on Figure 21. Address 16 = { 0, AD_CMP0} E PATCH0_A = { 0, AD_CMP1} E PATCH1_A = = AD_CMP2 Decoder CPUs { 0, AD_CMP3} E PATCH3_A AD_CMP1 { 0, AD_CMP1} E PATCH2_A AD_CMP0 AD_CMP3 Patch ports ROM DATA ROM EEPROM / RAM PATCH0_I INSTR0 (*) PATCH1_I INSTR1 (*) PATCH2_I INSTR2 (*) PATCH3_I INSTR3 (*) MUX Data (*): JUMP FPx instructions Figure 21 - Patch hardware 17.1 Principle of operation There are 4 possible patch start addresses PATCHx_A (x=0..3) available. In case the program counter (PC) of the CPU points to an address, which is equal to one of the PATCHx_A ports (and the patch is enabled) the PC will be redirected to the address defined by the PATCHx_I port. The patch instruction can be located in the EEPROM or the RAM. MLX80104/5 – Datasheet 390108010400 Page 69 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 17.2 Patch start address Initially the patches are disabled (Bit E=0). The Mlx16 ROM startup code must be written in a way that an EEPROM byte decides if patches must be applied. If yes, patch ports must be loaded. This operation must be done prior to any other to allow patch of any code. PATCHi_A At reset 15 E 0 14 13 12 11 10 x x x x x 9 x 8 7 6 5 AD_CMP0[14:0] x x x x 4 3 x 2 x 1 x 0 x x Port PATCHx_A (x = 0 to 3) must be loaded with the address where the patch should start. Note: This address is only 15 bits, but ROM is less than 32Kbytes. 17.3 Patch jump instruction PATCHx_I must be loaded with a special instruction (a jump into far page) and the address into the far page. Figure 22 shows a how to execute the patch in EEPROM while Figure 23 shows a how to execute the patch from RAM (it supposes RAM has been loaded before). PATCHx_I At reset 15 0 x 14 1 x 13 0 x 12 0 x 11 0 x 10 0 x 9 0 x 8 0 x 7 1 x 6 1 x 5 1 x 4 x 3 2 1 FPAD[4:0] x x x 0 3 1 0 0 0 2 1 FPAD[4:0] x x x 0 3 0 0 x Fp7 15 1 14 0 13 0 12 0 11 0 10 0 Resulting patch start address 9 8 7 6 5 4 0 0 FPAD[4:0] 2 0 Fp7 value (Defined on Table 6) Figure 22 - Patch code in EEPROM PATCHx_I At reset 15 0 x 14 1 x 13 0 x 12 0 x 11 0 x 10 0 x 9 0 x 8 0 x 7 1 x 6 0 x 5 1 x 4 x 3 x Fp5 15 1 14 0 13 1 12 0 11 0 Resulting patch start address 10 9 8 7 6 5 4 0 0 1 FPAD[4:0] 2 0 1 0 Fp5 value (Defined on Table 6) Figure 23 - Patch code in RAM MLX80104/5 – Datasheet 390108010400 Page 70 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet Notes: - A patch can only start on an 8 bytes boundary. - The last instruction of the patch must be a far jump back to the first correct ROM instruction. Important: The access time to EEPROM is longer than for ROM; therefore the execution time of the patched code will be a bit slower than the same code in executed from ROM. Abnormal cases where two patches are at the same address but have different instruction is solved by giving priority to the lowest patch id. See examples below. Examples: If PATCH0_A = PATCH1_A, PATCH0_I is used If PATCH0_A = PATCH3_A, PATCH0_I is used If PATCH1_A = PATCH2_A = PATCH3_A, PATCH1_I is used MLX80104/5 – Datasheet 390108010400 Page 71 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 18. Application Hints Further information regarding the use of the IO and SW pins can be found in the Application note “Standard input/output pin configurations”. 18.1 Application Examples The SWx are used for connection to a switch matrix as well as for single switches to GND or VS The IOx pins can be used for different purposes: 1. Single switch input connected to GND or VS incl. switch diagnostics 2. Rotating encoder input 3. General purpose digital input 4. Open drain high voltage capable output 5. ADC Input The pin IREF, via an external bipolar transistor, is used to generate a 5V voltage to supply external pull up resistors. MLX80104/5 – Datasheet 390108010400 Page 72 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet VBat 22µF AWD VS 100nF VS optional IREF IO4 VDD_pu SW0 SW1 SW2 SW3 SW4 VS SW5 IO5 SW6 MLX80104 VS SW7 VS Diagnostic 7.5k SW8 IO6 SW9 Diagnostic 7.5k VDD_pu VDD_pu IO7 IO0 Encoder 1 IO1 IO2 Encoder 2 IO3 TI0 TI1 LIN TO 180p GND Figure 24 - Application schematic sample 18.1.1. Switch Matrix Hints If more than two switches are closed at the same time, it can happen that reading the switches gives a wrong result. A “ghost” switch is detected, that means it will read out a certain switch is pressed, but this switch is not really pressed (See Figure 25). To avoid this effect, diodes can be used for decoupling the switches. The diodes prevent the fault current by a closed switch in another row. Note: This wiring with diodes is only necessary if it is possible to press more than three switches at the same time. Example: In a matrix without diodes (left example) the open switch 2b (“ghost” switch from left example) is recognized as closed. The closed switches 1b, 1c and 2c setup a wrong current path. This wrong path is prevented in the protected wiring (right example) by the diode 1c. MLX80104/5 – Datasheet 390108010400 Page 73 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet a b c a 1 1 2 2 3 3 b c correct realization wrong realization Figure 25 - Reading the switch matrix MLX80104/5 – Datasheet 390108010400 Page 74 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 19. Software Development For software development a software development environment consisting of  Compiler  Linker  Debugger  User library  LIN2.x / J2602 API and a hardware development kit consisting of  Evaluation board  Emulator  Application board are available at Melexis. The kit description can be found in [4]. 19.1 UniROM (80104 only) Beside the software development at customer side a ready-to-use firmware, so called uniROM, is available. The uniROM firmware offers a ready to use application software which removes the need for new software development for new LIN applications. This Software can be configured to the need of different applications. Further information can be found in [1]. The main features are:  LIN protocol specification according to LIN 2.x and J2602  19.2kBaud and 10.4kBaud transmission speed  Up to 5 LIN configurable LIN frames: o Configurable data byte length o Configurable LIN identifier o Configurable communication direction (slave to master, master to slave) o Configurable data byte content on byte level  Event triggered frame  Go to sleep command  Node configuration services o Assign NAD o Assign frame ID range o Assign frame ID (according LIN2.0) o Read by identifier o J2602 target reset o J2602 broadcast reset MLX80104/5 – Datasheet 390108010400 Page 75 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet  Error detection (Communication error (according LIN2.x), EEPROM error, Thermal overload error, under voltage error, over voltage error etc.)  EEPROM user area for production data  Hardware CRC to protect EEPROM data  Internal 12MHz RC-oscillator. For higher accuracy an external resonator can be applied. But this is only necessary for slave to slave communication)  Window watchdog and additional independent analog watchdog  18 configurable high voltage I/O pins which are ground shift tolerant and can be used as following: o Up to 18 switch inputs (low side or low side can be configured for each pin separately) ) incl. broken line detection o Switch matrix inputs (5x5, 5x4, 4x4, 4x3, 3x3, 3x2) incl. broken line detection o Up to 18 configurable open drain outputs o Up to eight 10bit ADC inputs o Up to 8 PWM outputs with common frequency between 45Hz … 46,9kHz and different duty cycles for each output o Support of SMART Fets with current sense o Up to two rotary encoders supported  Configurable debouncing times for switches  Internal supply voltage measurement  Configurable Wake up sources (LIN, switches, ADC)  Software SPI and I C-interface supported for controlling IO extension  Constant current source output IREF (2mA) for building an external help supply 2 MLX80104/5 – Datasheet 390108010400 Page 76 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 20. Programming Interface The MLX80104/05 programming interface consists of the pins:    Pin 6 - TO => output Pin 8 - TI0 => input 0 Pin 7 - TI1 => input 1 TO is an open drain output. In case a third party programmer is used, an external pull-up resistor of 500Ohm against 3.3V to this pin is necessary. In case the Melexis Mini E-Mlx emulator with Melexis interface adapter or the PTC-04 is used, no extra pull-up resistor is needed. IO3 IO4 IO6 SW6 SW7 VS SW8 28 27 26 25 24 23 22 Additionally it is necessary to connect the MLX80104/05 with the supply voltage Vs and to stop the analog watchdog by connecting AWD (Pin 21) with GND. GNDA 1 21 AWD IREF 2 20 SW9 SW5 3 19 IO7 SW4 4 18 IO0 SW3 5 17 GNDD TO 6 16 GNDL TI1 7 15 LIN 8 9 10 11 12 13 14 TI0 IO5 IO2 SW2 SW1 SW0 IO1 MLX80104/05 QFN 5x5 28 Figure 26 - Pin out MLX80104/05 – Top view MLX80104/5 – Datasheet 390108010400 Page 77 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 20.1 Characteristics for the interface pins Parameter Symbol Condition Min Typ Max Unit 7 18 V 7.8 8.2 V 10 mA 2 4.5 V 0 3.4 V Pin VS Supply voltage VS Supply voltage during OTP programming VS Supply current, active without switch current Undervoltage lockout IS 6 VS_UV PIN AWD Input voltage range Pull down current VAWD IPD_AWD 2 µA PIN TO Input voltage range Pull up resistor (only necessary in case third party programmer is used) Input frequency VTO 0 RTO_PULLUP FTI 3.4 500 max output load 20pF V Ω 20 MHz 3.4 V PIN TI0,TI1 Input voltage range VTI 0 Input threshold rising edge VTI_RISE 1.7 V Input threshold falling edge VTI_FALL 1.5 V Input frequency MLX80104/5 – Datasheet 390108010400 FTI Page 78 of 100 20 MHz June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 20.2 Melexis Mini E-Mlx emulator To use the MLX80104/05 programming interface directly with the Melexis Mini E-Mlx connector it is necessary to put external components (see Figure 27) and a 9 pin mini circular connector with shield on the PCB. The connector could be a MD-90SM from CUI INC. This part can be ordered for instance from Digi-Key (CP-2290-ND). The Melexis emulator does not provide the supply voltage for the MLX80104/05. Because of this the module has to be powered by an external power supply. To disable the analog watchdog during programming and debugging it is necessary to connect pin 21 AWD to GND via a Jumper JP1. Pin No Name Function 1 TI0 Test input 0 2 GND Ground 3 VS VS output 4 TI1 Test input 1 5 LIN/MUST Open (not used) 6 V0 Open (not used) 7 V2 3.3V input 8 TO Test output 9 V1 Open (not used) Shield GND Ground Table 27 - Pin description 9 pin mini circular connector MLX80104/5 – Datasheet 390108010400 Page 79 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet Figure 27 - MLX80104/05 programming interface with the Melexis Mini E-Mlx emulator MLX80104/5 – Datasheet 390108010400 Page 80 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 20.3 Melexis Mini E-Mlx emulator and Melexis interface adapter In case there is not enough space to put all necessary components on the PCB as described in chapter 20.1 it is possible to use the Melexis interface adapter. This connector includes the 9 pin mini circular connector as well as all necessary components. Figure 28 - Melexis MLX80104/05 programming interface adapter The interface adapter provides an 10 pin header on top side as well as an 10 pin female header on the bottom side to connect the adapter to the MLX80104/05 module. The Melexis emulator does not provide the supply voltage for the MLX80104/05. Because of this the module has to be powered by an external power supply. Pin No Name Function 1 GND Ground 2 TO Test output 3 TI1 Test input 1 4 TI0 Test input 0 5 VS VS input 6 n.c. not used 7 AWD Analog watchdog 8 LIN/MUST not used 9 V1 not used 10 TM_ENABLE not used Table 28 - Pin description 10 pin header connector MLX80104/5 – Datasheet 390108010400 Page 81 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet Figure 29 - MLX80104/05 programming interface with the Melexis Mini E-Mlx emulator and Melexis interface adapter MLX80104/5 – Datasheet 390108010400 Page 82 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 20.4 Melexis Programmer PTC-04 The PTC-04 can be used for programming OTP & EEPROM via Melexis Test Interface. 3 test pins must be accessible by the PTC-04 programmer. These pins are TO (Test Interface output), TI0 and TI1 (both Test Interface inputs are used for data and clock). Additionally, the analog Watchdog pin AWD must be connected to GND to disable it. Otherwise, the IC will be reset via the analog Watchdog which makes it impossible to execute any operation via the Melexis Test Interface. A more detailed schematic can be found in Figure 31. Customer EOL Programming System with Melexis MLX80104/05 PSF Library DLL (using Microsoft Windows XP or 7) Melexis PTC-04 USB Melexis PTC-04 Power Supply Shielded wire (length max 50cm for max. programming speed) GND VS USB DB15 Female Connector AWD TO TI0 TI1 Customer Module MLX80104 MLX80105 EOL (OTP, EEPROM) via Melexis Test Interface Power supply Figure 30 - Connection diagram between PTC-04 and MLX80104/5 There is no additional power supply for the MLX80104/5 necessary. It will be powered via the PTC-04. Melexis suggests to keep the cable length between the PTC-04 and the MLX80105 as short as possible to allow a maximum programming speed (in the range of 0.5m maximum). Shielded wires must be used. The most critical connections regarding the used cable and the cable length are TO, TI0 and TI1. In case the cable length is longer than 0.5m the customer has to be secure that the shape of the signals for TO (at the PTC-04), TI0 and TI1 (at the MLX80104/05) are still correct. Otherwise the test interface speed has to be reduced by using the Melexis PSF DLL function SetSetting(). MLX80104/5 – Datasheet 390108010400 Page 83 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 20.4.1. PTC04 DB 15 Female Connector All unused pins of the connector have to be left open. PTC05 DB15 Female Connector 7 8 15 Pins 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MLX80104/5 – Datasheet 390108010400 6 14 5 13 Name VBAT N.C. DGND MUST TXD0 VOUT_PPS2 MUST0 / TI0 MICE / TO LIN_OUT +5V_DIG_CON DGND RXD0 XCK0 N.C. MUST1 / TI1 12 2 3 4 11 10 1 9 Description Power Supply (output) Not connected Digital Ground Analog test pin USART Transmit Data VOUT_PPS2 Digital test pin TI0 Digital test pin TO LIN BUS +5V DC Supply Digital Ground USART Receive Data USART Clock Not connected Digital test pin TI1 Page 84 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet Figure 31 - MLX80104/05 programming interface with the Melexis PTC-04 MLX80104/5 – Datasheet 390108010400 Page 85 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 20.5 Third party programmer In case a third party programmer tool is used, the MLX80104/05 based module has to provide at least following connections. MLX80104/05 Pin No Name Function 1,17,16 GND Ground 6 TO Test output 7 TI1 Test input 1 8 TI0 Test input 0 21 AWD Analog watchdog Table 29 - Connections for third party programmer MLX80104/5 – Datasheet 390108010400 Page 86 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 21. Operating under Disturbance 21.1 Loss of battery If the MLX80104/5 is disconnected from the battery, the bus pin is in high Impedance State. There is no impact to the bus traffic and to the ECU itself. The IC will be reverse powered if switches are placed outside and via wiring harness a short circuit to battery or a faulty blocked switch is connected to the MLX80104/5.To prevent undefined failure currents the ports for connections to external switches or loads have to be protected by a serial resistor of at least 100Ώ. 21.2 Loss of Ground In case of an interrupted ECU ground connection there is no influence to the bus line. 21.3 Short circuit to battery The LIN transmitter output current is limited to the specified value in case of short circuit to battery in order to protect the MLX80104/5 itself. 21.4 Short circuit to ground If the bus line is shorted to negative shifted ground levels, there is no current flow from the ECU ground to the bus and no distortion of the bus traffic. If the controller detects a short circuit of the bus to ground (RxD timeout) the transceiver can be set into sleep mode. The internal slave termination resistor is switched off and only a high impedance termination is applied to the bus. The failure current of the whole system can be reduced by at least ten times to prevent a fast discharge of the car battery. If the failure disappears, the bus level will become recessive again and will wake up the system even if no local wake up is present or possible. 21.5 Thermal overload The MLX80104/5 is protected against thermal overloads. If the chip temperature exceeds the specified value, the transmitter is switched off until thermal recovery. The receiver is still working during thermal shutdown. 21.6 Undervoltage Vs If the ECU battery supply voltage is missing or decreases under the specified value, the LIN pin functions as passive. MLX80104/5 – Datasheet 390108010400 Page 87 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 22. Marking/Order Code 22.1 Marking MLX80104 80104D Silicon Revision M27237 Lot Number Assembly Date Code – week number 1 1110AG Firmware Revision Assembly Date Code – Year 22.2 Order Code MLX80104 MLX80104 KLQ DAG 000 RE Delivery Form (RE = Reel) Option Code (000 = Standard) Firmware Version AG Silicon Version D Package Code (LQ=QFN, LW=QFN with wettable flanks) Temperature Code (K=-40 to 125°C) Product Name MLX80104/5 – Datasheet 390108010400 Page 88 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 22.3 Marking MLX80105 80105E M25574 1 1110 Silicon Revision Lot Number Assembly Date Code – week number Assembly Date Code – Year 22.4 Order Code MLX80105 MLX80105 KLQ EAA 000 RE Delivery Form (RE = Reel) Option Code (000 = Standard) Firmware Version (AA=no Firmware) Silicon Version E Package Code (LQ=QFN, LW=QFN with wettable flanks) Temperature Code (K=-40 to 125°C) Product Name MLX80104/5 – Datasheet 390108010400 Page 89 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet IO3 IO4 IO6 SW6 SW7 VS SW8 28 27 26 25 24 23 22 23. Pin Description GNDA 1 21 AWD IREF 2 20 SW9 SW5 3 19 IO7 SW4 4 18 IO0 SW3 5 17 GNDD TO 6 16 GNDL TI1 7 15 LIN 9 10 11 12 13 14 IO5 IO2 SW2 SW1 SW0 IO1 TI0 8 MLX80104/5 QFN 5x5 28 Figure 32 - Pin out MLX80104/5 – Top view MLX80104/5 – Datasheet 390108010400 Page 90 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet Table 1 – Pin Description MLX80104 QFN 5x5 28 Pin No Name Function 1 GNDA Analogue ground and ADC ground 2 IREF IREF output O 3 SW5 Switch matrix I/O, single switch input, open drain output, wake up capable I/O 4 SW4 Switch matrix I/O, single switch input, open drain output, wake up capable I/O 5 SW3 Switch matrix I/O, single switch input, open drain output, wake up capable I/O 6 TO Test output, unconnected in application mode O 7 TI1 Test input - connect to GND in application mode I 8 TI0 Test input - connect to GND in application mode I 9 IO5 SWx functionality and ADC input, wake up capable, PWM output I/O 10 IO2 SWx functionality and ADC input, wake up capable, PWM output I/O 11 SW2 Switch matrix I/O, single switch input, open drain output, wake up capable I/O 12 SW1 Switch matrix I/O, single switch input, open drain output, wake up capable I/O 13 SW0 Switch matrix I/O, single switch input, open drain output, wake up capable I/O 14 IO1 SWx functionality and ADC input, wake up capable, PWM output I/O 15 LIN Connection to LIN bus IO 16 GNDL LIN driver ground GND 17 GNDD Digital ground GND 18 IO0 SWx functionality and ADC input, wake up capable, PWM output I/O 19 IO7 SWx functionality and ADC input, wake up capable, PWM output I/O 20 SW9 Switch matrix I/O, single switch input, open drain output, wake up capable I/O 21 AWD Watch dog load capacitor I/O 22 SW8 Switch matrix I/O, single switch input, open drain output, wake up capable I/O 23 VS High voltage supply, battery voltage P 24 SW7 Switch matrix I/O, single switch input, open drain output, wake up capable I/O 25 SW6 Switch matrix I/O, single switch input, open drain output, wake up capable I/O 26 IO6 SWx functionality and ADC input, wake up capable, PWM output I/O 27 IO4 SWx functionality and ADC input, wake up capable, PWM output I/O 28 IO3 SWx functionality and ADC input, wake up capable, PWM output I/O MLX80104/5 – Datasheet 390108010400 I/O Type Page 91 of 100 GND June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 24. Mechanical Specification 1 2 N E2 L K E Bottom Exposed Pad D A A3 D2 e A1 b Figure 33 - QFN28 Drawing Table 2 – QFN28 Package Dimensions Symbol min QFN28 nom max [1] [2] [3] [4] [5] [6] A A1 0.80 0 0.90 0.02 1.00 0.05 A3 b D 0.18 0.20 0.25 0.30 D2 E 3.00 5.00 3.10 3.25 E2 e K 3.00 5.00 3.10 3.25 L N [6][3] ND [5] NE [5] 0.45 0.50 0.20 0.55 [1] 28 7 7 [2] 0.65 Dimensions and tolerances conform to ASME Y14.5M-1994 All dimensions are in Millimeters. All angels are in degrees N is the total number of terminals Dimension b applies to metalized terminal and is measured between 0.25 and 0.30mm from terminal tip ND and NE refer to the number of terminals on each D and E side respectively Depopulation is possible in a symmetrical fashion MLX80104/5 – Datasheet 390108010400 Page 92 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 25. Land Pattern Recommendations This recommendation is provided as a guideline for board layout. Table 3 – QFN28 Land Pattern Dimensions Symbol Land X1 Land Y1 Tab Land X2 Tab Land Y2 Land Space C1 Land Space C2 (in mm) 0.30 1.00 3.25 3.25 4.70 4.70 MLX80104/5 – Datasheet 390108010400 Page 93 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 26. ESD/EMC Remarks Electronic semiconductor products are sensitive to Electro Static Discharge (ESD). Always observe Electro Static Discharge control procedures whenever handling semiconductor products. 26.1 ESD/EMC Recommendations for the MLX80104/5 In order to minimize EMC influences, the PCB has to be designed according to EMC guidelines. The MLX80104/5 is an ESD sensitive device and has to be handled according to the rules in IEC61340-5-2. MLX80104/5 will apply the requirements in the application according to the specification and to ISO7637-2 26.2 Automotive Qualification Test Pulses The following chapter is valid for a complete assembled module. That means that automotive test pulses are applied to the complete module and not to the single IC. Therefore attention must be taken, that only protected pins (protection done the IC itself or by external components) are wired to a module connector. In the recommended application diagrams, the reverse polarity diode together with the capacitors on supply pins, the protection resistors in several lines and the load dump protected IC itself will protect the module against the below listed automotive test pulses. The exact values of the capacitors for the application have to be chosen in dependence of the automotive requirements of the module. For the LIN pin the specification “LIN Physical Layer Spec 2.x” is valid. Supply Pin VS is protected via the reverse polarity diode and the supply capacitors. No damage will occur for defined test pulses. A deviation of characteristics is allowed during pulse 1 and 2; but the module will recover to the normal function after the pulse without any additional action. During test pulse 3a, 3b, 5 the module will work within characteristic limits. Test pulses on supply lines Parameter Symbol Us Dim Test Condition Transient test pulses in accordance to ISO7637-2 (supply lines) Test pulses are defined with the 12V DC voltage shift on the supply lines. Application schematics are according application notes. Test pulse #1 vpulse1 -100 V 5000 pulses, t1 = 5s, td = 2ms, Ri = 10Ω Test pulse #2a vpulse2 75 V 5000 pulses, t1 = 0.5s, td = 0.05ms, Ri = 2Ω Test pulse #3a vpulse3a -200 V 1h, t1 = 0.1ms, t4 = 10ms, t5 = 90ms, Ri = 50Ω Test pulse #3b vpulse3b 200 V 1h, t1 = 0.1ms, t4 = 10ms, t5 = 90ms, Ri = 50Ω Test pulse #5b vpulse5 45 V 10 pulses, td = 400ms, Ri = 0.5Ω MLX80104/5 – Datasheet 390108010400 Page 94 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet Test pulses on LIN line Parameter Symbol Us Dim Test Condition Transient test pulses in accordance to ISO7637-3 (signal lines) Test pulses are defined with the 12V DC voltage shift on the signal lines. Application schematics are according application notes. vpulse1 -100 V 5000 pulses, t1 = 5s, td = 2ms, Ri = 10Ω vpulse2 75 V 5000 pulses, t1 = 0.5s, td = 0.05ms, Ri = 2Ω Test pulse #3a vpulse3a -200 V 1000 bursts, t1 = 0.1ms, t4 = 10ms, t5 = 90ms, Ri = 50Ω Test pulse #3b vpulse3b 200 V 1000 bursts, t1 = 0.1ms, t4 = 10ms, t5 = 90ms, Ri = 50Ω Test pulse #1 8 Test pulse #2a 9 26.3 EMC Test pulse definition EMC Test Pulse shapes Test Pulse 1 Test pulse 2 200 ms V 0.5...5s < 100 µs 50 µs V 12 V 0V 10% t 1 µs 90% vpulse1 vpulse2 90% 10% 12V 1 µs 2 ms 0V t 200 ms 0.5...5s Test Pulse 3a Test Pulse 3b 100 ns 5 ns V 90% V 12V vpulse3b 10% 0V t vpulse3b vpulse3a vpulse3a 10% 12V 0V 100 µs 10 ms 90 ms 100 µs 90% 10 ms t 90 ms 5 ns 100 ns Test Pulse 5 (Load Dump) V Pulse 5 90% Pulse 5 at device vpulse5 40V 10% 12V t tr = 0.1...10ms td = 40...400ms 8 9 Test pulse 1 is not part of ISO 7637-3 for signal lines, this test is made additional. Test pulse 2 is not part of ISO 7637-3 for signal lines, this test is made additional. MLX80104/5 – Datasheet 390108010400 Page 95 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 27. References [1] [2] Software Functional Specification for MLX80104 UniROM LIN Specification Package 2.1 [3] GM LIN/J2602 Implementation Specification [4] MLX80104/08 – Software Development Kit November 24, 2006 Issue 1.4 December 19, 2006 28. List of Abbreviations Dp Ep Fp GCC MLX80104/5 – Datasheet 390108010400 Direct page EEPROM Far page GNU Compiler Collection Page 96 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 29. Revision History Version Changes 0.1 Remark First preliminary release Date March 2008 0.11 Updated application schematic March 2008 001 Update of block diagram of MLX80104 Increase RAM size to 512byte Update absolute maximum ratings Update static characteristics Definition of pull up/down resistance on SWx and IOx in sleep mode Chapter ADC Add additional channel IREF Chapter PWM unit Increase number of PWM channels on IOx to eight Change the access to duty cycle register Chapter mechanical specification Update package dimensions Update chapter automotive test pulses December 2008 002 Correct test pin description in chapter Pin description Chapter Timer added Application example modified ADC chapter updated Chapter Patches added February 2010 003 Update absolute maximum ratings July 2010 004 Chapter PWM Unit Equation for PWM_DIV register added Frequency table added Chapter Timer Equation for Timer register added Chapter ADC Description for input divider added September 2010 005 Chapter Programming Interface added September 2010 006 Small layout changes done 007 Chapter Application Examples Application Schematic modified, capacitor value at VS pin increased to fulfil the performance status A Chapter PWM unit Block Diagram PWM unit modified Chapter Automotive Qualification Test Pulses Voltage levels updated 008 Order Information updated Marking MLX80104/5 updated Disclaimer updated Chapter Software Development added 009 Package drawing corrected MLX80104/5 – Datasheet 390108010400 January 2011 August 2011 January 2012 March 2012 Page 97 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 010 Chapter “Memory Mapping” updated Chapter “Programming Interface” New sub-chapter “Melexis programmer PTC-04” added New chapter “Land Pattern Recommendations” added Chapter “Operating Conditions” updated Chapter “Melexis Programmer PTC-04” updated June 2012 011 Chapter “List of Abbreviations” added Chapter “EEPROM” updated April 2013 012 Chapter “Programming Interface” updated July 2013 013 Chapter “Order Code” updated 014 Chapter “Order Code” updated Chapter “Melexis Mini E-Mlx emulator and Melexis interface adapter” updated Chapter “Entering Sleep Mode by API” updated 015 Chapter “Order Code” updated Chapter “Static Characteristics” updated May 2014 016 Chapter “Operating Conditions” updated Chapter “Switch diagnosis” updated Chapter “Order Code” updated (wettable flanks) Chapter “Reserved EEPROM Segments” added Chapter “The IREF pin” updated Parameter “LIN current during loss of Ground” updated in chapter “Static Characteristics” April 2015 017 Chapter “Characteristics for the interface pins” Parameter “Supply voltage during OTP programming” updated MLX80104/5 – Datasheet 390108010400 January 2014 Page 98 of 100 March 2014 Only MLX80105 affected June 2016 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 30. Standard information regarding manufacturability of Melexis products with different soldering processes Our products are classified and qualified regarding soldering technology, solderability and moisture sensitivity level according to following test methods: Reflow Soldering SMD’s (Surface Mount Devices)   IPC/JEDEC J-STD-020 Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices (classification reflow profiles according to table 5-2) EIA/JEDEC JESD22-A113 Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability Testing (reflow profiles according to table 2) Wave Soldering SMD’s (Surface Mount Devices) and THD’s (Through Hole Devices)   EN60749-20 Resistance of plastic- encapsulated SMD’s to combined effect of moisture and soldering heat EIA/JEDEC JESD22-B106 and EN60749-15 Resistance to soldering temperature for through-hole mounted devices Iron Soldering THD’s (Through Hole Devices)  EN60749-15 Resistance to soldering temperature for through-hole mounted devices Solderability SMD’s (Surface Mount Devices) and THD’s (Through Hole Devices)  EIA/JEDEC JESD22-B102 and EN60749-21 Solderability For all soldering technologies deviating from above mentioned standard conditions (regarding peak temperature, temperature gradient, temperature profile etc) additional classification and qualification tests have to be agreed upon with Melexis. The application of Wave Soldering for SMD’s is allowed only after consulting Melexis regarding assurance of adhesive strength between device and board. Melexis is contributing to global environmental conservation by promoting lead free solutions. For more information on qualifications of RoHS compliant products (RoHS = European directive on the Restriction Of the use of certain Hazardous Substances) please visit the quality page on our website: http://www.melexis.com/quality.aspx MLX80104/5 – Datasheet 390108010400 Page 99 of 100 June 2016 Rev 017 MLX80104/5 LIN Slave Controller for Switches Datasheet 31. Disclaimer Devices sold by Melexis are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. Melexis makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Melexis reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with Melexis for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by Melexis for each application. The information furnished by Melexis is believed to be correct and accurate. However, Melexis shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of Melexis’ rendering of technical or other services. © 2012 Melexis NV. All rights reserved. For the latest version of this document, go to our website at www.melexis.com Or for additional information contact Melexis Direct: Europe, Africa, Asia: America: Phone: +32 1367 0495 Phone: +1 248 306 5400 E-mail: sales_europe@melexis.com E-mail: sales_usa@melexis.com ISO/TS 16949 and ISO14001 Certified MLX80104/5 – Datasheet 390108010400 Page 100 of 100 June 2016 Rev 017