AH-27

AH-27 Micrel Application Hint 27 Slowing Voltage Regulator Turn-On by Jerry Kmetz Slow Turn-On Circuits The turn-on time interval of a voltage regulator is essentially determined by the bandwidth of the regulator, its maximum output current, and the load capacitance. To some extent the rise time of the applied input voltage (which is normally quite short, tens of milliseconds, or less) also affects the turn-on time. However, the regulator output voltage typically steps abruptly at turn-on. Increasing the turn-on interval via some form of slew-limiting decreases the surge current seen by both the regulator and the system. This application hint addresses designing circuitry to change the step-function to a smoother RC charge waveform. Various performance features exist between the three circuits that are presented. These are (1) whether stability is impacted, (2) whether start-up output is 0V, and (3) whether the circuit quickly recovers from momentarily interrupted input voltage or shorted output. The following table summarizes the features of each circuit: Circuit Stability Start-Up VIN Interrupt Number Impacted? Pedestal? Recovery? 1 2 3 yes no no 1.2V 1.8V 0V no no yes VOUT Short Recovery? no yes no As CT charges, the regulator output (VOUT) asymptotically approaches the desired value. If a turn-on time of 300 milliseconds is desired then about three time constants should be allowed for charge time: then 3τ = 0.3s, or τ = 0.1s = R1 × CT = 300kΩ × 0.33µF. Figure 2 shows the waveforms of the circuit of Figure 1. This circuit has three shortcomings: (1) the approximately 1.2V step at turn-on, (2) the addition of capacitor CT places a zero in the closed-loop transfer function (which affects frequency and transient responses and can potentially cause stability problems) and (3) the recovery time associated with a momentarily short-circuited output may be unacceptably long. This is because if the output is shorted CT is discharged only by R2; if the short is removed before CT is fully discharged the regulator output will not exhibit the desired turn-on behavior. INPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 10 5 0 Slow Turn-On Circuit Performance Features 1. The Simplest Approach Figure 1 illustrates a typical LDO voltage regulator, the MIC29153, with an additional capacitor (CT) in parallel with the series leg (R1) of the feedback voltage divider. Since the voltage (VADJ) will be maintained at VREF by the regulator loop, the output of this circuit will still rapidly step to VREF and then rise slowly. Since VREF is usually only about 1.2V, this eliminates a large part of the surge current. 4 2 0 0 0.2 0.4 0.6 0.8 1.0 TIME (s) Figure 2. Turn-On Behavior for Circuit of Figure 1 Typical LDO Regulator VIN IN CIN 22µF GND MIC29153 VREF ADJ R2 100k VADJ OUT R1 300k CT 0.33µF COUT 22µF VOUT Figure 1. Simplest Slow Turn-On Circuit 3-202 1997 AH-27 Typical LDO Regulator VIN IN CIN 22µF GND MIC29153 VREF OUT R1 300k ADJ VADJ D1, D2 = 1N4148 D1 R2 100k D2 CT 0.33µF COUT 22µF VOUT Micrel Figure 3. Improved Slow Turn-On Circuit 2. Improved Simple Approach Figure 3 is an improvement on the circuit of Figure 1 in that it addresses the problems of potential instability and recovery time. Diode D1 is added to the circuit to decouple the (charged) capacitor from the feedback network, thereby eliminating the effect of CT on the closed-loop transfer function. Because of the non-linear effect of D1 being in series with CT, there is a slightly longer “tail” associated with approaching the final output voltage at turn-on. In the event of a momentarily shorted output, diode D2 provides a lowimpedance discharge path for CT and thus assures the desired turn-on behavior upon recovery. Figure 4 shows the waveforms of the circuit of Figure 3. Note that the initial step-function output is now 0.6V higher than with the circuit of Figure 1. This approximately 1.8V turn-on pedestal may be objectionable, especially in applications where the output voltage is relatively low by design. INPUT VOLTAGE (V) 3. Eliminating Initial Start-Up Pedestal The circuits of Figures 1 and 3 depend upon the existence of an output voltage (to create VADJ) and, therefore, produce the initial step-function voltage pedestals of about 1.2V and 1.8V, as can be seen in Figures 2 and 4, respectively. The approach of Figure 5 facilitates placing the output voltage origin at zero volts because VCONTROL is derived from the input voltage. No reactive component is added to the feedback circuit. The value of RT should be considerably smaller than R3 to assure that the junction of RT and CT acts like a voltage source driving R3 and so RT is the primary timing control. If sufficient current is introduced into the loop summing junction (via R3) to generate VADJ ≥ VREF, then VOUT will be zero volts. As RT charges CT the voltage VCONTROL decays, which would eventually result in VADJ < VREF. However, since in normal operation VADJ = VREF, VOUT will become greater than zero volts. The process continues until VCONTROL decays to VREF+0.6V and VOUT reaches the desired value. This circuit requires a regulator with an enable function, (e.g., the MIC29152) because a small (< 2V) spike is generated coincident with application of a step-function input voltage. Capacitor C1 and resistor R4 provide a short hold-off timing function that eliminates this spike. Figure 6 illustrates the timing of this operation. The small initial delay (about 40 milliseconds) is the time interval during which VADJ > VREF. Since VIN is usually fairly consistent in value R3 may be chosen to minimize this delay. Note that if R3 is calculated based on the minimum foreseen VIN (as described below), then higher values of VIN will produce additional delay before the turn-on ramp begins. Conversely, if VIN (max) is used for the calculation of R3, then lower values of VIN will not produce the desired turn-on characteristic; instead, there will be a small initial step-function prior to the desired turn-on ramp. Recovery from a momentarily shorted output is not addressed by this circuit, but interrupted input voltage is handled properly. Notice that the build-up of regulator output voltage differs from the waveforms of Figures 2 and 4 in that it is more ramp-like . This is because only an initial portion of the RC charge waveform is used; i.e., while VCONTROL > VREF+0.6V. The actual time constant used for Figure 5 is 0.33 second, so 3τ is one second. As shown by Figure 6, this provides about 600 milliseconds of ramp time, 3 10 5 0 OUTPUT VOLTAGE (V) 4 2 0 0 0.2 0.4 0.6 0.8 1.0 TIME (s) Figure 4. Turn-On Behavior of Figure 3 1997 3-203 AH-27 Typical LDO Regulator VIN CIN 22µF IN VREF GND ADJ EN MIC29152 VCONTROL C1 0.1µF RT 33k R3 240k D1 1N4148 R2 100k OUT VADJ R1 300k COUT 22µF VOUT Micrel R4 240k CT 10µF D2 1N4001 Figure 5. Slow Turn-On Without Pedestal Voltage INPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 10 5 0 4 2 0 0 0.2 0.4 0.6 0.8 1.0 TIME (s) Figure 6. Turn-On Behavior of Figure 5 which corresponds to the first 60% of the capacitor RC charge curve. R3 is calculated as follows: at turn-on time force VADJ = 1.5V (just slightly higher than VREF) then ICONTROL = 1.5V R1 × R2      R1 + R2  Since the MIC29152 is a low-dropout regulator, 6V was chosen for VIN(min). This corresponds to the small (approximately 40 msec) delay before the output begins to rise. With 7V input the initial delay is considerably more noticeable. and R3 = VIN min − 0.6V ICONTROL 3-204 1997