KS8893ML

KS8893M/ML/MI Integrated 3-Port 10/100 Managed Switch with PHYs Preliminary Data Sheet Rev. 1.0 General Description The KS8893M, a highly integrated layer 2 managed switch, is designed for low port count, cost-sensitive 10/100 Mbps switch systems. It offers an extensive feature set that includes rate limiting, tag/port-based VLAN, QoS priority, management, management information base (MIB) counters, MII/SNI, and CPU control/data interfaces to effectively address both current and emerging Fast Ethernet applications. The KS8893M contains two 10/100 transceivers with patented mixed-signal low-power technology, three media access control (MAC) units, a high-speed non-blocking switch fabric, a dedicated address lookup engine, and an on-chip frame buffer memory. Both PHY units support 10BASE-T and 100BASETX. In addition, one PHY unit supports 100BASEFX. The KS8893ML is the single power supply version with all the identical rich features of the KS8893M. ___________________________________________________________________________________________________ Functional Diagram 1 K LOOK-UP ENGINE FIFO, FLOW CONTROL, VLAN TAGGING, PRIORITY HP AUTO MDIX 10/100 T/TX/FX PHY 1 10/100 T/TX PHY 2 10/100 MAC 1 QUEUE MANAGEMENT HP AUTO MDIX 10/100 MAC 2 BUFFER MANAGEMENT RMII/MII/ SNI 10/100 MAC 3 FRAME BUFFERS SNI SPI SPI MIB COUNTERS MIIM SMI I2C P1 LED[3:0] P2 LED[3:0] CONTROL REGISTERS EEPROM INTERFACE LED DRIVERS STRAP IN CONFIGURATION June 2005 1 M9999-063005 Micrel KS8893M/ML/MI Features • Proven Integrated 3-Port 10/100 Ethernet Switch – 3rd generation switch with three MACs and two PHYs fully compliant to IEEE 802.3u standard – Non-blocking switch fabric assures fast packet delivery by utilizing an 1K MAC address lookup table and a store-and-forward architecture – Full duplex IEEE 802.3x flow control (pause) with force mode option – Half-duplex back pressure flow control – HP Auto MDI-X for reliable detection of and correction for straight-through and crossover cables with disable and enable option TM – Micrel LinkMD TDR-based cable diagnostics permit identification of faulty copper cabling – 100BASE-FX support on port 1 – MII interface supports both MAC mode and PHY mode – RMII interface support with external 50MHz system clock – 7-wire serial network interface (SNI) support for legacy MAC – Comprehensive LED Indicator support for link, activity, full/half duplex and 10/100 speed • Switch Monitoring Features – Port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port or MII – MIB counters for fully compliant statistics gathering, 34 MIB counters per port – Loopback modes for remote diagnostic of failure • Low Power Dissipation: – Full-chip hardware power-down (register configuration not saved) – Per port based software power-save on PHY (idle link detection, register configuration preserved) – Voltages: Core 1.2V I/O and Transceiver 3.3V • Industrial Temperature Range: –40oC to +85oC • Available in 128-Pin PQFP Applications • Universal Solutions – Media Converter – FTTx customer premises equipment – VoIP Phone – SOHO Residential Gateway – Broadband Gateway / Firewall / VPN – Integrated DSL/Cable Modem – Wireless LAN access point + gateway – Set-top/Game Box – Standalone 10/100 switch • Comprehensive Configuration Register Access – Serial management interface (SMI) to all internal registers – MII management (MIIM) interface to PHY registers 2 – SPI and I C Interface to all internal registers – I/0 pins strapping and EEPROM to program selective registers in unmanaged switch mode – Control registers configurable on the fly (port-priority, 802.1p/d/q, AN…) • Upgradeable Solutions(1) – Unmanaged switch with future option to migrate to a managed solution – Single PHY alternative with future expansion option for two ports • QoS/CoS Packet Prioritization Support – Per port, 802.1p and DiffServ-based – Re-mapping of 802.1p priority field per port basis – Four priority levels • Industrial Solutions – Applications requiring port redundancy and port monitoring – Sensor devices in redundant ring topology Note: • Advanced Switch Features – IEEE 802.1q VLAN support for up to 16 groups (fullrange of VLAN IDs) – VLAN ID tag/untag options, per port basis – IEEE 802.1p/q tag insertion or removal on a per port basis (egress) – Programmable rate limiting at the ingress and egress on a per port basis – Broadcast storm protection with % control (global and per port basis) – IEEE 802.1d spanning tree protocol support – Special tagging mode to inform the processor which ingress port receives the packet – IGMP snooping (Ipv4) and MLD snooping (Ipv6) support for multicast packet filtering – MAC filtering function to forward unknown unicast packets to specified port – Double-tagging support 1. Reduces cost and time of PCB re-spin. • Low Latency Support – Repeater mode LinkMD is a trademark of Micrel, Inc. Product names used in this datasheet are for identification purposes only and may be trademarks of their respective companies. June 2005 2 M9999-063005 Micrel KS8893M/ML/MI Ordering Information Part Number KS8893M KS8893ML KS8893MI KSZ8993M Temperature Range 0 C to 70 C 0oC to 70oC –40 C to +85 C 0 C to 70 C o o o o o o Package 128-Pin PQFP 128-Pin PQFP 128-Pin PQFP 128-Pin PQFP, Lead-free Contacts Location Corporate HQ Eastern USA Central USA Western USA China Korea Taiwan Singapore Japan Europe Western Europe New Zealand Address 2180 Fortune Drive 93 Branch Street 722 S. Denton Tap Suite 130 2180 Fortune Drive Room 712, Block B, Intl. Chamber of Commerce Bldg., Fuhua Rd 1, Futian 4F, KTB Building, 826-14, Yeoksam-dong, Kangnam-ku 4F, No. 18, Lane 321, Yang-Guang Street, Nei-Hu Chu 300 Beach Road, #10-07 The Concourse 2-3-1 Minato Mirai, Queen’s Tower A 14F, Nishi-ku 1st Floor, 3 Lockside Place, Mill Lane 10, avenue du Quebec, Villebon BP116 Office 2, CML Building 2 Perry Street City, State/Province, Country San Jose, CA 95131 USA Medford, NJ 08055 USA Coppell, TX 75019 USA San Jose, CA 95131 USA ShenZhen, PR China 518026 Seoul 135-080 Korea Taipei, 11468 Taiwan, R.O.C. Singapore 199555 Yokohama, Kanagawa 220-8543 Japan Newbury, Berks RG14 5QS UK Courtaboeuf Cedex 91944 France Masterton New Zealand Telephone +1 (408) 944-0800 +1 (609) 654-0078 +1 (972) 393-2533 +1 (408) 944-0800 +86 (755) 8302-7618 +82 (2) 3466-3000 +886 (2) 8751-0600 +65-6291-1318 +81-45-224-6616 +44 1635 524455 +33 (0) 1-6092-4190 + 64-6-378-9799 Fax +1 (408) 474-1000 +1 (609) 546-0989 +1 (972) 393-2540 +1 (408) 914-7878 +86 (755) 8302-7637 +82 (2) 3466-2999 +886 (2) 8751-0746 +65-6291-1332 +81-45-224-6716 +44 1635 524466 +33 (0) 1-6092-4189 + 64-6-378-9599 June 2005 3 M9999-063005 Micrel KS8893M/ML/MI Revision History Revision 1.0 Date 6/30/05 Summary of Changes Initial release June 2005 4 M9999-063005 Micrel KS8893M/ML/MI Contents General Description................................................................................................................................1 Functional Diagram ................................................................................................................................1 Features ...................................................................................................................................................2 Applications ............................................................................................................................................2 Ordering Information ..............................................................................................................................3 Contacts ..................................................................................................................................................3 Revision History......................................................................................................................................4 Contents ..................................................................................................................................................5 List of Figures .........................................................................................................................................9 List of Tables.........................................................................................................................................10 Pin Description and I/O Assignment...................................................................................................11 Pin Configuration..................................................................................................................................20 Functional Description .........................................................................................................................21 Functional Overview: Physical Layer Transceiver ............................................................................21 100BASE-TX Transmit.........................................................................................................................................................21 100BASE-TX Receive ..........................................................................................................................................................21 PLL Clock Synthesizer........................................................................................................................................................22 Scrambler/De-scrambler (100BASE-TX Only) ...................................................................................................................22 100BASE-FX Operation.......................................................................................................................................................22 100BASE-FX Signal Detection............................................................................................................................................22 100BASE-FX Far-End Fault.................................................................................................................................................22 10BASE-T Transmit .............................................................................................................................................................23 10BASE-T Receive ..............................................................................................................................................................23 Power Management.............................................................................................................................................................23 MDI/MDI-X Auto Crossover.................................................................................................................................................23 Straight Cable ................................................................................................................................................................24 Crossover Cable ............................................................................................................................................................25 Auto-Negotiation .................................................................................................................................................................25 LinkMD Cable Diagnostics .................................................................................................................................................27 Access ...........................................................................................................................................................................27 Usage ............................................................................................................................................................................27 Functional Overview: MAC and Switch ..............................................................................................28 Address Lookup ..................................................................................................................................................................28 Learning ...............................................................................................................................................................................28 Migration ..............................................................................................................................................................................28 Aging ....................................................................................................................................................................................28 Forwarding...........................................................................................................................................................................28 Switching Engine ................................................................................................................................................................31 MAC Operation ....................................................................................................................................................................31 Inter Packet Gap (IPG) ..................................................................................................................................................31 Back-Off Algorithm.........................................................................................................................................................31 Late Collision .................................................................................................................................................................31 Illegal Frames ................................................................................................................................................................31 Full Duplex Flow Control................................................................................................................................................31 Half-Duplex Backpressure .............................................................................................................................................31 Broadcast Storm Protection ...........................................................................................................................................32 MII Interface Operation........................................................................................................................................................32 RMII Interface Operation .....................................................................................................................................................33 SNI (7-Wire) Operation ........................................................................................................................................................34 MII Management Interface (MIIM) .......................................................................................................................................35 Serial Management Interface (SMI) ....................................................................................................................................36 Advanced Switch Functions ................................................................................................................37 Spanning Tree Support.......................................................................................................................................................37 Special Tagging Mode.........................................................................................................................................................38 IGMP Support ......................................................................................................................................................................39 IGMP Snooping .............................................................................................................................................................39 Multicast Address Insertion in the Static MAC Table .....................................................................................................39 June 2005 5 M9999-063005 Micrel KS8893M/ML/MI IPv6 MLD Snooping.............................................................................................................................................................39 Port Mirroring Support........................................................................................................................................................40 IEEE 802.1Q VLAN Support ................................................................................................................................................40 QoS Priority Support...........................................................................................................................................................41 Port-Based Priority..............................................................................................................................................................41 802.1p-Based Priority..........................................................................................................................................................41 DiffServ-Based Priority .......................................................................................................................................................42 Rate Limiting Support .........................................................................................................................................................42 Unicast MAC Address Filtering..........................................................................................................................................42 Configuration Interface .......................................................................................................................................................43 I2C Master Serial Bus Configuration ..............................................................................................................................43 I2C Slave Serial Bus Configuration ................................................................................................................................44 SPI Slave Serial Bus Configuration ...............................................................................................................................44 Loopback Support...............................................................................................................................................................47 Far-end Loopback..........................................................................................................................................................47 Near-end (Remote) Loopback .......................................................................................................................................48 MII Management (MIIM) Registers .......................................................................................................49 PHY1 Register 0 (PHYAD = 0x1, REGAD = 0x0): MII Basic Control .........................................................................50 PHY2 Register 0 (PHYAD = 0x2, REGAD = 0x0): MII Basic Control .........................................................................50 PHY1 Register 1 (PHYAD = 0x1, REGAD = 0x1): MII Basic Status ...........................................................................51 PHY2 Register 1 (PHYAD = 0x2, REGAD = 0x1): MII Basic Status ...........................................................................51 PHY1 Register 2 (PHYAD = 0x1, REGAD = 0x2): PHYID High ..................................................................................51 PHY2 Register 2 (PHYAD = 0x2, REGAD = 0x2): PHYID High ..................................................................................51 PHY1 Register 3 (PHYAD = 0x1, REGAD = 0x3): PHYID Low ...................................................................................51 PHY2 Register 3 (PHYAD = 0x2, REGAD = 0x3): PHYID Low ...................................................................................51 PHY1 Register 4 (PHYAD = 0x1, REGAD = 0x4): Auto-Negotiation Advertisement Ability ...................................52 PHY2 Register 4 (PHYAD = 0x2, REGAD = 0x4): Auto-Negotiation Advertisement Ability ...................................52 PHY1 Register 5 (PHYAD = 0x1, REGAD = 0x5): Auto-Negotiation Link Partner Ability .......................................52 PHY2 Register 5 (PHYAD = 0x2, REGAD = 0x5): Auto-Negotiation Link Partner Ability .......................................52 PHY1 Register 29 (PHYAD = 0x1, REGAD = 0x1D): LinkMD Control/Status ...........................................................53 PHY2 Register 29 (PHYAD = 0x2, REGAD = 0x1D): LinkMD Control/Status ...........................................................53 PHY1 Register 31 (PHYAD = 0x1, REGAD = 0x1F): PHY Special Control/Status ...................................................53 PHY2 Register 31 (PHYAD = 0x2, REGAD = 0x1F): PHY Special Control/Status ...................................................53 Register Map: Switch & PHY (8-bit registers) ....................................................................................54 Global Registers ............................................................................................................................................................54 Port Registers ................................................................................................................................................................54 Advanced Control Registers ..........................................................................................................................................54 Global Registers..................................................................................................................................................................54 Register 0 (0x00): Chip ID0 ...........................................................................................................................................54 Register 1 (0x01): Chip ID1 / Start Switch .....................................................................................................................55 Register 2 (0x02): Global Control 0 ...............................................................................................................................55 Register 3 (0x03): Global Control 1 ...............................................................................................................................56 Register 4 (0x04): Global Control 2 ...............................................................................................................................56 Register 4 (0x04): Global Control 2 (continued).............................................................................................................57 Register 5 (0x05): Global Control 3 ...............................................................................................................................57 Register 5 (0x05): Global Control 3 (continued).............................................................................................................58 Register 6 (0x06): Global Control 4 ...............................................................................................................................58 Register 6 (0x06): Global Control 4 (continued).............................................................................................................59 Register 7 (0x07): Global Control 5 ...............................................................................................................................59 Register 8 (0x08): Global Control 6 ...............................................................................................................................59 Register 9 (0x09): Global Control 7 ...............................................................................................................................59 Register 10 (0x0A): Global Control 8 .............................................................................................................................59 Register 11 (0x0B): Global Control 9 .............................................................................................................................60 Register 12 (0x0C): Global Control 10...........................................................................................................................60 Register 13 (0x0D): Global Control 11...........................................................................................................................61 Register 14 (0x0E): Global Control 12 ...........................................................................................................................61 Register 15 (0x0F): Global Control 13 ...........................................................................................................................61 Port Registers......................................................................................................................................................................62 Register 16 (0x10): Port 1 Control 0 ..............................................................................................................................62 Register 32 (0x20): Port 2 Control 0 ..............................................................................................................................62 Register 48 (0x30): Port 3 Control 0 ..............................................................................................................................62 Register 17 (0x11): Port 1 Control 1 ..............................................................................................................................63 June 2005 6 M9999-063005 Micrel KS8893M/ML/MI Register 33 (0x21): Port 2 Control 1 ..............................................................................................................................63 Register 49 (0x31): Port 3 Control 1 ..............................................................................................................................63 Register 18 (0x12): Port 1 Control 2 ..............................................................................................................................64 Register 34 (0x22): Port 2 Control 2 ..............................................................................................................................64 Register 50 (0x32): Port 3 Control 2 ..............................................................................................................................64 Register 19 (0x13): Port 1 Control 3 ..............................................................................................................................65 Register 35 (0x23): Port 2 Control 3 ..............................................................................................................................65 Register 51 (0x33): Port 3 Control 3 ..............................................................................................................................65 Register 20 (0x14): Port 1 Control 4 ..............................................................................................................................65 Register 36 (0x24): Port 2 Control 4 ..............................................................................................................................65 Register 52 (0x34): Port 3 Control 4 ..............................................................................................................................65 Register 21 (0x15): Port 1 Control 5 ..............................................................................................................................65 Register 37 (0x25): Port 2 Control 5 ..............................................................................................................................65 Register 53 (0x35): Port 3 Control 5 ..............................................................................................................................65 Register 22 (0x16): Port 1 Control 6 ..............................................................................................................................66 Register 38 (0x26): Port 2 Control 6 ..............................................................................................................................66 Register 54 (0x36): Port 3 Control 6 ..............................................................................................................................66 Register 23 (0x17): Port 1 Control 7 ..............................................................................................................................67 Register 39 (0x27): Port 2 Control 7 ..............................................................................................................................67 Register 55 (0x37): Port 3 Control 7 ..............................................................................................................................67 Register 24 (0x18): Port 1 Control 8 ..............................................................................................................................68 Register 40 (0x28): Port 2 Control 8 ..............................................................................................................................68 Register 56 (0x38): Port 3 Control 8 ..............................................................................................................................68 Register 25 (0x19): Port 1 Control 9 ..............................................................................................................................69 Register 41 (0x29): Port 2 Control 9 ..............................................................................................................................69 Register 57 (0x39): Port 3 Control 9 ..............................................................................................................................69 Register 26 (0x1A): Port 1 PHY Special Control/Status.................................................................................................70 Register 42 (0x2A): Port 2 PHY Special Control/Status.................................................................................................70 Register 58 (0x3A): Reserved, not applied to port 3 ......................................................................................................70 Register 27 (0x1B): Port 1 LinkMD Result .....................................................................................................................70 Register 43 (0x2B): Port 2 LinkMD Result .....................................................................................................................70 Register 59 (0x3B): Reserved, not applied to port 3 ......................................................................................................70 Register 28 (0x1C): Port 1 Control 12............................................................................................................................71 Register 44 (0x2C): Port 2 Control 12............................................................................................................................71 Register 60 (0x3C): Reserved, not applied to port 3......................................................................................................71 Register 29 (0x1D): Port 1 Control 13............................................................................................................................72 Register 45 (0x2D): Port 2 Control 13............................................................................................................................72 Register 61 (0x3D): Reserved, not applied to port 3......................................................................................................72 Register 30 (0x1E): Port 1 Status 0 ...............................................................................................................................73 Register 46 (0x2E): Port 2 Status 0 ...............................................................................................................................73 Register 62 (0x3E): Reserved, not applied to port 3 ......................................................................................................73 Register 31 (0x1F): Port 1 Status 1 ...............................................................................................................................73 Register 47 (0x2F): Port 2 Status 1 ...............................................................................................................................73 Register 63 (0x3F): Port 3 Status 1 ...............................................................................................................................73 Register 31 (0x1F): Port 1 Status 1 (continued).............................................................................................................74 Register 47 (0x2F): Port 2 Status 1 (continued).............................................................................................................74 Register 63 (0x3F): Port 3 Status 1 (continued).............................................................................................................74 Register 96 (0x60): TOS Priority Control Register 0 ......................................................................................................74 Register 97 (0x61): TOS Priority Control Register 1 ......................................................................................................75 Register 98 (0x62): TOS Priority Control Register 2 ......................................................................................................75 Register 99 (0x63): TOS Priority Control Register 3 ......................................................................................................76 Register 100 (0x64): TOS Priority Control Register 4 ....................................................................................................76 Register 101 (0x65): TOS Priority Control Register 5 ....................................................................................................77 Register 102 (0x66): TOS Priority Control Register 6 ....................................................................................................77 Register 103 (0x67): TOS Priority Control Register 7 ....................................................................................................78 Register 104 (0x68): TOS Priority Control Register 8 ....................................................................................................78 Register 105 (0x69): TOS Priority Control Register 9 ....................................................................................................79 Register 106 (0x6A): TOS Priority Control Register 10..................................................................................................79 Register 107 (0x6B): TOS Priority Control Register 11..................................................................................................80 Register 108 (0x6C): TOS Priority Control Register 12 .................................................................................................80 Register 109 (0x6D): TOS Priority Control Register 13 .................................................................................................81 Register 110 (0x6E): TOS Priority Control Register 14..................................................................................................81 June 2005 7 M9999-063005 Micrel KS8893M/ML/MI Absolute Maximum Ratings(1) ..............................................................................................................92 Operating Ratings(1) ..............................................................................................................................92 Electrical Characteristics(1) ..................................................................................................................93 Timing Specifications...........................................................................................................................95 EEPROM Timing ..................................................................................................................................................................95 SNI Timing............................................................................................................................................................................96 MII Timing.............................................................................................................................................................................97 MAC Mode MII Timing ...................................................................................................................................................97 PHY Mode MII Timing....................................................................................................................................................98 RMII Timing ..........................................................................................................................................................................99 SPI Timing..........................................................................................................................................................................100 Input Timing .................................................................................................................................................................100 Output Timing ..............................................................................................................................................................101 Auto-Negotiation Timing...................................................................................................................................................102 Register 111 (0x6F): TOS Priority Control Register 15..................................................................................................82 Register 112 (0x70): MAC Address Register 0 ..............................................................................................................82 Register 113 (0x71): MAC Address Register 1 ..............................................................................................................82 Register 114 (0x72): MAC Address Register 2 ..............................................................................................................82 Register 115 (0x73): MAC Address Register 3 ..............................................................................................................82 Register 116 (0x74): MAC Address Register 4 ..............................................................................................................82 Register 117 (0x75): MAC Address Register 5 ..............................................................................................................82 Register 118 (0x76): User Defined Register 1 ...............................................................................................................83 Register 119 (0x77): User Defined Register 2 ...............................................................................................................83 Register 120 (0x78): User Defined Register 3 ...............................................................................................................83 Register 121 (0x79): Indirect Access Control 0..............................................................................................................83 Register 122 (0x7A): Indirect Access Control 1 .............................................................................................................83 Register 123 (0x7B): Indirect Data Register 8 ...............................................................................................................83 Register 124 (0x7C): Indirect Data Register 7 ...............................................................................................................84 Register 125 (0x7D): Indirect Data Register 6 ...............................................................................................................84 Register 126 (0x7E): Indirect Data Register 5 ...............................................................................................................84 Register 127 (0x7F): Indirect Data Register 4................................................................................................................84 Register 128 (0x80): Indirect Data Register 3................................................................................................................84 Register 129 (0x81): Indirect Data Register 2................................................................................................................84 Register 130 (0x82): Indirect Data Register 1................................................................................................................84 Register 131 (0x83): Indirect Data Register 0................................................................................................................84 Register 132 (0x84): Digital Testing Status 0.................................................................................................................84 Register 133 (0x85): Digital Testing Control 0 ...............................................................................................................85 Register 134 (0x86): Analog Testing Control 0 ..............................................................................................................85 Register 135 (0x87): Analog Testing Control 1 ..............................................................................................................85 Register 136 (0x88): Analog Testing Control 2 ..............................................................................................................85 Register 137 (0x89): Analog Testing Control 3 ..............................................................................................................85 Register 138 (0x8A): Analog Testing Status ..................................................................................................................85 Register 139 (0x8B): Analog Testing Control 4..............................................................................................................85 Register 140 (0x8C): QM Debug 1 ................................................................................................................................85 Register 141 (0x8D): QM Debug 2 ................................................................................................................................85 Static MAC Address Table.............................................................................................................................................86 VLAN Table ...................................................................................................................................................................87 Dynamic MAC Address Table........................................................................................................................................88 MIB (Management Information Base) Counters.............................................................................................................89 Additional MIB Counter Information ...............................................................................................................................91 Reset Timing .......................................................................................................................................103 Reset Circuit........................................................................................................................................104 Selection of Isolation Transformers..................................................................................................105 Selection of Reference Crystal ..........................................................................................................105 Package Information...........................................................................................................................106 June 2005 8 M9999-063005 Micrel KS8893M/ML/MI List of Figures Figure 1. Typical Straight Cable Connection ......................................................................................................................................24 Figure 2. Typical Crossover Cable Connection ..................................................................................................................................25 Figure 3. Auto-Negotiation and Parallel Operation ............................................................................................................................26 Figure 4. Destination Address Lookup Flow Chart, Stage 1 .............................................................................................................29 Figure 5. Destination Address Resolution Flow Chart, Stage 2 .......................................................................................................30 Figure 6. 802.1p Priority Field Format .................................................................................................................................................41 Figure 7. KS8893M EEPROM Configuration Timing Diagram ...........................................................................................................43 Figure 8. SPI Write Data Cycle..............................................................................................................................................................45 Figure 9. SPI Read Data Cycle ..............................................................................................................................................................46 Figure 10. SPI Multiple Write.................................................................................................................................................................46 Figure 11. SPI Multiple Read.................................................................................................................................................................46 Figure 12: Far-End Loopback Path ......................................................................................................................................................47 Figure 13. Near-end (Remote) Loopback Path....................................................................................................................................48 Figure 14. EEPROM Interface Input Timing Diagram .........................................................................................................................95 Figure 15. EEPROM Interface Output Timing Diagram ......................................................................................................................95 Figure 16. SNI Input Timing Diagram...................................................................................................................................................96 Figure 17. SNI Output Timing Diagram................................................................................................................................................96 Figure 18. MAC Mode MII Timing – Data Received from MII..............................................................................................................97 Figure 19. MAC Mode MII Timing – Data Input to MII .........................................................................................................................97 Figure 20. PHY Mode MII Timing – Data Received from MII ..............................................................................................................98 Figure 21. PHY Mode MII Timing – Data Input to MII ..........................................................................................................................98 Figure 22: RMII Timing – Data Received from RMII............................................................................................................................99 Figure 23: RMII Timing – Data Input to RMII........................................................................................................................................99 Figure 24. SPI Input Timing.................................................................................................................................................................100 Figure 25. SPI Output Timing..............................................................................................................................................................101 Figure 26: Auto-Negotiation Timing...................................................................................................................................................102 Figure 27. Reset Timing ......................................................................................................................................................................103 Figure 28. Recommended Reset Circuit............................................................................................................................................104 Figure 29. Recommended Reset Circuit for interfacing with CPU/FPGA Reset Output...............................................................104 Figure 30. 128-Pin PQFP Package......................................................................................................................................................106 June 2005 9 M9999-063005 Micrel KS8893M/ML/MI List of Tables Table 1. FX and TX Mode Selection .....................................................................................................................................................22 Table 2. MDI/MDI-X Pin Definitions.......................................................................................................................................................23 Table 3. MII Signals ................................................................................................................................................................................32 Table 4: RMII Signal Description ..........................................................................................................................................................33 Table 5: RMII Signal Connections ........................................................................................................................................................34 Table 6. SNI Signals...............................................................................................................................................................................34 Table 7. MII Management Interface Frame Format .............................................................................................................................35 Table 8. Serial Management Interface (SMI) Frame Format...............................................................................................................36 Table 9: Spanning Tree States..............................................................................................................................................................37 Table 10. Special Tagging Mode Format .............................................................................................................................................38 Table 11. STPID Egress Rules (Processor to Switch Port 3)..............................................................................................................38 Table 12. STPID Egress Rules (Switch Port 3 to Processor).............................................................................................................39 Table 13. FID+DA Lookup in VLAN Mode ............................................................................................................................................40 Table 14. FID+SA Lookup in VLAN Mode ............................................................................................................................................41 Table 15. KS8893M SPI Connections...................................................................................................................................................45 Table 16. Format of Static MAC Table (8 Entries)...............................................................................................................................86 Table 17. Format of Static VLAN Table (16 Entries) ...........................................................................................................................87 Table 18. Format of Dynamic MAC Address Table (1K Entries) .......................................................................................................88 Table 19. Format of “Per Port” MIB Counters.....................................................................................................................................89 Table 20. Port 1’s “Per Port” MIB Counters Indirect Memory Offsets..............................................................................................90 Table 21. Format of “All Port Dropped Packet” MIB Counters .........................................................................................................90 Table 22. “All Port Dropped Packet” MIB Counters Indirect Memory Offsets ................................................................................90 Table 23. EEPROM Timing Parameters ...............................................................................................................................................95 Table 24. SNI Timing Parameters .........................................................................................................................................................96 Table 25. MAC Mode MII Timing Parameters ......................................................................................................................................97 Table 26. PHY Mode MII Timing Parameters .......................................................................................................................................98 Table 27: RMII Timing Parameters .......................................................................................................................................................99 Table 28. SPI Input Timing Parameters .............................................................................................................................................100 Table 29. SPI Output Timing Parameters ..........................................................................................................................................101 Table 30: Auto-Negotiation Timing Parameters ...............................................................................................................................102 Table 31. Reset Timing Parameters ...................................................................................................................................................103 Table 32. Transformer Selection Criteria...........................................................................................................................................105 Table 33. Qualified Single Port Magnetics ........................................................................................................................................105 Table 34. Typical Reference Crystal Characteristics .......................................................................................................................105 June 2005 10 M9999-063005 Micrel KS8893M/ML/MI Pin Description and I/O Assignment Pin Number 1 2 3 Pin Name P1LED2 P1LED1 P1LED0 Type (1) Ipu/O Ipu/O Ipu/O P1LED3 P1LED2 P1LED1 P1LED0 Description Port 1 LED Indicators (apply to all modes of operation, except Repeater Mode) [LEDSEL1, LEDSEL0] [0, 0] — Link/Act Full duplex/Col Speed [0, 1] — 100Link/Act 10Link/Act Full duplex [LEDSEL1, LEDSEL0] [1, 0] P1LED3 P1LED2 P1LED1 P1LED0 Act Link Full duplex/Col Speed [1, 1] — — — — Link/Act, 100Link/Act, 10Link/Act : Low (link), High (no link), Toggle (transmit / receive activity) Full duplex/Col : Low (full duplex), High (half duplex), Toggles (collision) Speed : Low (100BASE-TX), High (10BASE-T) Full duplex : Low (full duplex), High (half duplex) Act : Toggle (transmit / receive activity) Link : Low (link), High (no link) Repeater Mode (only) [LEDSEL1, LEDSEL0] [0, 0] P1LED3 P1LED2 P1LED1 P1LED0 RPT_COL RPT_LINK3/RX RPT_LINK2/RX RPT_LINK1/RX RPT_COL : Low (collision) RPT_LINK#/RX (# = port) : Low (link), High (no link), Toggles (receive activity) Notes: LEDSEL0 is external strap-in pin 70. LEDSEL1 is external strap-in pin 23. P1LED3 is pin 25. During reset, P1LED[2:0] are inputs for internal testing. Note: 1. Ipu/O = Input with internal pull-up during reset, output pin otherwise. June 2005 11 M9999-063005 Micrel KS8893M/ML/MI Pin Number 4 5 6 Pin Name P2LED2 P2LED1 P2LED0 Type (1) Ipu/O Ipu/O Ipu/O Description Port 2 LED Indicators (apply to all modes of operation, except Repeater Mode) [LEDSEL1, LEDSEL0] [0, 0] P2LED3 P2LED2 P2LED1 P2LED0 — Link/Act Full duplex/Col Speed [0, 1] — 100Link/Act 10Link/Act Full duplex [LEDSEL1, LEDSEL0] [1, 0] P2LED3 P2LED2 P2LED1 P2LED0 Act Link Full duplex/Col Speed [1, 1] — — — — Link/Act, 100Link/Act, 10Link/Act : Low (link), High (no link), Toggle (transmit / receive activity) Full duplex/Col : Low (full duplex), High (half duplex), Toggles (collision) Speed : Low (100BASE-TX), High (10BASE-T) Full duplex : Low (full duplex), High (half duplex) Act : Toggle (transmit / receive activity) Link : Low (link), High (no link) Repeater Mode (only) [LEDSEL1, LEDSEL0] [0, 0] P2LED3 P2LED2 P2LED1 P2LED0 RPT_ACT RPT_ERR3 RPT_ERR2 RPT_ERR1 RPT_ACT : Low (activity) RPT_ERR# (# = port) : Low (error status due to either isolation, partition, jabber, or JK error) 7 8 DGND VDDIO Gnd P Notes: LEDSEL0 is external strap-in pin 70. LEDSEL1 is external strap-in pin 23. P2LED3 is pin 20. During reset, P2LED[2:0] are inputs for internal testing. Digital ground 3.3V digital VDD Note: 1. P = Power supply. Gnd = Ground. Ipd = Input w/ internal pull-down. Ipu/O = Input with internal pull-up during reset, output pin otherwise. June 2005 12 M9999-063005 Micrel KS8893M/ML/MI Pin Number 9 10 11 12 Pin Name NC NC NC ADVFC Type (1) Ipd Ipd Ipu Ipu Description No connect No connect No connect 1 = advertise the switch’s flow control capability via auto negotiation. 0 = will not advertise the switch’s flow control capability via auto negotiation. 13 14 15 P2ANEN P2SPD P2DPX Ipu Ipd Ipd 1 = enable auto negotiation on port 2 0 = disable auto negotiation on port 2 1 = force port 2 to 100BT if P2ANEN = 0 0 = force port 2 to 10BT if P2ANEN = 0 1 = port 2 default to full duplex mode if P2ANEN = 1 and auto negotiation fails. Force port 2 in full duplex mode if P2ANEN = 0. 0 = port 2 default to half duplex mode if P2ANEN = 1 and auto negotiation fails. Force port 2 in half duplex mode if P2ANEN = 0. 16 P2FFC Ipd 1 = always enable (force) port 2 flow control feature 0 = port 2 flow control feature enable is determined by auto negotiation result. 17 18 19 20 NC NC NC P2LED3 Opu Ipd Ipd Opd No connect No connect No connect Port 2 LED indicator Note: Internal pull-down is weak; it will not turn ON the LED. See description in pin 4. 21 22 DGND VDDC / VOUT_1V2 Gnd P Digital ground VDDC: For KS8893M, this is an input power pin for the 1.2V digital core VDD. VOUT_1V2: For KS8893ML, this is a 1.2V output power pin to supply the KS8893ML’s input power pins: VDDAP (pin 63), VDDC (pins 91 and 123), and VDDA (pins 38, 43, and 57). 23 24 25 LEDSEL1 NC P1LED3 Ipd O Opd LED display mode select See description in pins 1 and 4. No connect Port 1 LED indicator Note: An external 1K pull-down is needed on this pin if it is connected to a LED. The 1K resistor will not turn ON the LED. See description in pin 1. Note: 1. P = Power supply. Gnd = Ground. O = Output. Ipu = Input w/ internal pull-up. Ipd = Input w/ internal pull-down. Opu = Output w/ internal pull-up. Opd = Output w/ internal pull-down. June 2005 13 M9999-063005 Micrel KS8893M/ML/MI Pin Number 26 Pin Name RMII_EN Type (1) Opd Description Strap pin for RMII Mode 0 = Disable 1 = Enable After reset, this pin has no meaning and is a no connect. 27 HWPOVR Ipd Hardware pin overwrite 0 = Disable. All strap-in pins configurations are overwritten by the EEPROM configuration data 1 = Enable. All strap-in pins configurations are overwritten by the EEPROM configuration data, except for register 0x2C bits [7:5], (port 2: auto-negotiation enable, force speed, force duplex). 28 P2MDIXDIS Ipd Port 2 Auto MDI/MDI-X PD (default) = enable PU = disable 29 P2MDIX Ipd Port 2 MDI/MDI-X setting when auto MDI/MDI-X is disabled. PD (default) = MDI-X (transmit on TXP2 / TXM2 pins) PU = MDI, (transmit on RXP2 / RXM2 pins) 30 31 32 P1ANEN P1SPD P1DPX Ipu Ipd Ipd 1 = enable auto negotiation on port 1 0 = disable auto negotiation on port 1 1 = force port 1 to 100BT if P1ANEN = 0 0 = force port 1 to 10BT if P1ANEN = 0 1 = port 1 default to full duplex mode if P1ANEN = 1 and auto negotiation fails. Force port 1 in full-duplex mode if P1ANEN = 0. 0 = port 1 default to half duplex mode if P1ANEN = 1 and auto negotiation fails. Force port 1 in half duplex mode if P1ANEN = 0. 33 P1FFC Ipd 1 = always enable (force) port 1 flow control feature 0 = port 1 flow control feature enable is determined by auto negotiation result. 34 35 36 37 38 39 40 41 Note: 1. P = Power supply. Gnd = Ground. I = Input. NC NC PWRDN AGND VDDA AGND MUX1 MUX2 Ipd Ipd Ipu Gnd P Gnd I I No connect No connect Chip power down input (active low) Analog ground 1.2V analog VDD Analog ground Factory test pin - float for normal operation Factory test pin - float for normal operation Ipu = Input w/ internal pull-up. Ipd = Input w/ internal pull-down. Opd = Output w/ internal pull-down. June 2005 14 M9999-063005 Micrel KS8893M/ML/MI Pin Number 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 Pin Name AGND VDDA FXSD1 RXP1 RXM1 AGND TXP1 TXM1 VDDATX VDDARX RXM2 RXP2 AGND TXM2 TXP2 VDDA AGND TEST1 TEST2 ISET AGND VDDAP AGND X1 X2 Type (1) Gnd P I I/O I/O Gnd I/O I/O P P I/O I/O Gnd I/O I/O P Gnd I I O Gnd P Gnd I O Description Analog ground 1.2V analog VDD Fiber signal detect / factory test pin Physical receive or transmit signal (+ differential) Physical receive or transmit signal (– differential) Analog ground Physical transmit or receive signal (+ differential) Physical transmit or receive signal (– differential) 3.3V analog VDD 3.3V analog VDD Physical receive or transmit signal (– differential) Physical receive or transmit signal (+ differential) Analog ground. Physical transmit or receive signal (– differential) Physical transmit or receive signal (+ differential) 1.2V analog VDD Analog ground Factory test pin - float for normal operation Factory test pin - float for normal operation Set physical transmit output current. Pull-down this pin with a 3.01K 1% resistor to ground. Analog ground 1.2V analog VDD for PLL Analog ground. 25MHz crystal/oscillator clock connections Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a 3.3V tolerant oscillator and X2 is a no connect. Note: Clock is +/- 50ppm for both crystal and oscillator. Hardware reset pin (active low) Unused pin – externally pull down for normal operation Unused pin – externally pull down for normal operation 67 68 69 Note: 1. P = Power supply. Gnd = Ground. I = Input. O = Output. I/O = Bi-directional. RST_N UNUSED UNUSED Ipu I I Ipu = Input w/ internal pull-up. June 2005 15 M9999-063005 Micrel KS8893M/ML/MI Pin Number 70 71 72 73 74 75 76 77 Pin Name LEDSEL0 SMTXEN SMTXD3 SMTXD2 SMTXD1 SMTXD0 SMTXER SMTXC / REFCLK Type (1) I I I I I I I I/O Description LED display mode select See description in pins 1 and 4. Switch MII transmit enable Switch MII transmit data bit 3 Switch MII transmit data bit 2 Switch MII transmit data bit 1 Switch MII transmit data bit 0 Switch MII transmit error Switch MII transmit clock (MII and SNI modes only) Output in PHY MII mode and SNI mode Input in MAC MII mode Reference Clock (RMII mode only) Input for 50MHz +/- 50ppm system clock Note: In RMII mode, pin X1 is pulled up to VDDIO supply with a 10K resistor and pin X2 is a no connect. 78 79 80 DGND VDDIO SMRXC Gnd P I/O Digital ground 3.3V digital VDD Switch MII receive clock. Output in PHY MII mode Input in MAC MII mode 81 82 SMRXDV SMRXD3 O Ipd/O Switch MII receive data valid Switch MII receive data bit 3 Strap option: switch MII full-duplex flow control PD (default) = disable PU = enable 83 SMRXD2 Ipd/O Switch MII receive data bit 2 Strap option: switch MII is in PD (default) = full-duplex mode PU = half-duplex mode 84 SMRXD1 Ipd/O Switch MII receive data bit 1 Strap option: Switch MII is in PD (default) = 100Mbps mode PU = 10Mbps mode 85 SMRXD0 I/O Switch MII receive data bit 0 Strap option: switch will accept packet size up to PD = 1536 bytes (inclusive) PU = 1522 bytes (tagged), 1518 bytes (untagged) 86 87 SCOL SCRS I/O I/O Switch MII collision detect Switch MII carrier sense Note: 1. P = Power supply. Gnd = Ground. I = Input. O = Output. Ipd/O = Input w/ internal pull-down during reset, output pin otherwise. I/O = Bi-directional. June 2005 16 M9999-063005 Micrel KS8893M/ML/MI Pin Number 88 89 Pin Name SCONF1 SCONF0 Type (1) I I Description Switch MII interface configuration (SCONF1, SCONF0) (0,0) (0,1) (1,0) (1,1) Description disable, outputs tri-stated PHY mode MII MAC mode MII PHY mode SNI 90 91 92 93 94 95 DGND VDDC UNUSED UNUSED MDC MDIO Gnd P I I I I/O Digital ground 1.2V digital VDD Unused pins – externally pull down for normal operation MII management interface: clock input MII management interface: data input/output Note: an external pull-up is needed on this pin when it is in use. 96 SPIQ O SPI slave mode: serial data output See description in pins 100 and 101. Note: an external pull-up is needed on this pin when it is in use. 97 SCL I/O SPI slave mode / I C slave mode: clock input I C master mode: clock output See description in pins 100 and 101. 2 2 98 SDA I/O SPI slave mode: serial data input I2C master/slave mode: serial data input/output See description in pins 100 and 101. Note: an external pull-up is needed on this pin when it is in use. 99 SPIS_N I SPI slave mode: chip select (active low) When SPIS_N is high, the KS8893M is deselected and SPIQ is held in high impedance state. A high-to-low transition is used to initiate SPI data transfer. See description in pins 100 and 101. Note: an external pull-up is needed on this pin when it is in use. Note: 1. P = Power supply. Gnd = Ground. I = Input. O = Output. I/O = Bi-directional. June 2005 17 M9999-063005 Micrel KS8893M/ML/MI Pin Number 100 101 Pin Name PS1 PS0 Type (1) I I Description Serial bus configuration pins to select mode of access to KS8893M internal registers. [PS1, PS0] = [0, 0] — I2C master (EEPROM) mode (If EEPROM is not detected, the KS8893M will be configured with the default values of its internal registers and the values of its strap-in pins.) Interface Signals SPIQ SCL SDA SPIS_N Type O O I/O I Description Not used (tri-stated) I C clock I C data I/O Not used 2 2 [PS1, PS0] = [0, 1] — I2C slave mode 2 The external I C master will drive the SCL clock. The KS8893M device addresses are: 1011_1111 1011_1110 SPIQ SCL SDA SPIS_N Type O I I/O I Description Not used (tri-stated) I C clock I C data I/O Not used 2 2 Interface Signals [PS1, PS0] = [1, 0] — SPI slave mode Interface Signals SPIQ SCL SDA SPIS_N Type O I I I Description SPI data out SPI clock SPI data In SPI chip select [PS1, PS0] = [1, 1] – SMI-mode In this mode, the KS8893M provides access to all its internal 8-bit registers through its MDC and MDIO pins. Note: When (PS1, PS0) ≠ (1,1), the KS8893M provides access to its 16-bit MIIM registers through its MDC and MDIO pins. 102 103 Note: 1. I = Input. UNUSED UNUSED I I Unused pins – externally pull up for normal operation June 2005 18 M9999-063005 Micrel KS8893M/ML/MI Pin Number 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Note: 1. P = Power supply. Gnd = Ground. I = Input. Pin Name UNUSED UNUSED DGND VDDIO UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED DGND VDDC UNUSED UNUSED UNUSED TESTEN SCANEN Type (1) I I Gnd P I I I I I I I I I I I I I I Gnd P I I I Ipd Ipd Description Unused pins – externally pull up for normal operation Digital ground 3.3V digital VDD Unused pins – externally pull up for normal operation Unused pin – externally pull down for normal operation Unused pin – externally pull down for normal operation Unused pin – externally pull down for normal operation Unused pin – externally pull down for normal operation Unused pin – externally pull down for normal operation Unused pin – externally pull down for normal operation Unused pin – externally pull down for normal operation Unused pin – externally pull down for normal operation Unused pin – externally pull down for normal operation Unused pin – externally pull down for normal operation Unused pin – externally pull down for normal operation Unused pin – externally pull down for normal operation Digital ground 1.2V digital VDD Unused pin – externally pull down for normal operation Unused pin – externally pull down for normal operation Unused pin – externally pull down for normal operation Scan Test Enable For normal operation, pull-down this pin to ground. Scan Test Scan Mux Enable For normal operation, pull-down this pin to ground. Ipd = Input w/ internal pull-down. June 2005 19 M9999-063005 Micrel Pin Configuration June 2005 UNUSED UNUSED UNUSED DGND VDDIO UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED DGND VDDC UNUSED UNUSED UNUSED TESTEN SCANEN 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 128-Pin PQFP (Top View) 20 P1LED2 P1LED1 P1LED0 P2LED2 P2LED1 P2LED0 DGND VDDIO NC NC NC ADVFC P2ANEN P2SPD P2DPX P2FFC NC NC NC P2LED3 DGND VDDC LEDSEL1 NC P1LED3 RMII_EN HWPOVR P2MDIXDIS P2MDIX P1ANEN P1SPD P1DPX P1FFC NC NC PWRDN AGND VDDA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 AGND VDDAP AGND ISET TEST2 TEST1 AGND VDDA TXP2 TXM2 AGND RXP2 RXM2 VDDARX VDDATX TXM1 TXP1 AGND RXM1 RXP1 FXSD1 VDDA AGND MUX2 MUX1 AGND 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 UNUSED PS0 PS1 SPIS_N SDA SCL SPIQ MDIO MDC UNUSED UNUSED VDDC DGND SCONF0 SCONF1 SCRS SCOL SMRXD0 SMRXD1 SMRXD2 SMRXD3 SMRXDV SMRXC VDDIO DGND SMTXC / REFCLK SMTXER SMTXD0 SMTXD1 SMTXD2 SMTXD3 SMTXEN LEDSEL0 UNUSED UNUSED RST_N X2 X1 KS8893M/ML/MI M9999-063005 Micrel KS8893M/ML/MI Functional Description The KS8893M contains two 10/100 physical layer transceivers and three MAC units with an integrated Layer 2 managed switch. The KS8893M has the flexibility to reside in either a managed or unmanaged design. In a managed design, the host processor has complete control of the KS8893M via the SMI interface, MIIM interface, SPI bus, or I2C bus. An unmanaged design is achieved through I/O strapping and/or EEPROM programming at system reset time. On the media side, the KS8893M supports IEEE 802.3 10BASE-T and 100BASE-TX on both PHY ports, and also 100BASE-FX on PHY port 1, which allows the KS8893M to be used as a media converter. The KS8893ML is the single supply version with all the identical rich features of the KS8893M. In the KS8893ML version, pin number 22 provides 1.2V output power to the KS8893ML’s VDDC, VDDA, and VDDAP power pins. Refer to the Pin Description table for information about pin 22 (Pin Description and I/0 Assignment). Physical signal transmission and reception are enhanced through the use of patented analog circuitries that make the design more efficient and allow for lower power consumption and smaller chip die size. Functional Overview: Physical Layer Transceiver 100BASE-TX Transmit The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-toNRZI conversion, and MLT3 encoding and transmission. The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output current is set by an external1% 3.01KΩ resistor for the 1:1 transformer ratio. The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output is also incorporated into the 100BASE-TX transmitter. 100BASE-TX Receive The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion. The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, and then tunes itself for optimization. This is an ongoing process and self-adjusts against environmental changes such as temperature variations. Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is used to compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive. The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/5B decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC. June 2005 21 M9999-063005 Micrel KS8893M/ML/MI PLL Clock Synthesizer The KS8893M generates 125MHz, 31.25MHz, 25MHz, and 10MHz clocks for system timing. Internal clocks are generated from an external 25MHz crystal or oscillator. In RMII mode, these internal clocks are generated from an external 50MHz oscillator or system clock. Scrambler/De-scrambler (100BASE-TX Only) The purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference (EMI) and baseline wander. Transmitted data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). The scrambler generates a 2047-bit non-repetitive sequence, and the receiver then de-scrambles the incoming data stream using the same sequence as at the transmitter. 100BASE-FX Operation 100BASE-FX operation is similar to 100BASE-TX operation with the differences being that the scrambler/descrambler and MLT3 encoder/decoder are bypassed on transmission and reception. In addition, auto negotiation is bypassed and auto MDI/MDI-X is disabled. 100BASE-FX Signal Detection In 100BASE-FX operation, FXSD1 (fiber signal detect), input pin 44, is usually connected to the fiber transceiver SD (signal detect) output pin. 100BASE-FX mode is activated when the FXSD1 input pin is greater than 1V. When FXSD1 is between 1V and 1.8V, no fiber signal is detected and a far-end fault (FEF) is generated. When FXSD1 is over 2.2V, the fiber signal is detected. Alternatively, the designer may choose not to implement the FEF feature. In this case, the FXSD1 input pin is tied high to force 100BASE-FX mode. 100BASE-FX signal detection is summarized in the following table: FXSD1 Input Voltage Less than 0.2V Greater than 1V, but less than 1.8V Mode TX mode FX mode No signal detected. Far-end fault generated Greater than 2.2V FX mode Signal detected Table 1. FX and TX Mode Selection To ensure proper operation, a resistive voltage divider is recommended to adjust the fiber transceiver SD output voltage swing to match the FXSD1 pin’s input voltage threshold. 100BASE-FX Far-End Fault A far-end fault (FEF) occurs when the signal detection is logically false on the receive side of the fiber transceiver. The KS8893M detects a FEF when its FXSD1 input is between 1V and 1.8V. When a FEF is detected, the KS8893M signals its fiber link partner that a FEF has occurred by sending 84 1’s followed by a zero in the idle period between frames. By default, FEF is enabled. FEF can be disabled through register setting. June 2005 22 M9999-063005 Micrel 10BASE-T Transmit KS8893M/ML/MI The 10BASE-T driver is incorporated with the 100BASE-TX driver to allow for transmission using the same magnetics. They are internally wave-shaped and pre-emphasized into outputs with a typical 2.3V amplitude. The harmonic contents are at least 27dB below the fundamental frequency when driven by an all-ones Manchesterencoded signal. 10BASE-T Receive On the receive side, input buffers and level detecting squelch circuits are employed. A differential input receiver circuit and a phase-locked loop (PLL) perform the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400mV or with short pulse widths to prevent noise at the RXP-or-RXM input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KS8893M decodes a data frame. The receiver clock is maintained active during idle periods in between data reception. Power Management The KS8893M features a per-port power down mode. To save power, a PHY port that is not in use can be powered down via port control register, or MII PHY register. In addition, there is a full chip power down mode. When activated, the entire chip will be powered down. MDI/MDI-X Auto Crossover To eliminate the need for crossover cables between similar devices, the KS8893M supports HP Auto MDI/MDI-X and IEEE 802.3u standard MDI/MDI-X auto crossover. HP Auto MDI/MDI-X is the default. The auto-sense function detects remote transmit and receive pairs and correctly assigns transmit and receive pairs for the KS8893M device. This feature is extremely useful when end users are unaware of cable types, and also, saves on an additional uplink configuration connection. The auto-crossover feature can be disabled through the port control registers, or MII PHY registers. The IEEE 802.3u standard MDI and MDI-X definitions are: MDI RJ-45 Pins 1 2 3 6 Signals TD+ TDRD+ RDRJ-45 Pins 1 2 3 6 MDI-X Signals RD+ RDTD+ TD- Table 2. MDI/MDI-X Pin Definitions June 2005 23 M9999-063005 Micrel KS8893M/ML/MI Straight Cable A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. The following diagram depicts a typical straight cable connection between a NIC card (MDI) and a switch, or hub (MDI-X). 10/100 Ethernet Media Dependent Interface 10/100 Ethernet Media Dependent Interface 1 Transmit Pair 2 3 4 Receive Pair 5 6 7 8 Straight Cable 1 Receive Pair 2 3 4 Transmit Pair 5 6 7 8 Modular Connector (RJ-45) NIC Modular Connector (RJ-45) HUB (Repeater or Switch) Figure 1. Typical Straight Cable Connection June 2005 24 M9999-063005 Micrel KS8893M/ML/MI Crossover Cable A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device. The following diagram shows a typical crossover cable connection between two switches or hubs (two MDI-X devices). 10/100 Ethernet Media Dependent Interface 10/100 Ethernet Media Dependent Interface 1 Receive Pair 2 3 4 Transmit Pair 5 6 7 8 Crossover Cable 1 Receive Pair 2 3 4 Transmit Pair 5 6 7 8 Modular Connector (RJ-45) HUB (Repeater or Switch) Modular Connector (RJ-45) HUB (Repeater or Switch) Figure 2. Typical Crossover Cable Connection Auto-Negotiation The KS8893M conforms to the auto negotiation protocol, defined in Clause 28 of the IEEE 802.3u specification. Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the best common mode of operation. In auto-negotiation, link partners advertise their capabilities across the link to each other. If auto-negotiation is not supported or the KS8893M link partner is forced to bypass auto-negotiation, the KS8893M sets its operating mode by observing the signal at its receiver. This is known as parallel detection, and allows the KS8893M to establish link by listening for a fixed signal protocol in the absence of auto-negotiation advertisement protocol. The link up process is shown in the following flow diagram. June 2005 25 M9999-063005 Micrel KS8893M/ML/MI Start Auto Negotiation Force Link Setting N o Parallel Operation Yes Bypass Auto Negotiation and Set Link Mode Attempt Auto Negotiation Listen for 100BASE-TX Idles Listen for 10BASE-T Link Pulses No Join Flow Link Mode Set ? Yes Link Mode Set Figure 3. Auto-Negotiation and Parallel Operation June 2005 26 M9999-063005 Micrel KS8893M/ML/MI LinkMD Cable Diagnostics The LinkMD feature utilizes time domain reflectometry (TDR) to analyze the cabling plant for common cabling problems such as open circuits, short circuits and impedance mismatches. LinkMD works by sending a pulse of known amplitude and duration down the MDI and MDI-X pairs and then analyzes the shape of the reflected signal. Timing the pulse duration gives an indication of the distance to the cabling fault with maximum distance of 200m and accuracy of +/- 2m. Internal circuitry displays the TDR information in a user-readable digital format. Note: Cable diagnostics are only valid for copper connections and do not support fiber optic operation. Access LinkMD is initiated by accessing registers {26,27} and {42,43}, the LinkMD Control/Status registers, for ports 1 and 2, respectively; and in conjunction with registers 29 and 45, Port Control Register 13, for ports 1 and 2, respectively. Alternatively, the MIIM PHY registers 0 and 29 can be used for LinkMD access. Usage The following is a sample procedure for using LinkMD with registers {26,27,29} on port 1. 1. Disable auto MDI/MDI-X by writing a ‘1’ to register 29, bit [2] to enable manual control over the differential pair used to transmit the LinkMD pulse. 2. Start cable diagnostic test by writing a ‘1’ to register 26, bit [4]. This enable bit is self-clearing. 3. Wait (poll) for register 26, bit [4] to return a ‘0’, indicating cable diagnostic test is completed. 4. Read cable diagnostic test results in register 26, bits [6:5]. The results are as follows: 00 = normal condition (valid test) 01 = open condition detected in cable (valid test) 10 = short condition detected in cable (valid test) 11 = cable diagnostic test failed (invalid test) The ‘11’ case, invalid test, occurs when the KS8893M is unable to shut down the link partner. In this instance, the test is not run, since it would be impossible for the KS8893M to determine if the detected signal is a reflection of the signal generated or a signal from another source. 5. Get distance to fault by concatenating register 26, bit [0] and register 27, bits [7:0]; and multiplying the result by a constant of 0.4. The distance to the cable fault can be determined by the following formula: D (distance to cable fault) = 0.4 x {(register 26, bit [0]),(register 27, bits [7:0])} D (distance to cable fault) is expressed in meters. Concatenated value of registers 26 and 27 is converted to decimal before multiplying by 0.4. The constant (0.4) may be calibrated for different cabling conditions, including cables with a velocity of propagation that varies significantly from the norm. For port 2 and for the MIIM PHY registers, LinkMD usage is similar. June 2005 27 M9999-063005 Micrel KS8893M/ML/MI Functional Overview: MAC and Switch Address Lookup The internal lookup table stores MAC addresses and their associated information. It contains a 1K unicast address table plus switching information. The KS8893M is guaranteed to learn 1K addresses and distinguishes itself from hash-based lookup tables, which depending on the operating environment and probabilities, may not guarantee the absolute number of addresses it can learn. Learning The internal lookup engine updates its table with a new entry if the following conditions are met: 1. The received packet's Source Address (SA) does not exist in the lookup table. 2. The received packet is good; the packet has no receiving errors, and is of legal length. The lookup engine inserts the qualified SA into the table, along with the port number and time stamp. If the table is full, the last entry of the table is deleted to make room for the new entry. Migration The internal lookup engine also monitors whether a station has moved. If a station has moved, it will update the table accordingly. Migration happens when the following conditions are met: 1. The received packet's SA is in the table but the associated source port information is different. 2. The received packet is good; the packet has no receiving errors, and is of legal length. The lookup engine will update the existing record in the table with the new source port information. Aging The lookup engine updates the time stamp information of a record whenever the corresponding SA appears. The time stamp is used in the aging process. If a record is not updated for a period of time, the lookup engine removes the record from the table. The lookup engine constantly performs the aging process and will continuously remove aging records. The aging period is about 200 seconds. This feature can be enabled or disabled through register 3 (0x03) bit [2]. Forwarding The KS8893M forwards packets using the algorithm that is depicted in the following flowcharts. Figure 4 shows stage one of the forwarding algorithm where the search engine looks up the VLAN ID, static table, and dynamic table for the destination address, and comes up with “port to forward 1” (PTF1). PTF1 is then further modified by spanning tree, IGMP snooping, port mirroring, and port VLAN processes to come up with “port to forward 2” (PTF2), as shown in Figure 5. The packet is sent to PTF2. June 2005 28 M9999-063005 Micrel KS8893M/ML/MI Start PTF1= NULL NO VLAN ID Valid? - Search VLAN table - Ingress VLAN filtering - Discard NPVID check YES Search complete. Get PTF1 from Static MAC Table FOUND Search Static Table This search is based on DA or DA+FID NOT FOUND Search complete. Get PTF1 from Dynamic MAC Table FOUND Dynamic Table Search This search is based on DA+FID NOT FOUND Search complete. Get PTF1 from VLAN Table PTF1 Figure 4. Destination Address Lookup Flow Chart, Stage 1 June 2005 29 M9999-063005 Micrel KS8893M/ML/MI PTF1 Spanning Tree Process - Check receiving port's receive enable bit - Check destination port's transmit enable bit - Check whether packets are special (BPDU or specified) IGMP Process - Applied to MAC #1 and MAC #2 - MAC #3 is reserved for microprocessor - IGMP will be forwarded to port 3 Port Mirror Process - RX Mirror TX Mirror RX or TX Mirror RX and TX Mirror Port VLAN Membership Check PTF2 Figure 5. Destination Address Resolution Flow Chart, Stage 2 The KS8893M will not forward the following packets: 1. Error packets These include framing errors, Frame Check Sequence (FCS) errors, alignment errors, and illegal size packet errors. 2. IEEE802.3x PAUSE frames KS8893M intercepts these packets and performs full duplex flow control accordingly. 3. "Local" packets Based on destination address (DA) lookup. If the destination port from the lookup table matches the port from which the packet originated, the packet is defined as "local." June 2005 30 M9999-063005 Micrel Switching Engine KS8893M/ML/MI The KS8893M features a high-performance switching engine to move data to and from the MACs’ packet buffers. It operates in store and forward mode, while the efficient switching mechanism reduces overall latency. The switching engine has a 32kB internal frame buffer. This buffer pool is shared between all three ports. There are a total of 256 buffers available. Each buffer is sized at 128 bytes. MAC Operation The KS8893M strictly abides by IEEE 802.3 standards to maximize compatibility. Inter Packet Gap (IPG) If a frame is successfully transmitted, the 96 bits time IPG is measured between the two consecutive MTXEN. If the current packet is experiencing collision, the 96 bits time IPG is measured from MCRS and the next MTXEN. Back-Off Algorithm The KS8893M implements the IEEE 802.3 standard for the binary exponential back-off algorithm, and optional "aggressive mode" back-off. After 16 collisions, the packet is optionally dropped depending on the switch configuration for register 4 (0x04) bit [3]. Late Collision If a transmit packet experiences collisions after 512 bit times of the transmission, the packet is dropped. Illegal Frames The KS8893M discards frames less than 64 bytes, and can be programmed to accept frames up to1518 bytes, 1536 bytes or 1916 bytes. These maximum frame size settings are programmed in register 4 (0x04). Since the KS8893M supports VLAN tags, the maximum sizing is adjusted when these tags are present. Full Duplex Flow Control The KS8893M supports standard IEEE 802.3x flow control frames on both transmit and receive sides. On the receive side, if the KS8893M receives a pause control frame, the KS8893M will not transmit the next normal frame until the timer, specified in the pause control frame, expires. If another pause frame is received before the current timer expires, the timer will be updated with the new value in the second pause frame. During this period (while it is flow controlled), only flow control packets from the KS8893M are transmitted. On the transmit side, the KS8893M has intelligent and efficient ways to determine when to invoke flow control. The flow control is based on availability of the system resources, including available buffers, available transmit queues and available receive queues. The KS8893M will flow control a port that has just received a packet if the destination port resource is busy. The KS8893M issues a flow control frame (XOFF), containing the maximum pause time defined by the IEEE 802.3x standard. Once the resource is freed up, the KS8893M sends out the other flow control frame (XON) with zero pause time to turn off the flow control (turn on transmission to the port). A hysteresis feature is provided to prevent the flow control mechanism from being constantly activated and deactivated. The KS8893M flow controls all ports if the receive queue becomes full. Half-Duplex Backpressure A half-duplex backpressure option (not in IEEE 802.3 standards) is also provided. The activation and deactivation conditions are the same as full duplex flow control. If backpressure is required, the KS8893M sends preambles to defer the other stations' transmission (carrier sense deference). To avoid jabber and excessive deference (as defined in the 802.3 standard), after a certain time, the KS8893M discontinues the carrier sense and then raises it again quickly. This short silent time (no carrier sense) prevents other stations from sending out packets thus keeping other stations in a carrier sense deferred state. If the port has packets to send during a backpressure situation, the carrier sense type backpressure is interrupted and those packets are transmitted instead. If there are no additional packets to send, carrier sense type backpressure is June 2005 31 M9999-063005 Micrel KS8893M/ML/MI reactivated again until switch resources free up. If a collision occurs, the binary exponential back-off algorithm is skipped and carrier sense is generated immediately, thus reducing the chance of further collisions and carrier sense is maintained to prevent packet reception. To ensure no packet loss in 10 BASE-T or 100 BASE-TX half duplex modes, the user must enable the following: 1. Aggressive back-off (register 3 (0x03), bit [0]) 2. No excessive collision drop (register 4 (0x04), bit [3]) Note: These bits are not set as defaults as this is not the IEEE standard. Broadcast Storm Protection The KS8893M has an intelligent option to protect the switch system from receiving too many broadcast packets. As the broadcast packets are forwarded to all ports except the source port, an excessive number of switch resources (bandwidth and available space in transmit queues) may be utilized. The KS8893M has the option to include “multicast packets” for storm control. The broadcast storm rate parameters are programmed globally, and can be enabled or disabled on a per port basis. The rate is based on a 67ms interval for 100BT and a 500ms interval for 10BT. At the beginning of each interval, the counter is cleared to zero, and the rate limit mechanism starts to count the number of bytes during the interval. The rate definition is described in register 6 (0x06) and 7 (0x07). The default setting is 0x63 (99 decimal). This is equal to a rate of 1%, calculated as follows: 148,800 frames/sec * 67ms/interval * 1% = 99 frames/interval (approx.) = 0x63 Note: 148,800 frames/sec is based on 64-byte block of packets in 100BASE-TX with 12 bytes of IPG and 8 bytes of preamble between two packets. MII Interface Operation The Media Independent Interface (MII) is specified in Clause 22 of the IEEE 802.3u Standard. It provides a common interface between physical layer and MAC layer devices. The MII provided by the KS8893M is connected to the device’s third MAC. The interface contains two distinct groups of signals: one for transmission and the other for reception. The following table describes the signals used by the MII bus. KS8893M PHY-Mode Connections External MAC Controller Signals MTXEN MTXER MTXD3 MTXD2 MTXD1 MTXD0 MTXC MCOL MCRS MRXDV MRXER MRXD3 MRXD2 MRXD1 MRXD0 MRXC KS8893M PHY Signals SMTXEN SMTXER SMTXD[3] SMTXD[2] SMTXD[1] SMTXD[0] SMTXC SCOL SCRS SMRXDV (not used) SMRXD[3] SMRXD[2] SMRXD[1] SMRXD[0] SMRXC Pin Descriptions Transmit enable Transmit error Transmit data bit 3 Transmit data bit 2 Transmit data bit 1 Transmit data bit 0 Transmit clock Collision detection Carrier sense Receive data valid Receive error Receive data bit 3 Receive data bit 2 Receive data bit 1 Receive data bit 0 Receive clock Table 3. MII Signals KS8893M MAC-Mode Connections External PHY Signals MTXEN MTXER MTXD3 MTXD2 MTXD1 MTXD0 MTXC MCOL MCRS MRXDV MRXER MRXD3 MRXD2 MRXD1 MRXD0 MRXC KS8893M MAC Signals SMRXDV (not used) SMRXD[3] SMRXD[2] SMRXD[1] SMRXD[0] SMRXC SCOL SCRS SMTXEN SMTXER SMTXD[3] SMTXD[2] SMTXD[1] SMTXD[0] SMTXC June 2005 32 M9999-063005 Micrel KS8893M/ML/MI The MII operates in either PHY mode or MAC mode. The data interface is a nibble wide and runs at ¼ the network bit rate (not encoded). Additional signals on the transmit side indicate when data is valid or when an error occurs during transmission. Similarly, the receive side has signals that convey when the data is valid and without physical layer errors. For half duplex operation, the SCOL signal indicates if a collision has occurred during transmission. The KS8893M does not provide the MRXER signal for PHY mode operation and the MTXER signal for MAC mode operation. Normally, MRXER indicates a receive error coming from the physical layer device and MTXER indicates a transmit error from the MAC device. Since the switch filters error frames, these MII error signals are not used by the KS8893M. So, for PHY mode operation, if the device interfacing with the KS8893M has an MRXER input pin, it needs to be tied low. And, for MAC mode operation, if the device interfacing with the KS8893M has an MTXER input pin, it also needs to be tied low. RMII Interface Operation The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). RMII provides a common interface between physical layer and MAC layer devices, is fully compliant with the IEEE 802.3u Standard, and has the following key characteristics: 1. 2. 3. 4. Supports 10Mbps and 100Mbps data rates. Uses a single 50 MHz clock reference (provided externally). Provides independent 2-bit wide (di-bit) transmit and receive data paths. Contains two distinct groups of signals: one for transmission and the other for reception The RMII provided by the KS8893M is connected to the device’s third MAC. It complies with the RMII Specification. The following table describes the signals used by the RMII bus. Refer to RMII Specification for full detail on the signal description. Direction (with respect to the PHY) Input Output Output Output Input Input Input Output Direction (with respect to the MAC) Input or Output Input Input Input Output Output Output Input (not required) --- RMII Signal Name REF_CLK CRS_DV RXD1 RXD0 TX_EN TXD1 TXD0 RX_ER RMII Signal Description Synchronous 50 MHz clock reference for receive, transmit and control interface Carrier sense/ Receive data valid Receive data bit 1 Receive data bit 0 Transmit enable Transmit data bit 1 Transmit data bit 0 Receive error KS8893M RMII Signal (direction) REFCLK (input) SMRXDV (output) SMRXD[1] (output) SMRXD[0] (output) SMTXEN (input) SMTXD[1] (input) SMTXD[0] (input) (not used) SMTXER* (input) --- --- --- * Connects to RX_ER signal of RMII PHY device Table 4: RMII Signal Description June 2005 33 M9999-063005 Micrel KS8893M/ML/MI The KS8893M filters error frames, and thus does not implement the RX_ER output signal. To detect error frames from RMII PHY devices, the SMTXER input signal of the KS8893M is connected to the RXER output signal of the RMII PHY device. Collision detection is implemented in accordance with the RMII Specification. In RMII mode, tie MII signals, SMTXD[3:2] and SMTXER, to ground if they are not used. The KS8893M RMII can interface with RMII PHY and RMII MAC devices. The latter allows two KS8893M devices to be connected back-to-back. The following table shows the KS8893M RMII pin connections with an external RMII PHY and an external RMII MAC, such as another KS8893M device. KS8893M PHY-MAC Connections External KS8893M PHY Signals MAC Signals REF_CLK REFCLK TX_EN TXD1 TXD0 CRS_DV RXD1 RXD0 RX_ER SMRXDV SMRXD[1] SMRXD[0] SMTXEN SMTXD[1] SMTXD[0] SMTXER Pin Descriptions Reference Clock Carrier sense/ Receive data valid Receive data bit 1 Receive data bit 0 Transmit enable Transmit data bit 1 Transmit data bit 0 Receive error KS8893M MAC-MAC Connections KS8893M External MAC Signals MAC Signals REFCLK REF_CLK SMRXDV SMRXD[1] SMRXD[0] SMTXEN SMTXD[1] SMTXD[0] (not used) TX_EN TXD1 TXD0 CRS_DV RXD1 RXD0 (not used) Table 5: RMII Signal Connections SNI (7-Wire) Operation The serial network interface (SNI) or 7-wire is compatible with some controllers used for network layer protocol processing. In SNI mode, the KS8893M acts like a PHY and the external controller functions as the MAC. The KS8893M can interface directly with external controllers using the 7-wire interface. These signals are divided into two groups, one for transmission and the other for reception. The signals involved are described in the following table. Pin Descriptions Transmit enable Serial transmit data Transmit clock Collision detection Carrier sense Serial receive data Receive clock External MAC Controller Signals TXEN TXD TXC COL CRS RXD RXC Table 6. SNI Signals KS8893M PHY Signals SMTXEN SMTXD[0] SMTXC SCOL SMRXDV SMRXD[0] SMRXC June 2005 34 M9999-063005 Micrel KS8893M/ML/MI The SNI interface is a bit wide data interface and therefore runs at the network bit rate (not encoded). An additional signal on the transmit side indicates when data is valid. Similarly, the receive side has an indicator that conveys when the data is valid. For half duplex operation, the KS8893M’s SCOL signal is used to indicate that a collision has occurred during transmission. MII Management Interface (MIIM) The KS8893M supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the states of the KS8893M. An external device with MDC/MDIO capability is used to read the PHY status or configure the PHY settings. Further detail on the MIIM interface is found in Clause 22.2.4.5 of the IEEE 802.3u Specification. The MIIM interface consists of the following: A physical connection that incorporates the data line (MDIO) and the clock line (MDC). A specific protocol that operates across the aforementioned physical connection that allows an external controller to communicate with the KS8893M device. Access to a set of eight 16-bit registers, consisting of six standard MIIM registers [0:5] and two custom MIIM registers [29, 31]. The following table depicts the MII Management Interface frame format. Preamble Start of Frame Read/Write OP Code 10 01 PHY Address Bits [4:0] Read Write 32 1’s 32 1’s 01 01 AAAAA AAAAA REG Address Bits [4:0] RRRRR RRRRR Z0 10 DDDDDDDD_DDDDDDDD DDDDDDDD_DDDDDDDD Z Z TA Data Bits [15:0] Idle Table 7. MII Management Interface Frame Format June 2005 35 M9999-063005 Micrel KS8893M/ML/MI Serial Management Interface (SMI) The SMI is the KS8893M non-standard MIIM interface that provides access to all KS8893M configuration registers. This interface allows an external device to completely monitor and control the states of the KS8893M. The SMI interface consists of the following: A physical connection that incorporates the data line (MDIO) and the clock line (MDC). A specific protocol that operates across the aforementioned physical connection that allows an external controller to communicate with the KS8893M device. Access to all KS8893M configuration registers. Register access includes the Global, Port and Advanced Control Registers 0-141 (0x00 – 0x8D), and indirect access to the standard MIIM registers [0:5] and custom MIIM registers [29, 31]. The following table depicts the SMI frame format. Preamble Start of Frame Read/Write OP Code 00 00 PHY Address Bits [4:0] Read Write 32 1’s 32 1’s 01 01 1xRRR 0xRRR REG Address Bits [4:0] RRRRR RRRRR Z0 10 0000_0000_DDDD_DDDD xxxx_xxxx_DDDD_DDDD Z Z TA Data Bits [15:0] Idle Table 8. Serial Management Interface (SMI) Frame Format SMI register read access is selected when OP Code is set to “00” and bit 4 of the PHY address is set to ‘1’. SMI register write access is selected when OP Code is set to “00” and bit 4 of the PHY address is set to ‘0’. PHY address bit[3] is undefined for SMI register access, and hence can be set to either ‘0’ or ‘1’ in read/write operations. To access the KS8893M registers 0-141 (0x00 – 0x8D), the following applies: PHYAD[2:0] and REGAD[4:0] are concatenated to form the 8-bit address; that is, {PHYAD[2:0], REGAD[4:0]} = bits [7:0] of the 8-bit address. Registers are 8 data bits wide. For read operation, data bits [15:8] are read back as 0’s. For write operation, data bits [15:8] are not defined, and hence can be set to either ‘0’ or ‘1’. SMI register access is the same as the MIIM register access, except for the register access requirements presented in this section. June 2005 36 M9999-063005 Micrel KS8893M/ML/MI Advanced Switch Functions Spanning Tree Support To support spanning tree, port 3 is the designated port for the processor. The other ports (port 1 and port 2) can be configured in one of the five spanning tree states via “transmit enable”, “receive enable” and “learning disable” register settings in registers 18 and 34 for ports 1 and 2, respectively. The following table shows the port setting and software actions taken for each of the five spanning tree states. Disable State The port should not forward or receive any packets. Learning is disabled. Blocking State Only packets to the processor are forwarded. Learning is disabled. Listening State Only packets to and from the processor are forwarded. Learning is disabled. Learning State Only packets to and from the processor are forwarded. Learning is enabled. Forwarding State Packets are forwarded and received normally. Learning is enabled. Port Setting Software Action The processor should not send any packets to the port. The switch may still send specific packets to the processor (packets that match some entries in the “static MAC table” with “overriding bit” set) and the processor should discard those packets. Address learning is disabled on the port in this state. Software Action The processor should not send any packets to the port(s) in this state. The processor should program the “Static MAC table” with the entries that it needs to receive (for example, BPDU packets). The “overriding” bit should also be set so that the switch will forward those specific packets to the processor. Address learning is disabled on the port in this state. Software Action The processor should program the “Static MAC table” with the entries that it needs to receive (for example, BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state. See “Special Tagging Mode” for details. Address learning is disabled on the port in this state. Software Action The processor should program the “Static MAC table” with the entries that it needs to receive (for example, BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state. See “Special Tagging Mode” for details. Address learning is enabled on the port in this state. Software Action The processor programs the “Static MAC table” with the entries that it needs to receive (for example, BPDU packets). The “overriding” bit is set so that the switch forwards those specific packets to the processor. The processor can send packets to the port(s) in this state. See “Special Tagging Mode” for details. Address learning is enabled on the port in this state. Table 9: Spanning Tree States “transmit enable = 0, receive enable = 0, learning disable =1” Port Setting “transmit enable = 0, receive enable = 0, learning disable =1” Port Setting “transmit enable = 0, receive enable = 0, learning disable =1” Port Setting “transmit enable = 0, receive enable = 0, learning disable = 0” Port Setting “transmit enable = 1, receive enable = 1, learning disable = 0” June 2005 37 M9999-063005 Micrel KS8893M/ML/MI Special Tagging Mode Special Tagging Mode is designed for spanning tree protocol IGMP snooping and is flexible for use in other applications. Special Tagging, similar to 802.1Q Tagging, requires software to change network drivers to insert/modify/strip/interpret the special tag. This mode is enabled by setting both register 11 bit [0] and register 48 bit [2] to ‘1’. 802.1Q Tag Format TPID (tag protocol identifier, 0x8100) + TCI. Special Tag Format STPID (special tag identifier, 0x810 + 4 bit for “port mask”) + TCI Table 10. Special Tagging Mode Format The STPID is only seen and used by the port 3 interface, which should be connected to a processor. Packets from the processor to the switch’s port 3 should be tagged with the STPID and the port mask, defined as follows: “0001”, forward packet to port 1 only “0010”, forward packet to port 2 only “0011”, broadcast packet to port 1 and port 2 Packets with normal tags (“0000” port masks) will use KS8893M internal MAC table lookup to determine the forwarding port(s). Also, if packets from the processor are not tagged, the KS8893M will treat them as normal packets and use internal MAC table lookup to determine the forwarding port(s). The KS8893M uses a non-zero “port mask” to bypass the internal MAC table lookup result, and override any port setting, regardless of port states (disable, blocking, listening, learning). The table below shows the processor to switch egress rules when dealing with STPID. Ingress Tag Field TX port “tag insertion” TX port “tag removal” Egress Action to Tag Field - Modify tag field to 0x8100 (0x810+ port mask) 0 0 - Recalculate CRC - No change to TCI if not null VID - Replace VID with ingress (port 3) port VID if null VID - (STPID + TCI) will be removed (0x810+ port mask) 0 1 - Padding to 64 bytes if necessary - Recalculate CRC - Modify tag field to 0x8100 (0x810+ port mask) 1 0 - Recalculate CRC - No change to TCI if not null VID - Replace VID with ingress (port 3) port VID if null VID - Modify tag field to 0x8100 (0x810+ port mask) 1 1 - Recalculate CRC - No change to TCI if not null VID - Replace VID with ingress (port 3) port VID if null VID Not Tagged Don’t care Don’t care - Determined by the Dynamic MAC Address Table Table 11. STPID Egress Rules (Processor to Switch Port 3) June 2005 38 M9999-063005 Micrel KS8893M/ML/MI For packets from regular ports (port 1 & port 2) to port 3, the port mask is used to tell the processor which port the packets were received on, defined as follows: “0001”, packet from port 1 “0010”, packet from port 2 No port mask values, other than the previous two defined ones, should be received in this direction in Special Tagging Mode. The switch to processor egress rules are defined as follows: Ingress Packets Egress Action to Tag Field - Modify TPID to 0x810 + “port mask”, which indicates source port. Tagged with 0x8100 + TCI - No change to TCI if VID is not null - Replace null VID with ingress port VID - Recalculate CRC - Insert TPID to 0x810 + “port mask”, which indicates source port Not tagged. - Insert TCI with ingress port VID - Recalculate CRC Table 12. STPID Egress Rules (Switch Port 3 to Processor) IGMP Support For Internet Group Management Protocol (IGMP) support in layer 2, the KS8893M provides two components: IGMP Snooping The KS8893M traps IGMP packets and forwards them only to the processor (port 3). The IGMP packets are identified as IP packets (either Ethernet IP packets, or IEEE 802.3 SNAP IP packets) with IP version = 0x4 and protocol version number = 0x2. Multicast Address Insertion in the Static MAC Table Once the multicast address is programmed in the Static MAC Table, the multicast session is trimmed to the subscribed ports, instead of broadcasting to all ports. To enable IGMP support, set register 5 bit [6] to ‘1’. Also, Special Tagging Mode needs to be enabled, so that the processor knows which port the IGMP packet was received on. This is achieved by setting both register 11 bit [0] and register 48 bit [2] to ‘1’. IPv6 MLD Snooping The KS8893M traps IPv6 Multicast Listener Discovery (MLD) packets and forwards them only to the processor (port 3). MLD snooping is controlled by register 5 bit 5 (MLD snooping enable) and register 5 bit 4 (MLD option). With MLD snooping enabled, the KS8893M traps packets that meet all of the following conditions: • • • • IPv6 multicast packets Hop count limit = 1 IPv6 next header = 1 or 58 (or = 0 with hop-by-hop next header = 1 or 58) IPv6 next header = 43, 44, 50, 51, or 60 (or = 0 with hop-by-hop next header = 43, 44, 50, 51, or 60) If the MLD option bit is set to “1”, the KS8893M traps packets with the following additional condition: For MLD snooping, Special Tagging Mode also needs to be enabled, so that the processor knows which port the MLD packet was received on. This is achieved by setting both register 11 bit [0] and register 48 bit [2] to ‘1’. June 2005 39 M9999-063005 Micrel Port Mirroring Support KS8893M supports “Port Mirroring” comprehensively as: “receive only” mirror on a port KS8893M/ML/MI All the packets received on the port are mirrored on the sniffer port. For example, port 1 is programmed to be “receive sniff” and port 3 is programmed to be the “sniffer port”. A packet received on port 1 is destined to port 2 after the internal lookup. The KS8893M forwards the packet to both port 2 and port 3. The KS8893M can optionally even forward “bad” received packets to the “sniffer port”. “transmit only” mirror on a port All the packets transmitted on the port are mirrored on the sniffer port. For example, port 1 is programmed to be “transmit sniff” and port 3 is programmed to be the “sniffer port”. A packet received on port 2 is destined to port 1 after the internal lookup. The KS8893M forwards the packet to both port 1 and port 3. “receive and transmit” mirror on two ports All the packets received on port A and transmitted on port B are mirrored on the sniffer port. To turn on the “AND” feature, set register 5 bit [0] to ‘1’. For example, port 1 is programmed to be “receive sniff”, port 2 is programmed to be “transmit sniff”, and port 3 is programmed to be the “sniffer port”. A packet received on port 1 is destined to port 2 after the internal lookup. The KS8893M forwards the packet to both port 2 and port 3. Multiple ports can be selected as “receive sniff” or “transmit sniff”. In addition, any port can be selected as the “sniffer port”. All these per port features can be selected through registers 17, 33 and 49 for ports 1, 2 and 3, respectively. IEEE 802.1Q VLAN Support The KS8893M supports 16 active VLANs out of the 4096 possible VLANs specified in the IEEE 802.1Q specification. KS8893M provides a 16-entries VLAN Table, which converts the 12-bits VLAN ID (VID) to the 4-bits Filter ID (FID) for address lookup. If a non-tagged or null-VID-tagged packet is received, the ingress port default VID is used for lookup. In VLAN mode, the lookup process starts with VLAN Table lookup to determine whether the VID is valid. If the VID is not valid, the packet is dropped and its address is not learned. If the VID is valid, the FID is retrieved for further lookup. The FID + Destination Address (FID+DA) are used to determine the destination port. The FID + Source Address (FID+SA) are used for address learning. DA found in Static MAC Table? No No Yes Yes Yes Yes DA+FID found in Dynamic MAC Table? No Yes Don’t care No Yes Don’t care Use FID flag? FID match? Action Broadcast to the membership ports defined in the VLAN Table bits [18:16] Send to the destination port defined in the Dynamic MAC Address Table bits [53:52] Send to the destination port(s) defined in the Static MAC Address Table bits [50:48] Broadcast to the membership ports defined in the VLAN Table bits [18:16] Send to the destination port defined in the Dynamic MAC Address Table bits [53:52] Send to the destination port(s) defined in the Static MAC Address Table bits [50:48] Don’t care Don’t care 0 1 1 1 Don’t care Don’t care Don’t care No No Yes Table 13. FID+DA Lookup in VLAN Mode June 2005 40 M9999-063005 Micrel KS8893M/ML/MI FID+SA found in Dynamic MAC Table? No Yes Action Learn and add FID+SA to the Dynamic MAC Address Table Update time stamp Table 14. FID+SA Lookup in VLAN Mode Advanced VLAN features, such as “Ingress VLAN filtering” and “Discard Non PVID packets” are also supported by the KS8893M. These features can be set on a per port basis, and are defined in register 18, 34 and 50 for ports 1, 2 and 3, respectively. QoS Priority Support The KS8893M provides Quality of Service (QoS) for applications such as VoIP and video conferencing. Offering four priority queues per port, the per-port transmit queue can be split into four priority queues: Queue 3 is the highest priority queue and Queue 0 is the lowest priority queue. Bit [0] of registers 16, 32 and 48 is used to enable split transmit queues for ports 1, 2 and 3, respectively. If a port's transmit queue is not split, high priority and low priority packets have equal priority in the transmit queue. There is an additional option to either always deliver high priority packets first or use weighted fair queuing for the four priority queues. This global option is set and explained in bit [3] of register 5. Port-Based Priority With port-based priority, each ingress port is individually classified as a high priority receiving port. All packets received at the high priority receiving port are marked as high priority and are sent to the high-priority transmit queue if the corresponding transmit queue is split. Bits [4:3] of registers 16, 32 and 48 are used to enable portbased priority for ports 1, 2 and 3, respectively. 802.1p-Based Priority For 802.1p-based priority, the KS8893M examines the ingress (incoming) packets to determine whether they are tagged. If tagged, the 3-bit priority field in the VLAN tag is retrieved and compared against the “priority mapping” value, as specified by the registers 12 and 13. The “priority mapping” value is programmable. The following figure illustrates how the 802.1p priority field is embedded in the 802.1Q VLAN tag. Bytes 8 Preamble 6 DA 6 SA 2 VPID 2 TCI 2 length LLC 46-1500 Data 4 FCS Bits 802.1q VLAN Tag 16 Tagged Packet Type (8100 for Ethernet) 3 802.1p 1 CFI 12 VLAN ID Figure 6. 802.1p Priority Field Format June 2005 41 M9999-063005 Micrel KS8893M/ML/MI 802.1p-based priority is enabled by bit 5 of registers 16, 32 and 48 for ports 1, 2 and 3, respectively. The KS8893M provides the option to insert or remove the priority tagged frame's header at each individual egress port. This header, consisting of the 2 bytes VLAN Protocol ID (VPID) and the 2-byte Tag Control Information field (TCI), is also referred to as the IEEE 802.1Q VLAN tag. Tag Insertion is enabled by bit [2] of registers 16, 32 and 48 for ports 1, 2 and 3, respectively. At the egress port, untagged packets are tagged with the ingress port’s default tag. The default tags are programmed in register sets {19,20}, {35,36} and {51,52} for ports 1, 2 and 3, respectively. The KS8893M will not add tags to already tagged packets. Tag Removal is enabled by bit [1] of registers 16, 32 and 48 for ports 1, 2 and 3, respectively. At the egress port, tagged packets will have their 802.1Q VLAN Tags removed. The KS8893M will not modify untagged packets. The CRC is recalculated for both tag insertion and tag removal. 802.1p Priority Field Re-mapping is a QoS feature that allows the KS8893M to set the “User Priority Ceiling” at any ingress port. If the ingress packet’s priority field has a higher priority value than the default tag’s priority field of the ingress port, the packet’s priority field is replaced with the default tag’s priority field. The “User Priority Ceiling” is enabled by bit [3] of registers 17, 33 and 49 for ports 1, 2 and 3, respectively. DiffServ-Based Priority DiffServ-based priority uses the ToS registers (registers 96 to 111) in the Advanced Control Registers section. The ToS priority control registers implement a fully decoded, 64-bit Differentiated Services Code Point (DSCP) register to determine packet priority from the 6-bit ToS field in the IP header. When the most significant 6 bits of the ToS field are fully decoded, the resultant of the 64 possibilities is compared with the corresponding bits in the DSCP register to determine priority. Rate Limiting Support The KS8893M supports hardware rate limiting from 64 Kbps to 88 Mbps, independently on the “receive side” and on the “transmit side” on a per port basis. For 10BASE-T, a rate setting above 10 Mbps means the rate is not limited. On the receive side, the data receive rate for each priority at each port can be limited by setting up Ingress Rate Control Registers. On the transmit side, the data transmit rate for each priority queue at each port can be limited by setting up Egress Rate Control Registers. The size of each frame has options to include minimum IFG (Inter Frame Gap) or Preamble byte, in addition to the data field (from packet DA to FCS). For ingress rate limiting, KS8893M provides options to selectively choose frames from all types, multicast, broadcast, and flooded unicast frames. The KS8893M counts the data rate from those selected type of frames. Packets are dropped at the ingress port when the data rate exceeds the specified rate limit. For egress rate limiting, the Leaky Bucket algorithm is applied to each output priority queue for shaping output traffic. Inter frame gap is stretched on a per frame base to generate smooth, non-burst egress traffic. The throughput of each output priority queue is limited by the egress rate specified. If any egress queue receives more traffic than the specified egress rate throughput, packets may be accumulated in the output queue and packet memory. After the memory of the queue or the port is used up, packet dropping or flow control will be triggered. As a result of congestion, the actual egress rate may be dominated by flow control/dropping at the ingress end, and may be therefore slightly less than the specified egress rate. To reduce congestion, it is a good practice to make sure the egress bandwidth exceeds the ingress bandwidth. Unicast MAC Address Filtering The unicast MAC address filtering function works in conjunction with the static MAC address table. First, the static MAC address table is used to assign a dedicated MAC address to a specific port. If a unicast MAC address is not recorded in the static table, it is also not learned in the dynamic MAC table. The KS8893M is then configured with the option to either filter or forward unicast packets for an unknown MAC address. This option is enabled and configured in register 14. June 2005 42 M9999-063005 Micrel KS8893M/ML/MI This function is useful in preventing the broadcast of unicast packets that could degrade the quality of the port in applications such as voice over Internet Protocol (VoIP). Configuration Interface The KS8893M can operate as both a managed switch and an unmanaged switch. In unmanaged mode, the KS8893M is typically programmed using an EEPROM. If no EEPROM is present, the KS8893M is configured using its default register settings. Some defaults settings are configured via strap-in pin options. The strap-in pins are indicated in the “KS8893M Pin Description and I/O Assignment” table. I2C Master Serial Bus Configuration With an additional I2C (“2-wire”) EEPROM, the KS8893M can perform more advanced switch features like “broadcast storm protection” and “rate control” without the need of an external processor. For KS8893M I2C Master configuration, the EEPROM stores the configuration data for register 0 to register 120 (as defined in the KS8893M register map) with the exception of the “Read Only” status registers. After the deassertion of reset, the KS8893M sequentially reads in the configuration data for all 121 registers, starting from register 0. The configuration access time (tprgm) is less than 15 ms, as depicted in the following figure. RST_N SCL SDA .... .... .... tprgm