KS8995MA_11

KS8995MA/FQ Integrated 5-Port 10/100 Managed Switch Rev 2.9 General Description The KS8995MA/FQ is a highly integrated Layer 2 managed switch with optimized bill of materials (BOM) cost for low port count, cost-sensitive 10/100Mbps switch systems with both copper and optic fiber media. It also provides an extensive feature set such as tag/port-based VLAN, quality of service (QoS) priority, management, MIB counters, dual MII interfaces and CPU control/data interfaces to effectively address both current and emerging fast Ethernet applications. The KS8995MA/FQ contains five 10/100 transceivers with patented mixed-signal low-power technology, five media access control (MAC) units, a high-speed nonblocking switch fabric, a dedicated address lookup engine, and an on-chip frame buffer memory. All PHY units support 10BASE-T and 100BASE-TX. In addition, two of the PHY units support 100BASE-FX (KS8995MA is ports 4 and 5, KS8995FQ is port 3 and port 4). Functional Diagram Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com September 2008 M9999-091508 Micrel, Inc. KS8995MA/FQ Auto MDI/MDIX Auto MDI/MDIX Auto MDI/MDIX Auto MDI/MDIX Auto MDI/MDIX MII-P5 MDC, MDI/O MII- SW or SNI Control Reg I/F LED0[5:1] LED1[5:1] LED2[5:1] 10/100 T/Tx 1 10/100 T/Tx 2 10/100 T/Tx/Fx 3 10/100 T/Tx/Fx 4 10/100 T/Tx 5 10/100 MAC 1 10/100 MAC 2 10/100 MAC 3 10/100 MAC 4 10/100 MAC 5 SNI SPI 1K Look Up Engine FIFO, Flow Control, VLAN Tagging, Priority Queue Mgmnt Buffer Mgmnt Frame Buffers MIB Counters EEPROM I/F LED I/F Control Registers KSZ8995FQ Notes: 1. KS8995MA has either TX copper or FX fiber for port 4 and port 5, other ports are the TX copper only. 2. KS8995FQ has either TX copper or FX fiber for port 3 and port 4, other ports are the TX copper only. Semptember 2008 2 M9999-091508 Micrel, Inc. KS8995MA/FQ • Per-port based software power-save on PHY (idle link detection, register configuration preserved) • QoS/CoS packets prioritization supports: per port, 802.1p and DiffServ based • 802.1p/q tag insertion or removal on a per-port basis (egress) • MDC and MDI/O interface support to access the MII PHY control registers (not all control registers) • MII local loopback support • On-chip 64Kbyte memory for frame buffering (not shared with 1K unicast address table) • Wire-speed reception and transmission • Integrated look-up engine with dedicated 1K MAC addresses • Full duplex IEEE 802.3x and half-duplex back pressure flow control • Comprehensive LED support • 7-wire SNI support for legacy MAC interface • Automatic MDI/MDI-X crossover for plug-and-play • Disable automatic MDI/MDI-X option • Low power: Core: 1.8V Digital I/O: 3.3V Analog I/O: 2.5V or 3.3V • 0.18µm CMOS technology • Commercial temperature range: 0°C to +70°C • Industrial temperature range: –40°C to +85°C • Available in 128-pin PQFP package Features • Integrated switch with five MACs and five fast Ethernet transceivers fully compliant to IEEE 802.3u standard • Shared memory based switch fabric with fully nonblocking configuration • 1.4Gbps high-performance memory bandwidth • 10BASE-T, 100BASE-TX, and 100BASE-FX modes • Dual MII configuration: MII-Switch (MAC or PHY mode MII) and MII-P5 (PHY mode MII) • IEEE 802.1q tag-based VLAN (16 VLANs, full-range VID) for DMZ port, WAN/LAN separation or interVLAN switch links • VLAN ID tag/untag options, per-port basis • Programmable rate limiting 0Mbps to 100Mbps, ingress and egress port, rate options for high and low priority, per-port basis in 32Kbps increments • Flow control or drop packet rate limiting (ingress port) • Integrated MIB counters for fully compliant statistics gathering, 34 MIB counters per port • Enable/Disable option for huge frame size up to 1916 bytes per frame • IGMP v1/v2 snooping for multicast packet filtering • Special tagging mode to send CPU info on ingress packet’s port value • SPI slave (complete) and MDIO (MII PHY only) serial management interface for control of register configuration • MAC-id based security lock option • Control registers configurable on-the-fly (port-priority, 802.1p/d/q, AN...) • CPU read access to MAC forwarding table entries • 802.1d Spanning Tree Protocol • Port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port or MII • Broadcast storm protection with % control – global and per-port basis • Optimization for fiber-to-copper media conversion • Full-chip hardware power-down support (register configuration not saved) Applications • • • • • • • • • Broadband gateway/firewall/VPN Integrated DSL or cable modem multi-port router Wireless LAN access point plus gateway Home networking expansion Standalone 10/100 switch Hotel/campus/MxU gateway Enterprise VoIP gateway/phone FTTx customer premise equipment Managed Media converter Ordering Information Part Number Standard KS8995MA KS8995FQ KS8995MAI KS8995FQI Pb-Free KSZ8995MA KSZ8995FQ KSZ8995MAI KSZ8995FQI Temperature Range 0°C to +70°C 0°C to +70°C –40°C to +85°C –40°C to +85°C Package 128-Pin PQFP 128-Pin PQFP 128-Pin PQFP 128-Pin PQFP Semptember 2008 3 M9999-091508 Micrel, Inc. KS8995MA/FQ Revision History Revision 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 Date 10/10/03 10/30/03 4/01/04 1/19/05 4/13/05 2/6/06 7/12/06 6/01/07 03/20/08 09/15/08 Summary of Changes Created. Editorial changes on electrical characteristics. Editorial changes on the TTL input and output electrical characteristics. Insert recommended reset circuit, pg. 70. Editorial, Pg. 36. Changed VDDIO to 3.3V. Changed Jitter to 16 ns Max. Added Pb-Free option for Industrial version. Add a note for VLAN table write, improve the timing diagram for MII interface, update pin description for PCRS, PCOL, etc. And update the description of the register bits for the loopback, etc. Add the package thermal information in the operating rating and the transformer power consumption information in the electrical characteristics note. Add KSZ8995FQ information and pin description. Add KSZ8995FQ block diagram and descriptions for revision ID and LED mode. Semptember 2008 4 M9999-091508 Micrel, Inc. KS8995MA/FQ Contents System Level Applications........................................................................................................................................... 8 Pin Configuration ........................................................................................................................................................ 10 Pin Description (by Number)...................................................................................................................................... 11 Pin Description (by Name) ......................................................................................................................................... 17 Introduction ................................................................................................................................................................. 23 Functional Overview: Physical Layer Transceiver .................................................................................................. 23 100BASE-TX Transmit.............................................................................................................................................. 23 100BASE-TX Receive............................................................................................................................................... 23 PLL Clock Synthesizer.............................................................................................................................................. 23 Scrambler/De-Scrambler (100BASE-TX only).......................................................................................................... 24 100BASE-FX Operation............................................................................................................................................ 24 100BASE-FX Signal Detection ................................................................................................................................. 24 100BASE-FX far End fault ........................................................................................................................................ 24 10BASE-T Transmit .................................................................................................................................................. 24 10BASE-T Receive ................................................................................................................................................... 24 Power Management.................................................................................................................................................. 24 MDI/MDI-X Auto Crossover ...................................................................................................................................... 24 Auto-Negotiation ....................................................................................................................................................... 24 Functional Overview: Switch Core ............................................................................................................................ 25 Address Look-Up ...................................................................................................................................................... 25 Learning .................................................................................................................................................................... 25 Migration ................................................................................................................................................................... 25 Aging ......................................................................................................................................................................... 25 Forwarding ................................................................................................................................................................ 25 Switching Engine ...................................................................................................................................................... 26 Media Access Controller (MAC) Operation............................................................................................................... 26 Inter-Packet Gap (IPG) ............................................................................................................................................. 26 Backoff Algorithm ...................................................................................................................................................... 26 Late Collision ............................................................................................................................................................ 26 Illegal Frames ........................................................................................................................................................... 26 Flow Control .............................................................................................................................................................. 26 Half-Duplex Back Pressure ........................................................................................................................... 28 Broadcast Storm Protection ...................................................................................................................................... 28 MII Interface Operation ............................................................................................................................................. 29 SNI Interface Operation ............................................................................................................................................ 31 Advanced Functionality.............................................................................................................................................. 31 Spanning Tree Support............................................................................................................................................. 31 Special Tagging Mode .............................................................................................................................................. 32 IGMP Support ........................................................................................................................................................... 33 Port Mirroring Support............................................................................................................................................... 34 VLAN Support ........................................................................................................................................................... 34 Rate Limit Support .................................................................................................................................................... 35 Configuration Interface.............................................................................................................................................. 36 I2C Master Serial Bus Configuration ......................................................................................................................... 38 SPI Slave Serial Bus Configuration .......................................................................................................................... 38 MII Management Interface (MIIM) ............................................................................................................................ 41 Register Description ................................................................................................................................................... 42 Global Registers ....................................................................................................................................................... 43 Register 0 (0x00): Chip ID0 ...................................................................................................................................... 43 Register 1 (0x01): Chip ID1 / Start Switch ................................................................................................................ 43 Register 2 (0x02): Global Control 0 .......................................................................................................................... 43 Register 3 (0x03): Global Control 1 .......................................................................................................................... 43 Register 4 (0x04): Global Control 2 .......................................................................................................................... 44 Register 5 (0x05): Global Control 3 .......................................................................................................................... 45 Semptember 2008 5 M9999-091508 Micrel, Inc. KS8995MA/FQ Register 6 (0x07): Global Control 4 .......................................................................................................................... 46 Register 7 (0x07): Global Control 5 .......................................................................................................................... 46 Register 8 (0x08): Global Control 6 .......................................................................................................................... 46 Register 9 (0x09): Global Control 7 .......................................................................................................................... 46 Register 10 (0x0A): Global Control 8 ........................................................................................................................ 47 Register 11 (0x0B): Global Control 9 ........................................................................................................................ 47 Port Registers ........................................................................................................................................................... 48 Register 16 (0x10): Port 1 Control 0 ......................................................................................................................... 48 Register 17 (0x11): Port 1 Control 1 ......................................................................................................................... 49 Register 18 (0x12): Port 1 Control 2 ......................................................................................................................... 49 Register 19 (0x13): Port 1 Control 3 ......................................................................................................................... 50 Register 20 (0x14): Port 1 Control 4 ......................................................................................................................... 50 Register 21 (0x15): Port 1 Control 5 ......................................................................................................................... 51 Register 22 (0x16): Port 1 Control 6 ......................................................................................................................... 51 Register 23 (0x17): Port 1 Control 7 ......................................................................................................................... 51 Register 24 (0x18): Port 1 Control 8 ......................................................................................................................... 51 Register 25 (0x19): Port 1 Control 9 ......................................................................................................................... 52 Register 26 (0x1A): Port 1 Control 10....................................................................................................................... 52 Register 27 (0x1B): Port 1 Control 11....................................................................................................................... 52 Register 28 (0x1C): Port 1 Control 12 ...................................................................................................................... 53 Register 29 (0x1D): Port 1 Control 13 ...................................................................................................................... 54 Register 30 (0x1E): Port 1 Status 0 .......................................................................................................................... 54 Register 31 (0x1F): Port 1 Control 14 ....................................................................................................................... 55 Advanced Control Registers ..................................................................................................................................... 55 Register 96 (0x60): TOS Priority Control Register 0 ................................................................................................ 55 Register 97 (0x61): TOS Priority Control Register 1 ................................................................................................ 55 Register 98 (0x62): TOS Priority Control Register 2 ................................................................................................ 55 Register 99 (0x63): TOS Priority Control Register 3 ................................................................................................ 55 Register 100 (0x64): TOS Priority Control Register 4 .............................................................................................. 55 Register 101 (0x65): TOS Priority Control Register 5 .............................................................................................. 56 Register 102 (0x66): TOS Priority Control Register 6 .............................................................................................. 56 Register 103 (0x67): TOS Priority Control Register 7 .............................................................................................. 56 Register 104 (0x68): MAC Address Register 0......................................................................................................... 56 Register 105 (0x69): MAC Address Register 1......................................................................................................... 56 Register 106 (0x6A): MAC Address Register 2 ........................................................................................................ 56 Register 107 (0x6B): MAC Address Register 3 ........................................................................................................ 56 Register 108 (0x6C): MAC Address Register 4 ........................................................................................................ 56 Register 109 (0X6D): MAC Address Register 5 ....................................................................................................... 56 Register 110 (0x6E): Indirect Access Control 0 ........................................................................................................ 56 Register 111 (0x6F): Indirect Access Control 1 ........................................................................................................ 56 Register 112 (0x70): Indirect Data Register 8 .......................................................................................................... 56 Register 113 (0x71): Indirect Data Register 7 .......................................................................................................... 57 Register 114 (0x72): Indirect Data Register 6 .......................................................................................................... 57 Register 115 (0x73): Indirect Data Register 5 .......................................................................................................... 57 Register 116 (0x74): Indirect Data Register 4 .......................................................................................................... 57 Register 117 (0x75): Indirect Data Register 3 .......................................................................................................... 57 Register 118 (0x76): Indirect Data Register 2 .......................................................................................................... 57 Register 119 (0x77): Indirect Data Register 1 .......................................................................................................... 57 Register 120 (0x78): Indirect Data Register 0 .......................................................................................................... 57 Register 121 (0x79): Digital Testing Status 0 ........................................................................................................... 57 Register 122 (0x7A): Digital Testing Status 1 ........................................................................................................... 57 Register 123 (0x7B): Digital Testing Control 0 ......................................................................................................... 57 Register 124 (0x7C): Digital Testing Control 1 ......................................................................................................... 57 Register 125 (0x7D): Analog Testing Control 0 ........................................................................................................ 57 Register 126 (0x7E): Analog Testing Control 1 ........................................................................................................ 57 Register 127 (0x7F): Analog Testing Status ............................................................................................................. 57 Semptember 2008 6 M9999-091508 Micrel, Inc. KS8995MA/FQ Static MAC Address .................................................................................................................................................... 58 VLAN Address ............................................................................................................................................................. 60 Dynamic MAC Address............................................................................................................................................... 61 MIB Counters ............................................................................................................................................................... 62 MIIM Registers ............................................................................................................................................................. 65 Register 0: MII Control .............................................................................................................................................. 65 Register 1: MII Status ............................................................................................................................................... 65 Register 2: PHYID HIGH........................................................................................................................................... 66 Register 3: PHYID LOW ........................................................................................................................................... 66 Register 4: Advertisement Ability.............................................................................................................................. 66 Register 5: Link Partner Ability ................................................................................................................................. 66 Absolute Maximum Ratings(1) .................................................................................................................................... 67 Operating Ratings(2) .................................................................................................................................................... 67 Electrical Characteristics(4, 5) ...................................................................................................................................... 67 Timing Diagrams ......................................................................................................................................................... 69 Selection of Isolation Transformer(1) ......................................................................................................................... 77 Package Information ................................................................................................................................................... 78 Semptember 2008 7 M9999-091508 Micrel, Inc. KS8995MA/FQ System Level Applications 10/100 MAC 1 Switch Controller On-Chip Frame Buffers 10/100 PHY 1 10/100 PHY 2 10/100 PHY 3 10/100 PHY 4 10/100 PHY 5 1-port WAN I/F 4-port LAN 10/100 MAC 2 10/100 MAC 3 10/100 MAC 4 10/100 MAC 5 SPI/GPIO SPI Ethernet MAC CPU Ethernet MAC MII-SW MII-P5 External WAN port PHY not required. Figure 1. Broadband Gateway 10/100 MAC 1 Switch Controller On-Chip Frame Buffers 10/100 PHY 1 10/100 PHY 2 10/100 PHY 3 10/100 PHY 4 10/100 PHY 5 4-port LAN 10/100 MAC 2 10/100 MAC 3 10/100 MAC 4 10/100 MAC 5 WAN PHY & AFE (xDSL, CM...) CPU SPI/GPIO SPI MII-SW MII-P5 Ethernet MAC Figure 2. Integrated Broadband Router Semptember 2008 8 M9999-091508 Micrel, Inc. KS8995MA/FQ 10/100 MAC 1 Switch Controller On-Chip Frame Buffers 10/100 PHY 1 10/100 PHY 2 10/100 PHY 3 10/100 PHY 4 10/100 PHY 5 5-port LAN 10/100 MAC 2 10/100 MAC 3 10/100 MAC 4 10/100 MAC 5 Figure 3. Standalone Switch Figure 4. Using KSZ8995FQ for Dual Media Converter or Fiber daisy chain connection Semptember 2008 9 M9999-091508 Micrel, Inc. KS8995MA/FQ Pin Configuration 128-Pin PQFP Semptember 2008 10 M9999-091508 Micrel, Inc. KS8995MA/FQ Pin Description (by Number) Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Pin Name MDI-XDIS GNDA VDDAR RXP1 RXM1 GNDA TXP1 TXM1 VDDAT RXP2 RXM2 GNDA TXP2 TXM2 VDDAR GNDA ISET VDDAT RXP3 RXM3 GNDA TXP3 TXM3 VDDAT RXP4 RXM4 GNDA TXP4 TXM4 GNDA P I I Gnd O O P I I Gnd O O Gnd 4 4 4 4 3 3 3 3 Type(1) lpd Gnd P I I Gnd O O P I I Gnd O O P Gnd 2 2 2 2 1 1 1 1 Port 1-5 Pin Function(2) Disable auto MDI/MDI-X. PD (default) = normal operation. PU = disable auto MDI/MDI-X on all ports. Analog ground. 1.8V analog VDD. Physical receive signal + (differential). Physical receive signal – (differential). Analog ground. Physical transmit signal + (differential). Physical transmit signal – (differential). 2.5V or 3.3V analog VDD. Physical receive signal + (differential). Physical receive signal – (differential). Analog ground. Physical transmit signal + (differential). Physical transmit signal – (differential). 1.8V analog VDD. Analog ground. Set physical transmit output current. Pull-down with a 3.01kΩ1% resistor. 2.5V or 3.3V analog VDD. Physical receive signal + (differential). Physical receive signal - (differential). Analog ground. Physical transmit signal + (differential). Physical transmit signal – (differential). 2.5V or 3.3V analog VDD. Physical receive signal + (differential). Physical receive signal - (differential). Analog ground. Physical transmit signal + (differential). Physical transmit signal – (differential). Analog ground. Notes: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/internal pull-up. Ipd = Input w/internal pull-down. Ipd/O = Input w/internal pull-down during reset, output pin otherwise. Ipu/O = Input w/internal pull-up during reset, output pin otherwise. NC = No connect. 2. PU = Strap pin pull-up. PD = Strap pull-down. Semptember 2008 11 M9999-091508 Micrel, Inc. KS8995MA/FQ Pin Number 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Pin Name VDDAR RXP5 RXM5 GNDA TXP5 TXM5 VDDAT FXSD5/FXSD3 FXSD4 GNDA VDDAR GNDA VDDAR GNDA MUX1 MUX2 PWRDN_N RESERVE GNDD VDDC PMTXEN PMTXD3 PMTXD2 PMTXD1 PMTXD0 PMTXER PMTXC GNDD VDDIO PMRXC Type(1) P I I Gnd O O P Ipd Ipd Gnd P Gnd P Gnd NC NC Ipu NC Gnd P Ipd Ipd Ipd Ipd Ipd Ipd O Gnd P O Port 5 5 Pin Function 1.8V analog VDD. Physical receive signal + (differential). Physical receive signal – (differential). Analog ground. 5 5 Physical transmit signal + (differential). Physical transmit signal – (differential). 2.5V or 3.3V analog VDD. Fiber signal detect pin. FXSD5 is for port 5 of the KS8995MA. FXSD3 is for port 3 of the KS8995FQ Fiber signal detect pin for port 4. Analog ground. 1.8V analog VDD. Analog ground. 1.8V analog VDD. Analog ground. Factory test pins. MUX1 and MUX2 should be left unconnected for normal operation Mode MUX1 MUX2 Normal Operation NC NC Full-chip power down. Active low. Reserved pin. No connect. Digital ground. 1.8V digital core VDD. 5/3 4 5 5 5 5 5 5 5 PHY[5] MII transmit enable. PHY[5] MII transmit bit 3. PHY[5] MII transmit bit 2. PHY[5] MII transmit bit 1. PHY[5] MII transmit bit 0. PHY[5] MII transmit error. PHY[5] MII transmit clock. PHY mode MII. Digital ground. 3.3V digital VDD for digital I/O circuitry. 5 PHY[5] MII receive clock. PHY mode MII. Notes: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/internal pull-up. Ipd = Input w/internal pull-down. Ipd/O = Input w/internal pull-down during reset, output pin otherwise. Ipu/O = Input w/internal pull-up during reset, output pin otherwise. NC = No connect. Semptember 2008 12 M9999-091508 Micrel, Inc. KS8995MA/FQ Pin Number 61 62 63 64 65 66 67 Pin Name PMRXDV PMRXD3 PMRXD2 PMRXD1 PMRXD0 PMRXER PCRS Type(1) Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O Port 5 5 5 5 5 5 5 Pin Function(2) PHY[5] MII receive data valid. PHY[5] MII receive bit 3. Strap option: PD (default) = enable flow control; PU = disable flow control. PHY[5] MII receive bit 2. Strap option: PD (default) = disable back pressure; PU = enable back pressure. PHY[5] MII receive bit 1. Strap option: PD (default) = drop excessive collision packets; PU = does not drop excessive collision packets. PHY[5] MII receive bit 0. Strap option: PD (default) = disable aggressive back-off algorithm in half-duplex mode; PU = enable for performance enhancement. PHY[5] MII receive error. Strap option: PD (default) = packet size 1518/1522 bytes; PU = 1536 bytes. PHY[5] MII carrier sense/strap option for port 4 only. PD (default) = force half-duplex if auto-negotiation is disabled or fails. PU = force full-duplex if auto negotiation is disabled or fails. Refer to Register 76. PHY[5] MII collision detect/ strap option for port 4 only. PD (default) = no force flow control, normal operation. PU = force flow control. Refer to Register 66 Switch MII transmit enable. Switch MII transmit bit 3. Switch MII transmit bit 2. Switch MII transmit bit 1. Switch MII transmit bit 0. Switch MII transmit error. Switch MII transmit clock. Input in MAC mode, output in PHY mode MII. Digital ground. 3.3V digital VDD for digital I/O circuitry. Switch MII receive clock. Input in MAC mode, output in PHY mode MII. Switch MII receive data valid. Switch MII receive bit 3. Strap option: PD (default) = Disable Switch MII full-duplex flow control; PU = Enable Switch MII full-duplex flow control. Switch MII receive bit 2. Strap option: PD (default) = Switch MII in fullduplex mode; PU = Switch MII in half-duplex mode. 68 69 70 71 72 73 74 75 76 77 78 79 80 81 PCOL SMTXEN SMTXD3 SMTXD2 SMTXD1 SMTXD0 SMTXER SMTXC GNDD VDDIO SMRXC SMRXDV SMRXD3 SMRXD2 Ipd/O Ipd Ipd Ipd Ipd Ipd Ipd I/O Gnd P I/O Ipd/O Ipd/O Ipd/O 5 Notes: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/internal pull-up. Ipd = Input w/internal pull-down. Ipd/O = Input w/internal pull-down during reset, output pin otherwise. Ipu/O = Input w/internal pull-up during reset, output pin otherwise. NC = No connect. 2. PU = Strap pin pull-up. PD = Strap pull-down. Semptember 2008 13 M9999-091508 Micrel, Inc. KS8995MA/FQ Pin Number 82 Pin Name SMRXD1 Type(1) Ipd/O Port Pin Function(2) Switch MII receive bit 1. Strap option: PD (default) = Switch MII in 100Mbps mode; PU = Switch MII in 10Mbps mode. Switch MII receive bit 0; Strap option: LED mode PD (default) = mode 0; PU = mode 1. See “Register 11.” Mode 0, link at 100/Full LEDx[2,1,0]=0,0,0 10/Full LEDx[2,1,0]=0,0,1 100/Half LEDx[2,1,0]=0,1,0 10/Half LEDx[2,1,0]=0,1,1 100/Half LEDx[2,1,0]=0,1,1 10/Half LEDx[2,1,0]=1,0,1 Mode 0 Lnk/Act Fulld/Col Speed Mode 1 100Lnk/Act 10Lnk/Act Full duplex 83 SMRXD0 Ipd/O Mode 1, link at 100/Full LEDx[2,1,0]=0,1,0 10/Full LEDx[2,1,0]=1,0,0 LEDX_2 LEDX_1 LEDX_0 84 85 86 SCOL SCRS SCONF1 Ipd/O Ipd/O Ipd Switch MII collision detect. Switch mode carrier sense. Dual MII configuration pin. For the Switch MII, KSZ8995MA supports both MAC mode and PHY mode, KSZ8995FQ supports PHY mode only. Pin# (91, 86, 87): 000 001 010 011 100 101 110 111 Switch MII Disable, Otri PHY Mode MII MAC Mode MII PHY Mode SNI Disable PHY Mode MII MAC Mode MII PHY Mode SNI PHY [5] MII Disable, Otri Disable, Otri Disable, Otri Disable, Otri Disable PHY Mode MII PHY Mode MII PHY Mode MII 87 88 89 90 91 SCONF0 GNDD VDDC LED5-2 LED5-1 Ipd Gnd P Ipu/O Ipu/O 5 5 Dual MII configuration pin. Digital ground. 1.8V digital core VDD. LED indicator 2. Strap option: aging setup. See “Aging” section. PU (default) = aging enable; PD = aging disable. LED indicator 1. Strap option: PU (default): enable PHY[5] MII I/F. PD: tristate all PHY[5] MII output. See “Pin 86 SCONF1.” Notes: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/internal pull-up. Ipd = Input w/internal pull-down. Ipd/O = Input w/internal pull-down during reset, output pin otherwise. Ipu/O = Input w/internal pull-up during reset, output pin otherwise. NC = No connect. 2. PU = Strap pin pull-up. PD = Strap pull-down. Otri = Output tristated. Fulld = Full duplex Semptember 2008 14 M9999-091508 Micrel, Inc. KS8995MA/FQ Pin Number 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 Pin Name LED5-0 LED4-2 LED4-1 LED4-0 LED3-2 LED3-1 LED3-0 GNDD VDDIO LED2-2 LED2-1 LED2-0 LED1-2 LED1-1 LED1-0 MDC MDIO SPIQ SPIC/SCL SSPID/SDA Type(1) Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Gnd P Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu I/O Otri I/O I/O Port 5 4 4 4 3 3 3 Pin Function LED indicator 0. LED indicator 2. LED indicator 1. LED indicator 0. LED indicator 2. LED indicator 1. LED indicator 0. Digital ground. 3.3V digital VDD for digital I/O. 2 2 2 1 1 1 All All All All All LED indicator 2. LED indicator 1. LED indicator 0. LED indicator 2. LED indicator 1. LED indicator 0. Switch or PHY[5] MII management data clock. Switch or PHY[5] MII management data I/O. Features internal pull down to define pin state when not driven. (1) SPI serial data output in SPI slave mode; (2) output clock at 61kHz in I2C master mode. See “Pin 113.” (1) Input clock up to 5MHz in SPI slave mode; (2) output clock at 61kHz in I2C master mode. See “Pin 113.” (1) Serial data input in SPI slave mode; (2) serial data input/output in I2C master mode. See “Pin 113.” Active low. (1) SPI data transfer start in SPI slave mode. When SPIS_N is high, the KS8995MA/FQ is deselected and SPIQ is held in high impedance state, a high-to-low transition to initiate the SPI data transfer; (2) not used in I2C master mode. Serial bus configuration pin. For this case, if the EEPROM is not present, the KS8995MA/FQ will start itself with the PS[1.0] = 00 default register values. Pin Configuration Serial Bus Configuration I2C Master Mode for EEPROM Reserved SPI Slave Mode for CPU Interface Factory Test Mode (BIST) 112 SPIS_N Ipu All 113 PS1 Ipd PS[1.0]=00 PS[1.0]=01 PS[1.0]=10 PS[1.0]=11 Notes: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/internal pull-up. Ipd = Input w/internal pull-down. Ipd/O = Input w/internal pull-down during reset, output pin otherwise. Ipu/O = Input w/internal pull-up during reset, output pin otherwise. NC = No connect. Semptember 2008 15 M9999-091508 Micrel, Inc. KS8995MA/FQ Pin Number 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Pin Name PS0 RST_N GNDD VDDC TESTEN SCANEN NC X1 X2 VDDAP GNDA VDDAR GNDA GNDA TEST2 Type(1) Ipd Ipu Gnd P Ipd Ipd NC I O P Gnd P Gnd Gnd NC Port Pin Function Serial bus configuration pin. See “Pin 113.” Reset the KS8995MA/FQ. Active low. Digital ground. 1.8V digital core VDD. NC for normal operation. Factory test pin. NC for normal operation. Factory test pin. No connect. 25MHz crystal clock connection/or 3.3V tolerant oscillator input. Oscillator should be ±100ppm. 25MHz crystal clock connection. 1.8V analog VDD for PLL. Analog ground. 1.8V analog VDD. Analog ground. Analog ground. NC for normal operation. Factory test pin. Notes: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/internal pull-up. Ipd = Input w/internal pull-down. Ipd/O = Input w/internal pull-down during reset, output pin otherwise. Ipu/O = Input w/internal pull-up during reset, output pin otherwise. NC = No connect. Semptember 2008 16 M9999-091508 Micrel, Inc. KS8995MA/FQ Pin Description (by Name) Pin Number 39 38 124 42 44 2 16 30 6 12 21 27 34 40 120 127 126 49 88 116 58 76 99 17 106 105 104 103 102 101 98 Pin Name FXSD4 FXSD3/FXSD5 GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA NC GNDA GNDA GNDD GNDD GNDD GNDD GNDD GNDD ISET LED1-0 LED1-1 LED1-2 LED2-0 LED2-1 LED2-2 LED3-0 Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O 1 1 1 2 2 2 3 Type(1) I I Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd NC Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Port 4 3/5 Pin Function Fiber signal detect/Factory test pin. Fiber signal detect/Factory test pin for FQ or MA Analog ground. Analog ground. Analog ground. Analog ground. Analog ground. Analog ground. Analog ground. Analog ground. Analog ground. Analog ground. Analog ground. Analog ground. No connect. Analog ground. Analog ground. Digital ground. Digital ground. Digital ground. Digital ground. Digital ground. Digital ground. Set physical transmit output current. Pull-down with a 3.01kΩ1% resistor. LED indicator 0. LED indicator 1. LED indicator 2. LED indicator 0. LED indicator 1. LED indicator 2. LED indicator 0. Notes: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/internal pull-up. Ipd = Input w/internal pull-down. Ipd/O = Input w/internal pull-down during reset, output pin otherwise. Ipu/O = Input w/internal pull-up during reset, output pin otherwise. NC = No connect. Semptember 2008 17 M9999-091508 Micrel, Inc. KS8995MA/FQ Pin Number 97 96 95 94 93 92 91 90 107 108 1 45 46 Pin Name LED3-1 LED3-2 LED4-0 LED4-1 LED4-2 LED5-0 LED5-1 LED5-2 MDC MDIO MDI-XDIS MUX1 MUX2 Type(1) Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu I/O Ipd NC NC Port 3 3 4 4 4 5 5 5 All All 1-5 Pin Function(2) LED indicator 1. LED indicator 2. LED indicator 0. LED indicator 1. LED indicator 2. LED indicator 0. LED indicator 1. Strap option: PU (default) = enable PHY MII I/F PD: tristate all PHY MII output. See “Pin 86 SCONF1.” LED indicator 2. Strap option: aging setup. See “Aging” section. (default) = aging enable; PD = aging disable. Switch or PHY[5] MII management data clock. Switch or PHY[5] MII management data I/O. Disable auto MDI/MDI-X. Factory test pins. MUX1 and MUX2 should be left unconnected for normal operation. Mode Normal Operation MUX1 NC MUX2 NC 68 67 60 65 64 63 62 61 66 PCOL PCRS PMRXC PMRXD0 PMRXD1 PMRXD2 PMRXD3 PMRXDV PMRXER Ipd/O Ipd/O O Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O 5 5 5 5 5 5 5 5 5 PHY[5] MII collision detect/force flow control. See “Register 18.” For port 4 only. PD (default) = no force flow control. PU = force flow control. PHY[5] MII carrier sense/force duplex mode. See “Register 28.” For port 4 only. PD (default) = force half-duplex if auto-negotiation is disabled or fails. PU = force full-duplex if auto-negotiation is disabled or fails. PHY[5] MII receive clock. PHY mode MII. PHY[5] MII receive bit 0. Strap option: PD (default) = disable aggressive back-off algorithm in half-duplex mode; PU = enable for performance enhancement. PHY[5] MII receive bit 1. Strap option: PD (default) = drop excessive collision packets; PU = does not drop excessive collision packets. PHY[5] MII receive bit 2. Strap option: PD (default) = disable back pressure; PU = enable back pressure. PHY[5] MII receive bit 3. Strap option: PD (default) = enable flow control; PU = disable flow control. PHY[5] MII receive data valid. PHY[5] MII receive error. Strap option: PD (default) = 1522/1518 bytes; PU = packet size up to 1536 bytes. Notes: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/internal pull-up. Ipd = Input w/internal pull-down. Ipd/O = Input w/internal pull-down during reset, output pin otherwise. Ipu/O = Input w/internal pull-up during reset, output pin otherwise. NC = No connect. 2. PU = Strap pin pull-up. PD = Strap pull-down. Semptember 2008 18 M9999-091508 Micrel, Inc. KS8995MA/FQ Pin Number 57 55 54 53 52 51 56 114 113 Pin Name PMTXC PMTXD0 PMTXD1 PMTXD2 PMTXD3 PMTXEN PMTXER PS0 PS1 Type(1) O Ipd Ipd Ipd Ipd Ipd Ipd Ipd Ipd Port 5 5 5 5 5 5 5 Pin Function PHY[5] MII transmit clock. PHY mode MII. PHY[5] MII transmit bit 0. PHY[5] MII transmit bit 1. PHY[5] MII transmit bit 2. PHY[5] MII transmit bit 3. PHY[5] MII transmit enable. PHY[5] MII transmit error. Serial bus configuration pin. See “Pin 113.” Serial bus configuration pin. If EEPROM is not present, the KS8995MA/FQ will start itself with chip default (00)... Pin Configuration PS[1:0]=00 PS[1:0]=01 PS[1:0]=10 PS[1:0]=11 Serial Bus Configuration I2C Master Mode for EEPROM Reserved SPI Slave Mode for CPU Interface Factory Test Mode (BIST) 47 48 115 5 11 20 26 33 4 10 19 25 32 119 84 87 PWRDN_N RESERVE RST_N RXM1 RXM2 RXM3 RXM4 RXM5 RXP1 RXP2 RXP3 RXP4 RXP5 SCANEN SCOL SCONF0 Ipu NC Ipu I I I I I I I I I I Ipd Ipd/O Ipd 1 2 3 4 5 1 2 3 4 5 Full-chip power down. Active low. Reserved pin. No connect. Reset the KS8995MA/FQ. Active low. Physical receive signal – (differential). Physical receive signal – (differential). Physical receive signal – (differential). Physical receive signal – (differential). Physical receive signal – (differential). Physical receive signal + (differential). Physical receive signal + (differential). Physical receive signal + (differential). Physical receive signal + (differential). Physical receive signal + (differential). NC for normal operation. Factory test pin. Switch MII collision detect. Dual MII configuration pin. Notes: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/internal pull-up. Ipd = Input w/internal pull-down. Ipd/O = Input w/internal pull-down during reset, output pin otherwise. Ipu/O = Input w/internal pull-up during reset, output pin otherwise. NC = No connect. Semptember 2008 19 M9999-091508 Micrel, Inc. KS8995MA/FQ Pin Number 86 Pin Name SCONF1 Type(1) Ipd Port Pin Function(2) Dual MII configuration pin. For the Switch MII, KSZ8995MA supports both MAC mode and PHY mode, KSZ8995FQ supports PHY mode only. Pin# (91, 86, 87): 000 001 010 011 100 101 110 111 Switch MII Disable, Otri PHY Mode MII MAC Mode MII PHY Mode SNI Disable PHY Mode MII MAC Mode MII PHY Mode SNI PHY [5] MII Disable, Otri Disable, Otri Disable, Otri Disable, Otri Disable PHY Mode MII PHY Mode MII PHY Mode MII 85 78 SCRS SMRXC Ipd/O I/O Switch mode carrier sense. Switch MII receive clock. Input in MAC mode, output in PHY mode MII. Switch MII receive bit 0; Strap option: LED mode PD (default) = mode 0; PU = mode 1. See “Register 11.” 83 SMRXD0 Ipd/O 82 81 80 79 75 73 72 71 70 69 74 SMRXD1 SMRXD2 SMRXD3 SMRXDV SMTXC SMTXD0 SMTXD1 SMTXD2 SMTXD3 SMTXEN SMTXER Ipd/O Ipd/O Ipd/O Ipd/O I/O Ipd Ipd Ipd Ipd Ipd Ipd Mode 0 Mode 1 LEDX_2 Lnk/Act 100Lnk/Act LEDX_1 Fulld/Col 10Lnk/Act LEDX_0 Speed Full duplex Switch MII receive bit 1. Strap option: PD (default) = Switch MII in 100Mbps mode; PU = Switch MII in 10Mbps mode. Switch MII receive bit 2. Strap option: PD (default) = Switch MII in fullduplex mode; PU = Switch MII in half-duplex mode. Switch MII receive bit 3. Strap option: PD (default) = Disable Switch MII full-duplex flow control; PU = Enable Switch MII full-duplex flow control. Switch MII receive data valid. Switch MII transmit clock. Input in MAC mode, output in PHY mode MII. Switch MII transmit bit 0. Switch MII transmit bit 1. Switch MII transmit bit 2. Switch MII transmit bit 3. Switch MII transmit enable. Switch MII transmit error. Notes: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/internal pull-up. Ipd = Input w/internal pull-down. Ipd/O = Input w/internal pull-down during reset, output pin otherwise. Ipu/O = Input w/internal pull-up during reset, output pin otherwise. Otri = Output tristated. NC = No connect. 2. PU = Strap pin pull-up. PD = Strap pull-down. Fulld = Full duplex Semptember 2008 20 M9999-091508 Micrel, Inc. KS8995MA/FQ Pin Number 110 111 109 112 128 118 8 14 23 29 36 7 13 22 28 35 123 41 43 3 15 31 125 18 9 24 37 50 Pin Name SPIC/SCL SSPID/SDA SPIQ SPIS_N TEST2 TESTEN TXM1 TXM2 TXM3 TXM4 TXM5 TXP1 TXP2 TXP3 TXP4 TXP5 VDDAP VDDAR VDDAR VDDAR VDDAR VDDAR VDDAR VDDAT VDDAT VDDAT VDDAT VDDC Type(1) I/O I/O Otri Ipu NC Ipd O O O O O O O O O O P P P P P P P P P P P P Port All All All All Pin Function (1) Input clock up to 5MHz in SPI slave mode; (2) output clock at 61kHz in I2C master mode. See “Pin 113.” (1) Serial data input in SPI slave mode; (2) serial data input/output in I2C master mode. See “Pin 113.” (1) SPI serial data output in SPI slave mode; (2) output clock at 61kHz in I2C master mode. See “Pin 113.” Active low. (1) SPI data transfer start in SPI slave mode. When SPIS_N is high, the KS8995MA/FQ is deselected and SPIQ is held in high impedance state, a high-to-low transition to initiate the SPI data transfer; (2) not used in I2C master mode. NC for normal operation. Factory test pin. NC for normal operation. Factory test pin. 1 2 3 4 5 1 2 3 4 5 Physical transmit signal – (differential). Physical transmit signal – (differential). Physical transmit signal – (differential). Physical transmit signal – (differential). Physical transmit signal – (differential). Physical transmit signal + (differential). Physical transmit signal + (differential). Physical transmit signal + (differential). Physical transmit signal + (differential). Physical transmit signal + (differential). 1.8V analog VDD for PLL. 1.8V analog VDD. 1.8V analog VDD. 1.8V analog VDD. 1.8V analog VDD. 1.8V analog VDD. 1.8V analog VDD. 2.5V or 3.3V analog VDD. 2.5V or 3.3V analog VDD. 2.5V or 3.3V analog VDD. 2.5V or 3.3V analog VDD. 1.8V digital core VDD. Notes: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/internal pull-up. Ipd = Input w/internal pull-down. Ipd/O = Input w/internal pull-down during reset, output pin otherwise. Ipu/O = Input w/internal pull-up during reset, output pin otherwise. Otri = Output tristated. NC = No connect. Semptember 2008 21 M9999-091508 Micrel, Inc. KS8995MA/FQ Pin Number 89 117 59 77 100 121 122 Pin Name VDDC VDDC VDDIO VDDIO VDDIO X1 X2 Type(1) P P P P P I O Port Pin Function 1.8V digital core VDD. 1.8V digital core VDD. 3.3V digital VDD for digital I/O circuitry. 3.3V digital VDD for digital I/O circuitry. 3.3V digital VDD for digital I/O circuitry. 25MHz crystal clock connection/or 3.3V tolerant oscillator input. Oscillator should be ±100ppm. 25MHz crystal clock connection. Notes: 1. P = Power supply. I = Input. O = Output. Semptember 2008 22 M9999-091508 Micrel, Inc. KS8995MA/FQ Introduction The KS8995MA/FQ contains five 10/100 physical layer transceivers and five media access control (MAC) units with an integrated Layer 2 managed switch. The device runs in three modes. The first mode is as a five-port integrated switch. The second is as a five-port switch with the fifth port decoupled from the physical port. In this mode, access to the fifth MAC is provided through a media independent interface (MII). This is useful for implementing an integrated broadband router. The third mode uses the dual MII feature to recover the use of the fifth PHY. This allows the additional broadband gateway configuration, where the fifth PHY may be accessed through the MII-P5 port. The KS8995MA/FQ has the flexibility to reside in a managed or unmanaged design. In a managed design, a host processor has complete control of the KS8995MA/FQ via the SPI bus, or partial control via the MDC/MDIO interface. An unmanaged design is achieved through I/O strapping or EEPROM programming at system reset time. On the media side, the KS8995MA/FQ supports IEEE 802.3 10BASE-T, 100BASE-TX on all ports, and the KS8995MA supports 100BASE-FX on ports 4 and 5, and the KS8995FQ supports 100BASE-FX on ports 3 and 4. The KS8995MA/FQ can be used as fully managed 5-port standalone switch or two separate media converters. Physical signal transmission and reception are enhanced through the use of patented analog circuitry that makes the design more efficient and allows for lower power consumption and smaller chip die size. The major enhancements from the KS8995E to the KS8995MA/FQ are support for host processor management, a dual MII interface, tag as well as port based VLAN, spanning tree protocol support, IGMP snooping support, port mirroring support and rate limiting functionality. Functional Overview: Physical Layer Transceiver 100BASE-TX Transmit The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI conversion, MLT3 encoding and transmission. The circuit starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B coding followed by a scrambler. The serialized data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output current is set by an external 1% 3.01kΩ resistor for the 1:1 transformer ratio. It has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output is also incorporated into the 100BASE-TX transmitter. 100BASE-TX Receive The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion. The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss and phase distortion is a function of the length of the cable, the equalizer has to adjust its characteristics to optimize the performance. In this design, the variable equalizer will make an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization. This is an ongoing process and can self-adjust against environmental changes such as temperature variations. The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used to compensate for the effect of baseline wander and improve the dynamic range. The differential data conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive. The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal into the NRZ format. The signal is then sent through the de-scrambler followed by the 4B/5B decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC. PLL Clock Synthesizer The KS8995MA/FQ generates 125MHz, 42MHz, 25MHz, and 10MHz clocks for system timing. Internal clocks are generated from an external 25MHz crystal or oscillator. Semptember 2008 23 M9999-091508 Micrel, Inc. KS8995MA/FQ Scrambler/De-Scrambler (100BASE-TX only) The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander. The data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). This can generate a 2047-bit non-repetitive sequence. The receiver will then de-scramble the incoming data stream with the same sequence at the transmitter. 100BASE-FX Operation 100BASE-FX operation is very similar to 100BASE-TX operation except that the scrambler/de-scrambler and MLT3 encoder/decoder are bypassed on transmission and reception. In this mode the auto-negotiation feature is bypassed since there is no standard that supports fiber auto-negotiation. 100BASE-FX Signal Detection The physical port runs in 100BASE-FX mode if FXSDx >0.6V for ports 3, 4 (KSZ8995FQ) or ports 4, 5 (KSZ8995MA) only. This signal is internally referenced to 1.25V. The fiber module interface should be set by a voltage divider such that FXSDx ‘H’ is above this 1.25V reference, indicating signal detect, and FXSDx ‘L’ is below the 1.25V reference to indicate no signal. When FXSDx is below 0.6V then 100BASE-FX mode is disabled. Since there is no autonegotiation for 100BASE-FX mode, the ports must be forced to either full or half-duplex for the fiber ports. Note that strap-in options exist to set duplex mode for port 4, but not for port 3, 5. 100BASE-FX far End fault far end fault occurs when the signal detection is logically false from the receive fiber module. When this occurs, the transmission side signals the other end of the link by sending 84 1s followed by a zero in the idle period between frames. The far end fault may be disabled through register settings. 10BASE-T Transmit The output 10BASE-T driver is incorporated into the 100BASE-T driver to allow transmission with the same magnetics. They are internally wave-shaped and pre-emphasized into outputs with a typical 2.3V amplitude. The harmonic contents are at least 27dB below the fundamental when driven by an all-ones Manchester-encoded signal. 10BASE-T Receive On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and a PLL perform the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400mV or with short pulsewidths in order to prevent noises at the RXP or RXM input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KS8995MA/FQ decodes a data frame. The receiver clock is maintained active during idle periods in between data reception. Power Management The KS8995MA/FQ features a per port power down mode. To save power the user can power down ports that are not in use by setting port control registers or MII control registers. In addition, it also supports full chip power down mode. When activated, the entire chip will be shutdown. MDI/MDI-X Auto Crossover The KS8995MA/FQ supports MDI/MDI-X auto crossover. This facilitates the use of either a straight connection CAT5 cable or a crossover CAT-5 cable. The auto-sense function will detect remote transmit and receive pairs, and correctly assign the transmit and receive pairs from the Micrel device. This can be highly useful when end users are unaware of cable types and can also save on an additional uplink configuration connection. The auto crossover feature may be disabled through the port control registers. Auto-Negotiation The KS8995MA/FQ conforms to the auto-negotiation protocol as described by the 802.3 committee. Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the best common mode of operation. In auto-negotiation the link partners advertise capabilities across the link to each other. If auto-negotiation is not supported or the link partner to the KS8995MA/FQ is forced to bypass auto-negotiation, then the mode is set by observing the signal at the receiver. This is known as parallel mode because while the transmitter is sending auto-negotiation Semptember 2008 24 M9999-091508 Micrel, Inc. advertisements, the receiver is listening for advertisements or a fixed signal protocol. The flow for the link setup is shown in Figure 5. Start Auto Negotiation KS8995MA/FQ Force Link Setting No Parallel Operation Yes Bypass Auto-Negotiation and Set Link Mode Attempt Auto-Negotiation Listen for 100BASE-TX Idles Listen for 10BASE-T Link Pulses No Join Flow Link Mode Set ? Yes Link Mode Set Figure 5. Auto-Negotiation Functional Overview: Switch Core Address Look-Up The internal look-up table stores MAC addresses and their associated information. It contains a 1K unicast address table plus switching information. The KS8995MA/FQ is guaranteed to learn 1K addresses and distinguishes itself from a hash-based look-up table, which depending on the operating environment and probabilities, may not guarantee the absolute number of addresses it can learn. Learning The internal look-up engine updates its table with a new entry if the following conditions are met: • The received packet’s source address (SA) does not exist in the look-up table. • The received packet is good; the packet has no receiving errors and is of legal length. The look-up engine inserts the qualified SA into the table, along with the port number and time stamp. If the table is full, the last entry of the table is deleted first to make room for the new entry. Migration The internal look-up engine also monitors whether a station is moved. If this occurs, it updates the table accordingly. Migration happens when the following conditions are met: • The received packet’s SA is in the table but the associated source port information is different. • The received packet is good; the packet has no receiving errors and is of legal length. The look-up engine will update the existing record in the table with the new source port information. Aging The look-up engine will update the time stamp information of a record whenever the corresponding SA appears. The time stamp is used in the aging process. If a record is not updated for a period of time, the look-up engine will remove the record from the table. The look-up engine constantly performs the aging process and will continuously remove aging records. The aging period is 300 + 75 seconds. This feature can be enabled or disabled through Register 3 or by external pull-up or pull-down resistors on LED[5][2]. See “Register 3” section. Forwarding The KS8995MA/FQ will forward packets using an algorithm that is depicted in the following flowcharts. Figure 6 shows stage one of the forwarding algorithm where the search engine looks up the VLAN ID, static table, and Semptember 2008 25 M9999-091508 Micrel, Inc. KS8995MA/FQ dynamic table for the destination address, and comes up with “port to forward 1” (PTF1). PTF1 is then further modified by the spanning tree, IGMP snooping, port mirroring, and port VLAN processes to come up with “port to forward 2” (PTF2), as shown in Figure 7. This is where the packet will be sent. KS8995MA/FQ will not forward the following packets: • Error packets. These include framing errors, FCS errors, alignment errors, and illegal size packet errors. • 802.3x pause frames. The KS8995MA/FQ will intercept these packets and perform the appropriate actions. • “Local” packets. Based on destination address (DA) look-up. If the destination port from the look-up table matches the port where the packet was from, the packet is defined as “local.” Switching Engine The KS8995MA/FQ features a high-performance switching engine to move data to and from the MAC’s, packet buffers. It operates in store and forward mode, while the efficient switching mechanism reduces overall latency. The KS8995MA/FQ has a 64kB internal frame buffer. This resource is shared between all five ports. The buffer sharing mode can be programmed through Register 2. See “Register 2.” In one mode, ports are allowed to use any free buffers in the buffer pool. In the second mode, each port is only allowed to use 1/5 of the total buffer pool. There are a total of 512 buffers available. Each buffer is sized at 128B. Media Access Controller (MAC) Operation The KS8995MA/FQ strictly abides by IEEE 802.3 standards to maximize compatibility. Inter-Packet Gap (IPG) If a frame is successfully transmitted, the 96-bit time IPG is measured between the two consecutive MTXEN. If the current packet is experiencing collision, the 96-bit time IPG is measured from MCRS and the next MTXEN. Backoff Algorithm The KS8995MA/FQ implements the IEEE Std. 802.3 binary exponential back-off algorithm, and optional “aggressive mode” back off. After 16 collisions, the packet will be optionally dropped depending on the chip configuration in Register 3. See “Register 3.” Late Collision If a transmit packet experiences collisions after 512-bit times of the transmission, the packet will be dropped. Illegal Frames The KS8995MA/FQ discards frames less than 64 bytes and can be programmed to accept frames up to 1536 bytes in Register 4. For special applications, the KS8995MA/FQ can also be programmed to accept frames up to 1916 bytes in Register 4. Since the KS8995MA/FQ supports VLAN tags, the maximum sizing is adjusted when these tags are present. Flow Control The KS8995MA/FQ supports standard 802.3x flow control frames on both transmit and receive sides. On the receive side, if the KS8995MA/FQ receives a pause control frame, the KS8995MA/FQ will not transmit the next normal frame until the timer, specified in the pause control frame, expires. If another pause frame is received before the current timer expires, the timer will be updated with the new value in the second pause frame. During this period (being flow controlled), only flow control packets from the KS8995MA/FQ will be transmitted. On the transmit side, the KS8995MA/FQ has intelligent and efficient ways to determine when to invoke flow control. The flow control is based on availability of the system resources, including available buffers, available transmit queues and available receive queues. The KS8995MA/FQ flow controls a port that has just received a packet if the destination port resource is busy. The KS8995MA/FQ issues a flow control frame (XOFF), containing the maximum pause time defined in IEEE standard 802.3x. Once the resource is freed up, the KS8995MA/FQ sends out the other flow control frame (XON) with zero pause time to turn off the flow control (turn on transmission to the port). A hysteresis feature is also provided to prevent over-activation and deactivation of the flow control mechanism. The KS8995MA/FQ flow controls all ports if the receive queue becomes full. Semptember 2008 26 M9999-091508 Micrel, Inc. KS8995MA/FQ Start PTF1=NULL NO VLAN ID VALID? -Search VLAN table. -Ingress VLAN filtering -Discard NPVID check YES Search complete. Get PTF1 from static table. FOUND Search Static Table Search based on DA or DA+FID NOT FOUND Search complete. Get PTF1 from dynamic table. FOUND Dynamic Table Search This search is based on DA+FID NOT FOUND Search complete. Get PTF1 from VLAN table. PTF1 Figure 6. DA Look-Up Flowchart – Stage 1 PTF1 Spanning Tre e Process -Check receiving port's receive enable bit -Check destination port's transmit enable bit -Check whether packets are special (BPDU or specified) IGM P Proces s -Applied to MAC #1 to #4 -MAC#5 is reserved for microprocessor -IGM P will be forwarded to port 5 Port Mirror Process -RX Mirror -TX Mirror -RX or TX Mirror -RX and TX Mirror Port VLAN Membership Check PTF2 Figure 7. DA Resolution Flowchart – Stage 2 Semptember 2008 27 M9999-091508 Micrel, Inc. KS8995MA/FQ Half-Duplex Back Pressure The KS8995MA/FQ also provides a half-duplex back pressure option (note: this is not in IEEE 802.3 standards). The activation and deactivation conditions are the same as the ones given for full-duplex mode. If back pressure is required, the KS8995MA/FQ sends preambles to defer the other station's transmission (carrier sense deference). To avoid jabber and excessive deference as defined in IEEE 802.3 standard, after a certain period of time, the KS8995MA/FQ discontinues carrier sense but raises it quickly after it drops packets to inhibit other transmissions. This short silent time (no carrier sense) is to prevent other stations from sending out packets and keeps other stations in a carrier sense deferred state. If the port has packets to send during a back pressure situation, the carriersense-type back pressure is interrupted and those packets are transmitted instead. If there areno more packets to send, carrier-sense-type back pressure becomes active again until switch resources are free. If a collisionoccurs, the binary exponential backoff algorithm is skipped and carrier sense is generated immediately, reducing the chanceof further colliding and maintaining carrier sense to prevent reception of packets.To ensure no packet loss in 10BASE-T or 100BASE-TX half-duplex modes, the user must enable the following: • • Aggressive backoff (Register 3, bit 0) No excessive collision drop (Register 4, bit 3) • Back pressure (Register 4, bit 5) These bits are not set as the default because this is not the IEEE standard. Broadcast Storm Protection The KS8995MA/FQ has an intelligent option to protect the switch system from receiving too many broadcast packets. Broadcastpackets are normally forwarded to all ports except the source port and thus use too many switch resources (bandwidth andavailable space in transmit queues). The KS8995MA/FQ has the option to include “multicast packets” for storm control. Thebroadcast storm rate parameters are programmed globally and can be enabled or disabled on a per port basis. The rate is basedon a 50ms interval for 100BT and a 500ms interval for 10BT. At the beginning of each interval, the counter is cleared to zeroand the rate limit mechanism starts to count the number of bytes during the interval. The rate definition is described in Registers6 and 7. The default setting for Registers 6 and 7 is 0x4A (74 decimal). This is equal to a rate of 1%, calculated as follows: 148,800 frames/sec ¥ 50ms/interval ¥ 1% = 74 frames/interval (approx.) = 0x4A Semptember 2008 28 M9999-091508 Micrel, Inc. KS8995MA/FQ MII Interface Operation The media independent interface (MII) is specified by the IEEE 802.3 committee and provides a common interface betweenphysical layer and MAC layer devices. The KS8995MA/FQ provides two such interfaces. The MII-P5 interface is used to connectto the fifth PHY, whereas the MII-SW interface is used to connect to the fifth MAC. Each of these MII interfaces contains twodistinct groups of signals, one for transmission and the other for receiving. Table 1 describes the signals used in the MII-P5 interface. SNI Signal Description KS8995MA/FQ Signal MTXEN MTXER MTXD3 MTXD2 MTXD1 MTXD0 MTXC MCOL MCRS MRXDV MRXER MRXD3 MRXD2 MRXD1 MRXD0 MRXC MDC MDIO Transmit enable Transmit error Transmit data bit 3 Transmit data bit 2 Transmit data bit 1 Transmit data bit 0 Transmit clock Collision detection Carrier sense Receive data valid Receive error Receive data bit 3 Receive data bit 2 Receive data bit 1 Receive data bit 0 Receive clock Management data clock Management data I/O Table 1. MII – P5 Signals (PHY Mode) PMTXEN PMTXER PMTXD[3] PMTXD[2] PMTXD[1] PMTXD[0] PMTXC PCOL PCRS PMRXDV PMRXER PMRXD[3] PMRXD[2] PMRXD[1] PMRXD[0] PMRXC MDC MDIO Semptember 2008 29 M9999-091508 Micrel, Inc. KS8995MA/FQ The table 2 shows three connection ways, 1. The first and second columns show the connections for external MAC and MII-SW PHY mode. 2. The fourth and fifth columns show the connections for external PHY and MII-SW MAC mode. 3. The second and fifth columns show the back to back connections for two MII-SWs of two devices. PHY Mode Connection External MAC KS8995MA/FQ Signal Description MAC Mode Connection External PHY KS8995MA Only Signal MTXEN MTXER MTXD3 MTXD2 MTXD1 MTXD0 MTXC MCOL MCRS MRXDV MRXER MRXD3 MRXD2 MRXD1 MRXD0 MRXC SMTXEN SMTXER SMTXD[3] SMTXD[2] SMTXD[1] SMTXD[0] SMTXC SCOL SCRS SMRXDV Not used SMRXD[3] SMRXD[2] SMRXD[1] SMRXD[0] SMRXC Transmit enable Transmit error Transmit data bit 3 Transmit data bit 2 Transmit data bit 1 Transmit data bit 0 Transmit clock Collision detection Carrier sense Receive data valid Receive error Receive data bit 3 Receive data bit 2 Receive data bit 1 Receive data bit 0 Receive clock Table 2. MII – SW Signals MTXEN MTXER MTXD3 MTXD2 MTXD1 MTXD0 MTXC MCOL MCRS MRXDV MRXER MRXD3 MRXD2 MRXD1 MRXD0 MRXC SMRXDV Not used SMRXD[3] SMRXD[2] SMRXD[1] SMRXD[0] SMRXC SCOL SCRS SMTXEN SMTXER SMTXD[3] SMTXD[2] SMTXD[1] SMTXD[0] SMTXC The MII-P5 interface operates in PHY mode only, while the MII-SW interface operates in either MAC mode or PHY mode for KSZ8995MA. The MII-SW interface operates in PHY mode only for KSZ8995FQ. These interfaces are nibble-wide data interfaces and therefore run at 1/4 the network bit rate (not encoded). Additional signals on the transmit side indicate when data is valid or when an error occurs during transmission. Likewise, the receive side has indicators that convey when the data is valid and without physical layer errors. For half-duplex operation there is a signal that indicates a collision has occurred during transmission. Note that the signal MRXER is not provided on the MII-SW interface for PHY mode operation and the signal MTXER is not provided on the MII-SW interface for MAC mode operation. Normally MRXER would indicate a receive error coming from the physical layer device. MTXER would indicate a transmit error from the MAC device. These signals are not appropriate for this configuration. For PHY mode operation, if the device interfacing with the KS8995MA/FQ has an MRXER pin, it should be tied low. For MAC mode operation, if the device interfacing with the KS8995MA has an MTXER pin, it should be tied low. Semptember 2008 30 M9999-091508 Micrel, Inc. KS8995MA/FQ SNI Interface Operation The serial network interface (SNI) is compatible with some controllers used for network layer protocol processing. This interface can be directly connected to these types of devices. The signals are divided into two groups, one for transmission and the other for reception. The signals involved are described in Table 3. KS8995MA/FQ Signal SNI Signal Description TXEN TXD TXC COL CRS RXD RXC Transmit Enable Serial Transmit Data Transmit Clock Collision Detection Carrier Sense Serial Receive Data Receive Clock Table 3. SNI Signals SMTXEN SMTXD[0] SMTXC SCOL SMRXDV SMRXD[0] SMRXC This interface is a bit-wide data interface and therefore runs at the network bit rate (not encoded). An additional signal on the transmit side indicates when data is valid. Likewise, the receive side has an indicator that conveys when the data is valid. For half-duplex operation there is a signal that indicates a collision has occurred during transmission. Advanced Functionality Spanning Tree Support Port 5 is the designated port for spanning tree support. The other ports (port 1 – port 4) can be configured in one of the five spanning tree states via “transmit enable,” “receive enable,” and “learning disable” register settings in Registers 18, 34, 50, and 66 for ports 1, 2, 3, and 4, respectively. The following description shows the port setting and software actions taken for each of the five spanning tree states. Disable state: the port should not forward or receive any packets. Learning is disabled. Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1." Software action: the processor should not send any packets to the port. The switch may still send specific packets to the processor (packets that match some entries in the static table with “overriding bit” set) and the processor should discard those packets. Note: processor is connected to port 5 via MII interface. Address learning is disabled on the port in this state. Blocking state: only packets to the processor are forwarded. Learning is disabled. Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1" Software action: the processor should not send any packets to the port(s) in this state. The processor should program the “Static MAC table” with the entries that it needs to receive (e.g., BPDU packets). The “overriding” bit should also be set so that the switch will forward those specific packets to the processor. Address learning is disabled on the port in this state. Listening state: only packets to and from the processor are forwarded. Learning is disabled. Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1. "Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g. BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state, see “Special Tagging Mode” section for details. Address learning is disabled on the port in this state. Semptember 2008 31 M9999-091508 Micrel, Inc. KS8995MA/FQ Learning state: only packets to and from the processor are forwarded. Learning is enabled. Port setting: “transmit enable = 0, receive enable = 0, learning disable = 0.” Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g., BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state, see “Special Tagging Mode” section for details. Address learning is enabled on the port in this state. Forwarding state: packets are forwarded and received normally. Learning is enabled. Port setting: “transmit enable = 1, receive enable = 1, learning disable = 0.” Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g., BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state, see “Special Tagging Mode” section for details. Address learning is enabled on the port in this state. Special Tagging Mode The special tagging mode is designed for spanning tree protocol IGMP snooping and is flexible for use in other applications. The special tagging mode, similar to 802.1q, requires software to change network drivers to insert/modify/strip/interpret the special tag. This mode is enabled by setting both Register 11 bit 0 and Register 80 bit 2. 802.1q Tag Format TPID (tag protocol identifier, 0x8100) + TCI Special Tag Format STPID (special tag identifier, 0x8100) + TCI 0x810 + 4 bit for “port mask”) + TCI Table 4. Special Tagging Mode Format The STPID will only be seen and used on the port 5 interface, which should be connected to a processor. Packets from the processor to the switch should be tagged with STPID and the port mask defined as below: “0001” packet to port 1 only “0010” packet to port 2 only“0100” packet to port 3 only “1000” packet to port 4 only “0011” packet broadcast to port 1 and port 2 ...... “1111” packet broadcast to port 1, 2, 3 and 4. “0000” normal tag, will use the KS8995MA/FQ internal look-up result. Normal packets should use this setting. If packets from the processors do not have a tag, the KS8995MA/FQ will treat them as normal packets and an internal look-up will be performed.The KS8995MA/FQ uses a non-zero “port mask” to bypass the look-up result and override any port setting, regardless of port states (blocking, disable, listening, learning). Table 5 shows the egress rules when dealing with STPID. Semptember 2008 32 M9999-091508 Micrel, Inc. KS8995MA/FQ Ingress Tag Field (0x810+ port mask) Tx Port “Tag Insertion” 0 Tx Port “Tag Removal” 0 (0x810+ port mask) (0x810+ port mask) 0 1 1 0 (0x810+ port mask) 1 1 Not tagged Don’t care Don’t care Egress Action to Tag Field • Modify tag field to 0x8100. • Recalculate CRC. • No change to TCI if not null VID. • Replace VID with ingress (port 5) port VID if null VID. • (STPID + TCI) will be removed. • Padding to 64 bytes if necessary. • Recalculate CRC. • Modify tag field to 0x8100. • Recalculate CRC. • No change to TCI if not null VID. • Replace VID with ingress (port 5) port VID if null VID. • Modify tag field to 0x8100. • Recalculate CRC. • No change to TCI if not null VID. • Replace VID with ingress (port 5) port VID if null VID. Determined by the dynamic MAC address table. Table 5. STPID Egress Rules (Processor to Switch Port 5) For packets from regular ports (port 1 - port 4) to port 5, the port mask is used to tell the processor which port the packet was received on, defined as: “0001” from port 1, “0010” from port 2, “0100” from port 3, “1000” from port 4 No values other than the previous four defined should be received in this direction in the special mode. Table 6 shows the egress rule for this direction. Ingress Packets Egress Action to Tag Field Tagged with 0x8100 + TCI • • • • Modify TPID to 0x810 + “port mask,” which indicates source port. No change to TCI, if VID is not null. Replace null VID with ingress port VID. Recalculate CRC. Insert TPID to 0x810 + “port mask,” which indicates source port. Insert TCI with ingress port VID. Recalculate CRC. Table 6. STPID Egress Rules (Switch to Processor) Not tagged • • • IGMP Support There are two parts involved to support IGMP in Layer 2. The first part is “IGMP” snooping. The switch will trap IGMP packets and forward them only to the processor port. The IGMP packets are identified as IP packets (either Ethernet IP packets or IEEE 802.3 SNAP IP packets) AND IP version = 0x4 AND protocol number = 0x2. The second part is “multicast address insertion” in the static MAC table. Once the multicast address is programmed in the static MAC table, the multicast session will be trimmed to the subscribed ports, instead of broadcasting to all ports. To enable this feature, set Register 5 bit 6 to 1. Also “special tag mode” needs to be enabled, so that the processor knows which port the IGMP packet was received on. Enable “special tag mode” by setting both Register 11 bit 0 and Register 80 bit 2. Semptember 2008 33 M9999-091508 Micrel, Inc. KS8995MA/FQ Port Mirroring Support KS8995MA/FQ supports “port mirror” comprehensively as: 1. “Receive Only” mirror on a port. All the packets received on the port will be mirrored on the sniffer port. For example, port 1 is programmed to be “rx sniff,” and port 5 is programmed to be the “sniffer port.” A packet, received on port 1, is destined to port 4 after the internal look-up. The KS8995MA/FQ will forward the packet to both port 4 and port 5. KS8995MA/FQ can optionally forward even “bad” received packets to port 5. 2. “Transmit Only” mirror on a port. All the packets transmitted on the port will be mirrored on the sniffer port. For example, port 1 is programmed to be “tx sniff,” and port 5 is programmed to be the “sniffer port.” A packet, received on any of the ports, is destined to port 1 after the internal look-up. The KS8995MA/FQ will forward the packet to both ports 1 and 5. 3. “Receive and Transmit” mirror on two ports. All the packets received on port A AND transmitted on port B will be mirrored on the sniffer port. To turn on the “AND” feature, set Register 5 bit 0 to 1. For example, port 1 is programmed to be “rx sniff,” port 2 is programmed to be “transmit sniff,” and port 5 is programmed to be the “sniffer port.” A packet, received on port 1, is destined to port 4 after the internal look-up. The KS8995MA/FQ will forward the packet to port 4 only, since it does not meet the “AND” condition. A packet, received on port 1, is destined to port 2 after the internal look-up. The KS8995MA/FQ will forward the packet to both port 2 and port 5. Multiple ports can be selected to be “rx sniffed” or “tx sniffed.” And any port can be selected to be the “sniffer port.” All these per port features can be selected through Register 17. VLAN Support KS8995MA/FQ supports 16 active VLANs out of 4096 possible VLANs specified in IEEE 802.1q. KS8995MA/FQ provides a 16-entry VLAN table, which converts VID (12 bits) to FID (4 bits) for address look-up. If a non-tagged or null-VID-tagged packet is received, the ingress port VID is used for look-up. In the VLAN mode, the look-up process starts with VLAN table look-up to determine whether the VID is valid. If the VID is not valid, the packet will be dropped and its address will not be learned. If the VID is valid, FID is retrieved for further look-up. FID+DA is used to determine the destination port. FID+SA is used for learning purposes. DA found in Static MAC table No USE FID Flag? Don’t care FID Match? DA+FID found in Dynamic MAC table No Action Don’t care Don’t care Don’t care No No Yes No Yes Yes Yes Yes Don’t care 0 1 1 1 Yes Don’t care No Yes Don’t care Broadcast to the membership ports defined in the VLAN table bit [20:16]. Send to the destination port defined in the dynamic MAC table bit [54:52]. Send to the destination port(s) defined in the static MAC table bit [52:48]. Broadcast to the membership ports defined in the VLAN table bit [20:16]. Send to the destination port defined in the dynamic MAC table bit [54:52]. Send to the destination port(s) defined in the static MAC table bit [52:48]. Table 7. FID+DA Look-Up in the VLAN Mode Semptember 2008 34 M9999-091508 Micrel, Inc. KS8995MA/FQ SA+FID found in Dynamic MAC table No Action The SA+FID will be learned into the dynamic table. Time stamp will be updated. Table 8. FID+SA Look-Up in the VLAN Mode Yes Advanced VLAN features are also supported in KS8995MA/FQ, such as “VLAN ingress filtering” and “discard non PVID” defined in Register 18 bit 6 and bit 5. These features can be controlled on a port basis. Rate Limit Support KS8995MA/FQ supports hardware rate limiting on “receive” and “transmit” independently on a per port basis. It also supports rate limiting in a priority or non-priority environment. The rate limit starts from 0Kbps and goes up to the line rate in steps of 32Kbps. The KS8995MA/FQ uses one second as an interval. At the beginning of each interval, the counter is cleared to zero, and the rate limit mechanism starts to count the number of bytes during this interval. For receive, if the number of bytes exceeds the programmed limit, the switch will stop receiving packets on the port until the “one second” interval expires. There is an option provided for flow control to prevent packet loss. If the rate limit is programmed greater than or equal to 128Kbps and the byte counter is 8K bytes below the limit, the flow control will be triggered. If the rate limit is programmed lower than 128Kbps and the byte counter is 2K bytes below the limit, the flow control will be triggered. For transmit, if the number of bytes exceeds the programmed limit, the switch will stop transmitting packets on the port until the “one second” interval expires. If priority is enabled, the KS8995MA/FQ can support different rate controls for both high priority and low priority packets. This can be programmed through Registers 21–27. Semptember 2008 35 M9999-091508 Micrel, Inc. KS8995MA/FQ Configuration Interface The KS8995MA/FQ can function as a managed switch or unmanaged switch. If no EEPROM or micro-controller exists, the KS8995MA/FQ will operate from its default setting. Some default settings are configured via strap in options as indicated in the table below. Pin # Pin Name PU/PD(1) Description(1) 1 45 46 MDI-XDIS MUX1 MUX2 Ipd NC NC Disable auto MDI/MDI-X. PD = (default) = normal operation PU = disable auto MDI/MDI-X on all ports. Factory test pins. MUX1 and MUX2 should be left unconnected for normal operation. Mode MUX1 MUX2 Normal Operation 62 63 64 65 66 67 68 80 81 82 83 PMRXD3 PMRXD2 PMRXD1 PMRXD0 PMRXER PCRS PCOL SMRXD3 SMRXD2 SMRXD1 SMRXD0 Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O NC NC PHY[5] MII receive bit 3. Strap option: PD (default) = enable flow control; PU = disable flow control. PHY[5] MII receive bit 2. Strap option: PD (default) = disable back pressure; PU = enable back pressure. PHY[5] MII receive bit 1. Strap option: PD (default) = drop excessive collision packets; PU = does not drop excessive collision packets. PHY[5] MII receive bit 0. Strap option: PD (default) = disable aggressive backoff algorithm in half-duplex mode; PU = enable for performance enhancement. PHY[5] MII receive error. Strap option: PD (default) = 1522/1518 bytes; PU = packet size up to 1536 bytes. PHY[5] MII carrier sense/strap option for port 4 only. PD (default) = force halfduplex if auto-negotiation is disabled or fails. PU = force full-duplex if autonegotiation is disabled or fails. Refer to register 76. PHY[5] MII collision detect/strap option for port 4 only. PD (default) = no force flow control. PU = force flow control. Refer to register 66. Switch MII receive bit 3. Strap option: PD (default) = disable switch MII fullduplex flow control; PU = enable switch MII full-duplex flow control. Switch MII receive bit 2. Strap option: PD (default) = switch MII in full-duplex mode; PU = switch MII in half-duplex mode. Switch MII receive bit 1. Strap option: PD (default) = switch MII in 100Mbps mode; PU = switch MII in 10Mbps mode. Switch MII receive bit 0. Strap option: LED mode PD (default) = mode 0; PU = mode 1. See “Register 11.” Mode 0 Mode 1 LEDX_2 LEDX_1 LEDX_0 Notes: 1. NC = No connect. Ipd = Input w/internal pull-down. Ipd/O = Input w/internal pull-down during reset, output pin otherwise. Fulld = Full duplex. Lnk/Act Fulld/Col Speed 100Lnk/Act 10Lnk/Act Fulld Semptember 2008 36 M9999-091508 Micrel, Inc. KS8995MA/FQ Pin # Pin Name PU/PD(1) Description(1) 86 SCONF1 Ipd Dual MII configuration pin. For the Switch MII, KSZ8995MA supports both MAC mode and PHY mode, KSZ8995FQ supports PHY mode only. Pins 91, 86, 87 Switch MII PHY [5] MII 000 001 010 011 100 101 110 111 87 90 91 113 SCONF0 LED5-2 LED5-1 PS1 Ipd Ipu/O Ipu/O Ipd Dual MII configuration pin. Disable, Otri PHY Mode MII MAC Mode MII PHY Mode SNI Disable PHY Mode MII MAC Mode MII PHY Mode SNI Disable, Otri Disable, Otri Disable, Otri Disable, Otri Disable PHY Mode MII PHY Mode MII PHY Mode MII LED indicator 2. Strap option: Aging setup. See “Aging” section PU (default) = aging enable; PD = aging disable. LED indicator 1. Strap option: PU (default): enable PHY[5] MII I/F. PD: tristate all PHY[5] MII output. See “Pin 86 SCONF1.” Serial bus configuration pin. For this case, if the EEPROM is not present, the KS8995MA/FQ will start itself with the PS[1:0] =00 default register values . Pin Configuration Serial Bus Configuration PS[1:0]=00 PS[1:0]=01 PS[1:0]=10 PS[1:0]=11 I2C Master Mode for EEPROM Reserved SPI Slave Mode for CPU Interface Factory Test Mode (BIST) 114 128 PS0 TEST2 Ipd NC Serial bus configuration pin. See “Pin 113.” NC for normal operation. Factory test pin. Notes: 1. NC = No connect. Ipd = Input w/internal pull-down. Ipd/O = Input w/internal pull-down during reset, output pin otherwise. Otri = Output tristated. Semptember 2008 37 M9999-091508 Micrel, Inc. KS8995MA/FQ I2C Master Serial Bus Configuration If a 2-wire EEPROM exists, the KS8995MA/FQ can perform more advanced features like broadcast storm protection and rate control. The EEPROM should have the entire valid configuration data from Register 0 to Register 109 defined in the “Memory Map,” except the status registers. After reset, the KS8995MA/FQ will start to read all 110 registers sequentially from the EEPROM. The configuration access time (tprgm) is less than 15ms as shown in Figure 8. RST_N SCL SDA .... .... .... t prgm