KS8995MI

KS8995M Micrel KS8995M Integrated 5-Port 10/100 Managed Switch Rev 1.12 General Description The KS8995M is a highly integrated Layer-2 managed switch with optimized BOM (Bill of Materials) cost for low port count, cost-sensitive 10/100Mbps switch systems. It also provides an extensive feature set such as tag/port-based VLAN, QoS (Quality of Service) priority, management, MIB counters, dual MII interfaces and CPU control/data interfaces to effectively address both current and emerging Fast Ethernet applications. The KS8995M contains five 10/100 transceivers with patented mixed-signal low-power technology, five MAC (Media Access Control) units, a high-speed non-blocking switch fabric, a dedicated address look-up engine, and an on-chip frame buffer memory. All PHY units support 10BaseT and 100BaseTX. In addition, two of the PHY units support 100BaseFX (Ports 4 and 5). All support documentation can be found on Micrel’s web site at www.micrel.com. Features • Integrated switch with five MACs and five Fast Ethernet transceivers fully compliant to IEEE 802.3u standard • Shared memory based switch fabric with fully nonblocking configuration • 1.4Gbps high-performance memory bandwidth • 10BaseT, 100BaseTX and 100BaseFX modes (FX in Ports 4 and 5) • Dual MII configuration: MII-Switch (MAC or PHY mode MII) and MII-P5 (PHY mode MII) • IEEE 802.1q tag-based VLAN (16 VLANs, full-range VID) for DMZ port, WAN/LAN separation or inter-VLAN switch links • VLAN ID tag/untag options, per-port basis • Programmable rate limiting 0Mbps to 100Mbps, ingress and egress port, rate options for high and low priority, per-port-basis • Flow control or drop packet rate limiting (ingress port) • Integrated MIB counters for fully compliant statistics gathering, 34 MIB counters per port Functional Diagram Auto MDI/MDIX Auto MDI/MDIX Auto MDI/MDIX Auto MDI/MDIX Auto MDI/MDIX MII-P5 MDC, MDI/O MII-SW or SNI Control Reg I/F LED0[5:1] LED1[5:1] LED2[5:1] 10/100 T/Tx 1 10/100 T/Tx 2 10/100 T/Tx 3 10/100 T/Tx/Fx 4 10/100 T/Tx/Fx 5 10/100 MAC 1 10/100 MAC 2 10/100 MAC 3 10/100 MAC 4 10/100 MAC 5 SNI SPI FIFO, Flow Control, VLAN Tagging, Priority 1K look-up Engine Queue Mgmnt Buffer Mgmnt Frame Buffers MIB Counters EEPROM I/F LED I/F Control Registers KS8995M Micrel, Inc. • 1849 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 944-0970 • http://www.micrel.com December 2003 1 M9999-120403 KS8995M Micrel Features (continued) • Enable/Disable option for huge frame size up to 1916 bytes per frame • IGMP v1/v2 snooping for multicast packet filtering • Special tagging mode to send CPU info on ingress packet’s port value • SPI slave (complete) and MDIO (MII PHY only) serial management interface for control of register configuration • MAC-id based security lock option • Control registers configurable on-the-fly (port-priority, 802.1p/d/q, AN...) • CPU read access to MAC forwarding table entries • 802.1d Spanning Tree Protocol • Port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port or MII • Broadcast storm protection with percent control – global and per-port basis • Optimization for fiber-to-copper media conversion • Full-chip hardware power-down support (register configuration not saved) • Per-port based software power-save on PHY (idle link detection, register configuration preserved) • QoS/CoS packets prioritization supports: per port, 802.1p and DiffServ based • 802.1p/q tag insertion or removal on a per port basis (egress) • MDC and MDI/O interface support to access the MII PHY control registers (not all control registers) • MII local loopback support • On-chip 64Kbyte memory for frame buffering (not shared with 1K unicast address table) • Wire-speed reception and transmission • Integrated look-up engine with dedicated 1K MAC addresses • Full duplex IEEE 802.3x and half-duplex back pressure flow control • Comprehensive LED support • 7-wire SNI support for legacy MAC interface • Automatic MDI/MDI-X crossover for plug-and-play • Disable Automatic MDI/MDI-X option • Low power: Core: 1.8V I/O: 2.5V or 3.3V • 0.18µm CMOS technology • Commercial temperature range: 0°C to +70°C • Industrial temperature range: –40°C to +85°C • Available in 128-pin PQFP package Applications • • • • • • • • • Broadband gateway/firewall/VPN Integrated DSL or cable modem multi-port router Wireless LAN access point plus gateway Home networking expansion Standalone 10/100 switch Hotel/campus/MxU gateway Enterprise VoIP gateway/phone FTTx customer premise equipment Managed media converter Ordering Information Part Number KS8995M KSZ8995M KS8995MI Temperature Range 0°C to +70°C 0°C to +70°C –40°C to +85°C Package 128-Pin PQFP 128-Pin PQFP Lead Free 128-Pin PQFP M9999-120403 2 December 2003 KS8995M Micrel Revision History Revision 1.00 1.01 1.02 1.03 1.04 Date 11/05/01 11/09/01 12/03/01 12/12/01 12/13/01 Summary of Changes Created Pinout Mux1/2, DVCC-IO 2.5/3.3V, feature list, register spec 11-09 Editorial changes, added new register and MIB descriptions. Added paragraph describing TOS registers. Imported functional descriptions. Formatting. Incorporate changes per engineering feedback as well as updating functional descriptions and adding new timing information. Changed Rev. and For. Modes to PHY and MAC modes respectively. Added MIIM clarification in “MII Management Interface” section. Reformatted section sequence. Added hex register addresses. Added advertisement ability descriptions. Inserted switch forwarding flow charts. Added new KS8995M block diagram, editorial changes, register descriptions changes and crossreferences from functional descriptions to register and strap in options. Changed FXSD pins to inputs, added new descriptions to “Configuration Interfaces” section. Edited pin descriptions. Editorial changes in “Dynamic MAC Address table and “MIB Counters.” Updated figure 2 flowchart. Updated table 2 for MAC mode connections. Separate static MAC bit assignments for read and write. Edited read and write examples to MAC tables and MIB counters. Changed Table 3 KS8995M signals to “S” suffix. Changed aging description in Register 2, bit 0. Changed “Port Registers” section and listed all port register addresses. Changed port control 11 description for bits [7:5]. Changed MIB counter descriptions. Changed MII setting in “Pin Descriptions.” Changed pu/pd descriptions for SMRXD2. “Register 18,” changed pu/pd description for forced flow control. “Illegal Frames. ” Edited large packet sizes back in. “Elecrical Characteristics,” Added in typical supply current numbers for 100 BaseTX and 10 BaseTX operation. “Register 18,” Added in note for illegal half-duplex, force flow control. “Pin Description,” Added extra X1 clock input description. “Elecrical Characteristics,” Updated to chip only current numbers. Added SPI Timing. Feature Highlights. “Pin Description,” changed SMRXC and SMTXC to I/O. Input in MAC mode, output in PHY mode MII. “Elecrical Characteristics,” modified current consumption to chip only numbers. “Half-Duplex Back Pressure,” added description for no dropped packets in half-duplex mode. Added recommended operating conditions. Added Idle mode current consumption in “Elecrical Characteristics,” added “Selection of Isolation Transformers,” Added 3.01kΩ resistor instructions for ISET “Pin Description” section. Changed Polarity of transmit pairs in “Pin Description.” Changed description for Register 2, bit 1, in “Register Description” section. Added “Reset Timing” section. “Register 3” changed 802.1x to 802.3x. “Register 6,” changed default column to disable flow control for pull-down, and enable flow control for pull-up. “Register 29” and “Register 0” indicate loop back is at the PHY. Added description to register 4 bit 2 to indicate that STPID packets from CPU to normal ports are not allowed as 1522 byte tag packets. Fixed dynamic MAC address example errors in “Dynamic MAC Address Table.” Changed definition of forced MDI, MDIX in section “Register 29,” “Register 30” and “Register 0.” Added “Part Ordering Information.” Added Ambient operating temperature for KS8995MI Changed pin 120 description to NC. Changed SPIQ pin description to Otri. Changed logo. Changed contact information. 1.05 1.06 1.07 1.08 12/18/01 12/20/01 1/22/01 3/1/02 1.09 5/17/02 1.10 7/29/02 1.11 12/17/02 1.12 3/10/03 December 2003 3 M9999-120403 KS8995M Micrel Table of Contents System Level Applications ......................................................................................................................................... 7 Pin Description (by Number) ...................................................................................................................................... 9 Pin Description (by Name) ........................................................................................................................................ 15 Pin Configuration ...................................................................................................................................................... 21 Introduction ........................................................................................................................................................... 22 Functional Overview: Physical Layer Transceiver ................................................................................................ 22 100BaseTX Transmit ........................................................................................................................................... 22 100BaseTX Receive ............................................................................................................................................ 22 PLL Clock Synthesizer ......................................................................................................................................... 22 Scrambler/De-scrambler (100BaseTX only) ........................................................................................................ 22 100BaseFX Operation ......................................................................................................................................... 22 100BaseFX Signal Detection ............................................................................................................................... 22 100BaseFX Far End Fault ................................................................................................................................... 23 10BaseT Transmit ............................................................................................................................................... 23 10BaseT Receive ................................................................................................................................................ 23 Power Management ............................................................................................................................................. 23 MDI/MDI-X Auto Crossover ................................................................................................................................. 23 Auto-Negotiation .................................................................................................................................................. 23 Functional Overview: Switch Core .......................................................................................................................... 24 Address Look-Up ................................................................................................................................................. 24 Learning ........................................................................................................................................................... 24 Migration ........................................................................................................................................................... 24 Aging ........................................................................................................................................................... 24 Forwarding ........................................................................................................................................................... 24 Switching Engine ................................................................................................................................................. 24 MAC Operation .................................................................................................................................................... 24 Inter-Packet Gap (IPG) ................................................................................................................................ 24 Backoff Algorithm ......................................................................................................................................... 24 Late Collision ............................................................................................................................................... 26 Illegal Frames .............................................................................................................................................. 26 Flow Control ................................................................................................................................................. 26 Half-Duplex Back Pressure .......................................................................................................................... 26 Broadcast Storm Protection ......................................................................................................................... 26 MII Interface Operation ........................................................................................................................................ 26 SNI Interface Operation ....................................................................................................................................... 28 Advanced Functionality ............................................................................................................................................ 28 Spanning Tree Support ........................................................................................................................................ 28 Special Tagging Mode ......................................................................................................................................... 29 IGMP Support ...................................................................................................................................................... 30 Port Mirroring Support ......................................................................................................................................... 31 VLAN Support ...................................................................................................................................................... 31 Rate Limit Support ............................................................................................................................................... 32 Configuration Interface ........................................................................................................................................ 33 I2C Master Serial Bus Configuration ............................................................................................................ 35 SPI Slave Serial Bus Configuration ............................................................................................................. 35 MII Management Interface (MIIM) ....................................................................................................................... 38 M9999-120403 4 December 2003 KS8995M Register Description ................................................................................................................................................. Global Registers .................................................................................................................................................. Register 0 (0x00): Chip ID0 ......................................................................................................................... Register 1 (0x01): Chip ID1/Start Switch ..................................................................................................... Register 2 (0x02): Global Control 0 ............................................................................................................. Register 3 (0x03): Global Control 1 ............................................................................................................. Register 4 (0x04): Global Control 2 ............................................................................................................. Register 5 (0x05): Global Control 3 ............................................................................................................. Register 6 (0x06): Global Control 4 ............................................................................................................. Register 7 (0x07): Global Control 5 ............................................................................................................. Register 8 (0x08): Global Control 6 ............................................................................................................. Register 9 (0x09): Global Control 7 ............................................................................................................. Register 10 (0x0A): Global Control 8 ........................................................................................................... Register 11 (0x0B): Global Control 9 ........................................................................................................... Port Registers ...................................................................................................................................................... Register 16 (0x10): Port 1 Control 0 ........................................................................................................... Register 17 (0x11): Port 1 Control 1 ........................................................................................................... Register 18 (0x12): Port 1 Control 2 ........................................................................................................... Register 19 (0x13): Port 1 Control 3 ........................................................................................................... Register 20 (0x14): Port 1 Control 4 ........................................................................................................... Register 21 (0x15): Port 1 Control 5 ........................................................................................................... Register 22 (0x16): Port 1 Control 6 ........................................................................................................... Register 23 (0x17): Port 1 Control 7 ........................................................................................................... Register 24 (0x18): Port 1 Control 8 ........................................................................................................... Register 25 (0x19): Port 1 Control 9 ........................................................................................................... Register 26 (0x1A): Port 1 Control 10 ......................................................................................................... Register 27 (0x1B): Port 1 Control 11 ......................................................................................................... Register 28 (0x1C): Port 1 Control 12 ......................................................................................................... Register 29 (0x1D): Port 1 Control 13 ......................................................................................................... Register 30 (0x1E): Port 1 Status 0 ............................................................................................................ Register 31 (0x1F): Port 1 Status 1 ............................................................................................................. Advanced Control Registers ................................................................................................................................ Register 96 (0x60): TOS Priority Control Register 0 ................................................................................... Register 97 (0x61): TOS Priority Control Register 1 ................................................................................... Register 98 (0x62): TOS Priority Control Register 2 ................................................................................... Register 99 (0x63): TOS Priority Control Register 3 ................................................................................... Register 100 (0x64): TOS Priority Control Register 4 ................................................................................. Register 101 (0x65): TOS Priority Control Register 5 ................................................................................. Register 102 (0x66): TOS Priority Control Register 6 ................................................................................. Register 103 (0x67): TOS Priority Control Register 7 ................................................................................. Register 104 (0x68): MAC Address Register 0 ........................................................................................... Register 105 (0x69): MAC Address Register 1 ........................................................................................... Register 106 (0x6A): MAC Address Register 2 ........................................................................................... Register 107 (0x6B): MAC Address Register 3 ........................................................................................... Register 108 (0x6C): MAC Address Register 4 .......................................................................................... Register 109 (0X6D): MAC Address Register 5 .......................................................................................... Register 110 (0x6E): Indirect Access Control 0 .......................................................................................... Register 111 (0x6F): Indirect Access Control 1 .......................................................................................... December 2003 5 Micrel 39 39 39 39 40 40 41 42 42 43 43 43 43 43 44 44 44 45 46 46 46 46 46 47 47 47 47 48 49 49 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 51 51 M9999-120403 KS8995M Micrel Register 112 (0x70): Indirect Data Register 8 ............................................................................................. 51 Register 113 (0x71): Indirect Data Register 7 ............................................................................................. 51 Register 114 (0x72): Indirect Data Register 6 ............................................................................................. 51 Register 115 (0x73): Indirect Data Register 5 ............................................................................................. 51 Register 116 (0x74): Indirect Data Register 4 ............................................................................................. 51 Register 117 (0x75): Indirect Data Register 3 ............................................................................................. 51 Register 118 (0x76): Indirect Data Register 2 ............................................................................................. 51 Register 119 (0x77): Indirect Data Register 1 ............................................................................................. 51 Register 120 (0x78): Indirect Data Register 0 ............................................................................................. 51 Register 121 (0x79): Digital Testing Status 0 .............................................................................................. 51 Register 122 (0x7A): Digital Testing Status 1 ............................................................................................. 51 Register 123 (0x7B): Digital Testing Control 0 ............................................................................................ 51 Register 124 (0x7C): Digital Testing Control 1 ............................................................................................ 51 Register 125 (0x7D): Analog Testing Control 0 .......................................................................................... 51 Register 126 (0x7E): Analog Testing Control 1 .......................................................................................... 52 Register 127 (0x7F): Analog Testing Status ............................................................................................... 52 Static MAC Address .................................................................................................................................................. 53 VLAN Address ........................................................................................................................................................... 55 Dynamic MAC Address ............................................................................................................................................. 56 MIB Counters ........................................................................................................................................................... 57 MIIM Registers ........................................................................................................................................................... 60 Register 0: MII Control ................................................................................................................................ 60 Register 1: MII Status ................................................................................................................................. 61 Register 2: PHYID HIGH ............................................................................................................................. 61 Register 3: PHYID LOW ............................................................................................................................. 61 Register 4: Advertisement Ability ................................................................................................................ 61 Register 5: Link Partner Ability .................................................................................................................... 62 Absolute Maximum Ratings ..................................................................................................................................... 63 Operating Ratings ..................................................................................................................................................... 63 Electrical Characteristics .......................................................................................................................................... 63 Timing Diagrams ....................................................................................................................................................... 65 Selection of Isolation Transformers ........................................................................................................................ 72 Qualified Magnetic Lists ........................................................................................................................................... 72 Package Information ................................................................................................................................................. 73 M9999-120403 6 December 2003 KS8995M Micrel System Level Applications 10/100 MAC 1 Switch Controller On-Chip Frame Buffers 10/100 PHY 1 10/100 PHY 2 10/100 PHY 3 10/100 PHY 4 10/100 PHY 5 1-port WAN I/F 4-port LAN 10/100 MAC 2 10/100 MAC 3 10/100 MAC 4 10/100 MAC 5 SPI/GPIO SPI Ethernet MAC CPU Ethernet MAC MII-SW MII-P5 External WAN port PHY not needed Figure 1. Broadband Gateway 10/100 MAC 1 Switch Controller On-Chip Frame Buffers 10/100 PHY 1 10/100 PHY 2 10/100 PHY 3 10/100 PHY 4 10/100 PHY 5 4-port LAN 10/100 MAC 2 10/100 MAC 3 10/100 MAC 4 10/100 MAC 5 WAN PHY & AFE (xDSL, CM...) CPU SPI/GPIO SPI MII-SW MII-P5 Ethernet MAC Figure 2. Integrated Broadband Router December 2003 7 M9999-120403 KS8995M Micrel 10/100 MAC 1 Switch Controller On-Chip Frame Buffers 10/100 PHY 1 10/100 PHY 2 10/100 PHY 3 10/100 PHY 4 10/100 PHY 5 5-port LAN 10/100 MAC 2 10/100 MAC 3 10/100 MAC 4 10/100 MAC 5 Figure 3. Standalone Switch M9999-120403 8 December 2003 KS8995M Micrel Pin Description (by Number) Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Pin Name TEST1 GNDA VDDAR RXP1 RXM1 GNDA TXM1 TXP1 VDDAT RXP2 RXM2 GNDA TXM2 TXP2 VDDAR GNDA ISET VDDAT RXP3 RXM3 GNDA TXM3 TXP3 VDDAT RXP4 RXM4 GNDA TXM4 TXP4 GNDA VDDAR P I I Gnd O O P I I Gnd O O Gnd P 4 4 4 4 3 3 3 3 Type(1) NC Gnd P I I Gnd O O P I I Gnd O O P Gnd 2 2 2 2 1 1 1 1 Port Pin Function NC for normal operation. Factory test pin. Analog ground 1.8V analog VDD Physical receive signal + (differential) Physical receive signal - (differential) Analog ground Physical transmit signal - (differential) Physical transmit signal + (differential) 2.5V analog VDD Physical receive signal + (differential) Physical receive signal - (differential) Analog ground Physical transmit signal - (differential) Physical transmit signal + (differential) 1.8V analog VDD Analog ground Set physical transmit output current. Pull-down with a 3.01kΩ 1% resistor. 2.5V analog VDD Physical receive signal + (differential) Physical receive signal - (differential) Analog ground Physical transmit signal - (differential) Physical transmit signal + (differential) 2.5V analog VDD Physical receive signal + (differential) Physical receive signal - (differential) Analog ground Physical transmit signal - (differential) Physical transmit signal + (differential) Analog ground 1.8V analog VDD Note: 1. P = Power supply I = Input O = Output I/O = Bi-directional Gnd = Ground Ipu = Input w/ internal pull-up Ipd = Input w/ internal pull-down Ipd/O = Input w/ internal pull-down during reset, output pin otherwise Ipu/O = Input w/ internal pull-up during reset, output pin otherwise PU = Strap pin pull-up PD = Strap pin pull-down Otri = Output tristated NC = No Connect December 2003 9 M9999-120403 KS8995M Pin Number 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Pin Name RXP5 RXM5 GNDA TXM5 TXP5 VDDAT FXSD5 FXSD4 GNDA VDDAR GNDA VDDAR GNDA MUX1 MUX2 Type(1) I I Gnd O O P I I Gnd P Gnd P Gnd NC NC 5 4 5 5 Port 5 5 Pin Function Physical receive signal + (differential) Physical receive signal - (differential) Analog ground Physical transmit signal - (differential) Physical transmit signal + (differential) 2.5V analog VDD Fiber signal detect/factory test pin Fiber signal detect/factory test pin Analog ground 1.8V analog VDD Analog ground 1.8V analog VDD Analog ground MUX1 and MUX2 should be left unconnected for normal operation. They are factory test pins. Mode Normal Operation Remote Analog Loopback Mode for Testing only Reserved Power Save Mode for Testing only 47 48 49 50 51 52 53 54 55 56 57 58 Note: 1. P = Power supply I = Input O = Output I/O = Bi-directional Gnd = Ground Ipu = Input w/ internal pull-up Ipd = Input w/ internal pull-down Ipd/O = Input w/ internal pull-down during reset, output pin otherwise Ipu/O = Input w/ internal pull-up during reset, output pin otherwise PU = Strap pin pull-up PD = Strap pin pull-down Otri = Output tristated NC = No Connect Micrel Mux1 NC 0 1 1 Mux2 NC 1 0 1 PWRDN_N RESERVE GNDD VDDC PMTXEN PMTXD3 PMTXD2 PMTXD1 PMTXD0 PMTXER PMTXC GNDD Ipu NC Gnd P Ipd Ipd Ipd Ipd Ipd Ipd O Gnd 5 5 5 5 5 5 5 Full-chip power down. Active low. Reserved pin. No connect. Digital ground 1.8V digital core VDD PHY[5] MII transmit enable PHY[5] MII transmit bit 3 PHY[5] MII transmit bit 2 PHY[5] MII transmit bit 1 PHY[5] MII transmit bit 0 PHY[5] MII transmit error PHY[5] MII transmit clock. PHY mode MII. Digital ground M9999-120403 10 December 2003 KS8995M Pin Number 59 60 61 62 63 64 65 Pin Name VDDIO PMRXC PMRXDV PMRXD3 PMRXD2 PMRXD1 PMRXD0 Type(1) P O Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O 5 5 5 5 5 5 Port Pin Function 3.3/2.5V digital VDD for digital I/O circuitry PHY[5] MII receive clock. PHY mode MII PHY[5] MII receive data valid PHY[5] MII receive bit 3. Strap option: PD (default) = enable flow control; PU = disable flow control. PHY[5] MII receive bit 2. Strap option: PD (default) = disable back pressure; PU = enable back pressure. Micrel PHY[5] MII receive bit 1. Strap option: PD (default) = drop excessive collision packets; PU = does not drop excessive collision packets. PHY[5] MII receive bit 0. Strap option: PD (default) = disable aggressive back-off algorithm in half-duplex mode; PU = enable for performance enhancement. PHY[5] MII receive error. Strap option: PD (default) = 1522/1518 bytes; PU = packet size up to 1536 bytes. PHY[5] MII carrier sense/Force duplex mode. See “Register 76” for port 4 only. PD (default) = Force half-duplex if auto-negotiation is disabled or fails. PU = Force full-duplex if auto-negotiation is disabled or fails. PHY[5] MII collision detect/ Force flow control. See “Register 66” for port 4 only. PD (default) = No force flow control. PU = Force flow control. Switch MII transmit enable Switch MII transmit bit 3 Switch MII transmit bit 2 Switch MII transmit bit 1 Switch MII transmit bit 0 Switch MII transmit error Switch MII transmit clock. Input in MAC mode, output in PHY mode MII. Digital ground 3.3/2.5V digital VDD for digital I/O circuitry Switch MII receive clock. Input in MAC mode, output in PHY mode MII. Switch MII receive data valid Switch MII receive bit 3. Strap option: PD (default) = Disable Switch MII full-duplex flow control; PU = Enable Switch MII full-duplex flow control. Switch MII receive bit 2. Strap option: PD (default) = Switch MII in fullduplex mode; PU = Switch MII in half-duplex mode. 66 67 PMRXER PCRS Ipd/O Ipd/O 5 5 68 PCOL Ipd/O 5 69 70 71 72 73 74 75 76 77 78 79 80 81 Note: 1. P = Power supply I = Input O = Output I/O = Bi-directional Gnd = Ground SMTXEN SMTXD3 SMTXD2 SMTXD1 SMTXD0 SMTXER SMTXC GNDD VDDIO SMRXC SMRXDV SMRXD3 SMRXD2 Ipd Ipd Ipd Ipd Ipd Ipd I/O Gnd P I/O Ipd/O Ipd/O Ipd/O Ipu = Input w/ internal pull-up Ipd = Input w/ internal pull-down Ipd/O = Input w/ internal pull-down during reset, output pin otherwise Ipu/O = Input w/ internal pull-up during reset, output pin otherwise PU = Strap pin pull-up PD = Strap pin pull-down Otri = Output tristated NC = No Connect December 2003 11 M9999-120403 KS8995M Pin Number 82 83 Pin Name SMRXD1 SMRXD0 Type(1) Ipd/O Ipd/O Port Pin Function Switch MII receive bit 1. Strap option: PD (default) = Switch MII in 100Mbps mode; PU = Switch MII in 10Mbps mode. Switch MII receive bit 0; Strap option: LED Mode PD (default) = Mode 0; PU = Mode 1. See “Register 11.” Mode 0 LEDX_2 LEDX_1 LEDX_0 84 85 86 SCOL SCRS SCONF1 Ipd/O Ipd/O Ipd Switch MII collision detect Switch MII carrier sense Dual MII configuration pin Pin# (91, 86, 87): 000 001 010 011 100 101 110 111 87 88 89 90 91 92 93 94 95 96 97 SCONF0 GNDD VDDC LED5-2 LED5-1 LED5-0 LED4-2 LED4-1 LED4-0 LED3-2 LED3-1 Ipd Gnd P Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O 5 5 5 4 4 4 3 3 Switch MII Disable, Otri PHY Mode MII MAC Mode MII PHY Mode SNI Disable PHY Mode MII MAC Mode MII PHY Mode SNI PHY [5] MII Disable, Otri Disable, Otri Disable, Otri Disable, Otri Disable PHY Mode MII PHY Mode MII PHY Mode MII Lnk/Act Fulld/Col Speed Micrel Mode 1 100Lnk/Act 10Lnk/Act Fulld Dual MII configuration pin Digital ground 1.8V digital core VDD LED indicator 2. Strap option: Aging setup. See “Aging” section PU (default) = Aging Enable; PD = Aging disable. LED indicator 1. Strap option: PU (default): enable PHY MII I/F PD: tristate all PHY MII output. See “pin# 86 SCONF1.” LED indicator 0 LED indicator 2 LED indicator 1 LED indicator 0 LED indicator 2 LED indicator 1 Note: 1. P = Power supply I = Input O = Output I/O = Bi-directional Gnd = Ground Ipu = Input w/ internal pull-up Ipd = Input w/ internal pull-down Ipd/O = Input w/ internal pull-down during reset, output pin otherwise Ipu/O = Input w/ internal pull-up during reset, output pin otherwise PU = Strap pin pull-up PD = Strap pin pull-down Otri = Output tristated NC = No Connect M9999-120403 12 December 2003 KS8995M Pin Number 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Pin Name LED3-0 GNDD VDDIO LED2-2 LED2-1 LED2-0 LED1-2 LED1-1 LED1-0 MDC MDIO SPIQ SPIC/SCL SPID/SDA SPIS_N Type(1) Ipu/O Gnd P Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu I/O Otri I/O I/O Ipu 2 2 2 1 1 1 All All All All All All Port 3 Pin Function LED indicator 0 Digital ground 3.3/2.5V digital VDD for digital I/O LED indicator 2 LED indicator 1 LED indicator 0 LED indicator 2 LED indicator 1 LED indicator 0 Switch or PHY[5] MII management data clock Switch or PHY[5] MII management data I/O. Features internal pull down to define pin state when not driven. Micrel (1) SPI serial data output in SPI slave mode; (2) Not used in I2C master mode. See “pin# 113.” (1) Input clock up to 5MHz in SPI slave mode; (2) Output clock at 81KHz in I2C master mode. See “pin# 113.” (1) Serial data input in SPI slave mode; (2) Serial data input/output in I2C master mode See “pin# 113.” Active low. (1) SPI data transfer start in SPI slave mode. When SPIS_N is high, the KS8995M is deselected and SPIQ is held in high impedance state, a high-to-low transition to initiate the SPI data transfer; (2) Not used in I2C master mode. Serial bus configuration pin If EEPROM is not present, the KS8995M will start itself with chip default (00)... Pin Config. PS[1:0]=00 PS[1:0]=01 PS[1:0]=10 PS[1:0]=11 Serial Bus Configuration I2C Master Mode for EEPROM Reserved SPI Slave Mode for CPU Interface Factory Test Mode (BIST) 113 PS1 Ipd 114 115 116 117 118 Note: 1. P = Power supply I = Input O = Output I/O = Bi-directional Gnd = Ground PS0 RST_N GNDD VDDC TESTEN Ipd Ipu Gnd P Ipd Serial bus configuration pin. See “pin# 113.” Reset the KS8995M. Active low. Digital ground 1.8V digital core VDD NC for normal operation. Factory test pin. Ipu = Input w/ internal pull-up Ipd = Input w/ internal pull-down Ipd/O = Input w/ internal pull-down during reset, output pin otherwise Ipu/O = Input w/ internal pull-up during reset, output pin otherwise PU = Strap pin pull-up PD = Strap pin pull-down Otri = Output tristated NC = No Connect December 2003 13 M9999-120403 KS8995M Pin Number 119 120 121 122 123 124 125 126 127 128 Note: 1. P = Power supply I = Input O = Output I/O = Bi-directional Gnd = Ground Ipu = Input w/ internal pull-up Ipd = Input w/ internal pull-down Ipd/O = Input w/ internal pull-down during reset, output pin otherwise Ipu/O = Input w/ internal pull-up during reset, output pin otherwise PU = Strap pin pull-up PD = Strap pin pull-down Otri = Output tristated NC = No Connect Micrel Pin Name SCANEN NC X1 X2 VDDAP GNDA VDDAR GNDA GNDA TEST2 Type(1) Ipd NC I O P Gnd P Gnd Gnd NC Port Pin Function NC for normal operation. Factory test pin. No Connect 25MHz crystal clock connection/or 3.3V tolerant oscillator input. Oscillator should be ±100ppm. 25MHz crystal clock connection 1.8V analog VDD for PLL Analog ground 1.8V analog VDD Analog ground Analog ground NC for normal operation. Factory test pin. M9999-120403 14 December 2003 KS8995M Micrel Pin Description (by Name) Pin Number 39 38 124 42 44 2 16 30 6 12 21 27 34 40 120 127 126 49 88 116 58 76 99 17 106 105 104 103 102 101 98 Pin Name FXSD4 FXSD5 GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA NC GNDA GNDA GNDD GNDD GNDD GNDD GNDD GNDD ISET LED1-0 LED1-1 LED1-2 LED2-0 LED2-1 LED2-2 LED3-0 Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O 1 1 1 2 2 2 3 Type(1) I I Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd NC Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Port 4 5 Pin Function Fiber signal detect/factory test pin. Fiber signal detect/factory test pin. Analog ground Analog ground Analog ground Analog ground Analog ground Analog ground Analog ground Analog ground Analog ground Analog ground Analog ground Analog ground No connect Analog ground Analog ground Digital ground Digital ground Digital ground Digital ground Digital ground Digital ground Set physical transmit output current. Pull-down with a 3.01kΩ 1% resistor. LED indicator 0 LED indicator 1 LED indicator 2 LED indicator 0 LED indicator 1 LED indicator 2 LED indicator 0 Note: 1. P = Power supply I = Input O = Output I/O = Bi-directional Gnd = Ground Ipu = Input w/ internal pull-up Ipd = Input w/ internal pull-down Ipd/O = Input w/ internal pull-down during reset, output pin otherwise Ipu/O = Input w/ internal pull-up during reset, output pin otherwise PU = Strap pin pull-up PD = Strap pin pull-down Otri = Output tristated NC = No Connect December 2003 15 M9999-120403 KS8995M Pin Number 97 96 95 94 93 92 91 90 107 108 1 45 46 Pin Name LED3-1 LED3-2 LED4-0 LED4-1 LED4-2 LED5-0 LED5-1 LED5-2 MDC MDIO TEST1 MUX1 MUX2 Type(1) Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu I/O NC NC NC Port 3 3 4 4 4 5 5 5 All All Pin Function LED indicator 1 LED indicator 2 LED indicator 0 LED indicator 1 LED indicator 2 LED indicator 0 LED indicator 1. Strap option: PU (default): enable PHY MII I/F. PD: tristate all PHY MII output. See “pin# 86 SCONF1.” LED indicator 2. Strap option: Aging setup. See “Aging” section. (default) = Aging Enable; PD = Aging disable Switch or PHY[5] MII management data clock. Switch or PHY[5] MII management data I/O. NC for normal operation. Factory test pin. MUX1 and MUX2 should be left unconnected for normal operation. They are factory test pins. Mode Normal Operation Remote Analog Loopback Mode for Testing only Reserved Power Save Mode for Testing only 68 PCOL Ipd/O 5 Mux1 NC 0 1 1 Micrel Mux2 NC 1 0 1 PHY[5] MII collision detect/Force flow control. See “Register 18.” For port 4 only. PD (default) = No force flow control. PU = Force flow control. PHY[5] MII carrier sense/Force duplex mode See “Register 28.” For port 4 only. PD (default) = Force half-duplex if auto-negotiation is disabled or fails. PU = Force full-duplex if auto-negotiation is disabled or fails. PHY[5] MII receive clock. PHY mode MII. PHY[5] MII receive bit 0. Strap option: PD (default) = disable aggressive back-off algorithm in half-duplex mode; PU = enable for performance enhancement. PHY[5] MII receive bit 1. Strap option: PD (default) = drop excessive collision packets; PU = does not drop excessive collision packets. PHY[5] MII receive bit 2. Strap option: PD (default) = disable back pressure; PU = enable back pressure. PHY[5] MII receive bit 3. Strap option: PD (default) = enable flow control; PU = disable flow control. 67 PCRS Ipd/O 5 60 65 PMRXC PMRXD0 O Ipd/O 5 5 64 63 62 PMRXD1 PMRXD2 PMRXD3 Ipd/O Ipd/O Ipd/O 5 5 5 Note: 1. P = Power supply I = Input O = Output I/O = Bi-directional Gnd = Ground Ipu = Input w/ internal pull-up Ipd = Input w/ internal pull-down Ipd/O = Input w/ internal pull-down during reset, output pin otherwise Ipu/O = Input w/ internal pull-up during reset, output pin otherwise PU = Strap pin pull-up PD = Strap pin pull-down Otri = Output tristated NC = No Connect M9999-120403 16 December 2003 KS8995M Pin Number 61 66 57 55 54 53 52 51 56 114 113 Pin Name PMRXDV PMRXER PMTXC PMTXD0 PMTXD1 PMTXD2 PMTXD3 PMTXEN PMTXER PS0 PS1 Type(1) Ipd/O Ipd/O O Ipd Ipd Ipd Ipd Ipd Ipd Ipd Ipd Port 5 5 5 5 5 5 5 5 5 Pin Function PHY[5] MII receive data valid. Micrel PHY[5] MII receive error. Strap option: PD (default) = 1522/1518 bytes; PU = packet size up to 1536 bytes. PHY[5] MII transmit clock. PHY mode MII PHY[5] MII transmit bit 0 PHY[5] MII transmit bit 1 PHY[5] MII transmit bit 2 PHY[5] MII transmit bit 3 PHY[5] MII transmit enable PHY[5] MII transmit error Serial bus configuration pin. See “pin# 113.” Serial bus configuration pin If EEPROM is not present, the KS8995M will start itself with chip default (00)... Pin Config. PS[1:0]=00 PS[1:0]=01 PS[1:0]=10 PS[1:0]=11 Serial Bus Configuration I2C Master Mode for EEPROM Reserved SPI Slave Mode for CPU Interface Factory Test Mode (BIST) 47 48 115 5 11 20 26 33 4 10 19 25 32 119 84 PWRDN_N RESERVE RST_N RXM1 RXM2 RXM3 RXM4 RXM5 RXP1 RXP2 RXP3 RXP4 RXP5 SCANEN SCOL Ipu NC Ipu I I I I I I I I I I Ipd Ipd/O 1 2 3 4 5 1 2 3 4 5 Full-chip power down. Active low. Reserved pin. No connect. Reset the KS8995M. Active low. Physical receive signal - (differential) Physical receive signal - (differential) Physical receive signal - (differential) Physical receive signal - (differential) Physical receive signal - (differential) Physical receive signal + (differential) Physical receive signal + (differential) Physical receive signal + (differential) Physical receive signal + (differential) Physical receive signal + (differential) NC for normal operation. Factory test pin. Switch MII collision detect. Note: 1. P = Power supply I = Input O = Output I/O = Bi-directional Gnd = Ground Ipu = Input w/ internal pull-up Ipd = Input w/ internal pull-down Ipd/O = Input w/ internal pull-down during reset, output pin otherwise Ipu/O = Input w/ internal pull-up during reset, output pin otherwise PU = Strap pin pull-up PD = Strap pin pull-down Otri = Output tristated NC = No Connect December 2003 17 M9999-120403 KS8995M Pin Number 87 86 Pin Name SCONF0 SCONF1 Type(1) Ipd Ipd Port Pin Function Dual MII configuration pin Dual MII configuration pin Pin# (91, 86, 87): 000 001 010 011 100 101 110 111 85 78 83 SCRS SMRXC SMRXD0 Ipd/O I/O Ipd/O Switch MII carrier sense Switch MII Disable, Otri PHY Mode MII MAC Mode MII PHY Mode SNI Disable PHY Mode MII MAC Mode MII PHY Mode SNI PHY [5] MII Disable, Otri Disable, Otri Disable, Otri Disable, Otri Disable PHY Mode MII PHY Mode MII PHY Mode MII Micrel Switch MII receive clock. Input in MAC mode, output in PHY mode MII. Switch MII receive bit 0; Strap option: LED Mode PD (default) = Mode 0; PU = Mode 1. See “Register 11.” Mode 0 LEDX_2 LEDX_1 LEDX_0 Lnk/Act Fulld/Col Speed Mode 1 100Lnk/Act 10Lnk/Act Fulld 82 81 80 79 75 73 72 71 70 69 74 SMRXD1 SMRXD2 SMRXD3 SMRXDV SMTXC SMTXD0 SMTXD1 SMTXD2 SMTXD3 SMTXEN SMTXER Ipd/O Ipd/O Ipd/O Ipd/O I/O Ipd Ipd Ipd Ipd Ipd Ipd Switch MII receive bit 1. Strap option: PD (default) = Switch MII in 100Mbps mode; PU = Switch MII in 10Mbps mode. Switch MII receive bit 2. Strap option: PD (default) = Switch MII in full-duplex mode; PU = Switch MII in half-duplex mode. Switch MII receive bit 3. Strap option: PD (default) = Disable Switch MII full-duplex flow control; PU = Enable Switch MII full-duplex flow control. Switch MII receive data valid Switch MII transmit clock. Input in MAC mode, output in PHY mode MII. Switch MII transmit bit 0 Switch MII transmit bit 1 Switch MII transmit bit 2 Switch MII transmit bit 3 Switch MII transmit enable Switch MII transmit error Note: 1. P = Power supply I = Input O = Output I/O = Bi-directional Gnd = Ground Ipu = Input w/ internal pull-up Ipd = Input w/ internal pull-down Ipd/O = Input w/ internal pull-down during reset, output pin otherwise Ipu/O = Input w/ internal pull-up during reset, output pin otherwise PU = Strap pin pull-up PD = Strap pin pull-down Otri = Output tristated NC = No Connect M9999-120403 18 December 2003 KS8995M Pin Number 110 111 109 112 Pin Name SPIC/SCL SPID/SDA SPIQ SPIS_N Type(1) I/O I/O Otri Ipu Port All All All All Pin Function Micrel (1) Input clock up to 5MHz in SPI slave mode; (2) Output clock at 81KHz in I2C master mode. See “pin# 113.” (1) Serial data input in SPI slave mode; (2) Serial data input/output in I2C master mode. See “pin# 113.” (1) SPI serial data output in SPI slave mode; (2) Not used in I2C master mode. See “pin# 113.” Active low. (1) SPI data transfer start in SPI slave mode. When SPIS_N is high, the KS8995M is deselected and SPIQ is held in high impedance state, a high-to-low transition to initiate the SPI data transfer; (2) Not used in I2C master mode. No connect for normal operation. Factory test pin. No Connect for normal operation. Factory test pin. 128 118 8 14 23 29 36 7 13 22 28 35 123 41 43 3 15 31 125 18 9 24 37 50 TEST2 TESTEN TXP1 TXP2 TXP3 TXP4 TXP5 TXM1 TXM2 TXM3 TXM4 TXM5 VDDAP VDDAR VDDAR VDDAR VDDAR VDDAR VDDAR VDDAT VDDAT VDDAT VDDAT VDDC NC Ipd O O O O O O O O O O P P P P P P P P P P P P 1 2 3 4 5 1 2 3 4 5 Physical transmit signal + (differential) Physical transmit signal + (differential) Physical transmit signal + (differential) Physical transmit signal + (differential) Physical transmit signal + (differential) Physical transmit signal - (differential) Physical transmit signal - (differential) Physical transmit signal - (differential) Physical transmit signal - (differential) Physical transmit signal - (differential) 1.8V analog VDD for PLL 1.8V analog VDD 1.8V analog VDD 1.8V analog VDD 1.8V analog VDD 1.8V analog VDD 1.8V analog VDD 2.5V analog VDD 2.5V analog VDD 2.5V analog VDD 2.5V analog VDD 1.8V digital core VDD Note: 1. P = Power supply I = Input O = Output I/O = Bi-directional Gnd = Ground Ipu = Input w/ internal pull-up Ipd = Input w/ internal pull-down Ipd/O = Input w/ internal pull-down during reset, output pin otherwise Ipu/O = Input w/ internal pull-up during reset, output pin otherwise PU = Strap pin pull-up PD = Strap pin pull-down Otri = Output tristated NC = No Connect December 2003 19 M9999-120403 KS8995M Pin Number 89 117 59 77 100 121 122 Pin Name VDDC VDDC VDDIO VDDIO VDDIO X1 X2 Type(1) P P P P P I O Port Pin Function 1.8V digital core VDD 1.8V digital core VDD 3.3/2.5V digital VDD for digital I/O circuitry 3.3/2.5V digital VDD for digital I/O circuitry 3.3/2.5V digital VDD for digital I/O circuitry 25MHz crystal clock connection/or 3.3V tolerant oscillator input. Oscillator should be ±100ppm. 25MHz crystal clock connection. Micrel Note: 1. P = Power supply I = Input O = Output I/O = Bi-directional Gnd = Ground Ipu = Input w/ internal pull-up Ipd = Input w/ internal pull-down Ipd/O = Input w/ internal pull-down during reset, output pin otherwise Ipu/O = Input w/ internal pull-up during reset, output pin otherwise PU = Strap pin pull-up PD = Strap pin pull-down Otri = Output tristated NC = No Connect M9999-120403 20 December 2003 KS8995M December 2003 LED2-0 LED1-2 LED1-1 LED1-0 MDC MDIO SPIQ SPIC/SCL SPID/SDA SPIS_N PS1 PS0 RST_N GNDD VDDC TESTEN SCANEN NC X1 X2 VDDAP GNDA VDDAR GNDA GNDA TEST2 103 1 Pin Configuration 128-Pin PQFP (PQ) 21 39 65 TEST1 GNDA VDDAR RXP1 RXM1 GNDA TXM1 TXP1 VDDAT RXP2 RXM2 GNDA TXM2 TXP2 VDDAR GNDA ISET VDDAT RXP3 RXM3 GNDA TXM3 TXP3 VDDAT RXP4 RXM4 GNDA TXM4 TXP4 GNDA VDDAR RXP5 RXM5 GNDA TXM5 TXP5 VDDAT FXSD5 LED2-1 LED2-2 VDDIO GNDD LED3-0 LED3-1 LED3-2 LED4-0 LED4-1 LED4-2 LED5-0 LED5-1 LED5-2 VDDC GNDD SCONF0 SCONF1 SCRS SCOL SMRXD0 SMRXD1 SMRXD2 SMRXD3 SMRXDV SMRXC VDDIO GNDD SMTXC SMTXER SMTXD0 SMTXD1 SMTXD2 SMTXD3 SMTEXN PCOL PCRS PMRXER PMRXD0 PMRXD1 PMRXD2 PMRXD3 PMRXDV PMRXC VDDIO GNDD PMTXC PMTXER PMTXD0 PMTXD1 PMTXD2 PMTXD3 PMTXEN VDDC GNDD RESERVE PWRDN_N MUX2 MUX1 GNDA VDDAR GNDA VDDAR GNDA FXSD4 M9999-120403 Micrel KS8995M Micrel Introduction The KS8995M contains five 10/100 physical layer transceivers and five MAC (Media Access Control) units with an integrated layer 2 managed switch. The device runs in three modes. The first mode is as a five-port integrated switch. The second is as a five-port switch with the fifth port decoupled from the physical port. In this mode access to the fifth MAC is provided through an MII (Media Independent Interface). This is useful for implementing an integrated broadband router. The third mode uses the dual MII feature to recover the use of the fifth PHY. This allows the additional broadband gateway configuration, where the fifth PHY may be accessed through the MII-P5 port. The KS8995M has the flexibility to reside in a managed or unmanaged design. In a managed design, a host processor has complete control of the KS8995M via the SPI bus, or partial control via the MDC/MDIO interface. An unmanaged design is achieved through I/O strapping or EEPROM programming at system reset time. On the media side, the KS8995M supports IEEE 802.3 10BaseT, 100BaseTX on all ports, and 100BaseFX on ports 4 and 5. The KS8995M can be used as two separate media converters. Physical signal transmission and reception are enhanced through the use of patented analog circuitry that makes the design more efficient and allows for lower power consumption and smaller chip die size. The major enhancements from the KS8995E to the KS8995M are support for host processor management, a dual MII interface, tag as well as port based VLAN, spanning tree protocol support, IGMP snooping support, port mirroring support and rate limiting functionality. Functional Overview: Physical Layer Transceiver 100BaseTX Transmit The 100BaseTX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI conversion, MLT3 encoding and transmission. The circuit starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B coding followed by a scrambler. The serialized data is further converted from NRZ to NRZI format, and then transmitted in MLT3 current output. The output current is set by an external 1% 3.01kΩ resistor for the 1:1 transformer ratio. It has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot and timing jitter. The wave-shaped 10BaseT output is also incorporated into the 100BaseTX transmitter. 100BaseTX Receive The 100BaseTX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding and serial-to-parallel conversion. The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss and phase distortion is a function of the length of the cable, the equalizer has to adjust its characteristics to optimize the performance. In this design, the variable equalizer will make an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, it then tunes itself for optimization. This is an ongoing process and can self-adjust against environmental changes such as temperature variations. The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used to compensate for the effect of baseline wander and improve the dynamic range. The differential data conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive. The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal into the NRZ format. The signal is then sent through the de-scrambler followed by the 4B/5B decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC. PLL Clock Synthesizer The KS8995M generates 125MHz, 42MHz, 25MHz and 10MHz clocks for system timing. Internal clocks are generated from an external 25MHz crystal or oscillator. Scrambler/De-scrambler (100BaseTX only) The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander. The data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). This can generate a 2047-bit nonrepetitive sequence. The receiver will then de-scramble the incoming data stream with the same sequence at the transmitter. 100BaseFX Operation 100BaseFX operation is very similar to 100BaseTX operation except that the scrambler/de-scrambler and MLT3 encoder/ decoder are bypassed on transmission and reception. In this mode the auto-negotiation feature is bypassed since there is no standard that supports fiber auto-negotiation. 100BaseFX Signal Detection The physical port runs in 100BaseFX mode if FXSDx >0.6V for ports 4 and 5 only. This signal is internally referenced to 1.25V. The fiber module interface should be set by a voltage divider such that FXSDx ‘H’ is above this 1.25V reference, indicating signal M9999-120403 22 December 2003 KS8995M Micrel detect, and FXSDx ‘L’ is below the 1.25V reference to indicate no signal. When FXSDx is below 0.6V then 100BaseFX mode is disabled. Since there is no auto-negotiation for 100BaseFX mode, ports 4 and 5 must be forced to either full or half-duplex. Note that strap in options exist to set duplex mode for port 4, but not for port 5. 100BaseFX Far End Fault Far end fault occurs when the signal detection is logically false from the receive fiber module. When this occurs, the transmission side signals the other end of the link by sending 84 1s followed by a zero in the idle period between frames. The far end fault may be disabled through register settings. 10BaseT Transmit The output 10BaseT driver is incorporated into the 100BaseT driver to allow transmission with the same magnetics. They are internally wave-shaped and pre-emphasized into outputs with a typical 2.3V amplitude. The harmonic contents are at least 27dB below the fundamental when driven by an all-ones Manchester-encoded signal. 10BaseT Receive On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and a PLL perform the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400mV or with short pulse widths in order to prevent noises at the RXP or RXM input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KS8995M decodes a data frame. The receiver clock is maintained active during idle periods in between data reception. Power Management The KS8995M features a per port power down mode. To save power the user can power down ports that are not in use by setting port control registers or MII control registers. In addition, it also supports full chip power down mode. When activated, the entire chip will be shut down. MDI/MDI-X Auto Crossover The KS8995M supports MDI/MDI-X auto crossover. This facilitates the use of either a straight connection CAT-5 cable or a crossover CAT-5 cable. The auto-sense function will detect remote transmit and receive pairs, and correctly assign the transmit and receive pairs from the Micrel device. This can be highly useful when end users are unaware of cable types and can also save on an additional uplink configuration connection. The auto crossover feature may be disabled through the port control registers. Auto-Negotiation The KS8995M conforms to the auto-negotiation protocol as described by the 802.3 committee. Auto-negotiation allows UTP (Unshielded Twisted Pair) link partners to select the best common mode of operation. In auto-negotiation the link partners advertise capabilities across the link to each other. If auto-negotiation is not supported or the link partner to the KS8995M is forced to bypass auto-negotiation, then the mode is set by observing the signal at the receiver. This is known as parallel mode because while the transmitter is sending auto-negotiation advertisements, the receiver is listening for advertisements or a fixed signal protocol. The flow for the link set up is depicted in Figure 4. Start Auto Negotiation Force Link Setting No Parallel Operation Yes Bypass Auto-Negotiation and Set Link Mode Attempt Auto-Negotiation Listen for 100BaseTX Idles Listen for 10BaseT Link Pulses No Join Flow Link Mode Set ? Yes Link Mode Set Figure 4. Auto-Negotiation December 2003 23 M9999-120403 KS8995M Micrel Functional Overview: Switch Core Address Look-Up The internal look-up table stores MAC addresses and their associated information. It contains a 1K unicast address table plus switching information. The KS8995M is guaranteed to learn 1K addresses and distinguishes itself from hash-based look-up tables which, depending on the operating environment and probabilities, may not guarantee the absolute number of addresses it can learn. Learning The internal look-up engine will update its table with a new entry if the following conditions are met: • The received packet’s SA (Source Address) does not exist in the look-up table. • The received packet is good; the packet has no receiving errors, and is of legal length. The look-up engine will insert the qualified SA into the table, along with the port number, time stamp. If the table is full, the last entry of the table will be deleted first to make room for the new entry. Migration The internal look-up engine also monitors whether a station is moved. If it happens, it will update the table accordingly. Migration happens when the following conditions are met: • The received packet’s SA is in the table but the associated source port information is different. • The received packet is good; the packet has no receiving errors, and is of legal length. The look-up engine will update the existing record in the table with the new source port information. Aging The look-up engine will update the time stamp information of a record whenever the corresponding SA appears. The time stamp is used in the aging process. If a record is not updated for a period of time, the look-up engine will remove the record from the table. The look-up engine constantly performs the aging process and will continuously remove aging records. The aging period is 300 + 75 seconds. This feature can be enabled or disabled through Register 3 or by external pull-up or pull-down resistors on LED[5][2]. See “Register 3” section. Forwarding The KS8995M will forward packets using an algorithm that is depicted in the following flowcharts. Figure 5 shows stage one of the forwarding algorithm where the search engine looks up the VLAN ID, static table, and dynamic table for the destination address, and comes up with “port to forward 1” (PTF1). PTF1 is then further modified by the spanning tree, IGMP snooping, port mirroring, and port VLAN processes to come up with “port to forward 2” (PTF2) as shown in Figure 6. This is where the packet will be sent. The KS8995M will not forward the following packets: • Error packets. These include framing errors, FCS errors, alignment errors, and illegal size packet errors. • 802.3x pause frames. The KS8995M will intercept these packets and perform the appropriate actions. • “Local” packets. Based on DA (Destination Address) look-up. If the destination port from the look-up table matches the port where the packet was from, the packet is defined as “local.” Switching Engine The KS8995M features a high-performance switching engine to move data to and from the MAC’s packet buffers. It operates in store and forward mode, while the efficient switching mechanism reduces overall latency. The KS8995M has a 64kB internal frame buffer. This resource is shared between all five ports. The buffer sharing mode can be programmed through Register 2. See “Register 2.” In one mode, ports are allowed to use any free buffers in the buffer pool. In the second mode, each port is only allowed to use 1/5 of the total buffer pool. There are a total of 512 buffers available. Each buffer is sized at 128B. MAC (Media Access Controller) Operation The KS8995M strictly abides by IEEE 802.3 standards to maximize compatibility. Inter-Packet Gap (IPG) If a frame is successfully transmitted, the 96-bit time IPG is measured between the two consecutive MTXEN. If the current packet is experiencing collision, the 96-bit time IPG is measured from MCRS and the next MTXEN. Backoff Algorithm The KS8995M implements the IEEE Std 802.3 binary exponential back-off algorithm, and optional “aggressive mode” back off. After 16 collisions, the packet will be optionally dropped depending on the chip configuration in register 3. See “Register 3.” M9999-120403 24 December 2003 KS8995M Micrel Start PTF1=NULL NO VLAN ID VALID? -Search VLAN table -Ingress VLAN filtering -Discard NPVID check YES Search complete. Get PTF1 from static table FOUND Search Static Table This search is based on DA or DA+FID NOT FOUND Search complete. Get PTF1 from dynamic table FOUND Dynamic Table Search This search is based on DA+FID NOT FOUND Search complete. Get PTF1 from VLAN table PTF1 Figure 5. DA Look-Up Flowchart–Stage 1 PTF1 Spanning Tree Process -Check receiving port’s receive enable bit -Check destination port’s transmit enable bit -Check whether packets are special (BPDU or specified) IGMP Process -Applied to MAC #1 to #4 -MAC#5 is reserved for microprocessor -IGMP will be forwarded to port 5 Port Mirror Process -RX Mirror -TX Mirror -RX or TX Mirror -RX and TX Mirror Port VLAN Membership Check PTF2 Figure 6. DA Resolution Flowchart–Stage 2 December 2003 25 M9999-120403 KS8995M Micrel Late Collision If a transmit packet experiences collisions after 512-bit times of the transmission, the packet will be dropped. Illegal Frames The KS8995M discards frames less than 64 bytes and can be programmed to accept frames up to 1536 bytes in register 4. For special applications, the KS8995M can also be programmed to accept frames up to 1916 bytes in register 4. Since the KS8995M supports VLAN tags, the maximum sizing is adjusted when these tags are present. Flow Control The KS8995M supports standard 802.3x flow control frames on both transmit and receive sides. On the receive side, if the KS8995M receives a pause control frame, the KS8995M will not transmit the next normal frame until the timer, specified in the pause control frame, expires. If another pause frame is received before the current timer expires, the timer will be updated with the new value in the second pause frame. During this period (being flow controlled), only flow control packets from the KS8995M will be transmitted. On the transmit side, the KS8995M has intelligent and efficient ways to determine when to invoke flow control. The flow control is based on availability of the system resources, including available buffers, available transmit queues and available receive queues. The KS8995M will flow control a port, which just received a packet, if the destination port resource is being used up. The KS8995M will issue a flow control frame (XOFF), containing the maximum pause time defined in IEEE standard 802.3x. Once the resource is freed up, the KS8995M will send out the other flow control frame (XON) with zero pause time to turn off the flow control (turn on transmission to the port). A hysteresis feature is provided to prevent the flow control mechanism from being activated and deactivated too many times. The KS8995M will flow control all ports if the receive queue becomes full. Half-Duplex Back Pressure A half-duplex back pressure option (note: not in 802.3 standards) is also provided. The activation and deactivation conditions are the same as the above in full-duplex mode. If back pressure is required, the KS8995M will send preambles to defer the other stations’ transmission (carrier sense deference). To avoid jabber and excessive deference defined in 802.3 standard, after a certain time it will discontinue the carrier sense but it will raise the carrier sense quickly. This short silent time (no carrier sense) is to prevent other stations from sending out packets and keeps other stations in carrier sense deferred state. If the port has packets to send during a back pressure situation, the carrier-sense-type back pressure will be interrupted and those packets will be transmitted instead. If there are no more packets to send, carrier-sense-type back pressure will be active again until switch resources are free. If a collision occurs, the binary exponential backoff algorithm is skipped and carrier sense is generated immediately, reducing the chance of further colliding and maintaining carrier sense to prevent reception of packets. To ensure no packet loss in 10BaseT or 100BaseTX half-duplex modes, the user must enable the following: • Aggressive backoff (register 3, bit 0) • No excessive collision drop (register 4, bit 3) • Back pressure (register 4, bit 5) These bits are not set as the default because this is not the IEEE standard. Broadcast Storm Protection The KS8995M has an intelligent option to protect the switch system from receiving too many broadcast packets. Broadcast packets will be forwarded to all ports except the source port, and thus use too many switch resources (bandwidth and available space in transmit queues). The KS8995M has the option to include “multicast packets” for storm control. The broadcast storm rate parameters are programmed globally, and can be enabled or disabled on a per port basis. The rate is based on a 50ms interval for 100BT and a 500ms interval for 10BT. At the beginning of each interval, the counter is cleared to zero, and the rate limit mechanism starts to count the number of bytes during the interval. The rate definition is described in Register 6 and Register 7. The default setting for registers 6 and 7 is 0x4A, which is 74 decimal. This is equal to a rate of 1%, calculated as follows: 148,800 frames/sec × 50ms/interval × 1% = 74 frames/interval (approx.) = 0x4A MII Interface Operation The MII (Media Independent Interface) is specified by the IEEE 802.3 committee and provides a common interface between physical layer and MAC layer devices. The KS8995M provides two such interfaces. The MII-P5 interface is used to connect to the fifth PHY, whereas the MII-SW interface is used to connect to the fifth MAC. Each of these MII interfaces contains two distinct groups of signals, one for transmission and the other for receiving. Table 5 describes the signals used in the MII-P5 interface. M9999-120403 26 December 2003 KS8995M MII signal MTXEN MTXER MTXD3 MTXD2 MTXD1 MTXD0 MTXC MCOL MCRS MRXDV MRXER MRXD3 MRXD2 MRXD1 MRXD0 MRXC MDC MDIO Description Transmit enable Transmit error Transmit data bit 3 Transmit data bit 2 Transmit data bit 1 Transmit data bit 0 Transmit clock Collision detection Carrier sense Receive data valid Receive error Receive data bit 3 Receive data bit 2 Receive data bit 1 Receive data bit 0 Receive clock Management data clock Management data I/O KS8995M signal PMTXEN PMTXER PMTXD[3] PMTXD[2] PMTXD[1] PMTXD[0] PMTXC PCOL PCRS PMRXDV PMRXER PMRXD[3] PMRXD[2] PMRXD[1] PMRXD[0] PMRXC MDC MDIO Micrel Table 1. MII–P5 Signals (PHY Mode) PHY Mode Connection External MAC MTXEN MTXER MTXD3 MTXD2 MTXD1 MTXD0 MTXC MCOL MCRS MRXDV MRXER MRXD3 MRXD2 MRXD1 MRXD0 MRXC KS8995M Signal SMTXEN SMTXER SMTXD[3] SMTXD[2] SMTXD[1] SMTXD[0] SMTXC SCOL SCRS SMRXDV Not used SMRXD[3] SMRXD[2] SMRXD[1] SMRXD[0] SMRXC Description Transmit enable Transmit error Transmit data bit 3 Transmit data bit 2 Transmit data bit 1 Transmit data bit 0 Transmit clock Collision detection Carrier sense Receive data valid Receive error Receive data bit 3 Receive data bit 2 Receive data bit 1 Receive data bit 0 Receive clock MAC Mode Connection External PHY MTXEN MTXER MTXD3 MTXD2 MTXD1 MTXD0 MTXC MCOL MCRS MRXDV MRXER MRXD3 MRXD2 MRXD1 MRXD0 MRXC KS8995M Signal SMRXDV Not used SMRXD[3] SMRXD[2] SMRXD[1] SMRXD[0] SMRXC SCOL SCRS SMTXEN SMTXER SMTXD[3] SMTXD[2] SMTXD[1] SMTXD[0] SMTXC Table 2. MII–SW Signals December 2003 27 M9999-120403 KS8995M Micrel The MII-P5 interface operates in PHY mode only, while the MII-SW interface operates in either MAC mode or PHY mode. These interfaces are nibble wide data interfaces and therefore run at 1/4 the network bit rate (not encoded). Additional signals on the transmit side indicate when data is valid or when an error occurs during transmission. Likewise, the receive side has indicators that convey when the data is valid and without physical layer errors. For half-duplex operation there is a signal that indicates a collision has occurred during transmission. Note that the signal MRXER is not provided on the MII-SW interface for PHY mode operation and the signal MTXER is not provided on the MII-SW interface for MAC mode operation. Normally MRXER would indicate a receive error coming from the physical layer device. MTXER would indicate a transmit error from the MAC device. These signals are not appropriate for this configuration. For PHY mode operation, if the device interfacing with the KS8995M has an MRXER pin, it should be tied low. For MAC mode operation, if the device interfacing with the KS8995M has an MTXER pin, it should be tied low. SNI Interface Operation The SNI (Serial Network Interface) is compatible with some controllers used for network layer protocol processing. This interface can be directly connected to these types of devices. The signals are divided into two groups, one for transmission and the other for reception. The signals involved are described in Table 3. SNI Signal TXEN TXD TXC COL CRS RXD RXC Description Transmit enable Serial transmit data Transmit clock Collision detection Carrier sense Serial receive data Receive clock KS8995M Signal SMTXEN SMTXD[0] SMTXC SCOL SMRXDV SMRXD[0] SMRXC Table 3. SNI Signals This interface is a bit wide data interface and therefore runs at the network bit rate (not encoded). An additional signal on the transmit side indicates when data is valid. Likewise, the receive side has an indicator that conveys when the data is valid. For half-duplex operation there is a signal that indicates a collision has occurred during transmission. Advanced Functionality Spanning Tree Support To support spanning tree, port 5 is the designated port for the processor. The other ports (port 1 - port 4) can be configured in one of the five spanning tree states via “transmit enable,” “receive enable” and “learning disable” register settings in Registers 18, 34, 50, and 66 for ports 1, 2, 3 and 4, respectively. The following description shows the port setting and software actions taken for each of the five spanning tree states. Disable state: the port should not forward or receive any packets. Learning is disabled. Port setting: “transmit enable = 0, receive enable = 0, learning disable = 1” Software action: the processor should not send any packets to the port. The switch may still send specific packets to the processor (packets that match some entries in the static table with “overriding bit” set) and the processor should discard those packets. Note: processor is connected to port 5 via MII interface. Address learning is disabled on the port in this state. Blocking state: only packets to the processor are forwarded. Learning is disabled. Port setting: “transmit enable = 0, receive enable = 0, learning disable = 1” Software action: the processor should not send any packets to the port(s) in this state. The processor should program the static table with the entries that it needs to receive (e.g. BPDU packets). The “overriding” bit should also be set so that the switch will forward those specific packets to the processor. Address learning is disabled on the port in this state. Listening state: only packets to and from the processor are forwarded. Learning is disabled. Port setting: “transmit enable = 0, receive enable = 0, learning disable = 1” Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g. BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state, see “Special Tagging Mode” section for details. Address learning is disabled on the port in this state. M9999-120403 28 December 2003 KS8995M Micrel Learning state: only packets to and from the processor are forwarded. Learning is enabled. Port setting: “transmit enable = 0, receive enable = 0, learning disable = 0” Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g. BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state, see “Special Tagging Mode” section for details. Address learning is enabled on the port in this state. Forwarding state: packets are forwarded and received normally. Learning is enabled. Port setting: “transmit enable = 1, receive enable = 1, learning disable = 0” Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g. BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state, see “Special Tagging Mode” section for details. Address learning is enabled on the port in this state. Special Tagging Mode The special tagging mode is designed for spanning tree protocol IGMP snooping and is flexible for use in other applications. The special tagging mode, similar to 802.1q, requires software to change network drivers to insert/modify/strip/interpret the special tag. This mode is enabled by setting both register 11 bit 0 and register 80-bit 2. 802.1q Tag Format TPID (tag protocol identifier, 0x8100) + TCI Special Tag Format STPID (special tag identifier, 0x8100) + TCI 0x810 + 4 bit for “port mask”) + TCI Table 4. Special Tagging Mode Format The STPID will only be seen and used on the port 5 interface, which should be connected to a processor. Packets from the processor to the switch should be tagged with STPID and the port mask defined as below: “0001” packet to port 1 only “0010” packet to port 2 only “0100” packet to port 3 only “1000” packet to port 4 only “0011” packet broadcast to port 1 and port 2. ..... “1111” packet broadcast to port 1, 2, 3 and 4. “0000” normal tag, will use KS8995M internal look-up result. Normal packets should use this setting. If packets from the processors do not have a tag, the KS8995M will treat them as normal packets and an internal look-up will be performed. The KS8995M uses a non-zero “port mask” to bypass the look-up result and override any port setting, regardless of port states (blocking, disable, listening, learning). The Table 5 shows the egress rules when dealing with STPID. December 2003 29 M9999-120403 KS8995M Tx Port “Tag Insertion” 0 Tx Port “Tag Removal” 0 Micrel Ingress Tag Field (0x810+ port mask) Egress Action to Tag Field • • • • Modify tag field to 0x8100 Recalculate CRC No change to TCI if not null VID Replace VID with ingress (port 5) port VID if null VID (0x810+ port mask) 0 1 • (STPID + TCI) will be removed • Padding to 64 bytes if necessary • Recalculate CRC • • • • • • • • Modify tag field to 0x8100 Recalculate CRC No change to TCI if not null VID Replace VID with ingress (port 5) port VID if null VID Modify tag field to 0x8100 Recalculate CRC No change to TCI if not null VID Replace VID with ingress (port 5) port VID if null VID (0x810+ port mask) 1 0 (0x810+ port mask) 1 1 Not Tagged Don’t care Don’t care Determined by the dynamic MAC address table Table 5. STPID Egress Rules (Processor to Switch Port 5) For packets from regular ports (port 1 - port 4) to port 5, the port mask is used to tell the processor which port the packet was received on, defined as: “0001” from port 1, “0010” from port 2, “0100” from port 3, “1000” from port 4 No values other than the previous four defined should be received in this direction in the special mode. Table 6 shows the egress rule for this direction. Ingress Packets Tagged with 0x8100 + TCI Egress Action to Tag Field • • • • Modify TPID to 0x810 + “port mask,” which indicates source port No change to TCI, if VID is not null Replace null VID with ingress port VID Recalculate CRC Not tagged • Insert TPID to 0x810 + “port mask,” which indicates source port • Insert TCI with ingress port VID • Recalculate CRC Table 6. STPID Egress Rules (Switch to Processor) IGMP Support There are two parts involved to support IGMP in layer 2. The first part is “IGMP” snooping. The switch will trap IGMP packets and forward them only to the processor port. The IGMP packets are identified as IP packets (either Ethernet IP packets or IEEE 802.3 SNAP IP packets) AND IP version = 0x4 AND protocol number = 0x2. The second part is “multicast address insertion” in the static MAC table. Once the multicast address is programmed in the static MAC table, the multicast session will be trimmed to the subscribed ports, instead of broadcasting to all ports. To enable this feature, set register 5 bit 6 to 1. Also “special tag mode” needs to be enabled, so that the processor knows which port the IGMP packet was received on. Enable “special tag mode” by setting both register 11 bit 0 and register 80-bit 2. M9999-120403 30 December 2003 KS8995M Micrel Port Mirroring Support KS8995M supports “port mirror” comprehensively as: 1. “Receive Only” mirror on a port. All the packets received on the port will be mirrored on the sniffer port. For example, port 1 is programmed to be “rx sniff,” and port 5 is programmed to be the “sniffer port.” A packet, received on port 1, is destined to port 4 after the internal look-up. The KS8995M will forward the packet to both port 4 and port 5. KS8995M can optionally forward even “bad” received packets to port 5. 2. “Transmit Only” mirror on a port. All the packets transmitted on the port will be mirrored on the sniffer port. For example, port 1 is programmed to be “tx sniff,” and port 5 is programmed to be the “sniffer port.” A packet, received on any of the ports, is destined to port 1 after the internal look-up. The KS8995M will forward the packet to both port 1 and port 5. 3. “Receive and Transmit” mirror on two ports. All the packets received on port A AND transmitted on port B will be mirrored on the sniffer port. To turn on the “AND” feature, set register 5 bit 0 to 1. For example, port 1 is programmed to be “rx sniff,” port 2 is programmed to be “transmit sniff” and port 5 is programmed to be the “sniffer port.” A packet, received on port 1, is destined to port 4 after the internal look-up. The KS8995M will forward the packet to port 4 only, since it does not meet the “AND” condition. A packet, received on port 1, is destined to port 2 after the internal lookup. The KS8995M will forward the packet to both port 2 and port 5. Multiple ports can be selected to be “rx sniffed” or “tx sniffed.” And any port can be selected to be the “sniffer port.” All these per port features can be selected through Register 17. VLAN Support KS8995M supports 16 active VLANs out of 4096 possible VLANs specified in IEEE 802.1q. KS8995M provides a 16-entry VLAN table, which converts VID (12 bits) to FID (4bits) for address look-up. If a non-tagged or null-VID-tagged packet is received, the ingress port VID is used for look-up. In the VLAN mode, the look-up process starts with VLAN table look-up to determine whether the VID is valid. If the VID is not valid, the packet will be dropped and its address will not be learned. If the VID is valid, FID is retrieved for further look-up. FID+DA is used to determine the destination port. FID+SA is used for learning purposes. DA found in Static MAC table No No Yes Yes Yes Yes DA+FID found in Dynamic MAC table No Yes Don’t care No Yes Don’t care USE FID Flag? Don’t care Don’t care 0 1 1 1 FID Match? Don’t care Don’t care Don’t care No No Yes Action Broadcast to the membership ports defined in the VLAN table bit [20:16] Send to the destination port defined in the dynamic MAC table bit [54:52] Send to the destination port(s) defined in the static MAC table bit [52:48] Broadcast to the membership ports defined in the VLAN table bit [20:16] Send to the destination port defined in the dynamic MAC table bit [54:52] Send to the destination port(s) defined in the static MAC table bit [52:48] Table 7. FID+DA Look-Up in the VLAN Mode December 2003 31 M9999-120403 KS8995M SA+FID found in Dynamic MAC table No Yes Micrel Action The SA+FID will be learned into the dynamic table. Time stamp will be updated Table 8. FID+SA Look-Up in the VLAN Mode Advanced VLAN features are also supported in KS8995M, such as “VLAN ingress filtering” and “discard non PVID” defined in register 18 bit 6 and bit 5. These features can be controlled on a port basis. Rate Limit Support KS8995M supports hardware rate limiting on “receive” and “transmit” independently on a per port basis. It also supports rate limiting in a priority or non-priority environment. The rate limit starts from 0Kbps and goes up to the line rate in steps of 32Kbps. The KS8995M uses one second as an interval. At the beginning of each interval, the counter is cleared to zero, and the rate limit mechanism starts to count the number of bytes during this interval. For receive, if the number of bytes exceeds the programmed limit, the switch will stop receiving packets on the port until the “one second” interval expires. There is an option provided for flow control to prevent packet loss. If the rate limit is programmed greater than or equal to 128Kbps and the byte counter is 8K bytes below the limit, the flow control will be triggered. If the rate limit is programmed lower than 128Kbps and the byte counter is 2K bytes below the limit, the flow control will be triggered. For transmit, if the number of bytes exceeds the programmed limit, the switch will stop transmitting packets on the port until the “one second” interval expires. If priority is enabled, the KS8995M can support different rate controls for both high priority and low priority packets. This can be programmed through registers 21 – 27. M9999-120403 32 December 2003 KS8995M Micrel Configuration Interface The KS8995M can function as a managed switch or unmanaged switch. If no EEPROM or micro-controller exists, the KS8995M will operate from its default setting. Some default settings are configured via strap in options as indicated in the table below. Pin # 1 45 46 Pin Name TEST1 MUX1 MUX2 PU/PD NC NC NC Description NC for normal operation. Factory test pin. MUX1 and MUX2 should be left unconnected for normal operation. They are factory test pins Mode Normal Operation Remote Analog Loopback Mode for Testing only Reserved Power Save Mode for Testing only 62 63 64 65 66 67 PMRXD3 PMRXD2 PMRXD1 PMRXD0 PMRXER PCRS Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O Mux1 NC 0 1 1 Mux2 NC 1 0 1 PHY[5] MII receive bit 3. Strap option: PD (default) = enable flow control; PU = disable flow control. PHY[5] MII receive bit 2. Strap option: PD (default) = disable back pressure; PU = enable back pressure. PHY[5] MII receive bit 1. Strap option: PD (default) = drop excessive collision packets; PU = does not drop excessive collision packets. PHY[5] MII receive bit 0. Strap option: PD (default) = disable aggressive back-off algorithm in half-duplex mode; PU = enable for performance enhancement. PHY[5] MII receive error. Strap option: PD (default) = 1522/1518 bytes; PU = packet size up to 1536 bytes. PHY[5] MII carrier sense/Force duplex mode. See “Register 76” for port 4 only. PD (default) = Force half-duplex if auto-negotiation is disabled or fails. PU = Force full-duplex if auto-negotiation is disabled or fails. PHY[5] MII collision detect/ Force flow control. See “Register 66” for port 4 only. PD (default) = No force flow control. PU = Force flow control. Switch MII receive bit 3. Strap option: PD (default) = Disable Switch MII full-duplex flow control; PU = Enable Switch MII full-duplex flow control. Switch MII receive bit 2. Strap option: PD (default) = Switch MII in full-duplex mode; PU = Switch MII in half-duplex mode. Switch MII receive bit 1. Strap option: PD (default) = Switch MII in 100Mbps mode; PU = Switch MII in 10Mbps mode. Switch MII receive bit 0; Strap option: LED Mode PD (default) = Mode 0; PU = Mode 1. See “Register 11.” Mode 0 LEDX_2 LEDX_1 LEDX_0 Lnk/Act Fulld/Col Speed Mode 1 100Lnk/Act 10Lnk/Act Fulld 68 80 81 82 83 PCOL SMRXD3 SMRXD2 SMRXD1 SMRXD0 Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O December 2003 33 M9999-120403 KS8995M Pin # 86 Pin Name SCONF1 PU/PD Ipd Description Dual MII configuration pin. Pin# (91, 86, 87): 000 001 010 011 100 101 110 111 87 90 91 113 SCONF0 LED5-2 LED5-1 PS1 Ipd Ipu/O Ipu/O Ipd Switch MII Disable, Otri PHY Mode MII MAC Mode MII PHY Mode SNI Disable PHY Mode MII MAC Mode MII PHY Mode SNI PHY [5] MII Disable, Otri Disable, Otri Disable, Otri Disable, Otri Disable PHY Mode MII PHY Mode MII PHY Mode MII Micrel Dual MII configuration pin. LED indicator 2. Strap option: Aging setup. See “Aging” section. PU (default) = Aging Enable; PD = Aging disable. LED indicator 1. Strap option: PU (default): enable PHY MII I/F. PD: tristate all PHY MII output. See “pin# 86 SCONF1.” Serial bus configuration pin If EEPROM is not present, the KS8995M will start itself with chip default (00)... Pin Configuration PS[1:0]=00 PS[1:0]=01 PS[1:0]=10 PS[1:0]=11 Serial Bus Configuration I2C Master Mode for EEPROM Reserved SPI Slave Mode for CPU Interface Factory Test Mode (BIST) 114 128 PS0 TEST2 Ipd NC Serial bus configuration pin. See “pin# 113.” NC for normal operation. Factory test pin. M9999-120403 34 December 2003 KS8995M Micrel I2C Master Serial Bus Configuration If a 2-wire EEPROM exists, the KS8995M can perform more advanced features like “broadcast storm protection,” “rate control,” etc. The EEPROM should have the entire valid configuration data from register 0 to register 109 defined in the “Memory Map,” except the status registers. After reset, the KS8995M will start to read all 110 registers sequentially from the EEPROM. The configuration access time (tprgm) is less than 15ms as shown in Figure 7. RST_N SCL SDA .... .... .... t prgm