KS8995XA

KS8995XA Integrated 5-Port 10/100 QoS Switch Rev 2.6 General Description The KS8995XA is a highly integrated Layer-2 quality of service (QoS) switch with optimized bill of materials (BOM) cost for low port count, cost-sensitive 10/100Mbps switch systems. It also provides an extensive feature set including three different QoS priority schemes, a dual MII interface for BOM cost reduction, rate limiting to offload CPU tasks, software and hardware power-down, a MDC/MDIO control interface and port mirroring/monitoring to effectively address both current and emerging Fast Ethernet applications. The KS8995XA contains five 10/100 transceivers with patented mixed-signal low-power technology, five media access control (MAC) units, a high-speed non-blocking switch fabric, a dedicated address lookup engine, and an on-chip frame buffer memory. All PHY units support 10BASE-T and 100BASE-TX. In addition, two of the PHY units support 100BaseFX (Ports 4 and 5). Functional Diagram Auto MDI/MDI-X Auto MDI/MDI-X Auto MDI/MDI-X Auto MDI/MDI-X Auto MDI/MDI-X MII-P5 MDC, MDI/O MII-SW or SNI LED0[5:1] LED1[5:1] LED2[5:1] 10/100 T/Tx 1 10/100 T/Tx 2 10/100 T/Tx 3 10/100 T/Tx/Fx 4 10/100 T/Tx/Fx 5 10/100 MAC 1 FIFO, Flow Control, VLAN Tagging, Priority 1K Look-Up Engine Queue Mgmnt 10/100 MAC 2 10/100 MAC 3 10/100 MAC 4 10/100 MAC 5 SNI Buffer Mgmnt Frame Buffers LED I/F Control Registers KS8995XA EEPROM I/F Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com September 2008 M9999-091508 Micrel, Inc. KS8995XA Features • Integrated switch with five MACs and five Fast Ethernet transceivers fully compliant to IEEE 802.3u standard • Shared memory based switch fabric with fully nonblocking configuration • 10BASE-T, 100BASE-TX and 100BASE-FX modes (FX in Ports 4 and 5) • Dual MII configuration: MII-Switch (MAC or PHY mode MII) and MII-P5 (PHY mode MII) • VLAN ID tag/untag options, per-port basis • Enable/disable option for huge frame size up to 1916 bytes per frame • Broadcast storm protection with percent control – global and per-port basis • Optimization for fiber-to-copper media conversion • Full-chip hardware power-down support (register configuration not saved) • Per-port-based software power-save on PHY (idle link detection, register configuration preserved) • QoS/CoS packets prioritization supports: per port, 802.1p and DiffServ-based • 802.1p/q tag insertion or removal on a per-port basis (egress) • Port-based VLAN support • MDC and MDI/O interface support to access the MII PHY control registers (not all control registers) • MII local loopback support • On-chip 64Kbyte memory for frame buffering (not shared with 1K unicast address table) • 1.4Gbps high performance memory bandwidth • Wire-speed reception and transmission • Integrated look-up engine with dedicated 1K unicast MAC addresses • Automatic address learning, address aging and address migration • Full-duplex IEEE 802.3x and half-duplex back pressure flow control • Comprehensive LED support • 7-wire SNI support for legacy MAC interface • Automatic MDI/MDI-X crossover for plug-and-play • Disable automatic MDI/MDI-X option • Low power Core: 1.8V Digital I/O: 3.3V Analog I/O: 2.5 or 3.3V • 0.18µm CMOS technology • Commercial temperature range: 0°C to +70°C • Available in 128-pin PQFP package Applications • • • • • • • • • Broadband gateway/firewall/VPN Integrated DSL or cable modem multi-port router Wireless LAN access point plus gateway Home networking expansion Standalone 10/100 switch Hotel/campus/MxU gateway Enterprise VoIP gateway/phone FTTx customer premise equipment Media converter Ordering Information Part Number Standard KS8995XA Pb-Free KSZ8995XA Temperature Range 0°C to +70°C Package 128-Pin PQFP September 2008 2 M9999-091508 Micrel, Inc. KS8995XA Revision History Revision 2.0 2.1 2.2 2.3 Date 10/15/03 4/1/04 1/19/05 4/13/05 Summary of Changes Created. Editorial changes on TTL input and output electrical characteristics. Insert recommended reset circuit. Switched pins names for pins 7 & 8 on page 16. Changed VDDIO to 3.3V. Changed Jitter to 16 ns Max. Update pin description for PCRS, PCOL, etc. Update the description of the register and MIIM register for the loop-back, etc. And update the MII timing diagram. Add package thermal information in the operating rating and the transformer power consumption information in the electrical characteristics note. Add description for the revision ID and LED mode, etc. 2.4 2.5 2.6 7/14/06 6/01/07 9/15/08 September 2008 3 M9999-091508 Micrel, Inc. KS8995XA Contents System Level Applications........................................................................................................................................... 6 Pin Configuration .......................................................................................................................................................... 8 Pin Description (by Number)........................................................................................................................................ 9 Pin Description (by Name) ......................................................................................................................................... 14 Introduction ................................................................................................................................................................. 19 Functional Overview: Physical Layer Transceiver .................................................................................................. 19 100BASE-TX Transmit.............................................................................................................................................. 19 100BASE-TX Receive............................................................................................................................................... 19 PLL Clock Synthesizer.............................................................................................................................................. 19 Scrambler/De-Scrambler (100BASE-TX only).......................................................................................................... 19 100BASE-FX Operation............................................................................................................................................ 20 100BASE-FX Signal Detection ................................................................................................................................. 20 100BASE-FX Far End Fault...................................................................................................................................... 20 10BASE-T Transmit .................................................................................................................................................. 20 10BASE-T Receive ................................................................................................................................................... 20 Power Management.................................................................................................................................................. 20 MDI/MDI-X Auto Crossover ...................................................................................................................................... 20 Auto-Negotiation ....................................................................................................................................................... 20 Functional Overview: Switch Core ............................................................................................................................ 21 Address Look-Up ...................................................................................................................................................... 21 Learning .................................................................................................................................................................... 21 Migration ................................................................................................................................................................... 21 Aging ......................................................................................................................................................................... 21 Switching Engine ...................................................................................................................................................... 22 Media Access Controller (MAC) Operation............................................................................................................... 22 Inter-Packet Gap (IPG) ............................................................................................................................................. 22 Backoff Algorithm ...................................................................................................................................................... 22 Late Collision ............................................................................................................................................................ 22 Illegal Frames ........................................................................................................................................................... 22 Flow Control .............................................................................................................................................................. 22 Half-Duplex Back Pressure ....................................................................................................................................... 22 Broadcast Storm Protection ...................................................................................................................................... 23 MII Interface Operation ............................................................................................................................................. 24 SNI Interface Operation .............................................................................................................................................. 26 Advanced Functionality.............................................................................................................................................. 26 QoS Support ............................................................................................................................................................. 26 Rate Limit Support .................................................................................................................................................... 28 Configuration Interface.............................................................................................................................................. 29 2 I C Master Serial Bus Configuration ......................................................................................................................... 29 MII Management Interface (MIIM) ............................................................................................................................ 29 Register Map................................................................................................................................................................ 30 Global Registers ....................................................................................................................................................... 30 Register 0 (0x00): Chip ID0 ...................................................................................................................................... 30 Register 1 (0x01): Chip ID1/Start Switch .................................................................................................................. 30 Register 2 (0x02): Global Control 0 .......................................................................................................................... 30 Register 3 (0x03): Global Control 1 .......................................................................................................................... 31 Register 4 (0x04): Global Control 2 .......................................................................................................................... 32 Register 5 (0x05): Global Control 3 .......................................................................................................................... 33 Register 6 (0x06): Global Control 4 .......................................................................................................................... 33 Register 7 (0x07): Global Control 5 .......................................................................................................................... 34 Register 8 (0x08): Global Control 6 .......................................................................................................................... 34 Register 9 (0x09): Global Control 7 .......................................................................................................................... 34 Register 10 (0x0A): Global Control 8 ........................................................................................................................ 34 September 2008 4 M9999-091508 Micrel, Inc. KS8995XA Register 11 (0x0B): Global Control 9 ........................................................................................................................ 34 Port Registers ........................................................................................................................................................... 35 Register 16 (0x10): Port 1 Control 0 ......................................................................................................................... 35 Register 17 (0x11): Port 1 Control 1 ......................................................................................................................... 35 Register 18 (0x12): Port 1 Control 2 ......................................................................................................................... 36 Register 19 (0x13): Port 1 Control 3 ......................................................................................................................... 37 Register 20 (0x14): Port 1 Control 4 ......................................................................................................................... 37 Register 21 (0x15): Port 1 Control 5 ......................................................................................................................... 37 Register 22 (0x16): Port 1 Control 6 ......................................................................................................................... 37 Register 23 (0x17): Port 1 Control 7 ......................................................................................................................... 38 Register 24 (0x18): Port 1 Control 8 ......................................................................................................................... 38 Register 25 (0x19): Port 1 Control 9 ......................................................................................................................... 38 Register 26 (0x1A): Port 1 Control 10 ....................................................................................................................... 39 Register 27 (0x1B): Port 1 Control 11 ....................................................................................................................... 39 Register 28 (0x1C): Port 1 Control 12 ...................................................................................................................... 40 Register 29 (0x1D): Port 1 Control 13 ...................................................................................................................... 40 Register 30 (0x1E): Port 1 Status 0 .......................................................................................................................... 41 Register 31 (0x1F): Port 1 Control 14 ....................................................................................................................... 41 Advanced Control Registers ..................................................................................................................................... 43 Register 96 (0x60): TOS Priority Control Register 0 ................................................................................................ 43 Register 97 (0x61): TOS Priority Control Register 1 ................................................................................................ 43 Register 98 (0x62): TOS Priority Control Register 2 ................................................................................................ 43 Register 99 (0x63): TOS Priority Control Register 3 ................................................................................................ 43 Register 100 (0x64): TOS Priority Control Register 4 .............................................................................................. 43 Register 101 (0x65): TOS Priority Control Register 5 .............................................................................................. 43 Register 102 (0x66): TOS Priority Control Register 6 .............................................................................................. 43 Register 103 (0x67): TOS Priority Control Register 7 .............................................................................................. 43 Register 104 (0x68): MAC Address Register 0......................................................................................................... 43 Register 105 (0x69): MAC Address Register 1......................................................................................................... 43 Register 106 (0x6A): MAC Address Register 2 ........................................................................................................ 43 Register 107 (0x6B): MAC Address Register 3 ........................................................................................................ 43 Register 108 (0x6C): MAC Address Register 4 ........................................................................................................ 43 Register 109 (0X6D): MAC Address Register 5 ....................................................................................................... 43 MIIM Registers.......................................................................................................................................................... 44 Register 0: MII Control .............................................................................................................................................. 44 Register 1: MII Status ............................................................................................................................................... 44 Register 2: PHYID HIGH........................................................................................................................................... 45 Register 3: PHYID LOW ........................................................................................................................................... 45 Register 4: Advertisement Ability .............................................................................................................................. 45 Register 5: Link Partner Ability ................................................................................................................................. 45 (1) Absolute Maximum Ratings .................................................................................................................................... 46 (2) Operating Ratings .................................................................................................................................................... 46 (4, 5) Electrical Characteristics ...................................................................................................................................... 46 Timing Diagrams ......................................................................................................................................................... 48 Reset Circuit Diagram................................................................................................................................................. 53 (1) Selection of Isolation Transformer ......................................................................................................................... 54 Package Information ................................................................................................................................................... 55 September 2008 5 M9999-091508 Micrel, Inc. KS8995XA System Level Applications Figure 1. Broadband Gateway Switch Controller On-Chip Frame Bu ffers 10/100 MAC 1 10/100 MAC 2 10/100 MAC 3 10/100 MAC 4 10/100 MAC 5 10/100 PHY 1 10/100 PHY 2 10/100 PHY 3 10/100 PHY 4 10/100 PHY 5 EEPROM I/F EEPROM 4-port LAN CPU Ethernet MAC MII-SW MII-P5 KS8995XA Figure 2. Integrated Broadband Router September 2008 6 M9999-091508 Micrel, Inc. KS8995XA Figure 3. Standalone Switch September 2008 7 M9999-091508 Micrel, Inc. September 2008 Pin Configuration LED2-0 LED1-2 LED1-1 LED1-0 MDC MDIO SPIQ SPIC/SCL SPID/SDA SPIS_N PS1 PS0 RST_N GNDD VDDC TESTEN SCANEN NC X1 X2 VDDAP GNDA VDDAR GNDA GNDA TEST2 103 1 128-Pin PQFP (PQ) 8 39 65 MDIXDIS GNDA VDDAR RXP1 RXM1 GNDA TXP1 TXM1 VDDAT RXP2 RXM2 GNDA TXP2 TXM2 VDDAR GNDA ISET VDDAT RXP3 RXM3 GNDA TXP3 TXM3 VDDAT RXP4 RXM4 GNDA TXP4 TXM4 GNDA VDDAR RXP5 RXM5 GNDA TXP5 TXM5 VDDAT FXSD5 LED2-1 LED2-2 VDDIO GNDD LED3-0 LED3-1 LED3-2 LED4-0 LED4-1 LED4-2 LED5-0 LED5-1 LED5-2 VDDC GNDD SCONF0 SCONF1 SCRS SCOL SMRXD0 SMRXD1 SMRXD2 SMRXD3 SMRXDV SMRXC VDDIO GNDD SMTXC SMTXER SMTXD0 SMTXD1 SMTXD2 SMTXD3 SMTEXN PCOL PCRS PMRXER PMRXD0 PMRXD1 PMRXD2 PMRXD3 PMRXDV PMRXC VDDIO GNDD PMTXC PMTXER PMTXD0 PMTXD1 PMTXD2 PMTXD3 PMTXEN VDDC GNDD RESERVE PWRDN_N MUX2 MUX1 GNDA VDDAR GNDA VDDAR GNDA FXSD4 KS8995XA M9999-091508 Micrel, Inc. KS8995XA Pin Description (by Number) Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Pin Name MDI-XDIS GNDA VDDAR RXP1 RXM1 GNDA TXP1 TXM1 VDDAT RXP2 RXM2 GNDA TXP2 TXM2 VDDAR GNDA ISET VDDAT RXP3 RXM3 GNDA TXP3 TXM3 VDDAT RXP4 RXM4 GNDA TXP4 TXM4 GNDA P I I Gnd O O P I I Gnd O O Gnd 4 4 4 4 3 3 3 3 Type(1) Ipd Gnd P I I Gnd O O P I I Gnd O O P Gnd 2 2 2 2 1 1 1 1 Port 1-5 Pin Function(2) Disable auto MDI/MDI-X. PD (default) = normal operation. PU = disable auto MDI/MDI-X on all ports. Analog ground. 1.8V analog VDD. Physical receive signal + (differential). Physical receive signal – (differential). Analog ground. Physical transmit signal + (differential). Physical transmit signal – (differential). 2.5V or 3.3V analog VDD. Physical receive signal + (differential). Physical receive signal – (differential). Analog ground. Physical transmit signal + (differential). Physical transmit signal – (differential). 1.8V analog VDD. Analog ground. Set physical transmit output current. Pull-down with a 3.01kΩ1% resistor. 2.5V or 3.3V analog VDD. Physical receive signal + (differential). Physical receive signal - (differential). Analog ground. Physical transmit signal + (differential). Physical transmit signal – (differential). 2.5V or 3.3V analog VDD. Physical receive signal + (differential). Physical receive signal - (differential). Analog ground. Physical transmit signal + (differential). Physical transmit signal – (differential). Analog ground. Notes: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/internal pull-up. Ipd = Input w/internal pull-down. Ipd/O = Input w/internal pull-down during reset, output pin otherwise. Ipu/O = Input w/internal pull-up during reset, output pin otherwise. 2. PU = Strap pin pull-up. PD = Strap pull-down. Otri = Output tristated. September 2008 9 M9999-091508 Micrel, Inc. KS8995XA Pin Number 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Pin Name VDDAR RXP5 RXM5 GNDA TXP5 TXM5 VDDAT FXSD5 FXSD4 GNDA VDDAR GNDA VDDAR GNDA NC / MUX1 NC / MUX2 PWRDN_N RESERVE/NC GNDD VDDC PMTXEN PMTXD3 PMTXD2 PMTXD1 PMTXD0 PMTXER PMTXC GNDD VDDIO PMRXC Type(1) P I I Gnd O O P I I Gnd P Gnd P Gnd I I Ipu Port 5 5 Pin Function(2) 1.8V analog VDD. Physical receive signal + (differential). Physical receive signal – (differential). Analog ground. 5 5 Physical transmit signal + (differential). Physical transmit signal – (differential). 2.5V or 3.3V analog VDD. 5 4 Fiber signal detect/factory test pin. Fiber signal detect/factory test pin. Analog ground. 1.8V analog VDD. Analog ground. 1.8V analog VDD. Analog ground. No connect. Factory test pin. No connect. Factory test pin. Full-chip power down. Active low. Reserved pin. No connect. Gnd P Ipd Ipd Ipd Ipd Ipd Ipd O Gnd P O 5 5 5 5 5 5 5 5 Digital ground. 1.8V digital core VDD. PHY[5] MII transmit enable. PHY[5] MII transmit bit 3. PHY[5] MII transmit bit 2. PHY[5] MII transmit bit 1. PHY[5] MII transmit bit 0. PHY[5] MII transmit error. PHY[5] MII transmit clock. PHY mode MII. Digital ground. 3.3V digital VDD for digital I/O circuitry. PHY[5] MII receive clock. PHY mode MII. Notes: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/internal pull-up. Ipd = Input w/internal pull-down. Ipd/O = Input w/internal pull-down during reset, output pin otherwise. Ipu/O = Input w/internal pull-up during reset, output pin otherwise. 2. PU = Strap pin pull-up. PD = Strap pull-down. Otri = Output tristated. September 2008 10 M9999-091508 Micrel, Inc. KS8995XA Pin Number 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 Pin Name PMRXDV PMRXD3 PMRXD2 PMRXD1 PMRXD0 PMRXER PCRS PCOL SMTXEN SMTXD3 SMTXD2 SMTXD1 SMTXD0 SMTXER SMTXC GNDD VDDIO SMRXC SMRXDV SMRXD3 SMRXD2 SMRXD1 SMRXD0 SCOL SCRS Type(1) Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O Ipd Ipd Ipd Ipd Ipd Ipd I/O Gnd P I/O Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O Port 5 5 5 5 5 5 5 5 Pin Function(2) PHY[5] MII receive data valid. PHY[5] MII receive bit 3. Strap option: PD (default) = enable flow control; PU = disable flow control. PHY[5] MII receive bit 2. Strap option: PD (default) = disable back pressure; PU = enable back pressure. PHY[5] MII receive bit 1. Strap option: PD (default) = drop excessive collision packets; PU = does not drop excessive collision packets. PHY[5] MII receive bit 0. Strap option: PD (default) = disable aggressive back-off algorithm in half-duplex mode; PU = enable for performance enhancement. PHY[5] MII receive error. Strap option: PD (default) = packet size 1518/1522 bytes; PU = 1536 bytes. PHY[5] MII carrier sense/strap option for port 4 only. PD (default) = force half-duplex if auto-negotiation is disabled or fails. PU = force fullduplex if auto negotiation is disabled or fails. Refer to Register 76. PHY[5] MII collision detect/ strap option for port 4 only. PD (default) = no force flow control, normal operation. PU = force flow control. Refer to Register 66. Switch MII transmit enable. Switch MII transmit bit 3. Switch MII transmit bit 2. Switch MII transmit bit 1. Switch MII transmit bit 0. Switch MII transmit error. Switch MII transmit clock. PHY or MAC mode MII. Digital ground. 3.3V digital VDD for digital I/O circuitry. Switch MII receive clock. PHY or MAC mode MII. Switch MII receive data valid. Switch MII receive bit 3. Strap option: PD (default) = Disable Switch MII full-duplex flow control; PU = Enable Switch MII full-duplex flow control. Switch MII receive bit 2. Strap option: PD (default) = Switch MII in fullduplex mode; PU = Switch MII in half-duplex mode. Switch MII receive bit 1. Strap option: PD (default) = Switch MII in 100Mbps mode; PU = Switch MII in 10Mbps mode. Switch MII receive bit 0; Strap option: see “Register 11[1].” Switch MII collision detect. Switch mode carrier sense. Notes: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/internal pull-up. Ipd = Input w/internal pull-down. Ipd/O = Input w/internal pull-down during reset, output pin otherwise. Ipu/O = Input w/internal pull-up during reset, output pin otherwise. 2. PU = Strap pin pull-up. PD = Strap pull-down. Otri = Output tristated. September 2008 11 M9999-091508 Micrel, Inc. KS8995XA Pin Number 86 Pin Name SCONF1 Type(1) Ipd Port Pin Function(2) Dual MII configuration pin. Pin# (91, 86, 87): 000 001 010 011 100 101 110 111 Switch MII Disable, Otri PHY Mode MII MAC Mode MII PHY Mode SNI Disable PHY Mode MII MAC Mode MII PHY Mode SNI PHY [5] MII Disable, Otri Disable, Otri Disable, Otri Disable, Otri Disable PHY Mode MII PHY Mode MII PHY Mode MII 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 SCONF0 GNDD VDDC LED5-2 LED5-1 LED5-0 LED4-2 LED4-1 LED4-0 LED3-2 LED3-1 LED3-0 GNDD VDDIO LED2-2 LED2-1 LED2-0 LED1-2 LED1-1 LED1-0 Ipd Gnd P Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Gnd P Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O 2 2 2 1 1 1 5 5 5 4 4 4 3 3 3 Dual MII configuration pin. Digital ground. 1.8V digital core VDD. LED indicator 2. Aging setup. See “Aging” section. LED indicator 1. Strap option: PU (default): enable PHY[5] MII I/F. PD: tristate all PHY[5] MII output. See “Pin# 86 SCONF1.” LED indicator 0. LED indicator 2. LED indicator 1. LED indicator 0. LED indicator 2. LED indicator 1. LED indicator 0. Digital ground. 3.3V digital VDD for digital I/O. LED indicator 2. LED indicator 1. LED indicator 0. LED indicator 2. LED indicator 1. LED indicator 0. Notes: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/internal pull-up. Ipd = Input w/internal pull-down. Ipd/O = Input w/internal pull-down during reset, output pin otherwise. Ipu/O = Input w/internal pull-up during reset, output pin otherwise. NC = No connect. 2. PU = Strap pin pull-up. PD = Strap pull-down. Otri = Output tristated. September 2008 12 M9999-091508 Micrel, Inc. KS8995XA Pin Number 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Pin Name LED1-0 MDC MDIO Reserved SCL SDA Reserved PS1 PS0 RST_N GNDD VDDC TESTEN SCANEN NC X1 X2 VDDAP GNDA VDDAR GNDA GNDA TEST2 Type(1) Ipu/O Ipu Ipu/O Port 1 All All All Pin Function LED indicator 0.(2) Switch or PHY[5] MII management data clock.(2) Switch or PHY[5] MII management data I/O. No connect. Output clock at 81kHz in I2C master mode. Serial data input/output in I2C master mode. No connect No connect or pull-down. No connect or pull-down. Reset the KS8995XA. Active low. Digital ground. 1.8V digital core VDD. Factory test pin. Factory test pin. No connection. 25MHz crystal clock connection/or 3.3V tolerant oscillator input. Oscillator should be ±100ppm. 25MHz crystal clock connection. 1.8V analog VDD for PLL. Analog ground. 1.8V analog VDD. Analog ground. Analog ground. Factory test pin. I/O I/O All All All Ipd Ipd Ipu Gnd P Ipd Ipd NC I O P Gnd P Gnd Gnd Notes: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/internal pull-up. Ipd = Input w/internal pull-down. Ipd/O = Input w/internal pull-down during reset, output pin otherwise. Ipu/O = Input w/internal pull-up during reset, output pin otherwise. NC = No connect. 2. PU = Strap pin pull-up. PD = Strap pull-down. Otri = Output tristated. September 2008 13 M9999-091508 Micrel, Inc. KS8995XA Pin Description (by Name) Pin Number 39 38 2 6 12 16 21 27 30 34 40 42 44 120 124 126 127 49 58 76 88 99 116 17 106 105 104 103 102 101 98 97 Pin Name FXSD4 FXSD5 GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA NC GNDA GNDA GNDA GNDD GNDD GNDD GNDD GNDD GNDD ISET LED1-0 LED1-1 LED1-2 LED2-0 LED2-1 LED2-2 LED3-0 LED3-1 Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O 1 1 1 2 2 2 3 3 Type(1) I I Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd NC Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Port 4 5 Pin Function Fiber signal detect/factory test pin. Fiber signal detect/factory test pin. Analog ground. Analog ground. Analog ground. Analog ground. Analog ground. Analog ground. Analog ground. Analog ground. Analog ground. Analog ground. Analog ground. No connection. Analog ground. Analog ground. Analog ground. Digital ground. Digital ground. Digital ground. Digital ground. Digital ground. Digital ground. Set physical transmit output current. Pull down with a 3.01kΩ1% resistor. LED indicator 0. LED indicator 1. LED indicator 2. LED indicator 0. LED indicator 1. LED indicator 2. LED indicator 0. LED indicator 1. Notes: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/internal pull-up. Ipd = Input w/internal pull-down. Ipd/O = Input w/internal pull-down during reset, output pin otherwise. Ipu/O = Input w/internal pull-up during reset, output pin otherwise. NC = No connect. September 2008 14 M9999-091508 Micrel, Inc. KS8995XA Pin Number 96 95 94 93 92 91 90 107 108 45 46 68 67 60 65 64 63 62 61 66 57 55 54 53 52 51 56 114 113 Pin Name LED3-2 LED4-0 LED4-1 LED4-2 LED5-0 LED5-1 LED5-2 MDC MDIO NC / MUX1 NC / MUX2 PCOL PCRS PMRXC PMRXD0 PMRXD1 PMRXD2 PMRXD3 PMRXDV PMRXER PMTXC PMTXD0 PMTXD1 PMTXD2 PMTXD3 PMTXEN PMTXER PS0 PS1 Type(1) Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu Ipu/O Port 3 4 4 4 5 5 5 All All I I Pin Function(2) LED indicator 2. LED indicator 0. LED indicator 1. LED indicator 2. LED indicator 0. LED indicator 1. Strap option: PU (default): enable PHY MII I/F Pd: tristate all PHY MII output. See “Pin# 86 SCONF1.” LED indicator 2. Aging setup. See “Aging” section. Switch or PHY[5] MII management data clock. Switch or PHY[5] MII management data I/O. No connect. Factory test pin. No connect. Factory test pin. PHY[5] MII collision detect/ strap option for port 4 only. PD (default) = no force flow control, normal operation. PU = force flow control. Refer to Register 66. PHY[5] MII carrier sense/strap option for port 4 only. PD (default) = force half-duplex if auto-negotiation is disabled or fails. PU = force fullduplex if auto negotiation is disabled or fails. Refer to Register 76. PHY[5] MII receive clock. PHY mode MII. PHY[5] MII receive bit 0. Strap option: PD (default) = disable aggressive back-off algorithm in half-duplex mode; PU = enable for performance enhancement. PHY[5] MII receive bit 1. Strap option: PD (default) = drop excessive collision packets; PU = does not drop excessive collision packets. PHY[5] MII receive bit 2. Strap option: PD (default) = disable back pressure; PU = enable back pressure. PHY[5] MII receive bit 3. Strap option: PD (default) = enable flow control; PU = disable flow control. PHY[5] MII receive data valid. PHY[5] MII receive error. Strap option: PD (default) = packet size 1518/ 1522 bytes; PU = 1536 bytes. PHY[5] MII transmit clock. PHY mode MII. PHY[5] MII transmit bit 0. PHY[5] MII transmit bit 1. PHY[5] MII transmit bit 2. PHY[5] MII transmit bit 3. PHY[5] MII transmit enable. PHY[5] MII transmit error. No connect or pull down. No connect or pull down. 2. PU = Strap pin pull-up. PD = Strap pull-down. Ipd/O Ipd/O O Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O O Ipd Ipd Ipd Ipd Ipd Ipd Ipd Ipd 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Notes: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/internal pull-up. Ipd = Input w/internal pull-down. Ipd/O = Input w/internal pull-down during reset, output pin otherwise. Ipu/O = Input w/internal pull-up during reset, output pin otherwise. September 2008 15 M9999-091508 Micrel, Inc. KS8995XA Pin Number 47 48 109 112 115 5 11 20 26 33 4 10 19 25 32 119 110 84 87 86 Pin Name PWRDN_N RESERVE/NC Reserved Reserved RST_N RXM1 RXM2 RXM3 RXM4 RXM5 RXP1 RXP2 RXP3 RXP4 RXP5 SCANEN SCL SCOL SCONF0 SCONF1 Type(1) Ipu Port Pin Function(2) Full-chip power down. Active low. Reserved pin. No connect. All All Ipu I I I I I I I I I I Ipd I/O Ipd/O Ipd Ipd All 1 2 3 4 5 1 2 3 4 5 No connect. No connect. Reset the KS8995X. Active low. Physical receive signal - (differential). Physical receive signal - (differential). Physical receive signal - (differential). Physical receive signal - (differential). Physical receive signal - (differential). Physical receive signal + (differential). Physical receive signal + (differential). Physical receive signal + (differential). Physical receive signal + (differential). Physical receive signal + (differential). Factory test pin. Output clock at 81kHz in I2C master mode. See “Pin# 113.” Switch MII collision detect. Dual MII configuration pin. Dual MII configuration pin. Pin# (91, 86, 87): 000 001 010 011 100 101 110 111 Switch MII Disable, Otri PHY Mode MII MAC Mode MII PHY Mode SNI Disable PHY Mode MII MAC Mode MII PHY Mode SNI PHY [5] MII Disable, Otri Disable, Otri Disable, Otri Disable, Otri Disable PHY Mode MII PHY Mode MII PHY Mode MII 85 111 78 83 SCRS SDA SMRXC SMRXD0 Ipd/O I /O I/O Ipd/O All Switch MII carrier sense. Serial data input/output in I2C master mode. See “Pin# 113.” Switch MII receive clock. PHY or MAC mode MII. Switch MII receive bit 0; strap option: see “Register 11[1].” 2. Otri = Output tristated. Notes: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/internal pull-up. Ipd = Input w/internal pull-down. Ipd/O = Input w/internal pull-down during reset, output pin otherwise. Ipu/O = Input w/internal pull-up during reset, output pin otherwise. September 2008 16 M9999-091508 Micrel, Inc. KS8995XA Pin Number 82 81 80 79 75 73 72 71 70 69 74 1 128 118 7 13 22 28 35 8 14 23 29 36 123 3 15 31 41 43 125 Pin Name SMRXD1 SMRXD2 SMRXD3 SMRXDV SMTXC SMTXD0 SMTXD1 SMTXD2 SMTXD3 SMTXEN SMTXER MDIXDIS TEST2 TESTEN TXP1 TXP2 TXP3 TXP4 TXP5 TXM1 TXM2 TXM3 TXM4 TXM5 VDDAP VDDAR VDDAR VDDAR VDDAR VDDAR VDDAR Type(1) Ipd/O Ipd/O Ipd/O Ipd/O I/O Ipd Ipd Ipd Ipd Ipd Ipd Ipd Port Pin Function(2) Switch MII receive bit 1. Strap option: PD (default) = Switch MII in 100Mbps mode; PU = Switch MII in 10Mbps mode. Switch MII receive bit 2. Strap option: PD (default) = Switch MII in fullduplex mode; PU = Switch MII in half-duplex mode. Switch MII receive bit 3. Strap option: PD (default) = Disable Switch MII full-duplex flow control; PU = Enable Switch MII full-duplex flow control. Switch MII receive data valid. Switch MII transmit clock. PHY or MAC mode MII. Switch MII transmit bit 0. Switch MII transmit bit 1. Switch MII transmit bit 2. Switch MII transmit bit 3. Switch MII transmit enable. Switch MII transmit error. 1-5 Disable auto MDI/MDI-X. Factory test pin. Ipd O O O O O O O O O O P P P P P P P 1 2 3 4 5 1 2 3 4 5 Factory test pin. Physical transmit signal + (differential). Physical transmit signal + (differential). Physical transmit signal + (differential). Physical transmit signal + (differential). Physical transmit signal + (differential). Physical transmit signal – (differential). Physical transmit signal – (differential). Physical transmit signal – (differential). Physical transmit signal – (differential). Physical transmit signal – (differential). 1.8V analog VDD for PLL. 1.8V analog VDD. 1.8V analog VDD. 1.8V analog VDD. 1.8V analog VDD. 1.8V analog VDD. 1.8V analog VDD. Notes: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/internal pull-up. Ipd = Input w/internal pull-down. Ipd/O = Input w/internal pull-down during reset, output pin otherwise. Ipu/O = Input w/internal pull-up during reset, output pin otherwise. 2. PU = Strap pin pull-up. PD = Strap pull-down. September 2008 17 M9999-091508 Micrel, Inc. KS8995XA Pin Number 9 18 24 37 50 89 117 59 77 100 121 122 Pin Name VDDAT VDDAT VDDAT VDDAT VDDC VDDC VDDC VDDIO VDDIO VDDIO X1 X2 Type(1) P P P P P P P P P P I O Port Pin Function 2.5V or 3.3V analog VDD. 2.5V or 3.3V analog VDD. 2.5V or 3.3V analog VDD. 2.5V or 3.3V analog VDD. 1.8V digital core VDD. 1.8V digital core VDD. 1.8V digital core VDD. 3.3V digital VDD for digital I/O circuitry. 3.3V digital VDD for digital I/O circuitry. 3.3V digital VDD for digital I/O circuitry. 25MHz crystal clock connection/or 3.3V tolerant oscillator input. Oscillator should be ±100ppm. 25MHz crystal clock connection. Notes: 1. P = Power supply. I = Input. O = Output. September 2008 18 M9999-091508 Micrel, Inc. KS8995XA Introduction The KS8995XA contains five 10/100 physical layer transceivers and five media access control (MAC) units with an integrated Layer 2 switch. The device runs in three modes. The first mode is as a five-port integrated switch. The second is as a five-port switch with the fifth port decoupled from the physical port. In this mode access to the fifth MAC is provided through a media independent interface (MII) . This is useful for implementing an integrated broadband router. The third mode uses the dual MII feature to recover the use of the fifth PHY. This allows the additional broadband gateway configuration, where the fifth PHY may be accessed through the MII-P5 port. The KS8995XA is optimized for an unmanaged design in which the configuration is achieved through I/O strapping or EEPROM programming at system reset time. On the media side, the KS8995XA supports IEEE 802.3 10BASE-T, 100BASE-TX on all ports, and 100BASE-FX on ports 4 and 5. The KS8995XA can be used as two separate media converters. Physical signal transmission and reception are enhanced through the use of patented analog circuitry that makes the design more efficient and allows for lower power consumption and smaller chip die size. The major enhancements from the KS8995E to the KS8995XA are support for programmable rate limiting, a dual MII interface, MDC/MDIO control interface for IEEE 802.3-defined register configuration (not all the registers), per-port broadcast storm protection, local loopback and lower power consumption. The KS8995XA is pin-compatible to the managed switch, the KS8995M. Functional Overview: Physical Layer Transceiver 100BASE-TX Transmit The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI conversion, MLT3 encoding and transmission. The circuit starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B coding followed by a scrambler. The serialized data is further converted from NRZ to NRZI format, and then transmitted in MLT3 current output. The output current is set by an external 1% 3.01kΩ resistor for the 1:1 transformer ratio. It has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot and timing jitter. The wave-shaped 10BASE-T output is also incorporated into the 100BASE-TX transmitter. 100BASE-TX Receive The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding and serial-to-parallel conversion. The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss and phase distortion is a function of the length of the cable, the equalizer has to adjust its characteristics to optimize the performance. In this design, the variable equalizer will make an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, then it tunes itself for optimization. This is an ongoing process and can self-adjust against environmental changes such as temperature variations. The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used to compensate for the effect of baseline wander and improve the dynamic range. The differential data conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive. The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal into the NRZ format. The signal is then sent through the de-scrambler followed by the 4B/5B decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC. PLL Clock Synthesizer The KS8995XA generates 125MHz, 42MHz, 25MHz, and 10MHz clocks for system timing. Internal clocks are generated from an external 25MHz crystal. Scrambler/De-Scrambler (100BASE-TX only) The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline September 2008 19 M9999-091508 Micrel, Inc. KS8995XA wander. The data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). This can generate a 2047-bit nonrepetitive sequence. The receiver will then de-scramble the incoming data stream with the same sequence at the transmitter. 100BASE-FX Operation 100BASE-FX operation is very similar to 100BASE-TX operation except that the scrambler/de-scrambler and MLT3 encoder/decoder are bypassed on transmission and reception. In this mode the auto-negotiation feature is bypassed since there is no standard that supports fiber auto-negotiation. 100BASE-FX Signal Detection The physical port runs in 100BASE-FX mode if FXSDx >0.6V for ports 4 and 5 only. This signal is internally referenced to 1.25V.The fiber module interface should be set by a voltage divider such that FXSDx ‘H’ is above this 1.25V reference, indicating signal detect, and FXSDx ‘L’ is below the 1.25V reference to indicate no signal. When FXSDx is below 0.6V then 100BASE-FX mode is disabled. 100BASE-FX Far End Fault Far end fault occurs when the signal detection is logically false from the receive fiber module. When this occurs, the transmission side signals the other end of the link by sending 84 1’s followed by a zero in the idle period between frames. The far end fault may be disabled through register settings. 10BASE-T Transmit The output 10BASE-T driver is incorporated into the 100BASE-T driver to allow transmission with the same magnetics. They are internally wave-shaped and pre-emphasized into outputs with a typical 2.3V amplitude. The harmonic contents are at least 27dB below the fundamental when driven by an all-ones Manchester-encoded signal. 10BASE-T Receive On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and a PLL perform the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400mV or with short pulsewidths in order to prevent noises at the RXP or RXM input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KS8995XA decodes a data frame. The receiver clock is maintained active during idle periods in between data reception. Power Management The KS8995XA features a per port power down mode. To save power the user can power down ports that are not in use by setting port control registers or MII control registers. In addition, it also supports full chip power down mode. When activated, the entire chip will be shutdown. MDI/MDI-X Auto Crossover The KS8995XA supports MDI/MDI-X auto crossover. This facilitates the use of either a straight connection CAT-5 cable or a crossover CAT-5 cable. The auto-sense function will detect remote transmit and receive pairs, and correctly assign the transmit and receive pairs from the Micrel device. This can be highly useful when end users are unaware of cable types and can also save on an additional uplink configuration connection. The auto crossover feature may be disabled through the port control registers. Auto-Negotiation The KS8995XA conforms to the auto-negotiation protocol as described by the 802.3 committee. Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the best common mode of operation. In auto-negotiation the link partners advertise capabilities across the link to each other. If auto-negotiation is not supported or the link partner to the KS8995XA is forced to bypass auto-negotiation, then the mode is set by observing the signal at the receiver. This is known as parallel mode because while the transmitter is sending auto-negotiation advertisements, the receiver is listening for advertisements or a fixed signal protocol. The flow for the link set up is depicted in Figure 4. September 2008 20 M9999-091508 Micrel, Inc. KS8995XA Start Auto Negotiation Force Link Setting No Yes Bypass Auto-Negotiation and Set Link Mode Attempt Auto-Negotiation Listen for 100BaseTX Idles Listen for 10BaseT Link Pulses No Join Flow Link Mode Set ? Yes Link Mode Set Figure 4. Auto-Negotiation Functional Overview: Switch Core Address Look-Up The internal look-up table stores MAC addresses and their associated information. It contains a 1K unicast address table plus switching information. The KS8995XA is guaranteed to learn 1K addresses and distinguishes itself from hash-based look-up tables which, depending on the operating environment and probabilities, may not guarantee the absolute number of addresses it can learn. Learning The internal look-up engine will update its table with a new entry if the following conditions are met: • The received packet’s source address (SA) does not exist in the look-up table. • The received packet is good; the packet has no receiving errors, and is of legal length. The look-up engine will insert the qualified SA into the table, along with the port number, time stamp. If the table is full, the last entry of the table will be deleted first to make room for the new entry. Migration The internal look-up engine also monitors whether a station is moved. If it happens, it will update the table accordingly. Migration happens when the following conditions are met: • The received packet’s SA is in the table but the associated source port information is different. • The received packet is good; the packet has no receiving errors, and is of legal length. The look-up engine will update the existing record in the table with the new source port information. Aging The look-up engine will update the time stamp information of a record whenever the corresponding SA appears. The time stamp is used in the aging process. If a record is not updated for a period of time, the look-up engine will remove the record from the table. The look-up engine constantly performs the aging process and will continuously remove aging records. The aging period is 300 ±75 seconds. This feature can be enabled or disabled through register 3 or by external pull-up or pull-down resistors on LED[5][2]. See “Register 3” section. September 2008 21 M9999-091508 Micrel, Inc. KS8995XA Switching Engine The KS8995XA features a high performance switching engine to move data to and from the MAC’s packet buffers. It operates in store and forward mode, while the efficient switching mechanism reduces overall latency. The KS8995XA has a 64kB internal frame buffer. This resource is shared between all five ports. The buffer sharing mode can be programmed through Register 2. See “Register 2.” In one mode, ports are allowed to use any free buffers in the buffer pool. In the second mode, each port is only allowed to use 1/5 of the total buffer pool. There are a total of 512 buffers available. Each buffer is sized at 128B. Media Access Controller (MAC) Operation The KS8995XA strictly abides by IEEE 802.3 standards to maximize compatibility. Inter-Packet Gap (IPG) If a frame is successfully transmitted, the 96-bit time IPG is measured between the two consecutive MTXEN. If the current packet is experiencing collision, the 96-bit time IPG is measured from MCRS and the next MTXEN. Backoff Algorithm The KS8995XA implements the IEEE Std. 802.3 binary exponential back-off algorithm, and optional “aggressive mode” back off. After 16 collisions, the packet will be optionally dropped depending on the chip configuration in Register 3. See “Register 3.” Late Collision If a transmit packet experiences collisions after 512-bit times of the transmission, the packet will be dropped. Illegal Frames The KS8995XA discards frames less than 64 bytes and can be programmed to accept frames up to 1536 bytes in Register 4. For special applications, the KS8995XA can also be programmed to accept frames up to 1916 bytes in Register 4. Since the KS8995XA supports VLAN tags, the maximum sizing is adjusted when these tags are present. Flow Control The KS8995XA supports standard 802.3x flow control frames on both transmit and receive sides. On the receive side, if the KS8995XA receives a pause control frame, the KS8995XA will not transmit the next normal frame until the timer, specified in the pause control frame, expires. If another pause frame is received before the current timer expires, the timer will be updated with the new value in the second pause frame. During this period (being flow controlled), only flow control packets from the KS8995XA will be transmitted. On the transmit side, the KS8995XA has intelligent and efficient ways to determine when to invoke flow control. The flow control is based on availability of the system resources, including available buffers, available transmit queues and available receive queues. The KS8995XA will flow control a port, which just received a packet, if the destination port resource is being used up. The KS8995XA will issue a flow control frame (XOFF), containing the maximum pause time defined in IEEE standard 802.3x. Once the resource is freed up, the KS8995XA will send out the other flow control frame (XON) with zero pause time to turn off the flow control (turn on transmission to the port). A hysteresis feature is provided to prevent the flow control mechanism from being activated and deactivated too many times. The KS8995XA will flow control all ports if the receive queue becomes full. Half-Duplex Back Pressure A half-duplex back pressure option (note: not in 802.3 standards) is also provided. The activation and deactivation conditions are the same as the above in full-duplex mode. If back pressure is required, the KS8995XA will send preambles to defer the other stations’ transmission (carrier sense deference). To avoid jabber and excessive deference defined in 802.3 standard, after a certain time it will discontinue the carrier sense but it will raise the carrier sense quickly. This short silent time (no carrier sense) is to prevent other stations from sending out packets and keeps other stations in carrier sense deferred state. If the port has packets to send during a back pressure situation, the carrier-sense-type back pressure will be interrupted and those packets will be transmitted instead. If there are no September 2008 22 M9999-091508 Micrel, Inc. KS8995XA more packets to send, carrier-sense-type back pressure will be active again until switch resources are free. If a collision occurs, the binary exponential back-off algorithm is skipped and carrier sense is generated immediately, reducing the chance of further colliding and maintaining carrier sense to prevent reception of packets. To ensure no packet loss in 10BASE-T or 100BASE-TX half-duplex modes, the user must enable the following: • • Aggressive backoff (register 3, bit 0) No excessive collision drop (register 4, bit 3) • Back pressure (register 4, bit 5) These bits are not set as the default because this is not the IEEE standard. Broadcast Storm Protection The KS8995XA has an intelligent option to protect the switch system from receiving too many broadcast packets. Broadcast packets will be forwarded to all ports except the source port, and thus use too many switch resources (bandwidth and available space in transmit queues). The KS8995XA has the option to include “multicast packets” for storm control. The broadcast storm rate parameters are programmed globally, and can be enabled or disabled on a per port basis. The rate is based on a 50ms interval for 100BT and a 500ms interval for 10BT. At the beginning of each interval, the counter is cleared to zero, and the rate limit mechanism starts to count the number of bytes during the interval. The rate definition is described in Register 6 and Register 7. The default setting for registers 6 and 7 is 0x4A, which is 74 decimal. This is equal to a rate of 1%, calculated as follows: 148,800 frames/sec × 50ms/interval × 1% = 74 frames/interval (approx.) = 0x4 September 2008 23 M9999-091508 Micrel, Inc. KS8995XA MII Interface Operation The media independent interface (MII) is specified by the IEEE 802.3 committee and provides a common interface between physical layer and MAC layer devices. The KS8995XA provides two such interfaces. The MII-P5 interface is used to connect to the fifth PHY, whereas the MII-SW interface is used to connect to the fifth MAC. Each of these MII interfaces contains two distinct groups of signals, one for transmission and the other for receiving. The table below describes the signals used in the MII-P5 interface. The MII-P5 interface operates in PHY mode only, while the MII-SW interface operates in either MAC mode or PHY mode. These interfaces are nibble-wide data interfaces and therefore run at 1/4 the network bit rate (not encoded). Additional signals on the transmit side indicate when data is valid or when an error occurs during transmission. Likewise, the receive side has indicators that convey when the data is valid and without physical layer errors. For half-duplex operation, there is a signal that indicates a collision has occurred during transmission. Note that the signal MRXER is not provided on the MII-SW interface for PHY mode operation and the signal MTXER is not provided on the MII-SW interface for MAC mode operation. Normally MRXER would indicate a receive error coming from the physical layer device. MTXER would indicate a transmit error from the MAC device. These signals are not appropriate for this configuration. For PHY mode operation, if the device interfacing with the KS8995XA has an MRXER pin, it should be tied low. For MAC mode operation, if the device interfacing with the KS8995XA has an MTXER pin, it should be tied low. MII Signal MTXEN MTXER MTXD3 MTXD2 MTXD1 MTXD0 MTXC MCOL MCRS MRXDV MRXER MRXD3 MRXD2 MRXD1 MRXD0 MRXC MDC MDIO Description Transmit enable Transmit error Transmit data bit 3 Transmit data bit 2 Transmit data bit 1 Transmit data bit 0 Transmit clock Collision detection Carrier sense Receive data valid Receive error Receive data bit 3 Receive data bit 2 Receive data bit 1 Receive data bit 0 Receive clock Management data clock Management data I/O Table 1. MII – P5 Signals (PHY Mode) KS8995XA Signal PMTXEN PMTXER PMTXD[3] PMTXD[2] PMTXD[1] PMTXD[0] PMTXC PCOL PCRS PMRXDV PMRXER PMRXD[3] PMRXD[2] PMRXD[1] PMRXD[0] PMRXC MDC MDIO September 2008 24 M9999-091508 Micrel, Inc. KS8995XA PHY Mode Connection External MAC MTXEN MTXER MTXD3 MTXD2 MTXD1 MTXD0 MTXC MCOL MCRS MRXDV MRXER MRXD3 MRXD2 MRXD1 MRXD0 MRXC KS8995XA Signal SMTXEN SMTXER SMTXD[3] SMTXD[2] SMTXD[1] SMTXD[0] SMTXC SCOL SCRS SMRXDV Not used SMRXD[3] SMRXD[2] SMRXD[1] SMRXD[0] SMRXC Description Transmit enable Transmit error Transmit data bit 3 Transmit data bit 2 Transmit data bit 1 Transmit data bit 0 Transmit clock Collision detection Carrier sense Receive data valid Receive error Receive data bit 3 Receive data bit 2 Receive data bit 1 Receive data bit 0 Receive clock Table 2. MII – SW Signals MAC Mode Connection External PHY MTXEN MTXER MTXD3 MTXD2 MTXD1 MTXD0 MTXC MCOL MCRS MRXDV MRXER MRXD3 MRXD2 MRXD1 MRXD0 MRXC KS8995XA Signal SMRXDV Not used SMRXD[3] SMRXD[2] SMRXD[1] SMRXD[0] SMRXC SCOL SCRS SMTXEN SMTXER SMTXD[3] SMTXD[2] SMTXD[1] SMTXD[0] SMTXC September 2008 25 M9999-091508 Micrel, Inc. KS8995XA SNI Interface Operation The serial network interface (SNI) is compatible with some controllers used for network layer protocol processing. This interface can be directly connected to these types of devices. The signals are divided into two groups, one for transmission and the other for reception. The signals involved are described in the table below. SNI Signal TXEN TXD TXC COL CRS RXD RXC Description Transmit Enable Serial Transmit Data Transmit Clock Collision Detection Carrier Sense Serial Receive Data Receive Clock Table 3. SNI Signals KS8995XA Signal SMTXEN SMTXD[0] SMTXC SCOL SMRXDV SMRXD[0] SMRXC This interface is a bit-wide data interface and therefore runs at the network bit rate (not encoded). An additional signal on the transmit side indicates when data is valid. Likewise, the receive side has an indicator that conveys when the data is valid. For half-duplex operation there is a signal that indicates a collision has occurred during transmission. Advanced Functionality QoS Support The KS8995XA is a QoS switch, meaning that is it able to identify selected packets on its ingress ports, prioritize them, and service the packets according to their priority on the egress ports. In this way, the KS8995XA can provide statistically better service to the high priority packets that are latency sensitive, or require higher bandwidth. The KS8995XA supports ingress QoS classification using three different mechanisms: port-based priority, 802.1p tagbased priority, and DSCP priority for IPv4 packets. Port-based priority is useful when the user wants to give a device on a given port high priority. For example in Figure 7, port 1 is given high priority because it is connected to an IP phone and port 4 is given lower priority because it is connected to a computer whose data traffic may be less sensitive to network congestion. Each port on the KS8995XA can be set as high or low priority with an EEPROM. The port priority is set in bit 4 of registers 0x10, 0x20, 0x30, 0x40, 0x50 for ports 1, 2, 3, 4 and 5, respectively. Port-based priority is overridden by the OR’ed result of the 802.1p and DSCP priorities if they are all enabled at the same time. IP Phone Figure 7. Port-Based Priority September 2008 26 M9999-091508 Micrel, Inc. KS8995XA The KS8995XA can classify tagged packets using the 802.1p tag-based priority. In this prioritization scheme, the user can enable the 802.1p classification on a per port basis in bit 5 of registers 0x10, 0x20, 0x30, 0x40 and 0x50 for ports 1, 2, 3, 4, and 5, respectively. Then the user specifies the 802.1p base priority in register 0x02, bits [6-4]. When a tagged packet is received, the KS8995XA examines the 3 bit 802.1p priority field shown in Figure 6. These 3 bits are compared against the base priority. The prioritization policy is as follows: Comparison 802.1p Priority ≥Base Priority 802.1p Priority < Base Priority Table 4. 802.1p Priority Priority High Low Bytes 8 Preamble 6 DA 6 SA 4 TCI 2 Length LLC 46-1500 Data 4 CRC Bits 16 Ta gged Packet Type (8100 fo r Ethernet) 3 802.1 p 1 CFI 12 VLAN I D Figure 6. 802.3 Tagged Packet Bytes 8 Preamble 6 DA 6 SA 4 Ta g 2 2 Type 46-1500 Da ta 4 CRC Bits 4 IP V er. 0x 4 6 4 He ader Siz e 2 DiffServ Res. Figure 7. IPv4 Packet In order to support QoS from end-to-end in a network, the KS8995XA can also classify packets based on the IPv4 DiffServ field shown in Figure 7. The DiffServ field consists of 6 bits, which can be used to specify 64 code points. The KS8995XA provides 64 bits (DSCP[63:0]) in 8 registers (0x60 to 0x67), in which the user specifies the priority of each of the 64 code points. The DiffServ classification is enabled on a per port basis in bit 6 of registers 0x10, 0x20, 0x30, 0x40 and 0x50 for ports 1, 2, 3, 4, and 5, respectively. If the DiffServ classification is enabled on a port, the KS8995XA will decode the IPv4 DiffServ field and look at the user defined code point bit to determine if the packet is high priority or low priority. If the code point is a ‘1’, the packet is high priority. If the code point is ‘0’, the packet is low priority. September 2008 27 M9999-091508 Micrel, Inc. KS8995XA DiffServ Field (Binary) 000000 000001 000010 000011 000100 Code Point DSCP[0] DSCP[1] DSCP[2] DSCP[3] DSCP[4] KS8995X (Reg. and Bit) 0x67, bit 0 0x67, bit 1 0x67, bit 2 0x67, bit 3 0x67, bit 4 • • • 111011 111100 111101 111110 111111 • • • DSCP[59] DSCP[60] DSCP[61] DSCP[62] DSCP[63] Table 5. DiffServ Code Point • • • 0x60, bit 3 0x60, bit 4 0x60, bit 5 0x60, bit 6 0x60, bit 7 Once classification of the packets has been determined either by port-based priority, 802.1p tag-based priority or DiffServ priority, they are placed in either the high or low priority queue on the egress port. The user can enable the egress priority queues on a per port basis by setting bit 0 of registers 0x10, 0x20, 0x30, 0x40, and 0x50 for ports 1, 2, 3, 4 and 5, respectively. If the egress priority queue for a given port is not set, the port will treat all packets as if they are the same priority, even though packets are classified on their ingress ports. If the egress priority queue for a given port is enabled, packets are serviced based on the user programmable egress policy. The priority scheme selection is set in register 0x05 bits[3-2] as shown in Table 6. Register 0x05, bit 3 0 0 1 1 Register 0x05, bit 2 0 1 0 1 Egress Priority Scheme Always deliver high priority packets first Deliver high/low priority packets at a ratio of 10/1 Deliver high/low priority packets at a ratio of 5/1 Deliver high/low priority packets at a ratio of 2/1 Table 6. Transmit Priority Ratio The KS8995XA offers support for port-based, 802.1p tag-based, and IPv4 DiffServ priority, as well as programmable egress policies. These KS8995XA QoS features enable identifying, classifying and forwarding packets based on their priority. The system designer is able to use this device to build network elements that give more control over system resources, priority service to mission critical applications, and can be integrated into the next generation of multimedia networks. Rate Limit Support KS8995XA supports hardware rate limiting on “receive” and “transmit” independently on a per port basis. It also supports rate limiting in a priority or non-priority environment. The rate limit starts from 0Kbps and goes up to the line rate in steps of 32Kbps. The KS8995XA uses one second as an interval. At the beginning of each interval, the counter is cleared to zero, and the rate limit mechanism starts to count the number of bytes during this interval. September 2008 28 M9999-091508 Micrel, Inc. KS8995XA For receive, if the number of bytes exceeds the programmed limit, the switch will stop receiving packets on the port until the “one second” interval expires. There is an option provided for flow control to prevent packet loss. If the rate limit is programmed greater than or equal to 128Kbps and the byte counter is 8K bytes below the limit, the flow control will be triggered. If the rate limit is programmed lower than 128Kbps and the byte counter is 2K bytes below the limit, the flow control will be triggered. For transmit, if the number of bytes exceeds the programmed limit, the switch will stop transmitting packets on the port until the “one second” interval expires. If priority is enabled, the KS8995XA can support different rate controls for both high priority and low priority packets. This can be programmed through Registers 21 – 27. Configuration Interface The KS8995XA functions as an unmanaged switch. If no EEPROM exists, the KS8995XA will operate from its default and strap-in settings. I C Master Serial Bus Configuration If a 2-wire EEPROM exists, the KS8995XA can perform more advanced features like broadcast storm protection and rate control. The EEPROM should have the entire valid configuration data from register 0 to register 109 defined in the memory map, except the status registers. The configuration access time (tprgm) is less than 15ms as shown in Figure 8. RST_N SCL SDA 2 .... .... .... t prgm