KSZ8999I

KS8999 Integrated 9-Port 10/100 Switch with PHY and Frame Buffer Rev 1.14 General Description The KS8999 contains eight 10/100 physical layer transceivers, nine MAC (Media Access Control) units with an integrated layer 2 switch. The device runs in two modes. The first mode is an eight port integrated switch and the second is as a nine port switch with the ninth port available through an MII (Media Independent Interface). Useful configurations include a stand alone eight port switch as well as a eight port switch with a routing element connected to the extra MII port. The additional port is also useful for a public network interfacing. The KS8999 is designed to reside in an unmanaged design not requiring processor intervention. This is achieved through I/O strapping or EEPROM programming at system reset time. On the media side, the KS8999 supports 10BaseT, 100BaseTX and 100BaseFX as specified by the IEEE 802.3 committee. Physical signal transmission and reception are enhanced through use of analog circuitry that makes the design more efficient and allows for lower power consumption and smaller chip die size. Data sheets and support documentation can be found on Micrel’s web site at www.micrel.com. Functional Diagram Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com January 2005 KS8999 Micrel, Inc. KS8999 • Supports both commercial and industry temperature ― Commercial temperature range: 0°C to +70°C (KS8999) ― Industrial temperature range: –40°C to +85°C (KS8999I) • Supports lead free products: ― Commercial temperature range: 0°C to +70°C (KSZ8999) ― Industrial temperature range: –40°C to +85°C (KSZ8999I) • Available in 208-pin PQFP package • 9 port (8+1) 10/100 integrated switch with eight physical layer transceivers and one MII/SNI interface • Advanced Ethernet Switch with internal frame buffer ― 128K Byte of SRAM on chip for frame buffering ― 2.0Gbps high performance memory bandwidth ― Wire speed reception and transmission ― Integrated address look-up engine, supports 1K absolute MAC addresses ― Automatic address learning, address aging and address migration • Advanced Switch Features ― Supports 802.1p priority and port based priority ― Supports port based VLAN ― Supports 1536 byte frame for VLAN tag ― Supports DiffServ priority, 802.1p based priority or port based priority o broadcast storm protection • Proven transceiver technology for UTP and fiber operation ― 10BaseT, 100BaseTX and 100BaseFX modes of operation ― Supports for UTP or fiber on all 8-ports ― Indicators for link, activity, full/half-duplex and speed ― Hardware based 10/100, full/half, flow control and auto-negotiation ― Individual port forced modes (full duplex, 100BaseTX) when auto-negotiation is disabled ― Full-duplex IEEE 802.3x flow control ― Half-duplex back pressure flow control • Supports MDI/MDI-X auto crossover • External MAC interface (MII or 7-wire) for router applications • Unmanaged operation via strapping or EEPROM at system reset time (see Reset Reference Circuit section) • Comprehensive LED support • Single 2.0V power supply with options for 2.5V and 3.3V I/O • 900 mA (1.80W) including physical transmit drivers Features Ordering Information Part Number KS8999 KS8999I KSZ8999 KSZ8999I Temp Range 0°C to +70°C –40°C to +85°C 0°C to +70°C –40°C to +85°C Package 208-Pin PQFP 208-Pin PQFP 208-Pin PQFP 208-Pin PQFP January 2005 2 KS8999 Micrel, Inc. KS8999 Revision History Revision Date 1.00 1.01 11/27/00 03/30/01 Preliminary Release Summary of Changes Update maximum frame size Update EEPROM priority descriptions Update I/O pin definition Update I/O descriptions Update Electrical Characteristics Correct timing information Add MDI/MDI-X description Change electrical requirements Correct I/O descriptions Update PLL clock information Update timing information Correct LED[6][1:0] to float configuration Add reverse and forward timing Correct optional CPU timing Update Optional CPU interface Correct I/O description for MCOL and MCRS Correct pin 174 and 175 description Correct default to floating for pin 174 Change pin 87 TEST[3] to AUTOMDIX for enable/disable of auto MDI-MDIX function Add KS8999I industrial temperature Update non-periodic blinking in Mode 1 of LED[1:9][0] Add MRXD[0] description Changed VCC from 2.00 to 2.10 (typical) Added FEF disable to T[4] pin #173 Convert to new format. Correct pin type description. Correct selection of reference oscillator/crystal spec. Insert recommended reset circuit. Added lead free and Industrial temperature packages. 1.02 1.03 1.04 1.05 1.06 1.07 04/20/01 05/11/01 06/22/01 0/6/25/01 07/25/01 08/09/01 1.08 1/14/02 1.09 1.10 6/18/02 2/27/03 1.11 1.12 1.13 1.14 5/12/03 8/29/03 1/19/05 1/31/05 January 2005 3 KS8999 Micrel, Inc. KS8999 Contents System Level Applications .............................................................................................................................................6 Pin Configuration ............................................................................................................................................................7 Pin Description ................................................................................................................................................................8 I/O Grouping ..................................................................................................................................................................14 I/O Description ...............................................................................................................................................................14 Functional Overview: Physical Layer Transceiver ....................................................................................................19 100BaseTX Transmit ................................................................................................................................................19 100BaseTX Receive .................................................................................................................................................19 PLL Clock Synthesizer..............................................................................................................................................19 Scrambler/De-scrambler (100BaseTX only).............................................................................................................19 100BaseFX Operation ..............................................................................................................................................19 100BaseFX Signal Detection....................................................................................................................................19 100BaseFX Far End Fault ........................................................................................................................................19 10BaseT Transmit ....................................................................................................................................................19 10BaseT Receive .....................................................................................................................................................19 Power Management..................................................................................................................................................20 Power Save Mode ..............................................................................................................................................20 MDI/MDI-X Auto Crossover ......................................................................................................................................20 Auto-Negotiation .......................................................................................................................................................20 Functional Overview: Switch Core ..............................................................................................................................21 Address Look-Up ......................................................................................................................................................21 Learning ....................................................................................................................................................................21 Migration ...................................................................................................................................................................21 Aging.........................................................................................................................................................................21 Forwarding ................................................................................................................................................................21 Switching Engine ......................................................................................................................................................21 MAC Operation .........................................................................................................................................................22 Inter Packet Gap (IPG) .......................................................................................................................................22 Backoff Algorithm ...............................................................................................................................................22 Late Collision ......................................................................................................................................................22 Illegal Frames .....................................................................................................................................................22 Flow Control .......................................................................................................................................................22 Half Duplex Back Pressure ................................................................................................................................22 Broadcast Storm Protection......................................................................................................................................22 MII Interface Operation .................................................................................................................................................23 SNI Interface (7-wire) Operation ..................................................................................................................................25 Programmable Features ...............................................................................................................................................25 Priority Schemes.......................................................................................................................................................25 Per Port Method........................................................................................................................................................25 802.1p Method..........................................................................................................................................................25 IPv4 DSCP Method...................................................................................................................................................25 Other Priority Considerations....................................................................................................................................25 VLAN Operation.............................................................................................................................................................26 Station MAC Address (control frames only) ..............................................................................................................27 EEPROM Operation .......................................................................................................................................................27 Optional CPU Interface .................................................................................................................................................28 January 2005 4 KS8999 Micrel, Inc. KS8999 EEPROM Memory Map ..................................................................................................................................................29 General Control Register ..........................................................................................................................................29 Priority Classification Control –802.1p tag field ........................................................................................................29 Port 1 Control Register .............................................................................................................................................29 Port 2 Control Register .............................................................................................................................................30 Port 3 Control Register .............................................................................................................................................30 Port 4 Control Register .............................................................................................................................................30 Port 5 Control Register .............................................................................................................................................31 Port 6 Control Register .............................................................................................................................................31 Port 7 Control Register .............................................................................................................................................31 Port 8 Control Register .............................................................................................................................................32 Port 9 Control Register .............................................................................................................................................32 Port 1 VLAN Mask Register......................................................................................................................................32 Port 2 VLAN Mask Register......................................................................................................................................33 Port 3 VLAN Mask Register......................................................................................................................................33 Port 4 VLAN Mask Register......................................................................................................................................34 Port 5 VLAN Mask Register......................................................................................................................................34 Port 6 VLAN Mask Register......................................................................................................................................35 Port 7 VLAN Mask Register......................................................................................................................................35 Port 8 VLAN Mask Register......................................................................................................................................36 Port 9 VLAN Mask Register......................................................................................................................................36 Port 1 VLAN Tag Insertion Value Registers .............................................................................................................36 Port 2 VLAN Tag Insertion Value Registers .............................................................................................................37 Port 3 VLAN Tag Insertion Value Registers .............................................................................................................37 Port 4 VLAN Tag Insertion Value Registers .............................................................................................................37 Port 5 VLAN Tag Insertion Value Registers .............................................................................................................37 Port 6 VLAN Tag Insertion Value Registers .............................................................................................................37 Port 7 VLAN Tag Insertion Value Registers .............................................................................................................37 Port 8 VLAN Tag Insertion Value Registers .............................................................................................................37 Port 9 VLAN Tag Insertion Value Registers .............................................................................................................38 Diff Serv Code Point Registers .................................................................................................................................38 Station MAC Address Registers (all ports –MAC control frames only) ....................................................................38 Absolute Maximum Ratings .........................................................................................................................................39 Operating Ratings .........................................................................................................................................................39 Electrical Characteristics .............................................................................................................................................39 Timing Diagrams ...........................................................................................................................................................41 Reference Circuits.........................................................................................................................................................47 Reset Reference Circuit ................................................................................................................................................47 4B/5B Coding .................................................................................................................................................................49 MLT3 Coding..................................................................................................................................................................50 MAC Frame ....................................................................................................................................................................50 Selection of Isolation Transformers ............................................................................................................................51 Selection of Reference Oscillator/Crystal ..................................................................................................................51 Package Information .....................................................................................................................................................52 January 2005 5 KS8999 Micrel, Inc. KS8999 network access. The major benefits of using the KS8999 are the lower power consumption, unmanaged operation, flexible configuration, built in frame buffering, VLAN abilities and traffic priority control. Two such applications are depicted below. System Level Applications The KS8999 can be configured to fit either in an eight port 10/100 application or as a nine port 10/100 network interface with an extra MII/7-wire port. This MII/7-wire port can be connected to an external processor and used for routing purposes or public Figure 1. System Applications January 2005 6 KS8999 Micrel, Inc. KS8999 Pin Configuration 208-Pin PQFP (PQ) January 2005 7 KS8999 Micrel, Inc. KS8999 Pin Description Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Pin Name VDD_RX GND_RX GND_RX VDD_RX RXP[3] RXM[3] AOUT2 DOUT2 TXP[3] TXM[3] QH[5] QH[4] QH[3] QH[2] GND_TX VDD_TX VDD_TX GND-ISO TXP[4] TXM[4] GND_TX RXP[4] RXM[4] GND_RX VDD_RX ISET GND-ISO VDD_RX GND_RX RXP[5] RXM[5] GND_TX TXP[5] TXM[5] GND-ISO VDD_TX VDD_TX GND_TX GND Pwr GND I I GND O O GND Pwr Pwr GND 5 5 5 5 Type(1) Pwr GND GND Pwr I I O O O O Opd Opd Opd Opd GND Pwr Pwr GND O O GND I I GND Pwr 4 4 4 4 3 3 3 3 Port Pin Function 2.0V for equalizer Ground for equalizer Ground for equalizer 2.0V for equalizer Physical receive signal + (differential) Physical receive signal - (differential) Factory test output Factory test output Physical transmit signal + (differential) Physical transmit signal - (differential) Factory test pin –leave open for normal operation Factory test pin –leave open for normal operation Factory test pin –leave open for normal operation Factory test pin –leave open for normal operation Ground for transmit circuitry 2.0V for transmit circuitry 2.0V for transmit circuitry Analog ground Physical transmit signal + (differential) Physical transmit signal - (differential) Ground for transmit circuitry Physical receive signal + (differential) Physical receive signal - (differential) Ground for equalizer 2.0V for equalizer Set physical transmit output current Analog ground 2.0V for equalizer Ground for equalizer Physical receive signal + (differential) Physical receive signal - (differential) Ground for transmit circuitry Physical transmit signal + (differential) Physical transmit signal - (differential) Analog ground 2.0V for transmit circuitry 2.0V for transmit circuitry Ground for transmit circuitry January 2005 8 KS8999 Micrel, Inc. Pin Number 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 Pin Name QL[2] QL[3] QL[4] QL[5] TXP[6] TXM[6] DOUT AOUT RXP[6] RXM[6] VDD_RX GND_RX GND_RX VDD_RX GND-ISO RXP[7] RXM[7] GND_TX TXP[7] TXM[7] VDD_TX VDD_TX TXP[8] TXM[8] GND_TX RXP[8] RXM[8] GND_RX VDD_RX FXSD[5] FXSD[6] FXSD[7] FXSD[8] GND_RCV GND_RCV VDD_RCV VDD_RCV GND_RCV GND_RCV Type(1) Opd Opd Opd Opd O O O O I I Pwr GND GND Pwr GND I I GND O O Pwr Pwr O O GND I I GND Pwr Ipd Ipd Ipd Ipd GND GND Pwr Pwr GND GND 5 6 7 8 8 8 8 8 7 7 7 7 6 6 6 6 Port Pin Function Factory test pin –leave open for normal operation Factory test pin –leave open for normal operation Factory test pin –leave open for normal operation Factory test pin –leave open for normal operation Physical transmit signal + (differential) Physical transmit signal - (differential) Factory test output –leave open for normal operation Factory test output –leave open for normal operation Physical receive signal + (differential) Physical receive signal - (differential) 2.0V for equalizer Ground for equalizer Ground for equalizer 2.0V for equalizer Analog ground Physical receive signal + (differential) Physical receive signal - (differential) Ground for transmit circuitry Physical transmit signal + (differential) Physical transmit signal - (differential) 2.0V for transmit circuitry 2.0V for transmit circuitry Physical transmit signal + (differential) Physical transmit signal - (differential) Ground for transmit circuitry Physical receive signal + (differential) Physical receive signal - (differential) Ground for equalizer 2.0V for equalizer Fiber signal detect Fiber signal detect Fiber signal detect Fiber signal detect Ground for clock recovery circuit Ground for clock recovery circuit 2.0V for clock recovery circuit 2.0V for clock recovery circuit Ground for clock recovery circuit Ground for clock recovery circuit KS8999 January 2005 9 KS8999 Micrel, Inc. Pin Number 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 Pin Name VDD_RCV VDD_RCV BTOUT2 CTOUT2 RLPBK MUX[1] MUX[2] TEST[1] TEST[2] AUTOMDIX T[1] T[2] T[3] EN1P SDA SCL VDD GND MTXEN MTXD[3] MTXD[2] MTXD[1] MTXD[0] MTXER MTXC MCOL MCRS VDD-IO GND GND VDD BIST RST# LED[1][3] LED[1][2] LED[1][1] LED[1][0] LED[2][3] LED[2][2] Type(1) Pwr Pwr O O I I I I I I Ipu Ipd Ipd Ipd Ipd/O Ipd/O Pwr GND Ipd Ipd Ipd Ipd Ipd Ipd Ipd/O Ipd/O Ipd/O Pwr GND GND Pwr Ipd I Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O 1 1 1 1 2 2 9 9 9 9 9 9 9 9 9 Port Pin Function 2.0V for clock recovery circuit 2.0V for clock recovery circuit Factory test pin –leave open for normal operation Factory test pin –leave open for normal operation KS8999 Enable loop back for testing –pull-down/float for normal operation Factory test pin –float for normal operation Factory test pin –float for normal operation Factory test pin –float for normal operation Factory test pin –float for normal operation Auto MDI/MDIX enable and disable –pull-up/float enable; pull-down disable Factory test pin –float for normal operation Factory test pin –float for normal operation Factory test pin –float for normal operation Enable 802.1p for all ports Serial data from EEPROM or processor Clock for EEPROM or from processor 2.0V for core digital circuitry Ground for digital circuitry MII transmit enable MII transmit bit 3 MII transmit bit 2 MII transmit bit 1 MII transmit bit 0 MII transmit error MII transmit clock MII collision detected MII carrier sense 2.0V, 2.5V or 3.3V for I/O circuitry Ground for digital circuitry Ground for digital circuitry 2.0V for core digital circuitry Built in self test –tie low for normal operation Reset –active low LED indicator 3 LED indicator 2 LED indicator 1 LED indicator 0 LED indicator 3 LED indicator 2 January 2005 10 KS8999 Micrel, Inc. Pin Number 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 Pin Name LED[2][1] LED[2][0] MRXDV MRXD[3] MRXD[2] MRXD[1] MRXD[0] MRXC VDD-IO GND LED[3][3] LED[3][2] LED[3][1] LED[3][0] LED[4][3] LED[4][2] LED[4][1] LED[4][0] VDD GND LED[5][3] LED[5][2] LED[5][1] LED[5][0] LED[6][3] LED[6][2] LED[6][1] LED[6][0] LED[7][3] LED[7][2] LED[7][1] VDD-IO LED[7][0] LED[8][3] LED[8][2] LED[8][1] LED[8][0] GND GND Type(1) Ipu/O Ipu/O Opd Opu Opu Opu Opu Ipu/O Pwr GND Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Pwr GND Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Pwr Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O GND GND 7 8 8 8 8 5 5 5 5 6 6 6 6 7 7 7 3 3 3 3 4 4 4 4 Port 2 2 9 9 9 9 9 9 Pin Function LED indicator 1 LED indicator 0 MII receive data valid MII receive bit 3 MII receive bit 2 MII receive bit 1 MII receive bit 0 MII receive clock 2.0V, 2.5V or 3.3V for I/O circuitry Ground for digital circuitry LED indicator 3 LED indicator 2 LED indicator 1 LED indicator 0 LED indicator 3 LED indicator 2 LED indicator 1 LED indicator 0 2.0V for core digital circuitry Ground for digital circuitry LED indicator 3 LED indicator 2 LED indicator 1 LED indicator 0 LED indicator 3 LED indicator 2 LED indicator 1 LED indicator 0 LED indicator 3 LED indicator 2 LED indicator 1 2.0V, 2.5V or 3.3V for I/O circuitry LED indicator 0 LED indicator 3 LED indicator 2 LED indicator 1 LED indicator 0 Ground for digital circuitry Ground for digital circuitry KS8999 January 2005 11 KS8999 Micrel, Inc. Pin Number 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 Pin Name IO_SWM VDD LED[9][3] LED[9][2] LED[9][1] LED[9][0] MIIS[1] MIIS[0] MODESEL[3] MODESEL[2] MODESEL[1] MODESEL[0] TESTEN SCANEN PRSV CFGMODE T[5] T[4] Reserve Reserve X1 X2 VDD_PLLTX GND_PLLTX CTOUT BTOUT VDD_RCV VDD_RCV GND_RCV GND_RCV VDD_RCV VDD_RCV GND_RCV GND_RCV FXSD[1] FXSD[2] FXSD[3] FXSD[4] VDD_RX Type(1) Ipu Pwr Ipu/O Ipu/O Ipu/O Ipu/O Ipd Ipd Ipd Ipd Ipd Ipd Ipd Ipd Ipd Ipu I Ipdthevillage I I I O Pwr GND O O Pwr Pwr GND GND Pwr Pwr GND GND Ipd Ipd Ipd Ipd Pwr 1 2 3 4 9 9 9 9 9 9 Port Pin Function Factory test pin –tie high for normal operation 2.0V for core digital circuitry LED indicator 3 LED indicator 2 LED indicator 1 LED indicator 0 MII mode select bit 1 MII mode select bit 0 Selects LED and test modes Selects LED and test modes Selects LED and test modes Selects LED and test modes Factory test pin –tie low for normal operation Factory test pin –tie low for normal operation Reserve 6KB buffer for priority frames KS8999 Configures programming interface for EEPROM or processor Factory test pin –float for normal operation F/D = normal operation (default) U = disable FEF Reserved –floating for normal operation Reserved -floating for normal operation Crystal or clock input Connect to crystal 2.0 V for phase locked loop circuit Ground for phase locked loop circuit Factory test pin –leave open for normal operation Factory test pin –leave open for normal operation 2.0V for clock recovery circuit 2.0V for clock recovery circuit Ground for clock recovery circuit Ground for clock recovery circuit 2.0V for clock recovery circuit 2.0V for clock recovery circuit Ground for clock recovery circuit Ground for clock recovery circuit Fiber signal detect Fiber signal detect Fiber signal detect Fiber signal detect 2.0V for equalizer January 2005 12 KS8999 Micrel, Inc. Pin Number 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Pin Name GND_RX RXP[1] RXM[1] GND_TX TXP[1] TXM[1] VDD_TX VDD_TX TXP[2] TXM[2] GND_TX RXP[2] RXM[2] GND-ISO Type(1) GND I I GND O O Pwr Pwr O O GND I I GND 2 2 2 2 1 1 1 1 Port Pin Function Ground for equalizer Physical receive signal + (differential) Physical receive signal - (differential) Ground for transmit circuitry Physical transmit signal + (differential) Physical transmit signal - (differential) 2.0V for transmit circuitry 2.0V for transmit circuitry Physical transmit signal + (differential) Physical transmit signal - (differential) Ground for transmit circuitry Physical receive signal + (differential) Physical receive signal - (differential) Analog ground KS8999 Notes: 1. P = Power supply. GND = ground I = input O = output I/O = bi-directional Ipu = input w/ internal pull-up Ipd = input w/ internal pull-down Opu = output w/ internal pull-up Opd = output w/ internal pull-down Ipd/O = input w/ internal pull-down during reset, output pin otherwise Ipu/O = input w/ internal pull-up during reset, output pin otherwise January 2005 13 KS8999 Micrel, Inc. KS8999 I/O Grouping Group Name PHY MII SNI IND UP CTRL TEST PWR Description Physical Interface Media Independent Interface Serial Network Interface LED Indicators Unmanaged Programmable Control and Miscellaneous Test (Factory) Power and Ground I/O Descriptions Group PHY I/O Names RXP[1:8] RXM[1:8] TXP[1:8] TXM[1:8] FXSD[1:8] ISET Active Status Analog Analog H Analog Description Differential inputs (receive) for connection to media (transformer or fiber module) Differential outputs (transmit) for connection to media (transformer or fiber module) Fiber signal detect –connect to fiber signal detect output on fiber module with appropriate voltage divider if needed. Tie low for copper mode. Transmit Current Set. Connecting an external reference resistor to set transmitter output current. This pin connects to a 3KΩ1% resistor to ground if a transformer with 1:1 turn ratio is used. Four bit wide data bus for receiving MAC frames Receive data valid Receive collision detection Carrier sense Four bit wide data bus for transmitting MAC frames Transmit enable Transmit error MII receive clock MII transmit clock Serial transmit data Transmit enable Serial receive data Receive carrier sense/data valid Collision detection SNI receive clock SNI transmit clock Output (after reset) Mode 0: Speed (on = 100/off = 10) Mode 1: 10/100 + link + activity 10Mb link activity = slow blink (non-periodic blinking) 100Mb link activity = fast blink (non-periodic blinking) Mode 2: Collision (on = collision/off = no collision) Mode 3: Speed (on = 100/off = 10) Output (after reset) Mode 0: Full Duplex (on = full/off = half) Mode 1: Full Duplex (on = full/off = half) Mode 2: Full Duplex (on = full/off = half) Mode 3: Reserved MII SNI MRXD[0:3] MRXDV MCOL MCRS MTXD[0:3] MTXEN MTXER MRXC MTXC MTXD[0] MTXEN MRXD[0] MRXDV MCOL MRXC MTXC LED[1:9][0] H H H H H H H Clock Clock H H H H H Clock Clock L IND LED[1:9][1] L January 2005 14 KS8999 Micrel, Inc. Group I/O Names LED[1:9][2] Active Status L Description KS8999 LED[1:9][3] L Output (after reset) Mode 0: Collision (on = collision/off = no collision) Mode 1: Transmit Activity (on during transmission) Mode 2: Link activity (10Mb mode) Mode 3: Full Duplex + Collision (constant on = full duplex; intermittent on = collision; off = half-duplex with no collision) Output (after reset) Mode 0: Link + Activity When LED is solid “on”, it indicates the link is on for both 10 or 100BaseTX, but no data is transmitting or receiving. When LED is solid “off”, it indicates the link is off. When LED is blinking, it indicates data is transmitting or receiving for either 10 or 100 BaseTX Mode 1: Receive Activity (on = receiving/off = not receiving) Mode 2: Link activity (100Mb mode) Mode 3: Link + Activity (see description above) Note: Mode is set by MODESEL[3:0] ; please see description in UP (unmanaged programming) section. Mode select at reset time. LED mode is selected by using the table below. Note that under normal operation MODESEL[3:2] must be tied low. MODESEL Mode select at reset time. LED mode is selected by using the table below. Note that under normal operation MODESEL[3:2] must be tied low. 3210 Operation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 LED mode 0 LED mode 1 LED mode 2 LED mode 3 Used for factory testing Used for factory testing Used for factory testing Used for factory testing Used for factory testing Used for factory testing Used for factory testing Used for factory testing Used for factory testing Used for factory testing Used for factory testing Used for factory testing UP MODESEL[3:0] H LED[1][3] LED[1][2] LED[1][1] LED[1][0] Programs auto-negotiation on port 1 D = Disable auto-negotiation, F/U = Enable auto-negotiation (default) Programs auto-negotiation on port 2 D = Disable auto-negotiation, F/U = Enable auto-negotiation (default) Programs auto-negotiation on port 3 D = Disable auto-negotiation, F/U = Enable auto-negotiation (default) Programs auto-negotiation on port 4 D = Disable auto-negotiation, F/U = Enable auto-negotiation (default) January 2005 15 KS8999 Micrel, Inc. Group I/O Names LED[2][3] LED[2][2] LED[2][1] LED[2][0] LED[3][3] LED[3][2] LED[3][1] LED[3][0] LED[4][3] LED[4][2] LED[4][1] LED[4][0] LED[5][3] Active Status Description KS8999 LED[5][2] LED[5][1] LED[5][0] LED[9][3] LED[9][2] LED[9][1] LED[9][0] LED[6][3] LED[6][2] LED[6][1:0] Programs auto-negotiation on port 5 D = Disable auto-negotiation, F/U = Enable auto-negotiation (default) Programs auto-negotiation on port 6 D = Disable auto-negotiation, F/U = Enable auto-negotiation (default) Programs auto-negotiation on port 7 D = Disable auto-negotiation, F/U = Enable auto-negotiation (default) Programs auto-negotiation on port 8 D = Disable auto-negotiation, F/U = Enable auto-negotiation (default) Programs port speed on port 1. This is only effective if auto-negotiation is disabled. D = 10Mbps, F/U = 100Mbps (default) Programs port speed on port 2. This is only effective if auto-negotiation is disabled. D = 10Mbps, F/U = 100Mbps (default) Programs port speed on port 3. This is only effective if auto-negotiation is disabled. D = 10Mbps, F/U = 100Mbps (default) Programs port speed on port 4. This is only effective if auto-negotiation is disabled. D = 10Mbps, F/U = 100Mbps (default) Programs port speed on port 5. This is only effective if auto-negotiation is disabled. D = 10Mbps, F/U = 100Mbps (default) Programs port speed on port 6. This is only effective if auto-negotiation is disabled. D = 10Mbps, F/U = 100Mbps (default) Programs port speed on port 7. This is only effective if auto-negotiation is disabled. D = 10Mbps, F/U = 100Mbps (default) Programs port speed on port 8. This is only effective if auto-negotiation is disabled. D = 10Mbps, F/U = 100Mbps (default) Programs port duplex (full/ half) on port 1. This is only effective if autonegotiation is disabled or if this end has auto- negotiation enabled and the far end has auto negotiation disabled. D = Full-duplex, F/U = Half-duplex (default) Programs port duplex (full/ half) on port 2. This is only effective if autonegotiation is disabled or if this end has auto-negotiation enabled and the far end has auto-negotiation disabled. D = Full-duplex, F/U = Half-duplex (default) Programs port duplex (full/ half) on port 3. This is only effective if autonegotiation is disabled or if this end has auto-negotiation enabled and the far end has auto-negotiation disabled. D = Full-duplex, F/U = Half-duplex (default) Programs port duplex (full/ half) on port 4. This is only effective if autonegotiation is disabled or if this end has auto-negotiation enabled and the far end has auto-negotiation disabled. D = Full-duplex, F/U = Half-duplex (default) Programs port duplex (full/ half) on port 5. This is only effective if autonegotiation is disabled or if this end has auto-negotiation enabled and the far end has auto negotiation disabled. D = Full-duplex, F/U = Half-duplex (default) Programs port duplex (full/ half) on port 6. This is only effective if autonegotiation is disabled or if this end has auto-negotiation enabled and the far end has auto-negotiation disabled. D = Full-duplex, F/U = Half-duplex (default) Programs port duplex (full / half) on port 7. This is only effective if autonegotiation is disabled or if this end has auto-negotiation enabled and the far end has auto-negotiation disabled. D = Full-duplex, F/U = Half-duplex (default) Programs port duplex (full / half) on port 8. This is only effective if autonegotiation is disabled or if this end has auto-negotiation enabled and the far end has auto-negotiation disabled. D = Full-duplex, F/U = Half-duplex (default) Programs back-off aggressiveness for half-duplex mode D = Less aggressive back-off, F/U = More aggressive back-off (default) Programs retries for frames that encounter collisions. D = Drop frame after 16 collisions, F/U = Continue sending frame regardless of the number of collisions (default) Reserved – use float configuration January 2005 16 KS8999 Micrel, Inc. Group I/O Names LED[7][3] LED[7][2] LED[7][1] LED[7][0] LED[8][3] LED[8][2] LED[8][1] LED[8][0] MRXD[3] MRXD[2] MRXD[1] MRXD[0] CTRL EN1P H Active Status Description KS8999 Programs flow control D = No flow control, F/U = Flow control enabled (default) Programs broadcast storm protection. D = 5% broadcast frames allowed, F/U = Unlimited broadcast frames (default) Programs buffer sharing feature. D = Equal amount of buffers per port (113 buffers), F/U = Share buffers up to 512 buffers on a single port (default) Reserved – use float configuration Programs address aging. D = Aging disabled, F/U = Enable 5 minute aging (default) Programs frame length enforcement. D = Max length for VLAN is 1522 bytes and without VLAN is 1518 bytes F/U = Max length is 1536 bytes (default) Reserved Programs half-duplex back pressure. D = No half-duplex back pressure, F/U = Half-duplex back pressure enabled (default) Programs port 9 speed D = 10Mbps, F/U = 100Mbps (default) Programs port 9 duplex D = Half-duplex, F/U = Full duplex (default) Programs port 9 flow control D = Flow control, F/U = No flow control (default) D = reserved, F/U = normal operation (default) Enable 802.1p for all ports –this enables QoS based on the priority field in the layer 2 header. 0 = 802.1p selected by port in EEPROM 1 = Use 802.1p priority field unless disabled in EEPROM Note: This is also controlled by the EEPROM registers (registers 4-12 bit 4). The values in the EEPROM supersede this pin. Also, if the priority selection is unaltered in the EEPROM registers (register 3 bits 0-7) then values above 3 are considered high priority and less than 4 are low priority. MII mode selection –allows the MII to run in the following modes MIIS Operating mode 10 00 Disable MII interface 01 Reverse MII 10 Forward MII 11 7 wire mode (SNI) Priority buffer reserve –reserves 6KB of buffer space for the priority traffic if enabled. 0 = No priority reserve 1 = Reserve 6KB for priority traffic Note: This is also controlled by the EEPROM registers (register 2 bit 1). The value in the EEPROM supersedes this pin. Selects between EEPROM or processor for programming interface. 0 = Processor interface 1 = EEPROM interface or not programmed on this interface (SCL / SDA not used) External crystal or clock input Used when other polarity of crystal is needed. This is unused for a normal clock input. Clock for EEPROM Serial data for EEPROM System reset Factory test input –tie low for normal operation Factory test input –tie low for normal operation Factory test input –leave open for normal operation Factory test output –leave open for normal operation MIIS[1:0] H PRSV H CFGMODE H X1 X2 SCL SDA RST# TEST TESTEN SCANEN MUX[1:2] AOUT Clock Clock Clock I/O L H H H H January 2005 17 KS8999 Micrel, Inc. Group I/O Names DOUT AOUT2 DOUT2 BTOUT CTOUT BTOUT2 CTOUT2 TEST[1:2] AUTOMDIX T[1:3] & T[5] T[4] QH[2:5] QL[2:5] IO_SWM RLPBK BIST PWR VDD_RX GND_RX VDD_TX GND_TX VDD_RCV GND_RCV VDD_PLLTX GND_PLLTX GND-ISO VDD VDD-IO GND Note: 1. All unmanaged programming takes place at reset time only. For unmanaged programming: F = Float, D = Pull-down, U = Pull-up. See “Reference Circuits” section. KS8999 Active Status H H H H H H H H H H H H H H H H Description Factory test output –leave open for normal operation Factory test output –leave open for normal operation Factory test output –leave open for normal operation Factory test output –leave open for normal operation Factory test output –leave open for normal operation Factory test output –leave open for normal operation Factory test output –leave open for normal operation Factory test inputs –leave open for normal operation F/U = Enable Auto MDI/MDIX (normal operation) D = Disable Auto MDI/MDIX Factory test inputs –leave open (float) for normal operation F/D = normal operation (default) U = Disable FEF Factory test outputs –leave open for normal operation Factory test outputs –leave open for normal operation Factory test input –tie high for normal operation Factory test input –tie low for normal operation Factory test input –tie low for normal operation 2.0V for equalizer Ground for equalizer 2.0V for transmit circuitry Ground for transmit circuitry 2.0V for clock recovery circuitry Ground for clock recovery 2.0V for phase locked loop circuitry Ground for phase locked loop circuitry Analog ground 2.0V for core digital circuitry 2.0V, 2.5V or 3.3V for I/O circuitry Ground for digital circuitry January 2005 18 KS8999 Micrel, Inc. KS8999 Functional Overview: Physical Layer Transceiver 100BaseTX Transmit The 100BaseTX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling, NRZ to NRZI conversion, MLT3 encoding and transmission. The circuit starts with a parallel to serial conversion, which converts the data from the MAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B coding followed by a scrambler. The serialized data is further converted from NRZ to NRZI format, then transmitted in MLT3 current output. The output current is set by an external 1% 3.01kΩ resistor for the 1:1 transformer ratio. It has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot and timing jitters. The wave-shaped 10BaseT output is also incorporated into the 100BaseTX transmitter. 100BaseTX Receive The 100BaseTX receiver function performs adaptive equalization, DC restoration, MLT3 to NRZI conversion, data and clock recovery, NRZI to NRZ conversion, de-scrambling, 4B/5B decoding and serial to parallel conversion. The receiving side starts with the equalization filter to compensate inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss and phase distortion is a function of the length of the cable, the equalizer has to adjust its characteristics to optimize the performance. This is an ongoing process and can self adjust to the environmental changes such as temperature variations. The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used to compensate for the effect of base line wander and improve the dynamic range. The differential data conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive. The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal into the NRZ format. The signal is then sent through the de-scrambler followed by the 4B/5B decoder. Finally, the NRZ serial data is provided as the input data to the MAC. PLL Clock Synthesizer The KS8999 generates 125MHz, 62.5MHz, 25MHz and 10MHz clocks for system timing. Internal clocks are generated from an external 25MHz crystal. Scrambler/De-scrambler (100BaseTX only) The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander. The data is scrambled by the use of an 11-bit wide linear feedback shift register (LFSR). This can generate a 2047-bit non-repetitive sequence. The receiver will then de-scramble the incoming data stream with the same sequence at the transmitter. 100BaseFX Operation 100BaseFX operation is very similar to 100BaseTX operation with the differences being that the scrambler/descrambler and MLT3 encoder/decoder are bypassed on transmission and reception. In this mode the autonegotiation feature is bypassed since there is no standard that supports fiber auto-negotiation. 100BaseFX Signal Detection The physical port runs in 100BaseFX mode if FXSDx >0.6V. FXSDx is considered ‘low’ when 0.6V