ML2280CCP

May 1997 ML2280*, ML2283** Serial I/O 8-Bit A/D Converters GENERAL DESCRIPTION The ML2280 and ML2283 are 8-bit successive approximation A/D converters with serial I/O and configurable input multiplexers with up to 4 input channels. All errors of the sample-and-hold incorporated on the ML2280 and ML2283 are accounted for in the analog-todigital converters accuracy specification. The voltage reference can be externally set to any value between GND and VCC, thus allowing a full conversion over a relatively small voltage span if desired. The ML2283 is an enhanced double polysilicon, CMOS, pin-compatible second source for the ADC0833 A/D converter. All parameters are guaranteed over temperature with a power supply voltage of 5V ±10%. FEATURES s s s Conversion time: 6µs ML2280 capable of digitizing a 5V, 40kHz sine wave Total unadjusted error with external reference: ±1/2LSB or ±1LSB Sample-and-hold: 375ns acquisition 0 to 5V analog input range with single 5V power supply 2.5V reference provides 0 to 5V analog input range No zero- or full-scale adjust required Low power: 12.5mW MAX Analog input protection: 25mA (min) per input Differential analog voltage inputs (ML2280) Programmable multiplexer with differential or single ended analog inputs (ML2283) 0.3" width 8- or 14-pin DIP, or 8-Pin SOIC (ML2280) Superior pin-compatible replacement for ADC0833 s s s s s s s s s s * This Part Is Obsolete ** This Part Is End Of Life As Of August 1, 2000 BLOCK DIAGRAM ML2281 CONTROL AND TIMING CS CLK INPUT SHIFT-REGISTER DI ML2283 SARS OUTPUT SHIFT-REGISTER DO 4-BIT CONTROL AND TIMING CLK CS VIN+ A/D WITH SAMPLE & HOLD FUNCTION + SUCCESSIVE + APPROXIMATION COMP – – REGISTER 8pF Σ OUTPUT SHIFT-REGISTER DO SE CH0 VREF/2 4-CHANNEL S.E. OR 2-CHANNEL CH2 DIFF MULTIPLEXER CH1 CH3 A/D CONVERTER WITH SAMPLE & HOLD FUNCTION DGND VIN– D/A CONVERTER 8pF SHUNT REGULATOR AGND VREF/2 VCC V+ VCC GND 1 ML2280, ML2283 PIN CONFIGURATION ML2280 Single Differential Input 8-Pin PDIP CS VIN+ VIN– GND 1 2 3 4 8 7 6 5 ML2280 Single Differential Input 8-Pin SOIC CS VIN+ VIN– GND 1 2 3 4 8 7 6 5 ML2283 4-Channel MUX 14-Pin PDIP V+ CS CH0 CH1 CH2 CH3 DGND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VCC CLK DO VREF/2 VCC CLK DO VREF/2 VCC DI CLK SARS DO VREF/2 AGND TOP VIEW TOP VIEW TOP VIEW PIN DESCRIPTION NAME FUNCTION NAME FUNCTION VCC DGND AGND GND Positive supply. 5V ± 10% Digital ground. 0 volts. All digital inputs and outputs are referenced to this point. Analog ground. The negative reference voltage for A/D converter. Combined analog and digital ground. SARS Successive approximation register status. Digital output which indicates that a conversion is in progress. When SARS goes to 1, the sampling window is closed and conversion begins. When SARS goes to 0, conversion is completed. When CS = 1, SARS is in high impedance state. Clock. Digital input which clocks data in on DI on rising edges and out on DO on falling edges. Also used to generate clocks for A/D conversion. Data input. Digital input which contains serial data to program the MUX and channel assignments. Chip select. Selects the chip for multiplexer and channel assignment and A/D conversion. When CS = 1, all digital outputs are in high impedance state. When CS = 0, normal A/D conversion takes place. CH0, Analog inputs. Digitally selected to be single VIN+, VIN– ended (VIN) or; VIN+ or VIN– of a differential input. Analog range = GND - VIN - VCC. VREF/2 Reference. The analog input range is twice the positive reference voltage value applied to this pin. Input to the Shunt Regulator. Data out. Digital output which contains result of A/D conversion. The serial data is clocked out on falling edges of CLK. CLK DI V+ DO CS 2 ML2280, ML2283 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Current into V+ ...................................................... 15mA Supply Voltage, VCC ................................................. 6.5V Voltage Logic Inputs ........................................... –7 to VCC +7V Analog Inputs ................................ –0.3V to VCC +0.3V Input Current per Pin (Note 1) .............................. ±25mA Storage Temperature ................................ –65°C to 150°C Package Dissipation at TA = 25°C (Board Mount) ............................. 800mW Lead Temperature (Soldering 10 sec.) Dual-In-Line Package (Molded) .......................... 260°C Dual-In-Line Package (Ceramic) ......................... 300°C OPERATING CONDITIONS Supply Voltage, VCC ............................ 4.5VDC to 6.3VDC Temperature Range (Note 2) ................. TMIN - TA - TMAX ML2280 BIP, ML2283 BIP ...................... –40°C to 85°C ML2280 CIP, ML2283 CIP ML2280 BCP, ML2283 BCP ...................... 0°C to 70°C ML2280 CCP, ML2283 CCP ELECTRICAL CHARACTERISTICS Unless otherwise specified, TA = TMIN to TMAX, VCC = 5V ±10%, fCLK = 1.333MHz, and VREF/2 = 2.5V. ML228XB TYP MIN NOTE 3 ML228XC TYP NOTE 3 SYMBOL PARAMETER CONDITIONS MAX MIN MAX UNITS CONVERTER AND MULTIPLEXER CHARACTERISTICS Total Unadjusted Error Reference Input Resistance Common-Mode Input Range VREF/2 = 2.5V VREF/2 not connected (Notes 4, 6) (Note 4) (Notes 4, 7) 10 GND –0.05 ±1/16 15 ±1/2 ±2 20 VCC +0.05 ±1/4 10 GND –0.05 ±1/16 15 ±1 ±2 20 VCC +0.05 ±1/4 LSB LSB kW V LSB DC Common-Mode Common mode voltage Error voltage GND to VCC/2 (Note 5) AC Common-Mode Common mode voltage Error GND to VCC, 0 to 50kHz (Note 5) DC Power Supply Sensitivity AC Power Supply Sensitivity Change in Zero Error from VCC=5V to Internal Zener Operation VZ Internal Diode Regulated Breakdown (at V+) Input Resistance VCC = 5V ±10% VREF - VCC +0.1V (Note 5) 100mVP-P, 25kHz sine on VCC (Note 5) 15mA into V+ VCC = N.C. VREF/2 = 2.5V (Note 5) 15mA into V+ ±1/4 ±1/4 LSB ±1/32 ±1/4 ±1/32 ±1/4 LSB ±1/4 ±1/2 ±1/2 ±1/4 LSB LSB 6.9 6.9 V V+ (Note 4) 20 35 20 35 kW 3 ML2280, ML2283 ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER (Continued) ML228XB TYP MIN NOTE 3 ML228XC TYP NOTE 3 CONDITIONS MAX MIN MAX UNITS CONVERTER AND MULTIPLEXER CHARACTERISTICS (Continued) IOFF Off Channel Leakage Current On channel = VCC Off channel = 0V (Notes 4, 8) On channel = 0V Off channel = VCC (Notes 4, 8) ION On Channel Leakage Current On channel = 0V Off channel = VCC (Notes 4, 8) On channel = VCC Off channel = 0V (Notes 4, 8) –1 –1 –1 µA +1 +1 µA –1 µA +1 +1 µA SYMBOL PARAMETER CONDITIONS MIN TYP NOTE 3 MAX UNITS DIGITAL AND DC CHARACTERISTICS VIN(1) VIN(0) IIN(1) IIN(0) VOUT(1 VOUT(0) IOUT ISOURCE ISINK ICC Logical “1” Input Voltage Logical “0” Input Voltage Logical “1” Input Current Logical “0” Input Current Logical “1” Output Voltage Logical “0” Output Voltage HI-Z Output Current Output Source Current Output Sink Current Supply Current (Note 4) (Note 4) VIN = VCC (Note 4) VIN = 0V (Note 4) IOUT = –2mA (Note 4) IOUT = 2mA (Note 4) VOUT = 0V (Note 4) VOUT = VCC VOUT = 0V (Note 4) VOUT = VCC (Note 4) (Note 4) 1.3 –1 1 –6.5 8.0 2.5 –1 4.0 0.4 2.0 0.8 1 V V µA µA V V µA µA mA mA mA 4 ML2280, ML2283 ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER (Continued) TYP NOTE 3 CONDITIONS MIN MAX UNITS AC ELECTRICAL CHARACTERISTICS fCLK tACQ tC SNR Clock Frequency Sample-and-Hold Acquisition Conversion Time Signal to Noise Ratio ML2280 Not including MUX adddressing time VIN = 40kHz, 5V sine. fCLK = 1.333MHz (fSAMPLING @ 120kHz). Noise is sum of all nonfundamental components up to 1/2 of fSAMPLING (Note 11) VIN = 40kHz, 5V sine. fCLK = 1.333MHz (fSAMPLING @ 120kHz). THD is sum of 2, 3, 4, 5 harmonics relative to fundamental (Note 11) VIN = fA + fB. fA = 40kHz, 2.5V sine. fB = 39.8kHz, 2.5V Sine, fCLK = 1.333MHz (fSAMPLING @ 120kHz). IMD is (fA + fB), (fA – fB), (2fA + fB), (2fA – fB), (fA + 2fB), (fA – 2fB) relative to fundamental (Note 11) (Notes 4, 9) (Note 4) (Note 4) CL = 100pF (Note 4 & 10) Data MSB first Data LSB first CL = 10pF, RL = 10kW (see high impedance test circuits) (Note 5) CL = 100pF, RL = 2kW (Note 5) CIN COUT Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: (Note 4) 10 1/2 8 47 1333 kHz 1/fCLK 1/fCLK dB THD Total Harmonic Distortion ML2280 –60 dB IMD Intermodulation Distortion ML2280 –60 dB Clock Duty Cycle tSET-UP tHOLD tPD1, tPD0 t1H, t0H CS Falling Edge or Data Input Valid to CLK Rising Edge Data Input Valid after CLK Rising Edge CLK Falling Edge to Output Data Valid Rising Edge of CS to Data Output and SARS Hi-Z 40 130 80 60 % ns ns 90 50 40 80 5 5 200 110 90 160 ns ns ns ns pF pF Capacitance of Logic Input Capacitance of Logic Outputs When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < GND < or VIN > VCC) the absolute value of current at that pin should be limited to 25mA or less. 0°C to 70°C and –40°C to 85°C operating temperature range devices are 100% tested with temperature limits guaranteed by 100% testing, sampling, or by correlation with worst-case test conditions. Typicals are parametric norm at 25°C. Parameter guaranteed and 100% tested. Parameter guaranteed. Parameters not 100% tested are not in outgoing quality level calculation. Total unadjusted error includes offset, full-scale, linearity, multiplexer and sample-and-hold errors. For VIN– • VIN+ the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the VCC supply. Be careful, during testing at low VCC levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct—especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50mV forward bias of either diode. This means that as long as the analog V IN or VREF does not exceed the supply voltage by more than 50mV, the output code will be correct. To achieve an absolute 0V to 5V input voltage range will therefore require a minimum supply voltage of 4.950VDC over temperature variations, initial tolerance and loading. Leakage current is measured with the clock not switching. A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits, the minimum time the clock is high or the minimum time the clock is low must be at least 300ns. The maximum time the clock can be high or low is 60µs. Note 8: Note 9: Note 10: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see Block Diagram) to allow for comparator response time.. Note 11: Because of multiplexer addressing, test conditions for the ML2283 is VIN = 30kHz, 5V sine (fSAMPLING ª 89kHz) 5 ML2280, ML2283 t1H DATA OUTPUT CL RL VCC CS GND VOH GND t1H tr 90% 50% 10% t1H DO AND SARS OUTPUTS 90% t0H VCC VCC RL DATA OUTPUT CL DO AND SARS OUTPUTS CS GND VCC VOL t0H tr 90% 50% 10% t0H 10% Figure 1. High Impedance Test Circuits and Waveforms Data Input Timing CLK CLK tSET-UP CS tHOLD DATA IN (DI) DATA OUT (DO) Data Output Timing tPD0, tPD1 tPD0, tPD1 tSET-UP tHOLD tSET-UP SE ML2281 Start Conversion Timing CLK tSET-UP CS START CONVERSION DO BIT 7 (MSB) BIT 6 Figure 2. Timing Diagrams 6 ML2280, ML2283 ML2280 Timing 1 CLOCK (CLK) tSET-UP CHIP SELECT (CS) tC DATA OUT (DO) SAMPLE & HOLD ACQUISITION (tACQ) HI-Z 7 (MSB) 6 5 4 3 2 1 0 (LSB) * HI-Z 2 3 4 5 6 7 8 9 10 11 *LSB FIRST OUTPUT NOT AVAILABLE ON ML2280 ML2283 Timing 1 CLOCK (CLK) tSET-UP CHIP SELECT (CS) ADDRESS MUX START BIT DATA IN (DI) SGL/DIF SAR STATUS (SARS) SELECT BIT 1 ODD/SIGN SELECT BIT 0 DON’T CARE (DI DISABLED UNTIL NEXT CONVERSION A/D CONVERSION IN PROCESS HI-Z MSB FIRST DATA DATA OUT (DO) HI-Z SAMPLE & HOLD ACQUISITION (tACQ) 7 6 (MSB) 5 4 3 2 1 0 1 2 3 4 5 6 7 LSB FIRST DATA HI-Z OUTPUT DATA 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 HI-Z Figure 2. Timing Diagrams (Continued) 7 ML2280, ML2283 1.0 VCC = 5V VREF = 5V LINEARITY ERROR (LSB) 0.75 0.5 –55 C 0.25 25 C 125 C 0 0 0.01 0.1 1 CLOCK FREQUENCY (MHz) Figure 3. Linearity Error vs fCLK 1 VCC = 5V fCLK = 1.333MHz LOAD AB START LS193 B0 COUNT C D DOWN S R TMS320 SERIES D 5V Q Q Q LINEARITY ERROR (LSB) 0.75 D Q DSP Q D Q Q 0.5 –55 C 0.25 125 C 25 C ML2280 CLK VIN+ VIN– CS DO CLK FSR CLK DR CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 START 0 CS 0 1 2 3 4 5 FSR DO HI-Z D7 D6 D5 D4 D3 D2 D1 D0 HI-Z VREF (VDC) Figure 4. Linearity Error vs VREF Voltage Figure 5. Unadjusted Offset Error vs VREF Voltage 8 ML2280, ML2283 DI* CS 13 2 R START R R R 5-BIT SHIFT-REGISTER ODD/ SGL/DIF SELECT 1 SIGN R D CS SELECT 0 C START CLK 16 VCC 3 MUX ADDRESS + CS CH0* Σ – SARS* 11 Tx TIME DELAY C Q D R D Q R Q R CS DEOC DSTART 1 CS CH1 4 DSTART 2 CH2* 5 ANALOG MUX (EQUIVALENT) C + – C D C CS CH3* 6 CS CS VCC COMP VREF/2 VCC V+* DGND* 9 14 TO INTERNAL CIRCUITRY INPUT V CC 13 TO 16 INTERNAL 17 CIRCUITS 18 R LADDER AND DECODER C R B7 B6 B5 SAR LOGIC AND LATCH B4 B3 B2 B1 B0 COMP AGND* 8 INPUT PROTECTION—ALL LOGIC INPUTS LSB FIRST EOC 9-BIT SHIFT REGISTER EOC R C CS R C Q D 10 DO 1 7V SHUNT REGULATOR MSB FIRST PARALLEL XFR TO SHIFT REGISTER * SOME OF THESE FUNCTIONS/PINS ARE NOT AVAILABLE WITH ML2280. Figure 6. ML2288 Functional Block Diagram 9 ML2280, ML2283 FUNCTIONAL DESCRIPTION MULTIPLEXER ADDRESSING The design of these converters utilizes a sample data comparator structure which provides for a differential analog input to be converted by a successive approximation routine. The actual voltage converted is always the difference between an assigned “+” input terminal and a “–” input terminal. The polarity of each input terminal of the pair being converted indicates which line the converter expects to be the most positive. If the assigned “+” input is less than the “–” input, the converter responds with an all zeros output code. A unique input multiplexing scheme has been utilized to provide multiple analog channels with software configurable single ended, differential, or pseudo differential options. A particular input configuration is assigned during the MUX addressing sequence, prior to the start of a conversion. The MUX address selects which of the analog inputs are to be enabled and whether this input is single ended or differential. In the differential case, it also assigns the polarity of the analog channels. Differential inputs are restricted to adjacent channel pairs. For example, channel 0 and channel 1 may be selected as a different pair but channel 0 or channel 1 cannot act differentially with any other channel. In addition to selecting the differential mode, the sign may also be selected. Channel 0 may be selected as the positive input and channel 1 as the negative input or vice versa. This programmability is illustrated by the MUX addressing codes shown in Table 1. The MUX address is shifted into the converter via the DI input. Since the ML2280 contains only one differential input channel with a fixed polarity assignment, it does not require addressing. Since the input configuration is under software control, it can be modified, as required, at each conversion. A channel can be treated as a single-ended, ground referenced input for one conversion; then it can be reconfigured as part of a differential channel for another conversion. Figure 7 illustrates these different input modes. DIGITAL INTERFACE The block diagram and timing diagrams in Figures 2-5 illustrate how a conversion sequence is performed. A conversion is initiated when CS is pulsed low. This line must me held low for the entire conversion. The converter is now waiting for a start bit and its MUX assignment word. A clock is applied to the CLK input. On each rising edge of the clock, the data on DI is clocked into the MUX address shift register. The start bit is the first logic “1” that appears on the DI input (all leading edge zeros are ignored). After the start bit, the device clocks in the next 2 to 4 bits for the MUX assignment word. 0, 1 2 3 + + AGND SINGLE-ENDED MUX MODE MUX ADDRESS SGL/ ODD/ DIF SIGN 1 1 1 1 0 0 1 1 SELECT 1 0 1 0 1 + + COM is internally tied to AGND CHANNEL# 0 + + 1 2 3 DIFFERENTIAL MUX MODE MUX ADDRESS SGL/ ODD/ DIF SIGN 0 0 0 0 0 0 1 1 SELECT 1 0 1 0 1 – + – + 0 + 1 – + – 2 3 CHANNEL# Table 1. ML2283 MUX Addressing 4 Single-Ended or 2 Differential Channel 4 Single-Ended 0 1 2 3 + 0, 1 + + + AGND 2 Differential + (–) – (+) + (–) 2, 3 – (+) Mixed Mode + Figure 7. Analog Input Multiplexer Functional Options for ML2288 10 ML2280, ML2283 When the start bit has been shifted into the start location of the MUX register, the input channel has been assigned and a conversion is about to begin. An interval of 1/2 clock period is used for sample & hold settling through the selected MUX channels. The SAR status output goes high at this time to signal that a conversion is now in progress and the DI input is ignored. The DO output comes out of High impedance and provides a leading zero for this one clock period. When the conversion begins, the output of the comparator, which indicates whether the analog input is greater than or less than each successive voltage from the internal DAC, appears at the DO output on each falling edge of the clock. This data is the result of the conversion being shifted out (with MSB coming first) and can be read by external logic or µP immediately. After 8 clock periods, the conversion is completed. The SAR status line returns low to indicate this 1/2 clock cycle later. The serial data is always shifted out MSB first during the conversion. After the conversion has been completed, the data can be shifted out a second time with LSB first. The 2280 data is shifted out only once, MSB first. All internal registers are cleared when the CS input is high. If another conversion is desired, CS must make a high to low transition followed by address information. The DI input and DO output can be tied together and controlled through a bidirectional µP I/O bit with one connection. This is possible because the DI input is only latched in during the MUX addressing interval while the DO output is still in the high impedance state. REFERENCE The ML2280 and ML2283 are intended primarily for use in circuits requiring absolute accuracy. In this type of system, the analog inputs vary between very specific voltage limits and the reference voltage for the A/D converter must remain stable with time and temperature. For ratiometric applications, see the ML2281 and ML2284 which have a VREF input that can be tied to VCC. The voltage applied to the VREF/2 pin defines the voltage span of the analog input (the difference between VIN+ and VIN–) over which the 256 possible output codes apply. A full-scale conversion (an all 1s output code) will result when the voltage difference between a selected “+”input and “–” input is approximately twice the voltage at the VREF/2 pin. This internal gain of 2 from the applied reference to the fullscale input voltage allows biasing a low voltage reference diode from the 5VDC converter supply. To accommodate a 5V input span, only a 2.5V reference is required. The output code changes in accordance with the following equation:  V (+) − VIN(−)  Output Code = 256  IN   2(VREF / 2)  where the output code is the decimal equivalent of the 8-bit binary output (ranging from 0 to 255) and the term VREF/2 is the voltage to ground. The VREF/2 pin is the center point of a two resistor divider (each resistor is 10kW) connected from VCC to ground. Total ladder input resistance is the parallel combination of these two equal resist. As show in Figure 8, a reference diode requiring an external biasing resistor if its current requirements meet the indicated level. The minimum value of VREF/2 can be quite small (See Typical Performance Curves) to allow direct conversions of transducer outputs providing less than a 5V output span. Particular care must be taken with regard to noise pickup, circuit layout and system error voltage sources when operating with a reduced span due to the increased sensitivity of the converter (1LSB equals VREF/256). VCC 5V VCC 5V 10kΩ ML2280 ML2283 10kΩ 1.2V VREF/2 IZ VZ + ML2280 ML2283 10kΩ VREF/2 10kΩ 2.5V GND GND VFULL-SCALE ≅ 2.4V – VFULL-SCALE ≅ 5.0V VCC/2 – VZ VCC AND IZ min. < 2 5kΩ NOTE: NO EXTERNAL BIASING RESISTOR NEENED IF: VZ < Figure 8. Reference Biasing 11 ML2280, ML2283 ANALOG INPUTS AND SAMPLE/HOLD An important feature of the ML2280 and ML2283 is that they can be located at the source of the analog signal and then communicate with a controlling µP with just a few wires. This avoids bussing the analog inputs long distances and thus reduces noise pickup on these analog lines. However, in some cases, the analog inputs have a large common mode voltage or even some noise present along with the valid analog signal. The differential input of these converters reduces the effects of common mode input noise. Thus, if a common mode voltage is present on both “+” and “–” inputs, such as 60Hz, the converter will reject this common mode voltage since it only converts the difference between “+” and “–” inputs. The ML2280 and ML2283 have a true sample and hold circuit which samples both “+” and “–” inputs simultaneously. This simultaneous sampling with a true S/H will give common mode rejection and AC linearity performance that is superior to devices where the two input terminals are not sampled at the same instant and where true sample and hold capability does not exist. Thus, these A/D converters can reject AC common mode signals from DC-50kHz as well as maintain linearity for signals from DC50kHz. The signal at the analog input is sampled during the interval when the sampling switch is closed prior to conversion start. The sampling window (S/H acquisition time) is 1/2 CLK period wide and occurs 1/2 CLK period before DO goes from high impedance to active low state. When the sampling switch closes at the start of the S/H acquisition time, 8pF of capacitance is thrown onto the analog input. 1/ 2 CLK period later, the sampling switch is opened and the signal present at the analog input is stored. Any error on the analog input at the end of the S/H acquisition time will cause additional conversion error. Care should be taken to allow adequate charging or settling time from the source. If more charging or settling time is needed to reduce these analog input errors, a longer CLK period can be used. For latchup immunity each analog input has dual diodes to the supply rails, and a minimum of ±25mA (±100mA typically) can be injected into each analog input without causing latchup. ZERO ERROR ADJUSTMENT The zero of the A/D does not require adjustment. If the minimum analog input voltage value, VIN MIN is not ground, a zero offset can be done. The converter can be made to output 00000000 digital code for this minimum input voltage by biasing any VIN– input at this VIN MIN value. This utilizes the differential mode operation of the A/D. The zero error of the A/D converter relates to the location of the first riser of the transfer function and can be measured by grounding the VIN– input and applying a small magnitude positive voltage to the VIN+ input. Zero error is the difference between the actual DC input voltage which is necessary to just cause an output digital code transition from 00000000 to 00000001 and the ideal 1/2 LSB value (1/2 LSB = 9.8mV for VREF = 5.000VDC). FULL-SCALE ADJUSTMENT The full-scale adjustment can be made by applying a differential input voltage which is 1-1/2 LSB down from the desired analog full-scale voltage range and then adjusting the magnitude of the VREF input or VCC for a digital output code which is just changing from 11111110 to 11111111. ADJUSTMENT FOR AN ARBITRARY ANALOG INPUT VOLTAGE RANGE If the analog zero voltage of the A/D is shifted away from ground (for example, to accommodate an analog input signal which does not go to ground), this new zero reference should be properly adjusted first. A VIN+ voltage which equals this desired zero reference plus 1/2 LSB (where the LSB is calculated for the desired analog span, 1 LSB = analog span/256) is applied to selected “+” input and the zero reference voltage at the corresponding “–” input should then be adjusted to just obtain the 00000000 to 00000001 code transition. The full-scale adjustment should be made by forcing a voltage to the VIN+ input which is given be:  (V − VMIN)  VIN + fs adjust = VMAX − 1.5 ×  MAX  256   where VMAX = high end of the analog input range VMIN = low end (offset zero) of the analog range The VREF or VCC voltage is then adjusted to provide a code change from 11111110 to 11111111. 12 ML2280, ML2283 SHUNT REGULATOR A unique feature of the ML2283 is the inclusion of a shunt regulator connected from V+ terminal to ground which also connects to the VCC terminal (which is the actual converter supply) through a silicon diode as shown in Figure 8. When the regulator is turned on, the V+ voltage is clamped at 11VBE set by the internal resistor ratio. The typical I-V of the shunt regulator is shown in Figure 9. It should be noted that before V+ voltage is high enough to turn on the shunt regulator (which occurs at about 5.5V), 35kW resistance is observed between V+ and GND. When the shunt regulator is not used, V+ pin should be either left floating or tied to GND. The temperature coefficient of the regulator is –22mV/°C. 12V I+→ V+ 28.8kΩ VCC 15mA I+ CURRENT LIMITING RESISTOR, I+ ≤15mA 3.2kΩ 3.2kΩ GND SLOPE = 1 35kΩ V+ 5.5V 6.9V Figure 9. Shunt Regulator Figure 10. I-V Characteristic of the Shunt Regulator 13 ML2280, ML2283 APPLICATIONS CH0 CS CLK DI P13 P12 P11 P10 ML2283 8051 CH3 DO 8051 Interface and Controlling Software MNEMONIC START: ANL MOV MOV P1, #0F7H B, #5 A, #ADDR A ONE P1, #0FEH CONT P1, #1 PULSE B, LOOP 1 PULSE B, #8 PULSE A, P1 A A A, C A C, A B, LOOP 2 INSTRUCTION ;SELECT A/D (CS = 0) ;BIT COUNTER ¨ 5 ;A ¨ MUX BIT ;CY ¨ ADDRESS BIT ;TEST BIT ;BIT = 0 ;DI ¨ 0 ;CONTINUE ;BIT = 1 ;D1 ¨ 1 ;PULSE SK 0 Æ 1 Æ 0 ;CONTINUE UNTIL DONE ;EXTRA CLOCK FOR SYNC ;BIT COUNTER ¨ 8 ;PULSE SK 0 Æ 1 Æ 0 ;CY ¨ DO ;A ¨ RESULT ;A(0) BIT ¨ AND SHIFT ;C ¨ RESULT ;CONTINUE UNTIL DONE ;PULSE SUBROUTINE LOOP 1: RRC JC ZERO: ANL SJMP ORL ACALL DJNZ ACALL MOV ONE: CONT: LOOP 2: ACALL MOV RRC RRC MOV RLC MOV DJNZ RETI PULSE: ORL NOP ANL RET P1, #04 P1, #0FBH ;SK ¨ 1 ;DELAY ;SK ¨ 0 14 ML2280, ML2283 APPLICATIONS (Continued) MUX ADDRESS 5VDC 51kΩ (4) START BIT SGL/DIF 11 15 CLK + 2 CLK INT 12 13 14 PARALLEL INPUTS 3 4 5 6 8 GND 7 NC DO CLK 1 SHIFT/ LOAD SIN 10 NC 5VDC (OR VIN) INPUT SHIFT REGISTER 74HC165 VCC 14 5VDC DO 9 START 1kΩ 6 5 2 1kΩ 4 1 1kΩ 3 0 1kΩ START 5 VDC CLK 2 CS 12 CLK NC 11 SARS 3 13 D1 5VDC 51kΩ ANALOG INPUTS ML2283 VREF/2 9 2.5V VCC 1 14 0.01µF 10kΩ CLK AGND 8 DGND 7 V+ DO 14 CLOSE TO START THE A/D CONVERSION 10kΩ 0.001µF CLOCK GENERATOR 7 GND OUTPUT SHIFT REGISTER 74HC164 CLK CLK Q D CLK 1.3kΩ (8) 8 CLK QH 13 12 11 10 6 5 4 2 QA 3 SI B 9 CLR 14 VCC SI A 1 + 10µF 1/2 74HC74 MSB DATA DISPLAY LSB 5VDC ML2283 “Stand-Alone” or Evaluation Circuit 15 ML2280, ML2283 APPLICATIONS (Continued) VCC (5 VDC) 15VDC OP AMP + RSET VIN (+) VCC + 10µF – VCC (5VDC) 600Ω VIN (+) VCC + 10µF RL ML2283 5VDC 10kΩ TA MIN ADJ. 5kΩ TA MAX ADJ. 7.5kΩ –15VDC ML2280 VIN (–) VREF/2 VIN (–) DIODE CLAMPING IS NOT NEEDED IF CURRENT IS LIMITED TO 25mA Low-Cost Remote Temperature Sensor Protecting the Input VCC (5VDC) 0.1Ω 100Ω → ILOAD (2A FULL-SCALE) VCC (5VDC) + 10µF 2kΩ 9.1kΩ VIN (–) 240kΩ ML2280 VCC LOAD 3kΩ 120kΩ + 1µF Digitizing a Current Flow VCC (5VDC) 20kΩ XDR VXDR 1kΩ ZERO ADJ. 3kΩ VIN (+) VIN (–)* ML2280 VCC + 10µF 16kΩ + 1µF *VIN (–) = 0.15VCC 15% OF VCC ≤ VXDR ≤ 85% OF VCC Operating with Ratiometric Transducers 16 + VREF/2 0.35 VCC + – VIN (+) VREF/2 – 100Ω ZERO ADJ. 1kΩ FS ADJ. 2.5V 1kΩ FS ADJ. 8.2kΩ ML2280, ML2283 APPLICATIONS (Continued) VCC (5VDC) VCC (5VDC) + VIN VIN (+) VCC + 10µF 10kΩ FS ADJ. 1kΩ VIN (–) SETS ZERO CODE VOLTAGE VREF/2 1.5 + 1µF 330Ω 1.2kΩ + VIN VIN (+) VCC + 10µF 10kΩ FS ADJ. 1kΩ + – 300Ω 2kΩ ML2280 ML2280 SETS VOLTAGE SPAN 1.2V VIN (–) VREF/2 + 330Ω 1µF SET FOR 1.5V 1.2V 2.7kΩ 1kΩ 2VDC ZERO ADJ. Span Adjust: 0V - VIN - 3V Zero-Shift and Span Adjust: 2V - VIN - 5V 330Ω 10V 6.8kΩ 1kΩ GAIN STRAIN GUAGE LOAD CELL 300Ω/30mV FS 1.3kΩ 10kΩ + – + – 5.1V VCC VREF/2 DUAL 1MΩ ML2280 CS –IN DUAL +IN GND 1MΩ 20kΩ 10kΩ OFFSET 20kΩ 10V DO CLK • USES ONE MORE WIRE THAN LOAD CELL ITSELF • TWO MINI-DIPs COULD BE MOUNTED INSIDE LOAD CELL FOR DIGITAL OUTPUT TRANSDUCER • ELECTRONIC OFFSET AND GAIN TRIMS RELAX MECHANICAL SPECS FOR GUAGE FACTOR AND OFFSET • LOW LEVEL CELL OUTPUT IS CONVERTED IMMEDIATELY FOR HIGH NOISE IMMUNITY Digital Load Cell 17 ML2280, ML2283 APPLICATIONS (Continued) START LS193 LOAD AB B0 COUNT C D DOWN S R TMS320 SERIES D 5V Q Q Q D Q DSP Q D Q Q ML2280 CLK VIN+ VIN– CS DO CLK FSR CLK DR Sampling Rate 111kHz, Data Rate 1.33MHz CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 START CS FSR DO HI-Z D7 D6 D5 D4 D3 D2 D1 D0 HI-Z Interfacing ML2280 to TMS320 Series 18 ML2280, ML2283 PHYSICAL DIMMENSIONS inches (millimeters) Package: P08 8-Pin PDIP 0.365 - 0.385 (9.27 - 9.77) 0.055 - 0.065 (1.39 - 1.65) 8 PIN 1 ID 0.240 - 0.260 0.299 - 0.335 (6.09 - 6.60) (7.59 - 8.50) 0.020 MIN (0.51 MIN) (4 PLACES) 1 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN) 0.170 MAX (4.32 MAX) 0.125 MIN (3.18 MIN) 0.016 - 0.020 (0.40 - 0.51) SEATING PLANE 0º - 15º 0.008 - 0.012 (0.20 - 0.31) Package: S08 8-Pin SOIC 0.189 - 0.199 (4.80 - 5.06) 8 PIN 1 ID 0.148 - 0.158 0.228 - 0.244 (3.76 - 4.01) (5.79 - 6.20) 1 0.017 - 0.027 (0.43 - 0.69) (4 PLACES) 0.050 BSC (1.27 BSC) 0.059 - 0.069 (1.49 - 1.75) 0º - 8º 0.055 - 0.061 (1.40 - 1.55) 0.012 - 0.020 (0.30 - 0.51) SEATING PLANE 0.004 - 0.010 (0.10 - 0.26) 0.015 - 0.035 (0.38 - 0.89) 0.006 - 0.010 (0.15 - 0.26) 19 ML2280, ML2283 PHYSICAL DIMMENSIONS inches (millimeters) Package: P14 14-Pin PDIP 0.740 - 0.760 (18.79 - 19.31) 14 PIN 1 ID 0.240 - 0.260 0.295 - 0.325 (6.09 - 6.61) (7.49 - 8.25) 0.070 MIN (1.77 MIN) (4 PLACES) 1 0.050 - 0.065 (1.27 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN) 0.170 MAX (4.32 MAX) 0.125 MIN (3.18 MIN) 0.016 - 0.022 (0.40 - 0.56) SEATING PLANE 0º - 15º 0.008 - 0.012 (0.20 - 0.31) ORDERING INFORMATION PART NUMBER ALTERNATE PART NUMBER TOTAL UNADJUSTED ERROR TEMPERATURE RANGE PACKAGE SINGLE ANALOG INPUT, 8-PIN PACKAGE ML2280BIP (Obs) ML2280BIS (Obs) ML2280BCP (Obs) ML2280BCS (Obs) ML2280CIP (Obs) ML2280CIS (Obs) ML2280CCP (Obs) ML2280CCS (Obs) TWO ANALOG INPUTS, 14-PIN PACKAGE ML2283BIP (Obs) ML2283BCP (Obs) ML2283CIP (Obs) ML2283CCP (EOL) ADC0833CCN ADC0833BCN ADC0833BCN ADC0833CCN ±1/2 LSB ±1 LSB –40°C to 85°C 0°C to 70°C –40°C to 85°C 0°C to 70°C 14-Pin DIP (P014) 14-Pin DIP (P014) 14-Pin DIP (S014) 14-Pin DIP (P014) –40°C to 85°C –40°C to 85°C 0°C to 70°C 0°C to 70°C –40°C to 85°C –40°C to 85°CQ 0°C to 70°C 0°C to 70°C 8-Pin DIP (P08) 8-Pin SOIC (S08) 8-Pin DIP (P08) 8-Pin SOIC (S08) 8-Pin DIP (P08) 8-Pin SOIC (S08) 8-Pin DIP (P08) 8-Pin SOIC (S08) ±1/2 LSB ±1 LSB © Micro Linear 1997 is a registered trademark of Micro Linear Corporation Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending. Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application. 2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295 DS2280_83-01 20