ML4821

May 1997 Micro Linear GENERAL DESCRIPTION The ML4821 provides complete control for a “boost” type power factor correction system using the average current sensing method. Special care has been taken in the design of the ML4821 to increase system noise immunity. The circuit includes a precision reference, gain modulator, average current error amplifier, output error amplifier, over-voltage protection comparator, shutdown logic, as well as a high current output. In addition, start-up is simplified by an under-voltage lockout circuit. In a typical application, the ML4821 controls the AC input current by adjusting the pulse width of the output MOSFET. This modulates the line current so that its shape conforms to the shape of the input voltage. The reference for the current regulator is a product of the sinusoidal line voltage times the output of the error amplifier which is regulating the output DC voltage. Average line voltage compensation is provided in the gain modulator to ensure constant loop gain over a wide input voltage range. This compensation includes a special “brown-out” control which reduces output power below 90V RMS input. ML4821* Power Factor Controller FEATURES s s s s s s s s s Average current sensing for lowest possible harmonic distortion Average line compensation with brown-out control Precision buffered 5V reference 1A peak current totem-pole output drive Overvoltage comparator eliminates output “runaway” due to load removal Wide common mode range in current sense comparators for better noise immunity Large oscillator amplitude for better noise immunity Output driver internally limited to 17V “Sleep mode” shutdown input * Some Packages Are Obsolete BLOCK DIAGRAM 11 1 OVP ILIM VREF + – 0.7V + – – + SLEEP UNDER VOLTAGE LOCKOUT VREF 16 2 3 IA OUT IA– GND 18 – – + R S Q VLIMIT 17V VCC 15 IA+ 4 + OUT 14 5 8 ISINE VRMS OUT GAIN MODULATOR PGND RT OSC SYNC CT VREF 13 12 10 17 6 7 EA OUT EA– VREF SOFT START – + 9 Micro Linear 1 ML4821 PIN CONNECTION ML4821 18-Pin DIP (P18) ILIM IA OUT IA– IA+ ISINE EA OUT EA– VRMS SOFT START 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 ML4821 20-Pin SOIC (S20) GND CT VREF VCC OUT PGND RT OVP SYNC ILIM IA OUT IA– IA+ ISINE EA OUT EA– VRMS SOFT START N/C 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 GND CT VREF VCC OUT PGND RT OVP SYNC N/C TOP VIEW TOP VIEW PIN DESCRIPTION (Pin numbers in parentheses are for 20-pin packages) PIN NAME FUNCTION PIN NAME FUNCTION 1 (1) 2 (2) 3 (3) 4 (4) ILIM Peak cycle-by-cycle current limit input 10 (12) SYNC 11 (13) OVP Oscillator synchronization input Inhibits output pulses when the voltage at this pin exceeds 5V. Also, when the voltage at this pin is less than 0.7V, the IC goes into low current shut-down mode. Timing resistor for the oscillator Return for the high current totem pole output High current totem pole output Positive supply for the IC Buffered output for the 5V voltage reference Timing capacitor for the oscillator. Analog signal ground IA OUT Output and compensation node of the average current error amplifier IA– IA+ Inverting input of the average current error amplifier Non-Inverting input of the average current error amplifier and output of the gain modulator Gain modulator input 12 (14) RT 13 (15) PWR GND 14 (16) OUT 15 (17) VCC 16 (18) VREF 17 (19) CT 18 (20) GND 5 (5) 6 (6) 7 (7) 8 (8) 9 (9) ISINE EA OUT Output of output voltage error amplifier INV VRMS SOFT START Inverting input to error amplifier Input for average line voltage compensation Normally connected to soft start capacitor 2 Micro Linear ML4821 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Supply Current (ICC) ................................................ 35mA OUT Current, Source or Sink .................................... 1.0A Output Energy (capacitive load per cycle) .................... 5µJ ISINE Input Current .................................................. 1.2mA EA OUT Source Current .......................................... 50mA Oscillator Charge Current ......................................... 2mA Input Voltage ...................................... GND –0.3V to 5.5V Junction Temperature .............................................. 150 °C Storage Temperature Range ...................... –65°C to 150°C Lead Temperature (Soldering 10 sec.) ...................... 260 °C Thermal Resistance (θJA) Plastic DIP ........................................................ 75°C/W Plastic SOIC ..................................................... 95°C/W OPERATING CONDITIONS Temperature Range ML4821CX ................................................. 0°C to 70 °C ML4821IX .............................................. –40°C to 85 °C ELECTRICAL CHARACTERISTICS PARAMETER OSCILLATOR Initial accuracy Voltage stability Temperature stability Total Variation Ramp Valley to Peak RT Voltage Discharge Current SYNC Input Threshold REFERENCE Output Voltage Line regulation Load regulation Temperature stability Total Variation Output Noise Voltage Long Term Stability Short Circuit Current VOLTAGE ERROR AMPLIFIER Input Offset Voltage Input Bias Current Open Loop Gain PSRR Output Sink Current Output Source Current Unless otherwise specified, RT = 6.2k Ω, CT = 720pF, T A = Operating Temperature Range, VCC = 15V (Notes 1 & 2). CONDITIONS MIN TYP. MAX UNITS TA = 25°C 12V < VCC < 18V 90 100 1 2 110 kHz % % Line, Temperature 85 4.7 4.8 5.2 5.0 8.4 2.0 115 5.6 5.2 9.3 3.0 kHz V V mA V CT= 2V, RT = Open 7.8 1.5 TA = 25°C, IO = 1mA 12V < VCC < 24V 1mA < IO < 20mA 4.95 5.00 2 2 .4 5.05 10 15 V mV mV % line, load, temp 10Hz to 10kHz TA = 125°C, 1000 hrs VREF = 0V 4.9 50 5 –30 –85 5.1 V µV 25 –180 mV mA 0 –50 2 < EA OUT < 6V 12V < VCC < 24V EA OUT = 4V, INV = 5.5V EA OUT = 4.0V, INV = 4.8V 60 70 300 –10 75 100 500 –30 –15 –800 mV nA dB dB µA mA Micro Linear 3 ML4821 ELECTRICAL CHARACTERISTICS (Continued) PARAMETER VOLTAGE ERROR AMPLIFIER (Continued) Output High Voltage Output Low Voltage Unity Gain Bandwidth Soft Start Charge Current CURRENT ERROR AMPLIFIER Input Offset Voltage Input Bias Current Input Offset Current Open Loop Gain PSRR Output Voltage Low Output Voltage High Input Common Mode Range GAIN MODULATOR Gain VINV = 4.8V, VRMS = 0V VINV = 4.8V, VRMS = 1.75V VINV = 4.8V, VRMS = 2.6V VINV = 4.8V, VRMS = 5.2V VINV = 5.2V, VRMS = 5.2V VINV = 4.8V, ISINE = 500µ A, VRMS = 1.75V 360 0.75 3.1 1.25 0.22 1.2 3.88 1.75 0.38 –2 395 1.3 4.5 2.15 0.50 –4 420 µA µA 2 < EA OUT < 7V 12V < VCC < 24V IOL = 300µA IOH = –10mA 7.0 –0.3 80 65 100 85 0 7.5 2.5 0.5 –5 0 –0.15 5 –1 400 mV µA nA dB dB V V V VPIN9 = 4V –22 IPIN6 = –5mA, VPIN7 = 4.8V IPIN6 = 0, EA– = 5.5V 7.0 7.5 0 1.0 –38 –50 0.5 V V MHz µA CONDITIONS MIN TYP MAX UNITS Output Current Output Current Limit ILIM COMPARATOR Input Offset Voltage Input Bias Current OVP COMPARATOR Input Offset Voltage Hysteresis Input Bias Current Propagation Delay Shutdown Threshold PWM COMPARATOR Input Common Mode Range Propagation Delay +15 –100 –200 mV µA Output Off Output On –25 85 105 –0.3 150 0.4 0.7 5 130 –3 mV mV µA ns 1.0 V 0 150 8 V ns 4 Micro Linear ML4821 ELECTRICAL CHARACTERISTICS (Continued) PARAMETER OUTPUT Output Voltage Low Output Voltage High Output Voltage Low in UVLO Output Rise/Fall Time UNDERVOLTAGE LOCKOUT Start-up Threshold Shut-Down Threshold VREF Good Threshold SUPPLY Supply Current Internal Shunt Zener Voltage Note 1: Note 2: Note 3: CONDITIONS MIN TYP. MAX UNITS IOUT = 20mA IOUT = 200mA IOUT = –20mA IOUT = –200mA IOUT = –5mA, VCC = 8V CL = 1000pF 13 12 0.1 1.6 13.5 13.4 0.1 50 0.4 2.4 V V V V 0.8 V ns 14.5 8.5 4.4 16.5 11.0 V V V Start-up, VCC = 14V, TA = 25°C Operating, TA = 25°C ICC = 35mA 25 0.6 26 27 1.2 32 35 mA mA V Limits are guaranteed by 100% testing, sampling or correlation with worst case test conditions. VCC is raised above the start-up threshold first to activate the IC, then returned to 15V I Gain Modulator gain is defined as: OUTIA + IINEA OUT Micro Linear 5 ML4821 FUNCTIONAL DESCRIPTION OSCILLATOR The ML4821 oscillator charges the external capacitor connected to CT with a current equal to 2.5/RT. When the capacitor voltage reaches the upper threshold, the comparator changes state and the capacitor discharges to the lower threshold through Q1. The oscillator period can be described by the following relationship: TOSC = TRAMP + TDISCHARGE where: TRAMP = C(Ramp Valley to Peak) ÷ (IRT/2) and: TDISCHARGE = C(Ramp Valley to Pk) ÷ (8.4mA – IRT/2) CLOCK tD RAMP PEAK CT RAMP VALLEY VOLTAGE AND CURRENT ERROR AMPLIFIERS The ML4821 voltage error amplifier is a high open loop gain, wide bandwidth amplifier with a class A output. The soft start circuit controls the input to this amplifier for closed loop soft start operation. The current error amplifier (IA) is similar to the voltage error amplifier but is designed for very low offsets to allow the selection of a low value resistor for RSENSE. OUTPUT DRIVER STAGE The ML4821 Output Driver is a 1A peak output high speed totem pole circuit designed to quickly drive capacitive loads, such as power MOSFET gates. The driver circuit’s output voltage is internally limited to 17V. GAIN MODULATOR The ML4821 gain modulator responds linearly to current injected into the ISINE pin, and in an inverse-square fashion to voltage on the VRMS pin. At very low voltages on the VRMS pin, the gain modulator enforces a power limit, or ”brown-out protection”, upon the overall PFC circuit (Figures 6 and 7). The rectified line input sine wave is converted to a current for the ISINE input via a dropping resistor. In this way, most ground noise produces an insignificant effect on the reference to the PWM comparator. This gives the ML4821 a high degree of immunity to the disturbances common in high-power switching circuits. The ML4821 oscillator includes a SYNC input for synchronizing to an external frequency source. A positive pulse on this pin of 2V (typ) resets the oscillators comparator and initiates a discharge cycle for CT. The RT and CT component values which set the ML4821 oscillator frequency should be selected to produce a lower frequency than the external frequency source. RT RT VREF 1000 IRT IRT 2 + – FREQUENCY (kHz) CT 150pF 100 CT 8.4mA Q1 1nF 680pF SYNC 2kΩ 1kΩ Q2 10 0 10 20 RT (kΩ) 30 330pF 470pF 40 50 Figure 1. Oscillator Block Diagram. Figure 2. Oscillator Timing Resistance vs. Frequency. 6 Micro Linear ML4821 INV 7 +8V AVOL, OPEN-LOOP VOLTAGE GAIN (dB) 100 80 GAIN 60 40 PHASE 20 0 –20 10 100 1.0k 10k 100k f, FREQUENCY (Hz) 1.0M 120 150 180 10M 0 VCC = 15V VO = 1.0V TO 5.0V –30 RL = 100kΩ TA= 25°C 60 90 PHASE (DEGREES) – +8V VREF + 6.2kΩ EA OUT 6 S.S 9 Figure 3. Error and Current Amplifier Configuration Figure 4. Error Amplifier Open-loop Gain and Phase vs. Frequency. 0.5 OPERATING BOUNDRY 0 VSAT, OUTPUT SATURATION VOLTAGE (V) VCC –1.0 –2.0 TA = 25°C SOURCE SATURATION (LOAD TO GROUND) VCC = 15V 80µs PULSED LOAD 120 Hz RATE 0.4 DESIGN FOR BROWNOUT DESIGN FOR NORMAL OPERATIONS THIS IS THE MINIMUM OPERATING VOLTAGE POINT TA = –55°C K 0.3 3.0 TA = –55°C 2.0 1.0 0 SINK SATURATION (LOAD TO VCC) GND 0 200 400 600 800 TA = 25°C 0.2 0.23 0.1 THIS GAIN CURVE TAKES OUT THE 1/(VIN)2 DEPENDENCY OF THE VOLTAGE CONTROL LOOP 0 0 1 2 85VAC 3 120VAC 4 VRMS 5 220VAC 6 7 IO, OUTPUT LOAD CURRENT (mA) Figure 5. Output Saturation Voltage vs. Output Current. Figure 6. K-factor. Gain Modulator gain with respect to the voltage at VRMS. The output of the gain modulator is a current which appears on IA+ to form the reference for the current error amplifier and is given as: IGM = K × ISINE × (VEA − 0.8) where: ISINE is the current in the dropping resistor, VEA is the output of the error amplifier and K is a constant determined by the VRMS input. The output current of the gain modulator is limited to: IGM(MAX) = 2.5 RT This sets the system current limit.The multiplier output current is converted into the reference voltage for the current (IA) amplifier through a resistor to ground on IA+. Figure 6 shows the gain adjustor (K) with respect to the voltage at VRMS. The curve has been separated in two parts. The right hand part is for operation under normal conditions in the voltage range from minimum line voltage to maximum line voltage (90VAC to 260VAC). 85VAC on the curve has been chosen to account for tolerances. Under normal operating conditions as input voltage decreases the gain increases compensating for the drop in the loop gain. Under brownout conditions (below 85VAC) the gain decreases to limit the amount of current that is drawn from the line thus preventing an overload condition. This is a very useful feature since in many cases the load for a PFC is a constant power load. The input current has to go high to compensate for a drop in the input voltage. Micro Linear 7 ML4821 UNDER VOLTAGE LOCKOUT, OVP AND CURRENT LIMIT On power-up the ML4821 remains in the UVLO condition; output low and quiescent current low. The IC becomes operational when VCC reaches 16V. When VCC drops below 9V, the UVLO condition is imposed. During the UVLO condition, the VREF pin is “off”, making it usable as a “flag” for starting up a down-stream PWM converter. OVP, SHUTDOWN, AND IC BIAS When the input to the OVP comparator exceeds VREF, the output of the ML4821 is inhibited. The OVP input also functions as a “sleep” input, putting the IC into the low quiescent UVLO state when the OVP pin is pulled below 0.7V. 500 MULTIPLIER OUTPUT CURRENT (µA) RT = 5kΩ VRMS = 3V 5.5 400 – + ENABLE VREF 4.4V E/A OUTPUT VOLTAGE 4.5 300 3.5 LOGIC POWER VREF 16 200 2.5 100 1.5 1.0 0 100 200 300 400 500 9V – + 0 SINE INPUT CURRENT (µA) INTERNAL BIAS VCC 15 Figure 7. Gain Modulator Linearity. Figure 8. Under-Voltage Lockout Block Diagram. ∆VREF, REFERENCE VOLTAGE CHANGE (mV) 0 VCC = 15V –4.0 –8.0 –12 TA = –55°C –16 –20 –24 TA = 125°C 40 ICC SUPPLY CURRENT (mA) 30 20 TA = 25°C 10 TA = 25°C 0 0 10 20 30 VCC SUPPLY VOLTAGE (V) 0 20 40 60 80 100 120 IREF, REFERENCE SOURCE CURRENT (mA) Figure 9. Total Supply Current vs. Supply Voltage. Figure 10. Reference Load Regulation. 8 Micro Linear ML4821 OFF-LINE START-UP AND BIAS SUPPLY GENERATION The circuit in Figure 11 supplies VCC power to the ML4821. Start-up current is delivered via R10. The IC starts when VCC reaches 15.5V. After that time running power is delivered through the tap on L1. The configuration shown delivers a voltage proportional to the PFC output bus voltage. R10 39kΩ 2W TO B+ L1 NP NS 1µF 1000µF 1µF TO IC PIN 15 NP NS ≈ VOUT 14V Figure 11. Bias and Start-up Circuit. Micro Linear 9 ML4821 F1 5A, 250V D1 AC IN 90-264 VAC C1 1µF D2 D1 1N5406 L1 + D3 D4 D7 1N4934 C12 1µF C13 1µF D8 1N4934 R7 560kΩ D10 MUR850 C14 470µF C14 470µF DC OUT 382V R10 39kΩ C19 270µF 450V – R11 8.2kΩ R5 2kΩ R8 910kΩ ML4821 1 2 ILIM IA OUT IA– IA+ ISINE EA OUT EA– VRMS SOFT START GND CT VREF VCC OUT PGND RT OVP SYNC 18 17 16 15 14 13 12 11 10 R22 7.3Ω R6 2.7kΩ R13 20kΩ 3 4 5 R9 91kΩ C2 120pF 6 7 R20 825kΩ C5 1.5nF 8 9 C3 0.1µF R19 10.2kΩ R18 825kΩ D5 1N5406 R12 2.7kΩ C4 1.5nF R14 91kΩ C6 43nF R21 6.2kΩ C8 C10 0.1µF C11 750pF R17 10.5kΩ D6 1N5406 R1 0.25Ω R15 27kΩ C7 0.47µF Figure 12. 200W Output PFC Circuit 10 Micro Linear ML4821 PHYSICAL DIMENSIONS inches (millimeters) Package: P18 18-Pin PDIP 0.890 - 0.910 (22.60 - 23.12) 18 PIN 1 ID 0.240 - 0.260 0.295 - 0.325 (6.09 - 6.61) (7.49 - 8.26) 0.045 MIN (1.14 MIN) (4 PLACES) 1 0.050 - 0.065 (1.27 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN) 0.170 MAX (4.32 MAX) 0.125 MIN (3.18 MIN) 0.016 - 0.022 (0.40 - 0.56) SEATING PLANE 0º - 15º 0.008 - 0.012 (0.20 - 0.31) Package: S20 20-Pin SOIC 0.498 - 0.512 (12.65 - 13.00) 20 0.291 - 0.301 0.398 - 0.412 (7.39 - 7.65) (10.11 - 10.47) PIN 1 ID 1 0.024 - 0.034 (0.61 - 0.86) (4 PLACES) 0.050 BSC (1.27 BSC) 0.095 - 0.107 (2.41 - 2.72) 0º - 8º 0.090 - 0.094 (2.28 - 2.39) 0.012 - 0.020 (0.30 - 0.51) SEATING PLANE 0.005 - 0.013 (0.13 - 0.33) 0.022 - 0.042 (0.56 - 1.07) 0.007 - 0.015 (0.18 - 0.38) Micro Linear 11 ML4821 ORDERING INFORMATION PART NUMBER ML4821CP ML4821CS ML4821IP ML4821IS TEMPERATURE RANGE 0°C to 70°C 0°C to 70°C –40°C to 85°C –40°C to 85°C PACKAGE 18-Pin PDIP (P18) 20-Pin SOIC (S20) 18-Pin PDIP (P18) (Obsolete) 20-Pin SOIC (S20) (Obsolete) © Micro Linear 1997 Micro Linear is a registered trademark of Micro Linear Corporation Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending. Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application. 2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295 DS4821-01 12 Micro Linear