ML4825CQ

May 1997 ML4825* High Frequency Power Supply Controller GENERAL DESCRIPTION The ML4825 High Frequency PWM Controller is an IC controller optimized for use in Switch Mode Power Supply designs running at frequencies to 1MHz. Propagation delays are minimal through the comparators and logic for reliable high frequency operation while slew rate and bandwidth are maximized on the error amplifier. This controller is designed to work in either voltage or current mode and provides for input voltage feed forward. A 1V threshold current limit comparator provides cycleby-cycle current limit while exceeding a 1.4V threshold initiates a soft-start cycle. The soft start pin doubles as a maximum duty cycle clamp. An under-voltage lockout circuit with 800mV of hysteresis assures low startup current and drives the outputs low. This controller is similar in architecture and performance to the UC1825 controller, however the ML4825 includes many features not found on the 1825. These features are set in Italics. FEATURES s s s s s s s s s s s s s Practical operation at switching frequencies to 1.0MHz High current (2A peak) dual totem pole outputs Wide bandwidth error amplifier Fully latched logic with double pulse suppression Pulse-by-pulse current limiting Soft start and maximum duty cycle control Under voltage lockout with hysteresis Precision trimmed 5.1V bandgap reference Pin compatible improved replacement for UC1825 Fast shut down path from current limit to outputs Outputs preset to known condition after under voltage lockout Soft start latch ensures full soft start cycle Outputs pull low for undervotage lockout BLOCK DIAGRAM (Pin configuration shown for 16-pin version) 5 6 *Some Packages Are Obsolete or End Of Life CLOCK OUT RT CT OSC 4 7 3 RAMP E/A OUT 1.25V + R + – COMP S Q PWR VC OUT A V+ C TF.F. P Q Q POWER GND POWER VC OUT B PWR GND – + + 2 1 NI INV + – ERROR AMP 13 11 9µA 8 14 12 SS 4V 1V ENABLE VREF – 9 1V ILIM/SD – + 1.5V VREF 16 VREF GEN R Q – 9V INTERNAL BIAS VCC SIGNAL GND 15 10 + 1.4V – S UNDER VOLTAGE LOCKOUT + 1 ML4825 PIN CONFIGURATION ML4825 16-Pin PDIP 16-Pin SOIC NI ML4825 20-Pin PLCC 5.1V REF 20 NI E/A OUT CLOCK RT CT RAMP SS 2 3 4 5 6 7 8 15 14 13 12 11 10 9 VCC OUT B VC PWR GND OUT A GND ILIM/SD E/A OUT CLOCK NC RT CT 4 5 6 7 8 3 2 1 NC INV 1 16 5.1V REF 19 18 17 16 15 14 OUT B VC NC PWR GND OUT A 9 10 11 12 13 ILIM/SD RAMP TOP VIEW TOP VIEW PIN DESCRIPTION (Pin number in parentheses is for PLCC version) PIN NAME FUNCTION PIN NAME FUNCTION 1 (2) INV Inverting input to error amp. Non-inverting input to error amp. 9 (12) ILIM/SD 10 (13) GND Current limit sense pin. Normally connected to current sense resistor. Analog signal ground High current totem pole output. This output is the first one energized after power on reset 2 (3) NI 3 (4) E/A OUT 4 (5) CLOCK 5 (7) RT Output of error amplifier and input to main comparator Oscillator output Timing resistor for oscillator— sets charging current for oscillator timing capacitor (pin 6) Timing capacitor for oscillator Non-inverting input to main comparator. Connected to CT for voltage mode operation or to current sense resistor for current mode Normally connected to soft start capacitor 11 (14) OUT A 12 (15) PWR GND Return for the high current totem pole outputs 13 (17) VC 14 (18) OUT B 15 (19) VCC 16 (20) 5.1V REF Positive supply for the high current totem pole output High current totem pole output Positive supply for the IC Buffered output for the 5.1V voltage reference 6 (8) CT 7 (9) RAMP 8 (10) SS 2 GND SS NC VCC INV ML4825 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Supply Voltage (VC, VCC) ........................................... 30V Output Current, Source or Sink (OUT A, OUT B) DC ....................................................................... 0.5A Pulse (0.5µs) ......................................................... 2.0A Analog Inputs (INV, NI, RAMP) ................................ GND –0.3V to 7V (SS, ILIM) ........................................... GND –0.3V to 6V CLOCK Output Current ........................................... –5mA E/A OUT Output Current .......................................... 5mA Soft Start Sink Current ............................................ 20mA RT Charging Current ................................................ –5mA Junction Temperature ML4825IX, ML4825CX ....................................... 150°C Storage Temperature Range ..................... –65°C to 150°C Lead Temperature (soldering 10 sec.) ..................... 260°C Thermal Resistance (θJA) Plastic DIP or SOIC ......................................... 65°C/W Plastic Chip Carrier (PCC) ................................ 60°C/W OPERATING CONDITIONS Temperature Range ML4825CX ................................................ 0°C to 70°C ML4825IX .............................................. –40°C to 85°C ELECTRICAL CHARACTERISTICS PARAMETER OSCILLATOR Initial Accuracy Voltage Stability Temperature Stability Total Variation Clock Out High Clock Out Low Ramp Peak Ramp Valley Ramp Valley to Peak REFERENCE Output Voltage Unless otherwise specified, RT = 3.65kΩ, CT = 1000pF, TA = Operating Temperature Range, VCC = 15V (Note 1). CONDITIONS TJ = 25°C 10V < VCC < 30V, TA = 25°C Line, temperature MIN TYP MAX UNITS 360 –2 400 0.2 440 2 5 kHz % % kHz V 340 3.9 4.5 2.3 2.6 0.7 1.6 2.8 1.0 1.8 460 2.9 3.0 1.25 2.0 V V V V TJ = 25°C, IO = 1mA 10V < VCC < 30V 1mA < IO < 10mA –55°C < TJ < 150°C Line, load, temperature C suffix I suffix 5.00 5.00 –20 –20 5.10 5.10 2 5 0.2 5.20 5.20 20 20 0.4 5.25 5.25 V V mV mV % V V µV Line Regulation Load Regulation Temperature Stability Total Variation C suffix I suffix 4.95 4.95 50 5 –15 –50 Output Noise Voltage Long Term Stability Short Circuit Current ERROR AMPLIFIER Input Offset Voltage 10Hz to 10kHz TJ = 125°C, 1000 hours VREF = 0V C suffix I suffix 25 –100 mV mA –15 –15 0.6 0.1 15 15 3 1 mV mV µA µA dB Input Bias Current Input Offset Current Open Loop Gain 1 < VO < 4V 60 96 3 ML4825 ELECTRICAL CHARACTERISTICS (Continued) PARAMETER ERROR AMPLIFIER (Continued) CMRR PSRR Output Sink Current Output Source Current Output High Voltage Output Low Voltage Unity Gain Bandwidth Slew Rate PWM COMPARATOR Ramp Bias Current Duty Cycle Range E/A OUT Zero DC Threshold Delay to Output SOFT START Charge Current Discharge Current CURRENT LIMIT/SHUTDOWN ILIM Bias Current Current Limit Threshold Shutdown Threshold Delay to Output OUTPUT Output Low Level Output High Level Collector Leakage Rise/Fall Time UNDERVOLTAGE LOCKOUT Start Threshold UVLO Hysteresis SUPPLY Start Up Current ICC Note 1: CONDITIONS 1.5V < VCM < 5.5V 10V < VCC < 30V VEA OUT A = 1.0V VEA OUT A = 4.0V IEA OUT A = –0.5mA IEA OUT A = 1mA C suffix I suffix C suffix I suffix MIN 75 75 80 80 1 –0.5 4.0 0 3 6 TYP 95 95 110 110 2.5 –1.3 4.7 0.5 5.5 12 –1 MAX UNITS dB dB dB dB mA mA 5.0 1.0 V V MHz V/µs VRAMP = 0V, TA > 0°C C suffix I suffix C suffix I suffix 85 80 1.1 –5 –5 100 100 µA µA % % V nS µA mA VRAMP = 0V 1.25 50 1.7 80 SS = 0.5V SS = 1V 0V < VI(LIM) < 0.5V C suffix I suffix TA > 0°C TA < 0°C –3 1 –10 –10 0.9 1.25 1.25 –9 –20 10 10 1 1.4 1.4 40 1.1 1.55 1.60 70 0.4 2.2 µA µA V V V ns V V V V IOUT = 20mA IOUT = 200mA IOUT = –20mA IOUT = –200mA VC = 30V CL = 1000pF 8.8 0.3 VCC = 8V C suffix I suffix VINV, VRAMP, VI(LIM)/SD = 0V, VNI = 1V, TA = 25°C 0.1 0.1 10 13.0 12.0 0.25 1.2 13.5 13.0 100 30 9.2 0.8 1.1 26 500 60 9.6 1.2 2.5 3.5 33 µA ns V V mA mA mA Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. 4 ML4825 FUNCTIONAL DESCRIPTION OSCILLATOR The ML4825 oscillator charges the external capacitor (CT) with a current (ISET) equal to 3/RSET. When the capacitor voltage reaches the upper threshold (Ramp Peak), the comparator changes state and the capacitor discharges to the lower threshold (Ramp Valley) through Q1. While the capacitor is discharging, Q2 provides a high pulse. The oscillator period can be described by the following relationship: tOSC = tRAMP + tDEADTIME where: tRAMP = C (Ramp Valley to Peak) ISET 1k 100 1k 10k 100k 100k 100nF 47nF 22nF RT (Ω) 0nF 10k 4.7nF 2.2nF 1nF 470pF 1M FREQUENCY (Hz) Figure 2. Oscillator Timing Resistance vs Frequency and: tDEADTIME = C (Ramp Valley to Peak) IQ1 160 140 ISET TD (ns) 5 1.0nF 5.1V 3V ISET 120 RT 6 CT IQ1 + – 100 Q1 4 470pF 80 10k 100k FREQUENCY (Hz) 1M Figure 3. Oscillator Deadtime vs Frequency CLOCK tD RAMP PEAK CT RAMP VALLEY 4.70 2.20 1.00 0.47 0.22 0.10 0.047 0.47 Figure 1. Oscillator Block Diagram TD (µs) 1.0 2.2 4.7 10.0 22 47 100 CT (nF) Figure 4. Oscillator Deadtime vs CT (3kΩ ≤ RT ≤ 100kΩ) 5 ML4825 ERROR AMPLIFIER The ML4825 error amplifier is a 5.5MHz bandwidth 12V/µs slew rate op-amp with provision for limiting the positive output voltage swing (Output Inhibit line) for ease in implementing the soft start function. OUTPUT DRIVER STAGE The ML4825 Output Driver is a 2A peak output high speed totem pole circuit designed to quickly switch the gates of capacitive loads, such as power MOSFET transistors. SOFT START AND CURRENT LIMIT The ML4825 employs two current limits. When the voltage at ILIM/SD exceeds 1V, the outputs are immediately shut off and the cycle is terminated for the remainder of the oscillator period by resetting the RS flip flop. If the output current is rising quickly such that the voltage on ILIM/SD reaches 1.4V before the outputs have turned off, a soft start cycle is initiated. The soft start capacitor is discharged and outputs are held “off” until the voltage at SS reaches 1V, ensuring a complete soft start cycle. The duty cycle on start up is limited by limiting the output voltage of the error amplifier voltage to the voltage at SS. 5 100 80 4 VIN 60 AV 40 20 0 0 –20 0 0 –90 –180 100M (V) 3 VOUT 2 1 0 0.2 0.4 0.6 0.8 1.0 100 1k 10k 100k 1M 10M TIME (µs) FREQUENCY (Hz) Figure 5. Unity Gain Slew Rate VCC 3 POWER VC 13 Q2 VSAT (V) AV (dB) OUT A Figure 6. Open Loop Frequency Response 2 11 SOURCE OUT B 14 1 Q1 POWER GND SINK 12 0 0 0.5 IOUT (A) 1.0 1.5 Figure 7. Simplified Schematic Figure 8. Saturation Curves 6 ML4825 0.2 IL (A) 0 2 IL (A) 0 10 VOUT (V) VOUT (V) 15 –0.2 15 –2 10 5 5 0 0 40 80 120 160 200 TIME (ns) 0 0 100 200 300 400 500 TIME (ns) Figure 9. Rise/Fall Time (CL = 1000pF) Figure 10. Rise/Fall Time (CL = 10,000pF) 40 35 ICC — SUPPLY CURRENT 30 25 20 15 10 5 0 –60 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) Figure 11. Supply Current vs. Temperature 7 ML4825 PHYSICAL DIMENSIONS inches (millimeters) Package: P16 16-Pin PDIP 0.740 - 0.760 (18.79 - 19.31) 16 PIN 1 ID 0.240 - 0.260 0.295 - 0.325 (6.09 - 6.61) (7.49 - 8.26) 0.02 MIN (0.50 MIN) (4 PLACES) 1 0.055 - 0.065 (1.40 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN) 0.170 MAX (4.32 MAX) 0.125 MIN (3.18 MIN) 0.016 - 0.022 (0.40 - 0.56) SEATING PLANE 0º - 15º 0.008 - 0.012 (0.20 - 0.31) Package: S16W 16-Pin Wide SOIC 0.400 - 0.414 (10.16 - 10.52) 16 0.291 - 0.301 0.398 - 0.412 (7.39 - 7.65) (10.11 - 10.47) PIN 1 ID 1 0.024 - 0.034 (0.61 - 0.86) (4 PLACES) 0.050 BSC (1.27 BSC) 0.095 - 0.107 (2.41 - 2.72) 0º - 8º 0.090 - 0.094 (2.28 - 2.39) 0.012 - 0.020 (0.30 - 0.51) SEATING PLANE 0.005 - 0.013 (0.13 - 0.33) 0.022 - 0.042 (0.56 - 1.07) 0.009 - 0.013 (0.22 - 0.33) 11 ML4825 PHYSICAL DIMENSIONS inches (millimeters) (Continued) Package: Q20 20-Pin PLCC 0.385 - 0.395 (8.89 - 10.03) 0.350 - 0.356 (8.89 - 9.04) 1 0.042 - 0.056 (1.07 - 1.42) 0.025 - 0.045 (0.63 - 1.14) (RADIUS) 0.042 - 0.048 (1.07 - 1.22) 6 PIN 1 ID 16 0.350 - 0.356 (8.89 - 9.04) 0.385 - 0.395 (8.89 - 10.03) 0.200 BSC (5.08 BSC) 0.290 - 0.330 (7.36 - 8.38) 11 0.050 BSC (1.27 BSC) 0.026 - 0.032 (0.66 - 0.81) 0.165 - 0.180 (4.19 - 4.57) 0.146 - 0.156 (3.71 - 3.96) 0.009 - 0.011 (0.23 - 0.28) 0.100 - 0.110 (2.54 - 2.79) 0.013 - 0.021 (0.33 - 0.53) SEATING PLANE ORDERING INFORMATION PART NUMBER ML4825CP ML4825CS ML4825CQ ML4825IP ML4825IS ML4825IQ TEMPERATURE RANGE 0°C to 70°C 0°C to 70°C 0°C to 70°C –40°C to 85°C –40°C to 85°C –40°C to 85°C PACKAGE 16-Pin PDIP (P16) 16-Pin Wide SOIC (S16W) 20-Pin PLCC (Q20) (End Of Life) 16-Pin PDIP (P16) (End Of Life) 16-Pin Wide SOIC (S16W) (End Of Life) 20-Pin PLCC (Q20) (Obsolete) © Micro Linear 1997 is a registered trademark of Micro Linear Corporation Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending. Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application. 2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295 DS4825-01 9