ML4841CP

May 1997 ML4841* Variable Feedforward PFC/PWM Controller Combo GENERAL DESCRIPTION The ML4841 is a controller for power factor corrected, switched mode power supplies. Power Factor Correction (PFC) allows the use of smaller, lower cost bulk capacitors, reduces power line loading and stress on the switching FETs, and results in a power supply that fully complies with IEC1000-2-3 specifications. The ML4841 includes circuits for the implementation of a leading edge, average current, “boost” type power factor correction, and a trailing edge, pulse width modulator (PWM). The PFC frequency of the ML4841 is automatically set at half that of the PWM frequency generated by the internal oscillator. This technique allows the user to design with smaller output components while maintaining the optimum operating frequency for the PFC. An over-voltage comparator shuts down the PFC section in the event of a sudden decrease in load. The PFC section also includes peak current limiting and input voltage brown-out protection. FEATURES s s s Internally synchronized PFC and PWM in one IC Low total harmonic distortion Reduced ripple current in the storage capacitor between the PFC and PWM sections Average current, continuous mode, boost type, leading edge PFC High efficiency trailing edge PWM can be configured for current mode or voltage mode operation Average line voltage compensation with brown-out control PFC overvoltage comparator eliminates output “runaway” due to load removal Current-fed multiplier for improved noise immunity Overvoltage protection, UVLO, and soft start s s s s s s BLOCK DIAGRAM 16 VEAO VFB 15 2.5V IAC 2 VRMS 4 ISENSE 3 RAMP 1 8 RTCT 7 RAMP 2 9 8V VDC 6 VCC SS 5 8V 50µA 1.25V + + + + - *Some Packages Are End Of Life Or Obsoete 1 IEAO POWER FACTOR CORRECTOR OVP 3.5kΩ + 13 VCCZ 13.5V VCC 7.5V REFERENCE S -1V + - VEA IEA 2.7V + - VREF 14 Q Q PFC OUT Q Q 12 GAIN MODULATOR 3.5kΩ 8V R S R PFC ILIMIT OSCILLATOR ÷2 DUTY CYCLE LIMIT S VFB 2.5V + Q Q PWM OUT 11 VIN OK + R DC ILIMIT 1V - PULSE WIDTH MODULATOR VCCZ UVLO 1 ML4841 PIN CONFIGURATION ML4841 16-Pin PDIP (P16) 16-Pin Wide SOIC (S16W) IEAO 1 IAC 2 ISENSE 3 VRMS 4 SS 5 VDC 6 RT/CT 7 RAMP 1 8 16 VEAO 15 VFB 14 VREF 13 VCC 12 PFC OUT 11 PWM OUT 10 GND 9 RAMP 2 TOP VIEW PIN DESCRIPTION PIN NAME FUNCTION PIN NAME FUNCTION 1 2 3 4 5 6 7 8 IEAO IAC ISENSE VRMS SS VDC RTCT RAMP 1 PFC transconductance current error amplifier output PFC gain control reference input 9 10 11 RAMP 2 GND PWM ramp current sense input Ground PWM OUT PWM driver output PFC OUT VCC VREF VFB VEAO PFC driver output Positive supply (connected to an internal shunt regulator). Buffered output for the internal 7.5V reference PFC transconductance voltage error amplifier input PFC transconductance voltage error amplifier output Current sense input to the PFC current limit comparator Input for PFC RMS line voltage compensation Connection point for the PWM soft start capacitor PWM voltage feedback input Connection for oscillator frequency setting components PFC ramp input 12 13 14 15 16 2 ML4841 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. VCC Shunt Regulator Current .................................. 55mA ISENSE Voltage .................................................... -3V to 5V Voltage on Any Other Pin ...... GND - 0.3V to VCCZ + 0.3V IREF ........................................................................................... 20mA IAC Input Current .................................................... 10mA Peak PFC OUT Current, Source or Sink ................ 500mA Peak PWM OUT Current, Source or Sink .............. 500mA PFC OUT, PWM OUT Energy Per Cycle .................. 1.5mJ Junction Temperature .............................................. 150°C Storage Temperature Range ......................–65°C to 150°C Lead Temperature (Soldering, 10 sec) ..................... 260°C Thermal Resistance (θJA) Plastic DIP ....................................................... 80°C/W Plastic SOIC ................................................... 105°C/W OPERATING CONDITIONS Temperature Range ML4841CX ................................................ 0°C to 70°C ML4841IX ............................................... -40°C to 85°C ELECTRICAL CHARACTERISTICS Unless otherwise specified, ICC = 25mA, RT = 23kΩ, RRAMP1 = 28.7kΩ, CT = 400pF, CRAMP1 = 270pF, TA = Operating Temperature Range (Note 1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VOLTAGE ERROR AMPLIFIER Input Voltage Range Transconductance Feedback Reference Voltage Input Bias Current Output High Voltage Output Low Voltage Source Current Sink Current Open Loop Gain PSRR CURRENT ERROR AMPLIFIER Input Voltage Range Transconductance Input Offset Voltage Input Bias Current Output High Voltage Output Low Voltage Source Current Sink Current Open Loop Gain PSRR VCCZ - 3V < VCC < VCCZ - 0.5V ∆VIN = ± 0.5V, VOUT = 6V ∆VIN = ± 0.5V, VOUT = 1.5V -40 40 60 60 6.0 VNON INV = VINV, VEAO = 3.75V -1.5 130 195 ±3 -0.5 6.7 0.65 -90 90 75 75 1.0 2 310 ± 15 -1.0 V µ VCCZ - 3V < VCC < VCCZ - 0.5V ∆VIN = ± 0.5V, VOUT = 6V ∆VIN = ± 0.5V, VOUT = 1.5V -40 40 60 60 Note 2 6.0 VNON INV = VINV, VEAO = 3.75V 0 40 2.4 70 2.5 -0.5 6.7 0.65 -90 90 75 75 1.0 7 100 2.6 -1.0 V µ V µA V V µA µA dB dB mV µA V V µA µA dB dB Ω Ω 3 ML4841 ELECTRICAL CHARACTERISTICS (Continued) SYMBOL OVP COMPARATOR Threshold Voltage Hysteresis PFC ILIMIT COMPARATOR Threshold Voltage ∆(PFC ILIMIT VTH - Gain Modulator Output) Delay to Output DC ILIMIT COMPARATOR Threshold Voltage Input Bias Current Delay to Output VIN OK COMPARATOR Threshold Voltage Hysteresis GAIN MODULATOR Gain (Note 3) IAC = 100µA, VRMS = VFB = 0V IAC = 50µA, VRMS = 1.2V, VFB = 0V IAC = 50µA, VRMS = 1.8V, VFB = 0V IAC = 100µA, VRMS = 3.3V, VFB = 0V Bandwidth Output Voltage OSCILLATOR Initial Accuracy Voltage Stability Temperature Stability Total Variation Ramp Valley to Peak Voltage Dead Time CT Discharge Current REFERENCE Output Voltage Line Regulation Load Regulation Temperature Stability Total Variation Long Term Stability Line, Load, Temp TJ = 125ºC, 1000 Hours 7.25 5 TA = 25ºC, I(VREF) = 1mA VCCZ - 3V < VCC < VCCZ - 0.5V 1mA < I(VREF) < 20mA 7.4 7.5 2 2 0.4 7.65 25 7.6 10 15 V mV mV % V mV PFC Only VRAMP 2 = 0V, VRAMP 1 = 2.5V 260 4.5 Line, Temp 182 2.5 400 7.5 9.5 TA = 25ºC VCCZ - 3V < VCC < VCCZ - 0.5V 188 200 1 2 218 212 kHz % % kHz V ns mA IAC = 100µA IAC = 250µA, VRMS = 1.15V, VFB = 0V 0.74 0.35 1.15 0.52 0.14 0.50 1.65 0.74 0.20 10 0.82 0.90 0.65 2.15 0.96 0.26 MHz V 2.4 0.8 2.5 1.0 2.6 1.2 V V 0.9 1.0 ± 0.3 150 1.1 ±1 300 V µA ns -0.8 100 -1.0 190 150 300 -1.15 V mV ns 2.6 70 2.7 95 2.8 125 V mV PARAMETER CONDITIONS MIN TYP MAX UNITS 4 ML4841 ELECTRICAL CHARACTERISTICS (Continued) SYMBOL PFC Minimum Duty Cycle Maximum Duty Cycle Output Low Voltage VIEAO > 6.7V VIEAO < 1.2V IOUT = -20mA IOUT = -100mA IOUT = 10mA, VCC = 8V Output High Voltage IOUT = 20mA IOUT = 100mA Rise/Fall Time PWM DC VOL Duty Cycle Range Output Low Voltage IOUT = -20mA IOUT = -100mA IOUT = 10mA, VCC = 8V VOH Output High Voltage IOUT = 20mA IOUT = 100mA Rise/Fall Time SUPPLY VCCZ Shunt Regulator Voltage VCCZ Load Regulation VCCZ Total Variation Start-up Current Operating Current Undervoltage Lockout Threshold Undervoltage Lockout Hysteresis Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. Note 2: Includes all bias currents to other circuits connected to the VFB pin. Note 3: Gain = K x 5.3V; K = (IGAIN MOD – IOFFSET) x IAC x (VEAO – 1.5V)–1. PARAMETER CONDITIONS MIN TYP MAX UNITS 0 90 95 0.4 0.7 0.8 10 9.5 10.5 10 50 0.8 2.0 1.5 % % V V V V V ns CL = 1000pF 0-44 0-47 0.4 0.7 0.8 0-50 0.8 2.0 1.5 % V V V V V ns 10 9.5 10.5 10 50 CL = 1000pF 12.8 25mA < ICC < 55mA Load, Temp VCC = 11.2V, CL = 0 VCC < VCCZ - 0.5V, CL = 0 12.4 13.5 ± 100 14.2 ± 200 14.6 V mV V mA mA V V 0.7 17 1.0 21 VCCZ - 1.0 VCCZ - 0.7 VCCZ - 0.4 2.7 3.0 3.3 5 ML4841 TYPICAL PERFORMANCE CHARACTERISTICS 250 250 200 Transconductance (µ ) Transconductance (µ ) 200 Ω Voltage Error Amplifier (VEA) Transconductance (gm) 400 Variable Gain Block Constant - K VFB 15 2.5V IAC 2 VRMS 4 ISENSE 3 RAMP 1 8 - Ω 150 100 50 0 0 1 2 VFB (V) 3 4 5 300 200 100 0 0 1 2 3 VRMS (mV) 150 100 50 0 -500 0 IEA Input Voltage (mV) 500 Current Error Amplifier (IEA) Transconductance (gm) 4 5 Variable Gain Control Transfer Characteristic 16 VEAO VEA + + 1 IEAO OVP 3.5kΩ + - 13 VCCZ 13.5V VCC 7.5V REFERENCE S -1V + - IEA 2.7V + - VREF 14 Q Q PFC OUT Q Q 12 GAIN MODULATOR 3.5kΩ 8V R S R PFC ILIMIT FROM PWM OSCILLATOR ÷2 VCCZ UVLO Figure 1. PFC Section Block Diagram. 6 ML4841 FUNCTIONAL DESCRIPTION The ML4841 consists of an average current controlled, continuous boost Power Factor Corrector (PFC) front end and a synchronized Pulse Width Modulator (PWM) back end. The PWM section uses current mode control. The PWM stage uses conventional trailing-edge duty cycle modulation, while the PFC uses leading-edge modulation. This patented leading/trailing edge modulation technique results in a higher useable PFC error amplifier bandwidth, and can significantly reduce the size of the PFC DC buss capacitor. The synchronization of the PWM with the PFC simplifies the PWM compensation due to the controlled ripple on the PFC output capacitor (the PWM input capacitor). The PWM section of the ML4841 runs at twice the frequency of the PFC, which allows the use of smaller PWM output magnetics and filter capacitors while holding down the losses in the PFC stage power components. In addition to power factor correction, a number of protection features have been built into the ML4841. These include soft-start, PFC over-voltage protection, peak current limiting, brown-out protection, duty cycle limit, and under-voltage lockout. POWER FACTOR CORRECTION Power factor correction makes a non-linear load look like a resistive load to the AC line. For a resistor, the current drawn from the line is in phase with and proportional to the line voltage, so the power factor is unity (one). A common class of non-linear load is the input of a most power supplies, which use a bridge rectifier and capacitive input filter fed from the line. The peak-charging effect which occurs on the input filter capacitor in such a supply causes brief high-amplitude pulses of current to flow from the power line, rather than a sinusoidal current in phase with the line voltage. Such a supply presents a power factor to the line of less than one (another way to state this is that it causes significant current harmonics to appear at its input). If the input current drawn by such a supply (or any other non-linear load) can be made to follow the input voltage in instantaneous amplitude, it will appear resistive to the AC line and a unity power factor will be achieved. To hold the input current draw of a device drawing power from the AC line in phase with and proportional to the input voltage, a way must be found to prevent that device from loading the line except in proportion to the instantaneous line voltage. The PFC section of the ML4841 uses a boost-mode DC-DC converter to accomplish this. The input to the converter is the full wave rectified AC line voltage. No filtering is applied following the bridge rectifier, so the input voltage to the boost converter ranges, at twice line frequency, from zero volts to the peak value of the AC input and back to zero. By forcing the boost converter to meet two simultaneous conditions, it is possible to ensure that the current which the converter draws from the power line agrees with the instantaneous line voltage. One of these conditions is that the output voltage of the boost converter must be set higher than the peak value of the line voltage. A commonly used value is 385VDC, to allow for a high line of 270VAC. The other condition is that the current which the converter is allowed to draw from the line at any given instant must be proportional to the line voltage. The first of these requirements is satisfied by establishing a suitable voltage control loop for the converter, which in turn drives a current error amplifier and switching output driver. The second requirement is met by using the rectified AC line voltage to modulate the output of the voltage control loop. Such modulation causes the current error amplifier to command a power stage current which varies directly with the input voltage. In order to prevent ripple which will necessarily appear at the output of the boost circuit (typically about 10VAC on a 385V DC level) from introducing distortion back through the voltage error amplifier, the bandwidth of the voltage loop is deliberately kept low. A final refinement is to adjust the overall gain of the PFC such to be proportional to 1/VIN2, which linearizes the transfer function of the system as the AC input voltage varies. Since the boost converter topology in the ML4841 PFC is of the current-averaging type, no slope compensation is required. PFC SECTION Gain Modulator Figure 1 shows a block diagram of the PFC section of the ML4841. The gain modulator is the heart of the PFC, as it is this circuit block which controls the response of the current loop to line voltage waveform and frequency, rms line voltage, and PFC output voltage. There are three inputs to the gain modulator. These are: 1) A current representing the instantaneous input voltage (amplitude and waveshape) to the PFC. The rectified AC input sine wave is converted to a proportional current via a resistor and is then fed into the gain modulator at IAC. Sampling current in this way minimizes ground noise, as is required in high power switching power conversion environments. The gain modulator responds linearly to this current. 2) A voltage proportional to the long-term rms AC line voltage, derived from the rectified line voltage after scaling and filtering. This signal is presented to the gain modulator at VRMS. The gain modulator’s output is inversely proportional to VRMS2 (except at unusually low values of VRMS where special gain contouring takes over to limit power dissipation of the circuit components under heavy brown-out conditions). The relationship between VRMS and gain is designated as K, and is illustrated in the Typical Performance Characteristics. 7 ML4841 FUNCTIONAL DESCRIPTION (Continued) 3) The output of the voltage error amplifier, VEAO. The gain modulator responds linearly to variations in this voltage. The output of the gain modulator is a current signal, in the form of a full wave rectified sinusoid at twice the line frequency. This current is applied to the virtual-ground (negative) input of the current error amplifier. In this way the gain modulator forms the reference for the current error loop, and ultimately controls the instantaneous current draw of the PFC from the power line. The general form for the output of the gain modulator is: I × VEAO IGAINMOD ≅ AC × 1V 2 VRMS VREF PFC OUTPUT VEAO VFB 15 2.5V IAC 2 VRMS 4 ISENSE 3 - 16 IEAO 1 VEA + + IEA + - More exactly, the output current of the gain modulator is given by: IGAINMOD ≅ K × (VEAO − 1.5V) × IAC where K is in units of V-1. Note that the output current of the gain modulator is limited to ≅ 200µA. Current Error Amplifier The current error amplifier’s output controls the PFC duty cycle to keep the current through the boost inductor a linear function of the line voltage. At the inverting input to the current error amplifier, the output current of the gain modulator is summed with a current which results from a negative voltage being impressed upon the ISENSE pin (current into ISENSE ≅ VSENSE/3.5kΩ). The negative voltage on ISENSE represents the sum of all currents flowing in the PFC circuit, and is typically derived from a current sense resistor in series with the negative terminal of the input bridge rectifier. In higher power applications, two current transformers are sometimes used, one to monitor the ID of the boost MOSFET(s) and one to monitor the IF of the boost diode. As stated above, the inverting input of the current error amplifier is a virtual ground. Given this fact, and the arrangement of the duty cycle modulator polarities internal to the PFC, an increase in positive current from the gain modulator will cause the output stage to increase its duty cycle until the voltage on ISENSE is adequately negative to cancel this increased current. Similarly, if the gain modulator’s output decreases, the output duty cycle will decrease, to achieve a less negative voltage on the ISENSE pin. There is a modest degree of gain contouring applied to the transfer characteristic of the current error amplifier, to increase its speed of response to current-loop perturbations. However, the boost inductor will usually be the dominant factor in overall current loop response. Therefore, this contouring is significantly less marked than that of the voltage error amplifier. This is illustrated in the Typical Performance Characteristics. (1) GAIN MODULATOR Figure 2. Compensation Network Connections for the Voltage and Current Error Amplifiers Cycle-By-Cycle Current Limiter The ISENSE pin, as well as being a part of the current feedback loop, is a direct input to the cycle-by-cycle current limiter for the PFC section. Should the input voltage at this pin ever be more negative than -1V, the output of the PFC will be disabled until the protection flip-flop is reset by the clock pulse at the start of the next PFC power cycle. Overvoltage Protection The OVP comparator serves to protect the power circuit from being subjected to excessive voltages if the load should suddenly change. A resistor divider from the high voltage DC output of the PFC is fed to VFB. When the voltage on VFB exceeds 2.7V, the PFC output driver is shut down. The PWM section will continue to operate. The OVP comparator has 125mV of hysteresis, and the PFC will not restart until the voltage at VFB drops below 2.58V. The VFB should be set at a level where the active and passive external power components and the ML4841 are within their safe operating voltages, but not so low as to interfere with the boost voltage regulation loop. Error Amplifier Compensation The PWM loading of the PFC can be modeled as a negative resistor; an increase in input voltage to the PWM causes a decrease in the input current. This response dictates the proper compensation of the two transconductance error amplifiers. Figure 2 shows the types of compensation networks most commonly used for 8 ML4841 FUNCTIONAL DESCRIPTION (Continued) the voltage and current error amplifiers, along with their respective return points. The current loop compensation is returned to VREF to produce a soft-start characteristic on the PFC: as the reference voltage comes up from zero volts, it creates a differentiated voltage on IEAO which prevents the PFC from immediately demanding a full duty cycle on its boost converter. There are two major concerns when compensating the voltage loop error amplifier; stability and transient response. Optimizing interaction between transient response and stability requires that the error amplifier’s open-loop crossover frequency should be 1/2 that of the line frequency, or 23Hz for a 47Hz line (lowest anticipated international power frequency). The gain vs. input voltage of the ML4841’s voltage error amplifier has a specially shaped nonlinearity such that under steady-state operating conditions the transconductance of the error amplifier is at a local minimum. Rapid perturbations in line or load conditions will cause the input to the voltage error amplifier (VFB) to deviate from its 2.5V (nominal) value. If this happens, the transconductance of the voltage error amplifier will increase significantly, as shown in the Typical Performance Characteristics. This increases the gain-bandwidth product of the voltage loop, resulting in a much more rapid voltage loop response to such perturbations than would occur with a conventional linear gain characteristic. The current amplifier compensation is similar to that of the voltage error amplifier with the exception of the choice of crossover frequency. The crossover frequency of the current amplifier should be at least 10 times that of the voltage amplifier, to prevent interaction with the voltage loop. It should also be limited to less than 1/6th that of the switching frequency, e.g. 16.7kHz for a 100kHz switching frequency. For more information on compensating the current and voltage control loops, see Application Notes 33 and 34. Application Note 16 also contains valuable information for the design of this class of PFC. Oscillator (RT/CT) The oscillator frequency is determined by the values of RT and CT, which determine the ramp and off-time of the oscillator output clock: fOSC = tRAMP + tDISCHARGE 1 The discharge time of the oscillator may be determined using: tDISCHARGE = 2.5V × CT = 490 × CT 5.1 mA The deadtime is so small (tRAMP >> tDEADTIME) that the operating frequency can typically be approximated by: fOSC = 1 tRAMP (4) (5) EXAMPLE: For the application circuit shown in the data sheet, with the oscillator running at: fOSC = 200kHz = 1 tRAMP tRAMP = 0.51× R T × CT = 5 × 10−6 Solving for RT x CT yields 1 x 10-5. Selecting standard components values, CT = 390pF, and RT = 24.9kΩ. RAMP 1 The ramp voltage on this pin serves as a reference to which the PFC’s current error amp output is compared in order to set the duty cycle of the PFC switch. The external ramp voltage is derived from a RC network similar to the oscillator’s. The PWM’s oscillator sends a synchronous pulse every other cycle to reset this ramp. The ramp voltage should be limited to no more than the output high voltage (6V) of the current error amplifier. The timing resistor value should be selected such that the capacitor will not charge past this point before being reset. In order to ensure the linearity of the PFC loop’s transfer function and improve noise immunity, the charging resistor should be connected to the 13.5V VCC rather than the 7.5V reference. This will keep the charging voltage across the timing cap in the “linear” region of the charging curve. The component value selection is similar to oscillator RC component selection. fOSC = 1 t CHARGE + tDISCHARGE (6) (2) The ramp-charge time of the oscillator is derived from the following equation: The charge time of Ramp 1 is derived from the following equations:  V − 1.25 tRAMP = CT × R T × In REF   VREF − 3.75 at VREF = 7.5V: (3) t CHARGE = 2 fOSC (7) tRAMP = CT × R T × 0.51  V − Ramp Valley  t CHARGE = CT × R T × In CC   VCC − Ramp Peak  (8) 9 ML4841 FUNCTIONAL DESCRIPTION (Continued) At VCC = 13.5V and assuming Ramp Peak = 5V to allow for component tolerances: t CHARGE = 0.463 × R T × CT PWM Control (RAMP 2) The PWM section utilizes current mode control. RAMP 2 is generally used as the sampling point for a voltage representing the current in the primary of the PWM’s output transformer, derived either by a current sensing resistor or a current transformer. Soft Start Start-up of the PWM is controlled by the selection of the external capacitor at SS. A current source of 50µA supplies the charging current for the capacitor, and start-up of the PWM begins at 1.25V. Start-up delay can be programmed by the following equation: (9) The capacitor value should remain small to keep the discharge energy and the resulting discharge current through the part small. A good value to use is the same value used in the PWM timing circuit (CT). For the application circuit shown in the data sheet, using a 200kHz PWM and 390pF timing cap yields RT: RT = 1× 10−5 = 56.2kΩ (0.463)(390 × 10−12) (10) CSS = tDELAY × 50µA 1.25V (11) PWM SECTION Pulse Width Modulator The PWM section of the ML4841 is straightforward, but there are several points which should be noted. Foremost among these is its inherent synchronization to the PFC section of the device, to which it also provides its basic timing. The PWM operates in current-mode. In applications utilizing current mode control, the PWM ramp (RAMP 2) is usually derived directly from a current sensing resistor or current transformer in the primary of the output stage, and is thereby representative of the current flowing in the converter’s output stage. The DC ILIMIT comparator provides cycle-by-cycle current limiting and is connected to RAMP 2 internally. If the current sense signal exceeds the 1V threshold, the PWM switch is disabled until the protection flip-flop is rest by the clock pulse at the start of the next PWM power cycle. PWM Current Limit The DC ILIMIT comparator is a cycle-by-cycle current limiter for the PWM section. Should the input voltage at this pin ever exceed 1V, the output of the PWM will be disabled until the output flip-flop is reset by the clock pulse at the start of the next PWM power cycle. VIN OK Comparator The VIN OK comparator monitors the DC output of the PFC and inhibits the PWM if this voltage on VFB is less than its nominal 2.5V. Once this voltage reaches 2.5V, which corresponds to the PFC output capacitor being charged to its rated boost voltage, the soft-start commences. where CSS is the required soft start capacitance, and tDELAY is the desired start-up delay. It is important that the time constant of the PWM soft-start allows the PFC time to generate sufficient output power for the PWM section. The PWM start-up delay should be at least 5ms. Solving for the minimum value of CSS: CSS = 5ms × 50µA = 200nF 1.25V VBIAS VCC ML4841 10nF ceramic 1µF ceramic GND Figure 3. External Component Connections to VCC 10 ML4841 FUNCTIONAL DESCRIPTION (Continued) Generating VCC The ML4841 is a current-fed part. It has an internal shunt voltage regulator, which is designed to regulate the voltage internal to the part at 13.5V. This allows a low power dissipation while at the same time delivering 10V of gate drive at the PWM OUT and PFC OUT outputs. It is important to limit the current through the part to avoid overheating or destroying it. This can be easily done with a single resistor in series with the Vcc pin, returned to a bias supply of typically 18V to 20V. The resistor’s value must be chosen to meet the operating current requirement of the ML4841 itself (19mA max) plus the current required by the two gate driver outputs. EXAMPLE: With a VBIAS of 20V, a VCC limit of 14.6V (max) and driving a total gate charge of 100nC at 100kHz (1 IRF840 MOSFET and 2 IRF830 MOSFETs), the gate driver current required is: IGATEDRIVE = 100kHz × 45nC + 200kHz × 52nC = 15mA (12) LEADING/TRAILING MODULATION Conventional Pulse Width Modulation (PWM) techniques employ trailing edge modulation in which the switch will turn on right after the trailing edge of the system clock. The error amplifier output voltage is then compared with the modulating ramp. When the modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned OFF. When the switch is ON, the inductor current will ramp up. The effective duty cycle of the trailing edge modulation is determined during the ON time of the switch. Figure 4 shows a typical trailing edge control scheme. In the case of leading edge modulation, the switch is turned OFF right at the leading edge of the system clock. When the modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned ON. The effective duty-cycle of the leading edge modulation is determined during the OFF time of the switch. Figure 5 shows a leading edge control scheme. One of the advantages of this control technique is that it requires only one system clock. Switch 1 (SW1) turns off and switch 2 (SW2) turns on at the same instant to minimize the momentary “no-load” period, thus lowering ripple voltage generated by the switching action. With such synchronized switching, the ripple voltage of the first stage is reduced. Calculation and evaluation have shown that the 120Hz component of the PFC’s output ripple voltage can be reduced by as much as 30% using this method. ( )( ) RBIAS = 20V − 14.6V = 160Ω 19mA + 15mA (13) To check the maximum dissipation in the ML4841, check the current at the minimum VCC (12.4V): ICC = 20V − 12.4V = 47.5mA 160Ω The maximum allowable ICC is 55mA, so this is an acceptable design. The ML4841 should be locally bypassed with a 10nF and a 1µF ceramic capacitor. In most applications, an electrolytic capacitor of between 100µF and 330µF is also required across the part, both for filtering and as part of the start-up bootstrap circuitry. L1 + I1 VIN SW1 C1 RL SW2 I2 I3 I4 (14) RAMP DC VEAO REF U3 + –EA DFF RAMP VSW1 + – R Q D U2 Q CLK TIME OSC U4 U1 CLK TIME Figure 4. Typical Trailing Edge Control Scheme 11 ML4841 L1 + I1 VIN SW1 C1 RL SW2 I2 I3 I4 DC RAMP REF U3 + EA – VEAO VEAO + – CMP U1 DFF R Q D U2 Q CLK TIME VSW1 RAMP OSC U4 CLK TIME Figure 5. Leading/Trailing Edge Control Scheme 12 ML4841 TYPICAL APPLICATIONS Figure 6 is the application circuit for a complete 100W power factor corrected power supply, designed using the general methods and topology suggested in Application Note 33. AC INPUT 85 TO 265VAC C1 680nF F1 3.15A L1 3.1mH Q1 IRF840 R2A 453kΩ R1A 499kΩ R27 22kΩ R2B 453kΩ R21 22Ω D1 8A, 600V Q2 R17 IRF830 33Ω C25 100nF T1 R30 4.7kΩ R15 3Ω D6 600V R28 160Ω C3 100nF R1B 499kΩ R3 75kΩ 56.2kΩ R12 27kΩ C7 220pF C6 1nF R7B 178kΩ D3 50V R7A 178kΩ R19 220Ω R20 1.1Ω C20 1µF D5 600V D7 15V T2 L2 D11 MBR2545CT 33µH C24 1µF 12VDC C4 10nF C5 100µF BR1 4A, 600V C21 1800µF RTN R24 1.2kΩ C30 330µF C12 10µF R14 33Ω Q3 IRF830 C22 4.7µF R23 1.5kΩ R18 220Ω R22 8.66kΩ D12 1A, 50V D13 1A, 50V R26 10kΩ C23 100nF R25 2.26kΩ C2 470nF R4 13kΩ TL431 IEAO IAC ISENSE R5 300mΩ 1W VEAO VFB VREF VCC PFC OUT PWM OUT GND D8 1A, 20V D10 1A, 20V C15 10nF C16 1µF C13 100nF C14 1µF R8 2.37kΩ C31 1nF R11 750kΩ C8 82nF C9 8.2nF VRMS C19 1µF SS VDC RAMP 1 RAMP 2 DC ILIMIT 390pF ML4841 C18 390pF R6 24.9kΩ R10 6.2kΩ C17 220pF C11 10nF Figure 6. 100W Power Factor Corrected Power Supply. 13 ML4841 PHYSICAL DIMENSIONS inches (millimeters) Package: P16 16-Pin PDIP 0.740 - 0.760 (18.79 - 19.31) 16 PIN 1 ID 0.240 - 0.260 0.295 - 0.325 (6.09 - 6.61) (7.49 - 8.26) 0.02 MIN (0.50 MIN) (4 PLACES) 1 0.055 - 0.065 (1.40 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN) 0.170 MAX (4.32 MAX) 0.125 MIN (3.18 MIN) 0.016 - 0.022 (0.40 - 0.56) SEATING PLANE 0º - 15º 0.008 - 0.012 (0.20 - 0.31) Package: S16W 16-Pin Wide SOIC 0.400 - 0.414 (10.16 - 10.52) 16 0.291 - 0.301 0.398 - 0.412 (7.39 - 7.65) (10.11 - 10.47) PIN 1 ID 1 0.024 - 0.034 (0.61 - 0.86) (4 PLACES) 0.050 BSC (1.27 BSC) 0.095 - 0.107 (2.41 - 2.72) 0º - 8º 0.090 - 0.094 (2.28 - 2.39) 0.012 - 0.020 (0.30 - 0.51) SEATING PLANE 0.005 - 0.013 (0.13 - 0.33) 0.022 - 0.042 (0.56 - 1.07) 0.009 - 0.013 (0.22 - 0.33) 15 ML4841 ORDERING INFORMATION PART NUMBER ML4841CP ML4841CS ML4841IP ML4841IS TEMPERATURE RANGE 0°C to 70°C 0°C to 70°C -40°C to 85°C -40°C to 85°C PACKAGE 16-Pin Plastic DIP (P16) 16-Pin Wide SOIC (S16W) (EOL) 16-Pin Plastic DIP (P16) (OBS) 16-Pin Wide SOIC (S16W) (EOL) © Micro Linear 1997 is a registered trademark of Micro Linear Corporation. Products described herein may be covered by one or more of the following patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565761; 5,592,128; 5,594,376. Other patents are pending Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application. 2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295 DS4841-01 15