ML6694CH

May 1997 ML6694* 100BASE-TX Physical Layer with 5-Bit Interface GENERAL DESCRIPTION The ML6694 is a high-speed physical layer transceiver that provides a 5-bit (or symbol) interface to unshielded twisted pair cable media. The ML6694 is well suited for repeater applications using repeater controllers with the 5-bit interface. The ML6694 may also be used in FDDIover-copper applications. The ML6694 integrates 125MHz clock recovery/ generation, receive adaptive equalization, baseline wander correction and MLT-3/10BASE-T transmitter. FEATURES s s s s s s s s 5-bit (or symbol) parallel interface Compliant to IEEE 802.3u 100BASE-TX standard Compliant to ANSI X3T12 TP-PMD (FDDI) standard Single-jack 10BASE-T/100BASE-TX solution when used with external 10Mbps PHY 125MHz receive clock recovery/generation Baseline wander correction Adaptive equalization and MLT-3 encoding/decoding Supports full-duplex operation BLOCK DIAGRAM (PLCC Pin Configuration) * Some Packages Are End Of Life As Of August 1, 2000 41 40 10BTTXINP 44 TXC CLOCK SYTHESIZER 10BTTXINN TPOUTP 2 3 4 5 6 TSM4 TSM3 TSM2 TSM1 TSM0 CLOCK AND DATA RECOVERY TPINP EQUALIZER BLW CORRECTION MLT-3 DECODER LOOPBACK MUX DESERIALIZER RSM2 RSM1 RSM0 CONTROL LOGIC CMREF RGMSET SDO TPINN SERIALIZER NRZ TO NRZI AND NRZI TO MLT-3 ENCODER 100BASE-TX/10BASE-T TWISTED PAIR DRIVER TPOUTN RTSET 34 33 31 38 37 39 30 24 16 8 9 11 13 15 RXC RSM4 RSM3 NRZI TO NRZ DECODER SEL10/100 25 42 PWRDN 7 LPBK 1 ML6694 PIN CONFIGURATION ML6694 44-Pin PLCC (Q44) 10BTTXINN 40 39 38 37 36 35 34 33 32 31 30 29 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 PWRDN RSM4 RSM3 DGND1 RSM2 DVCC1 RSM1 DGND2 RSM0 RXC DGND3 7 8 9 10 11 12 13 14 15 16 17 18 10BTTXINP 41 AGND1 AVCC1 TSM0 TSM1 TSM2 TSM3 TSM4 LPBK TXC CMREF TPINP TPINN AVCC2 AGND2 TPOUTP TPOUTN AGND3 RTSET RGMSET NC DGND4A DGND4B DGND4C DGND5 DVCC5 SDO SEL10/100 NC DVCC2 NC 35 ML6694 44-Pin TQFP (H44-10) 10BTTXINN 34 33 32 31 30 29 28 27 26 25 24 23 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 PWRDN RSM4 RSM3 DGND1 RSM2 DVCC1 RSM1 DGND2 RSM0 RXC DGND3 1 2 3 4 5 6 7 8 9 10 11 12 10BTTXINP AGND1 AVCC1 TSM0 TSM1 TSM2 TSM3 TSM4 LPBK TXC AVCC3 CMREF TPINP TPINN AVCC2 AGND2 TPOUTP TPOUTN AGND3 RTSET RGMSET NC DVCC2 DGND4A DGND4B DGND4C DVCC5 DGND5 SDO SEL10/100 NC NC 2 AVCC3 ML6694 PIN DESCRIPTION (Pin numbers for TQFP package in parentheses) PIN NAME DESCRIPTION 1 2-6 7 (39) (40-44) (1) AGND1 TSM PWRDN RSM Analog ground. Transmit data TTL inputs. TSM inputs accept TX data symbols. Data appearing at TSM are clocked into the ML6694 on the rising edge of TXC. Device power down input. A low signal powers down all ciruits of the ML6694, and dissipates less than 20mA. Receive data TTL outputs. RSM outputs may be sampled synchronously with RXC’s rising edge. 8,9, (2, 3, 11,13, 5, 7, 9) 15 10 12 14 16 (4) (6) (8) (10) DGND1 DVCC1 DGND2 RXC Digital ground. Digital +5V power supply. Digital ground. Recovered receive symbol clock TTL output. This 25MHz clock is phase-aligned with the internal 125MHz bit clock recovered from the signal received at TPINP/N when data is present. Receive data at RSM change on the falling edges and should be sampled on the rising edges of this clock. RXC is phase aligned to TXC when 100BASE-TX signal is not present at TPINP/N Digital ground. Digital +5V power supply. Digital ground. Digital ground. Digital ground. Digital +5V power supply. Digital ground. Signal detect TTL output. A high output level indicates 100BASE-TX activity at TPINP/N with an amplitude exceeding the preset threshold. The signal detect function is active only in 100Mbps mode, that is when the pin SEL10/100 is low. Speed select TTL input. Driving this pin high disables 100BASE-TX transmit and receive functions, and enables the 10BASE-T transmit path from 10BTTXINP/N to TPOUTP/N. A low signal on SEL10/100 disables the 10BTTXINP/N inputs and enables 100BASE-TX operation. Analog positive power supply. Equalizer bias resistor input. An external 9.53kΩ, 1% resistor connected between RGMSET and AGND3 sets internal time constants controlling the receive equalizer transfer function. Transmit level bias resistor input. An external 2.49kΩ, 1% resistor connected between RTSET and AGND3 sets a precision constant bias current for the twisted pair transmit level. Analog ground. Transmit twisted pair outputs. This differential current output pair drives MLT-3 waveforms into the network coupling transformer in 100BASE-TX mode, and 10BASE-T or FLP waveforms in 10BASE-T mode. Analog ground. Analog +5V power supply. Receive twisted pair inputs. This differential input pair receives 100BASE-TX signals from the network. 17 18 19 20 21 22 23 24 (11) (12) (13) (14) (15) (16) (17) (18) DGND3 DVCC2 DGND4A DGND4B DGND4C DVCC5 DGND5 SD0 25 (19) SEL10/100 28 30 (22) (24) AVCC3 RGMSET 31 (25) RTSET 32 (26) AGND3 TPOUTN/P 33,34 (27,28) 35 36 (29) (30) AGND2 AVCC2 TPINN/P 37,38 (31, 32) 3 ML6694 PIN DESCRIPTION (Continued) PIN NAME DESCRIPTION 39 (33) CMREF Receiver common-mode reference output. This pin provides a common-mode bias point for the twisted-pair media line receiver. A typical value for CMREF is (VCC–1.26)V. 40,41 (34,35) 10BTTXINN/P 10BASE-T transmit waveform inputs. The ML6694 presents a linear copy of the input at 10BTTXINN/P to the TPOUTN/P outputs when the ML6694 functions in 10BASE-T mode. Signals presented to these pins must be centered at VCC/2 with a single ended amplitude of ± 0.25V. LPBK Loopback TTL input pin. Tying this pin to ground places the part in loopback mode; data at RSM are serialized, MLT-3 encoded, equalized then sent to the receive PLL for clock recovery and sent to the RSM outputs. Floating this pin or tying it to VCC places the part in its normal mode of operation. Analog +5V power supply. Transmit clock TTL input. This 25MHz clock is the frequency reference for the internal transmit PLL clock multiplier. This pin should be driven by an external 25MHz clock at TTL or CMOS levels. 42 (36) 43 44 (37) (38) AVCC1 TXC 4 ML6694 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. VCC Supply Voltage Range .................... GND –0.3V to 6V Input Voltage Range Digital Inputs ....................... GND –0.3V to VCC + 0.3V TPINP, TPINN, 10BTTXINN, 10BTTXINP ...................... GND –0.3V to VCC + 0.3V Output Current TPOUTP, TPOUTN .............................................. 60mA All other outputs .................................................. 10mA Junction Temperature .............................................. 150 °C Storage Temperature ................................ –65°C to 150°C Lead Temperature (Soldering, 10 sec) ...................... 260 °C OPERATING CONDITIONS VCC Supply Voltage ............................................. 5V ± 5% All VCC supply pins must be within 0.1V of each other. All GND pins must be within 0.1V of each other. TA, Ambient temperature ................................ 0°C to 70 °C RGMSET ...................................................... 9.53kΩ ± 1% RTSET .......................................................... 2.49kΩ ± 1% Receive transformer insertion loss ........................