ML6697

July 1997 PRELIMINARY ML6697 100BASE-TX Physical Layer with MII GENERAL DESCRIPTION The ML6697 implements the complete physical layer of the Fast Ethernet 100BASE-TX standard. The ML6697 offers a single-chip per-port solution for MII-based repeater applications. The ML6697 interfaces to the controller through the Media Independent Interface (MII). The ML6697 functionality includes 4B/5B encoding/ decoding, Stream Cipher scrambling/descrambling, 125MHz clock recovery/generation, receive adaptive equalization, baseline wander correction, and MLT-3 transmitter. FEATURES n Single-chip 100BASE-TX physical layer n Compliant to IEEE 802.3u 100BASE-TX standard n Supports MII-based repeater applications n Compliant MII (Media Indendent Interface) n 4B/5B encoder/decoder n Stream Cipher scrambler/descrambler n 125MHz clock recovery/generation n Baseline wander correction n Adaptive equalization and MLT-3 encoding/decoding BLOCK DIAGRAM (PLCC Package) 1 9 TXCLKIN TXCLK CLOCK SYNTHESIZER 3 4 5 6 7 8 TXD3 TXD2 TXD1 TXD0 TXEN TXER CRS RXEN RXCLK RXD3 RXD2 RXD1 RXD0 RXDV RXER PCS TRANSMIT STATE MACHINE 4B/5B ENCODER SCRAMBLER NRZ TO NRZI ENCODER SERIALIZER MLT-3 ENCODER FLP/100BASE-TX TWISTED PAIR DRIVER TPOUTP TPOUTN RTSET 40 39 37 18 19 17 10 12 14 16 21 23 CLOCK AND DATA RECOVERY NRZI TO NRZ DECODER PCS RECEIVE STATE MACHINE 5B/4B DECODER DESCRAMBLER MII MANAGEMENT REGISTERS AND CONTROL LOGIC DESERIALIZER EQUALIZER BLW CORRECTION MLT-3 DECODER LOOPBACK MUX TPINP TPINN CMREF RGMSET LINK100 45 44 46 36 43 PHYAD0 PHYAD1 PHYAD2 PHYAD3 32 24 25 29 30 31 PHYAD4 33 MDIO MDC 1 ML6697 PIN CONFIGURATION ML6697 52-Pin PLCC (Q52) TXCLKIN AGND1 AVCC1 TXD0 TXD1 TXD2 TXD3 TXEN NC NC NC NC 7 TXER TXCLK RXD3 DGND1 RXD2 DVCC1 RXD1 DGND2 RXD0 RXCLK CRS RXEN DGND3 8 9 10 11 12 13 14 15 16 17 18 19 20 21 RXDV 6 5 4 3 2 1 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 CMREF TPINP TPINN LINK100 AVCC2 AGND2 TPOUTP TPOUTN AGND3 RTSET RGMSET AVCC3B AVCC3A 22 23 DVCC2 RXER 24 MDC 25 MDIO 26 DGND4 27 DVCC5 28 DGND5 29 PHYAD0 30 PHYAD1 31 PHYAD2 32 PHYAD3 33 PHYAD4 2 NC ML6697 PIN CONFIGURATION (Continued) ML6697 64-Pin TQFP (H64-10) AGND1A AGND1B TXCLKIN AVCC1 TXD0 TXD1 TXD2 TXD3 TXEN TXER NC NC NC NC NC 50 64 TXCLK RXD3 DGND1A DGND1B RXD2 DVCC1A DVCC1B RXD1 DGND2A DGND2B RXD0 RXCLK CRS RXEN DGND3A DGND3B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 63 62 61 60 59 58 57 56 55 54 53 52 51 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 NC CMREF TPINP TPINN LINK100 AVCC2 AGND2A AGND2B TPOUTP TPOUTN AGND3A AGND3B RTSET RGMSET AVCC3B AVCC3A 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RXDV DVCC2 RXER MDC DGND4B DVCC5A DVCC5B DGND5B PHYAD0 PHYAD1 PHYAD2 PHYAD3 DGND4A DGND5A PHYAD4 MDIO NC 3 ML6697 PIN DESCRIPTION (Pin numbers for TQFP package in parentheses) PIN NAME DESCRIPTION 1 (56) TXCLKIN Transmit clock TTL input. This 25MHz clock is the frequency reference for the internal transmit PLL clock multiplier. This pin should be driven by an external 25MHz clock at TTL or CMOS levels. Analog ground. Transmit data TTL inputs. TXD inputs accept TX data from the MII. Data appearing at TXD are clocked into the ML6697 on the rising edge of TXCLK. Transmit enable TTL input. Driving this input high indicates to the ML6697 that transmit data are present at TXD. TXEN edges should be synchronous with TXCLK. Transmit error TTL input. Driving this pin high with TXEN also high causes the part to continuously transmit scrambled H symbols. When TXEN is low, TXER has no effect. Transmit clock TTL output. This 25MHz clock is phase-aligned with the internal 125MHz TX bit clock. Data appearing at TXD are clocked into the ML6697 on the rising edge of this clock. Receive data TTL outputs. RXD outputs are valid on RXCLK’s rising edge. Digital ground. Digital +5V power supply. Digital ground. Recovered receive clock TTL output. This 25MHz clock is phase-aligned with the internal 125MHz bit clock recovered from the signal received at TPINP/N. Receive data at RXD changes on the falling edges and should be sampled on the rising edges of this clock. RXCLK is phase aligned to TXCLKIN when the 100BASE-TX signal is not present at TPINP/N. Carrier Sense TTL output. CRS goes high in the presence of non-idle signals at TPINP/ N. CRS goes low when receive is idle. Receive enable TTL input. When this input is high, all the MII TTL outputs are enabled. When this input is low, all the MII TTL outputs are in high impedance mode. This input does not affect MDIO, TXCLK and CRS. Digital ground. Receive data valid TTL output. This output goes high when the ML6697 is receiving a data packet. RXDV should be sampled synchronously with RXCLK’s rising edge. Digital +5V power supply. Receive error TTL output. This output goes high to indicate error or invalid symbols within a packet, or corrupted idle between packets. RXER should be sampled synchronously with RXCLK’s rising edge. MII Management Interface clock TTL input. A clock at this pin clocks serial data into or out of the ML6697’s MII management registers through the MDIO pin. The maximum clock frequency at MDC is 2.5MHz. 2 3, 4 5, 6 7 (58, 57) (59,60, 61,62) (63) AGND1 TXD TXEN 8 (64) TXER 9 (1) TXCLK 10, 12, (2, 5, 14, 16 8, 11) 11 13 15 17 (3, 4) (6, 7) (9, 10) (12) RXD DGND1 DVCC1 DGND2 RXCLK 18 19 (13) (14) CRS RXEN 20 21 22 23 (15, 16) (17) (18) (19) DGND3 RXDV DVCC2 RXER 24 (20) MDC 4 ML6697 PIN DESCRIPTION (Continued) PIN NAME DESCRIPTION 25 (21) MDIO MII Management Interface data TTL input/output. Serial data are written to and read from the ML6697’s management registers through this I/O pin. Input data is sampled on the rising edge of MDC. Data output should be sampled synchronously with MDC's rising edge. Digital ground. Digital +5V power supply. Digital ground. MII Serial Management Interface address bit 0. MII Serial Management Interface address bit 1. MII Serial Management Interface address bit 2. MII Serial Management Interface address bit 3. MII Serial Management Interface address bit 4. Analog +5V power supply. Analog +5V power supply. Equalizer bias resistor input. An external 9.53kW, 1% resistor connected between RGMSET and AGND3 sets internal time constants controlling the receive equalizer transfer function. Transmit level bias resistor input. An external 2.49kW, 1% resistor connected between RTSET and AGND3 sets a precision constant bias current for the twisted pair transmit level. Analog ground. Transmit twisted pair outputs. This differential current output pair drives MLT-3 waveforms into the network coupling transformer. Analog ground. Analog +5V power supply. 100BASE-TX link activity open-drain output. LINK100 pulls low when there is 100BASE-TX activity at TPINP/N in 100BASE-TX or auto-negotiation modes. This output is capable of driving an LED directly. Receive twisted pair inputs. This differential input pair receives 100BASE-TX signals from the network. Receiver common-mode reference output. This pin provides a common-mode bias point for the twisted-pair media line receiver, typically (VCC – 1.26)V. Analog +5V power supply. 26 27 28 29 30 31 32 33 34 35 36 (22, 23) (24, 25) (26, 27) (28) (29) (30) (31) (32) (33) (34) (35) DGND4 DVCC5 DGND5 PHYAD0 PHYAD1 PHYAD2 PHYAD3 PHYAD4 AVCC3A AVCC3B RGMSET 37 (36) RTSET 38 (37, 38) AGND3 TPOUTN/P AGND2 AVCC2 LINK100 39, 40 (39, 40) 41 42 43 (41, 42) (43) (44) 44, 45 (45, 46) 46 52 (47) (55) TPINN/P CMREF AVCC1 5 ML6697 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. VCC Supply Voltage Range .................. GND –0.3V to 6V Input Voltage Range Digital Inputs ...................... GND –0.3V to VCC +0.3V TPINP, TPINN, .................... GND –0.3V to VCC +0.3V Output Current TPOUTP, TPOUTN ............................................. 60mA All other outputs ................................................. 10mA Junction Temperature ............................................. 150°C Storage Temperature ..............................–65°C to +150°C Lead Temperature (Soldering, 10 sec) .................... 260°C Thermal Resistance (qJA) PLCC ............................................................... 40°C/W TQFP ............................................................... 52°C/W OPERATING CONDITIONS VCC Supply Voltage ........................................... 5V ± 5% All VCC supply pins must be within 0.1V of each other. All GND pins must be within 0.1V of each other. TA, Ambient temperature .............................. 0°C to 70°C RGMSET .................................................... 9.53kW ± 1% RTSET ........................................................ 2.49kW ± 1% Receive transformer insertion loss ......................