11AA010/11LC010 11AA020/11LC020 11AA040/11LC040
11AA080/11LC080 11AA160/11LC160 11AA161/11LC161
1K-16K UNI/O® Serial EEPROM Family Data Sheet
Features:
• Single I/O, UNI/O® Serial Interface Bus • Low-Power CMOS Technology: - 1 mA active current, typical - 1 µA standby current (max.) (I-temp) • 128 x 8 through 2,048 x 8 Bit Organizations • Schmitt Trigger Inputs for Noise Suppression • Output Slope Control to Eliminate Ground Bounce • 100 kbps Max. Bit Rate – Equivalent to 100 kHz Clock Frequency • Self-Timed Write Cycle (including Auto-Erase) • Page-Write Buffer for up to 16 Bytes • STATUS Register for Added Control: - Write enable latch bit - Write-In-Progress bit • Block Write Protection: - Protect none, 1/4, 1/2 or all of array • Built-in Write Protection: - Power-on/off data protection circuitry - Write enable latch • High Reliability: - Endurance: 1,000,000 erase/write cycles - Data retention: > 200 years - ESD protection: > 4,000V • 3-lead SOT-23 and TO-92 Packages • 4-lead Chip Scale Package • 8-lead PDIP, SOIC, MSOP, TDFN Packages • Pb-Free and RoHS Compliant • Available Temperature Ranges: - Industrial (I): -40°C to +85°C - Automotive (E): -40°C to +125°C
Description:
The Microchip Technology Inc. 11AAXXX/11LCXXX (11XX*) devices are a family of 1 Kbit through 16 Kbit Serial Electrically Erasable PROMs. The devices are organized in blocks of x8-bit memory and support the patented** single I/O UNI/O® serial bus. By using Manchester encoding techniques, the clock and data are combined into a single, serial bit stream (SCIO), where the clock signal is extracted by the receiver to correctly decode the timing and value of each bit. Low-voltage design permits operation down to 1.8V (for 11AAXXX devices), with standby and active currents of only 1 uA and 1 mA, respectively. The 11XX family is available in standard packages including 8-lead PDIP and SOIC, and advanced packaging including 3-lead SOT-23, 3-lead TO-92, 4-lead Chip Scale, 8-lead TDFN, and 8-lead MSOP.
Package Types (not to scale)
MSOP (MS) NC NC NC VSS
1 2 3 4 8 7 6 5
PDIP/SOIC (P, SN) VCC NC NC SCIO NC NC NC Vss
1 2 3 4
VCC NC 6 NC 5 SCIO
8 7
TDFN (MN) NC 1 NC 2 NC 3 VSS 4
8 7 6 5
SOT23 (TT) VCC NC NC SCIO VSS 3 1 SCIO 2 VCC
Pin Function Table
Name SCIO VSS VCC Ground Supply Voltage Function Serial Clock, Data Input/Output
TO-92 (TO)
CS (Chip Scale)(1) VCC 1 2 VSS
SCIO 3 Vss SCIO Note 1: Vcc
4 NC
(Top down view, balls not visible)
Available in I-temp, “AA” only.
* 11XX is used in this document as a generic part number for the 11 series devices. ** Microchip’s UNI/O® Bus products are covered by the following patent issued in the U.S.A.: 7,376,020.
2010 Microchip Technology Inc.
Preliminary
DS22067H-page 1
11AAXXX/11LCXXX
DEVICE SELECTION TABLE
Part Number 11LC010 11AA010 11LC020 11AA020 11LC040 11AA040 11LC080 11AA080 11LC160 11AA160 11LC161 11AA161 Density Organization VCC Range (bits) 1K 1K 2K 2K 4K 4K 8K 8K 16K 16K 16K 16K 128 x 8 128 x 8 256 x 8 256 x 8 512 x 8 512 x 8 1,024 x 8 1,024 x 8 2,048 x 8 2,048 x 8 2,048 x 8 2,048 x 8 2.5-5.5V 1.8-5.5V 2.5-5.5V 1.8-5.5V 2.5-5.5V 1.8-5.5V 2.5-5.5V 1.8-5.5V 2.5-5.5V 1.8-5.5V 2.5-5.5V 1.8-5.5V Page Size (Bytes) 16 16 16 16 16 16 16 16 16 16 16 16 Temp. Ranges I,E I I,E I I,E I I,E I I,E I I, E I Device Address 0xA0 0xA0 0xA0 0xA0 0xA0 0xA0 0xA0 0xA0 0xA0 0xA0 0xA1 0xA1 Packages
P, SN, MS, MN, TO, TT P, SN, MS, MN, TO, TT, CS P, SN, MS, MN, TO, TT P, SN, MS, MN, TO, TT, CS P, SN, MS, MN, TO, TT P, SN, MS, MN, TO, TT, CS P, SN, MS, MN, TO, TT P, SN, MS, MN, TO, TT, CS P, SN, MS, MN, TO, TT P, SN, MS, MN, TO, TT,CS P, SN, MS, MN, TO, TT P, SN, MS, MN, TO, TT, CS
DS22067H-page 2
Preliminary
2010 Microchip Technology Inc.
11AAXXX/11LCXXX
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
VCC.............................................................................................................................................................................6.5V SCIO w.r.t. VSS .....................................................................................................................................-0.6V to VCC+1.0V Storage temperature ................................................................................................................................. -65°C to 150°C Ambient temperature under bias............................................................................................................... -40°C to 125°C ESD protection on all pins.......................................................................................................................................... 4 kV † NOTICE: Stresses above those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Electrical Characteristics: Industrial (I): VCC = 2.5V to 5.5V VCC = 1.8V to 2.5V Automotive (E): VCC = 2.5V to 5.5V Min. 0.7*VCC -0.3 -0.3 0.05*Vcc VCC -0.5 VCC -0.5 — — — — — — Max. VCC+1 0.3*VCC 0.2*VCC — — — 0.4 0.4 ±4 ±3 ±1 7 Units V V V V V V V V mA mA A pF VCC2.5V VCC < 2.5V VCC2.5V (Note 1) IOH = -300 A, VCC = 5.5V IOH = -200 A, Vcc = 2.5V IOI = 300 A, VCC = 5.5V IOI = 200 A, Vcc = 2.5V VCC = 5.5V (Note 1) Vcc = 2.5V (Note 1) VIN = VSS or VCC TA = 25°C, FCLK = 1 MHz, VCC = 5.0V (Note 1) VCC=5.5V; FBUS=100 kHz, CB=100 pF VCC=2.5V; FBUS=100 kHz, CB=100 pF VCC = 5.5V VCC = 2.5V VCC = 5.5V TA = 125°C VCC = 5.5V TA = 85°C VCC = 5.5V TA = -40°C to +85°C TA = -20°C to +85°C TA = -40°C to +125°C Test Conditions
DC CHARACTERISTICS Param. No. D1 D2 D3 D4 D5 D6 D7 D8
Sym. VIH VIL VHYS VOH VOL IO ILI CINT
Characteristic High-level input voltage Low-level input voltage Hysteresis of Schmitt Trigger inputs (SCIO) High-level output voltage Low-level output voltage Output current limit (Note 2) Input leakage current (SCIO) Internal Capacitance (all inputs and outputs)
D9 D10 D11
ICC Read Read Operating Current ICC Write Write Operating Current Iccs Standby Current
— — — — — —
3 1 5 3 5 1 50
mA mA mA mA A A A
D12 Note 1: 2:
ICCI
Idle Mode Current
—
This parameter is periodically sampled and not 100% tested. The SCIO output driver impedance will vary to ensure IO is not exceeded.
2010 Microchip Technology Inc.
Preliminary
DS22067H-page 3
11AAXXX/11LCXXX
TABLE 1-2: AC CHARACTERISTICS
Electrical Characteristics: Industrial (I): VCC = 2.5V to 5.5V VCC = 1.8V to 2.5V Automotive (E): VCC = 2.5V to 5.5V Min. 10 10 — — — — — — 600 10 5 — — — 1M Max. 100 100 ±0.08 ±0.75 ±5 ±0.25 100 100 — — — 50 5 10 — Units kHz µs UI — — (Note 3) TA = -40°C to +85°C TA = -20°C to +85°C TA = -40°C to +125°C Test Conditions
AC CHARACTERISTICS Param. No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Sym. FBUS TE TIJIT
Characteristic Serial bus frequency Bit period Input edge jitter tolerance
FDRIFT Serial bus frequency drift rate tolerance FDEV TOJIT TR TF Serial bus frequency drift limit Output edge jitter SCIO input rise time (Note 1) SCIO input fall time (Note 1) Start header setup time Start header low pulse time Input filter spike suppression (SCIO) Write cycle time (byte or page) Endurance (per page)
% per byte — % per command UI ns ns µs µs µs ns ms ms cycles — (Note 3) — — — — — (Note 1) Write, WRSR commands ERAL, SETAL commands 25°C, VCC = 5.5V (Note 2)
TSTBY Standby pulse time TSS THDR TSP TWC —
Note 1: This parameter is periodically sampled and not 100% tested. 2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained on Microchip’s web site: www.microchip.com. 3: A Unit Interval (UI) is equal to 1-bit period (TE) at the current bus frequency.
TABLE 1-3:
AC Waveform: VLO = 0.2V
AC TEST CONDITIONS
VHI = VCC - 0.2V CL = 100 pF Timing Measurement Reference Level Input Output 0.5 VCC 0.5 VCC
DS22067H-page 4
Preliminary
2010 Microchip Technology Inc.
11AAXXX/11LCXXX
FIGURE 1-1:
10
BUS TIMING – START HEADER
11 2
SCIO
Data ‘0’ Data ‘1’ Data ‘0’ Data ‘1’ Data ‘0’ Data ‘1’ Data ‘0’ Data ‘1’ MAK bit NoSAK bit
FIGURE 1-2:
BUS TIMING – DATA
2 7 12 8
SCIO
Data ‘0’
Data ‘1’
Data ‘1’
Data ‘0’
FIGURE 1-3:
BUS TIMING – STANDBY PULSE
9
SCIO Standby Mode
FIGURE 1-4:
BUS TIMING – JITTER
2 3 2 3 6 6 6 6
Ideal Edge from Master
Ideal Edge from Master
Ideal Edge from Slave
Ideal Edge from Slave
2010 Microchip Technology Inc.
Preliminary
DS22067H-page 5
11AAXXX/11LCXXX
2.0
2.1
FUNCTIONAL DESCRIPTION
Principles of Operation
The 11XX family of serial EEPROMs support the UNI/O® protocol. They can be interfaced with microcontrollers, including Microchip’s PIC® microcontrollers, ASICs, or any other device with an available discrete I/O line that can be configured properly to match the UNI/O protocol. The 11XX devices contain an 8-bit instruction register. The devices are accessed via the SCIO pin. Table 4-1 contains a list of the possible instruction bytes and format for device operation. All instructions, addresses, and data are transferred MSb first, LSb last. Data is embedded into the I/O stream through Manchester encoding. The bus is controlled by a master device which determines the clock period, controls the bus access and initiates all operations, while the 11XX works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is active.
FIGURE 2-1:
STATUS Register
BLOCK DIAGRAM
HV Generator
EEPROM I/O Control Logic Memory Control Logic X Dec Page Latches CurrentLimited Slope Control SCIO Sense Amp. R/W Control Array
Y Decoder
Vcc Vss
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Preliminary
2010 Microchip Technology Inc.
11AAXXX/11LCXXX
3.0
3.1
BUS CHARACTERISTICS
Standby Pulse
When the master has control of SCIO, a standby pulse can be generated by holding SCIO high for TSTBY. At this time, the 11XX will reset and return to Standby mode. Subsequently, a high-to-low transition on SCIO (the first low pulse of the header) will return the device to the active state. Once a command is terminated satisfactorily (i.e., via a NoMAK/SAK combination during the Acknowledge sequence), performing a standby pulse is not required to begin a new command as long as the device to be selected is the same device selected during the previous command. However, a period of TSS must be observed after the end of the command and before the beginning of the start header. After TSS, the start header (including THDR low pulse) can be transmitted in order to begin the new command.
If a command is terminated in any manner other than a NoMAK/SAK combination, then the master must perform a standby pulse before beginning a new command, regardless of which device is to be selected. Note: After a POR/BOR event occurs, a lowto-high transition on SCIO must be generated before proceeding with communication, including a standby pulse. An example of two consecutive commands is shown in Figure 3-1. Note that the device address is the same for both commands, indicating that the same device is being selected both times. A standby pulse cannot be generated while the slave has control of SCIO. In this situation, the master must wait for the slave to finish transmitting and to release SCIO before the pulse can be generated. If, at any point during a command, an error is detected by the master, a standby pulse should be generated and the command should be performed again.
FIGURE 3-1:
CONSECUTIVE COMMANDS EXAMPLE
MAK NoSAK Standby Pulse(1) Start Header Device Address MAK SAK
MAK NoSAK DS22067H-page 7
SCIO 01010101 NoMAK SAK TSS MAK NoSAK 10100000 MAK SAK
Data ‘1’
Start Header
Device Address
SCIO 01010101 10100000
Note 1: After a POR/BOR event, a low-to-high transition on SCIO is required to occur before the first standby pulse.
3.2
Start Data Transfer
All operations must be preceded by a start header. The start header consists of holding SCIO low for a period of THDR, followed by transmitting an 8-bit ‘01010101’ code. This code is used to synchronize the slave’s internal clock period with the master’s clock period, so accurate timing is very important.
When a standby pulse is not required (i.e., between successive commands to the same device), a period of TSS must be observed after the end of the command and before the beginning of the start header. Figure 3-2 shows the waveform for the start header, including the required Acknowledge sequence at the end of the byte.
FIGURE 3-2:
SCIO
TSS
START HEADER
THDR
Data ‘0’
Data ‘1’
Data ‘0’
Data ‘1’
Data ‘0’
Data ‘1’
Data ‘0’
2010 Microchip Technology Inc.
Preliminary
11AAXXX/11LCXXX
3.3 Acknowledge
FIGURE 3-4:
MAK (‘1’)
ACKNOWLEDGE BITS
SAK (‘1’)
An Acknowledge routine occurs after each byte is transmitted, including the start header. This routine consists of two bits. The first bit is transmitted by the master, and the second bit is transmitted by the slave. Note: A MAK must always be transmitted following the start header. The Master Acknowledge, or MAK, is signified by transmitting a ‘1’, and informs the slave that the current operation is to be continued. Conversely, a Not Acknowledge, or NoMAK, is signified by transmitting a ‘0’, and is used to end the current operation (and initiate the write cycle for write operations). Note: When a NoMAK is used to end a WRITE or WRSR instruction, the write cycle is not initiated if no bytes of data have been received. The slave Acknowledge, or SAK, is also signified by transmitting a ‘1’, and confirms proper communication. However, unlike the NoMAK, the NoSAK is signified by the lack of a middle edge during the bit period. Note: In order to guard against bus contention, a NoSAK will occur after the start header. A NoSAK will occur for the following events: • Following the start header • Following the device address, if no slave on the bus matches the transmitted address • Following the command byte, if the command is invalid, including Read, CRRD, Write, WRSR, SETAL, and ERAL during a write cycle. • If the slave becomes out of sync with the master • If a command is terminated prematurely by using a NoMAK, with the exception of immediately after the device address. See Figure 3.3 and Figure 3-4 for details. If a NoSAK is received from the slave after any byte (except the start header), an error has occurred. The master should then perform a standby pulse and begin the desired command again.
NoMAK (‘0’)
NoSAK(1)
Note 1:
A NoSAK is defined as any sequence that is not a valid SAK.
3.4
Device Addressing
A device address byte is the first byte received from the master device following the start header. The device address byte consists of a four-bit family code, for the 11XX this is set as ‘1010’. The last four bits of the device address byte are the device code, which is hardwired to ‘0000’ on the 11XXXX0 devices. The device code on 11XXXX1 devices is hardwired to ‘0001’. This allows both 11XXXX0 and 11XXXX1 devices to be used on the same bus without address conflicts.
FIGURE 3-5:
DEVICE ADDRESS BYTE ALLOCATION
MAK SAK
SLAVE ADDRESS
1
Note 1:
0
1
0
0
0
0
0(1)
This bit is a ‘1’ on the 11XXXX1.
3.5
Bus Conflict Protection
FIGURE 3-3:
Master
ACKNOWLEDGE ROUTINE
Slave
To help guard against high current conditions arising from bus conflicts, the 11XX features a current-limited output driver. The IOL and IOH specifications describe the maximum current that can be sunk or sourced, respectively, by the SCIO pin. The 11XX will vary the output driver impedance to ensure that the maximum current level is not exceeded.
MAK
SAK
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Preliminary
2010 Microchip Technology Inc.
11AAXXX/11LCXXX
3.6 Device Standby
3.8.1 FREQUENCY DRIFT
The 11XX features a low-power Standby mode during which the device is waiting to begin a new command. A high-to-low transition on SCIO will exit low-power mode and prepare the device for receiving the start header. Standby mode will be entered upon the following conditions: • A NoMAK followed by a SAK (i.e., valid termination of a command) • Reception of a standby pulse Note: In the case of the WRITE, WRSR, SETAL, or ERAL commands, the write cycle is initiated upon receipt of the NoMAK, assuming all other write requirements have been met. Within a system, there is a possibility that frequencies can drift due to changes in voltage, temperature, etc. The re-synchronization circuitry provides some tolerance for such frequency drift. The tolerance range is specified by two parameters, FDRIFT and FDEV. FDRIFT specifies the maximum tolerable change in bus frequency per byte. FDEV specifies the overall limit in frequency deviation within an operation (i.e., from the end of the start header until communication is terminated for that operation). The start header at the beginning of the next operation will reset the re-synchronization circuitry and allow for another FDEV amount of frequency drift.
3.8.2
EDGE JITTER
3.7
Device Idle
The 11XX features an Idle mode during which all serial data is ignored until a standby pulse occurs. Idle mode will be entered upon the following conditions: • Invalid device address • Invalid command byte, including Read, CRRD, Write, WRSR, SETAL and ERAL during a write cycle. • Missed edge transition • Reception of a MAK following a WREN, WRDI, SETAL, or ERAL command byte • Reception of a MAK following the data byte of a WRSR command An invalid start header will indirectly cause the device to enter Idle mode. Whether or not the start header is invalid cannot be detected by the slave, but will prevent the slave from synchronizing properly with the master. If the slave is not synchronized with the master, an edge transition will be missed, thus causing the device to enter Idle mode.
Ensuring that edge transitions from the master always occur exactly in the middle or end of the bit period is not always possible. Therefore, the re-synchronization circuitry is designed to provide some tolerance for edge jitter. The 11XX adjusts its phase every MAK bit, so TIJIT specifies the maximum allowable peak-to-peak jitter relative to the previous MAK bit. Since the position of the previous MAK bit would be difficult to measure by the master, the minimum and maximum jitter values for a system should be considered the worst-case. These values will be based on the execution time for different branch paths in software, jitter due to thermal noise, etc. The difference between the minimum and maximum values, as a percentage of the bit period, should be calculated and then compared against TIJIT to determine jitter compliance. Note: Because the 11XX only re-synchronizes during the MAK bit, the overall ability to remain synchronized depends on a combination of frequency drift and edge jitter (i.e., if the MAK bit edge is experiencing the maximum allowable edge jitter, then there is no room for frequency drift). Conversely, if the frequency has drifted to the maximum amount tolerable within a byte, then no edge jitter can be present.
3.8
Synchronization
At the beginning of every command, the 11XX utilizes the start header to determine the master’s bus clock period. This period is then used as a reference for all subsequent communication within that command. The 11XX features re-synchronization circuitry which will monitor the position of the middle data edge during each MAK bit and subsequently adjust the internal time reference in order to remain synchronized with the master. There are two variables which can cause the 11XX to lose synchronization. The first is frequency drift, defined as a change in the bit period, TE. The second is edge jitter, which is a single occurrence change in the position of an edge within a bit period, while the bit period itself remains constant.
2010 Microchip Technology Inc.
Preliminary
DS22067H-page 9
11AAXXX/11LCXXX
4.0 DEVICE COMMANDS
After the device address byte, a command byte must be sent by the master to indicate the type of operation to be performed. The code for each instruction is listed in Table 4-1.
TABLE 4-1:
READ CRRD WRITE WREN WRDI RDSR WRSR ERAL SETAL
INSTRUCTION SET
Instruction Code 0000 0011 0000 0110 0110 1100 1001 0110 1001 0001 0000 0101 0110 1110 0110 1101 0110 0111 Hex Code 0x03 0x06 0x6C 0x96 0x91 0x05 0x6E 0x6D 0x67 Description Read data from memory array beginning at specified address Read data from current location in memory array Write data to memory array beginning at specified address Set the write enable latch (enable write operations) Reset the write enable latch (disable write operations) Read STATUS register Write STATUS register Write ‘0x00’ to entire array Write ‘0xFF’ to entire array that the slave should output the next data byte. This continues until the master sends a NoMAK, which ends the operation. To provide sequential reads in this manner, the 11XX contains an internal Address Pointer which is incremented by one after the transmission of each byte. This Address Pointer allows the entire memory contents to be serially read during one operation. When the highest address is reached, the Address Pointer rolls over to address ‘0x000’ if the master chooses to continue the operation by providing a MAK.
Instruction Name
4.1
Read Instruction
The Read command allows the master to access any memory location in a random manner. After the READ instruction has been sent to the slave, the two bytes of the Word Address are transmitted, with an Acknowledge sequence being performed after each byte. Then, the slave sends the first data byte to the master. If more data is to be read, the master sends a MAK, indicating
FIGURE 4-1:
READ COMMAND SEQUENCE
MAK NoSAK Standby Pulse Start Header Device Address MAK SAK NoMAK SAK MAK SAK
SCIO 01010101 MAK SAK MAK SAK MAK SAK 1 0 1 0 0 0 0 0(1)
Command SCIO 00000011
Word Address MSB 15 14 13 12 11 10 9 8
Word Address LSB 76543210
MAK SAK
Data Byte 1 SCIO 76543210
Data Byte 2 76543210
Data Byte n 76543210
Note 1: For the 11XXXX1, this bit must be a ‘1’.
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Preliminary
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11AAXXX/11LCXXX
4.2 Current Address Read (CRRD) Instruction
TABLE 4-2:
Command —
INTERNAL ADDRESS COUNTER
Event MAK edge following each Address byte MAK/NoMAK edge following each data byte Action Counter is updated with newly received value Counter is incremented by 1 Power-on Reset Counter is undefined
The internal address counter featured on the 11XX maintains the address of the last memory array location accessed. The CRRD instruction allows the master to read data back beginning from this current location. Consequently, no word address is provided upon issuing this command. Note that, except for the initial word address, the READ and CRRD instructions are identical, including the ability to continue requesting data through the use of MAKs in order to sequentially read from the array. As with the READ instruction, the CRRD instruction is terminated by transmitting a NoMAK. Table 4-2 lists the events upon which the internal address counter is modified.
READ or WRITE READ, WRITE, or CRRD
Note: If, following each data byte in a READ, WRITE, or CRRD instruction, neither a MAK nor a NoMAK edge is received (i.e., if a standby pulse occurs instead), the internal address counter will not be incremented. Note: During a Write command, once the last data byte for a page has been loaded, the internal Address Pointer will rollover to the beginning of the selected page.
FIGURE 4-2:
CRRD COMMAND SEQUENCE
MAK NoSAK Device Address MAK SAK 0(1)
DS22067H-page 11
Standby Pulse SCIO
Start Header
01010101
1010000
MAK SAK
MAK SAK
Command SCIO 00000110
Data Byte 1 76543210
Data Byte 2 76543210
Data Byte n SCIO 76543210
Note 1: For the 11XXXX1, this bit must be a ‘1’.
NoMAK SAK
2010 Microchip Technology Inc.
Preliminary
MAK SAK
11AAXXX/11LCXXX
4.3 Write Instruction
Prior to any attempt to write data to the 11XX, the write enable latch must be set by issuing the WREN instruction (see Section 4.4). Once the write enable latch is set, the user may proceed with issuing a WRITE instruction (including the header and device address bytes) followed by the MSB and LSB of the Word Address. Once the last Acknowledge sequence has been performed, the master transmits the data byte to be written. The 11XX features a 16-byte page buffer, meaning that up to 16 bytes can be written at one time. To utilize this feature, the master can transmit up to 16 data bytes to the 11XX, which are temporarily stored in the page buffer. After each data byte, the master sends a MAK, indicating whether or not another data byte is to follow. A NoMAK indicates that no more data is to follow, and as such will initiate the internal write cycle. Note: If a NoMAK is generated before any data has been provided, or if a standby pulse occurs before the NoMAK is generated, the 11XX will be reset, and the write cycle will not be initiated. Upon receipt of each word, the four lower-order Address Pointer bits are internally incremented by one. The higher-order bits of the word address remain constant. If the master should transmit data past the end of the page, the address counter will roll over to the beginning of the page, where further received data will be written. Note: Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page size (16 bytes) and end at addresses that are integer multiples of the page size minus 1. As an example, the page that begins at address 0x30 ends at address 0x3F. If a page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary.
FIGURE 4-3:
WRITE COMMAND SEQUENCE
MAK NoSAK Device Address MAK SAK No MAK SAK Twc MAK SAK
Standby Pulse SCIO
Start Header
01010101
1 0 1 0 0 0 0 0(1)
MAK SAK
MAK SAK MAK SAK
Command SCIO 01101100
Word Address MSB 15 14 13 12 11 10 9 8
Word Address LSB 76543210
MAK SAK
Data Byte 1 SCIO 76543210
Data Byte 2 76543210
Data Byte n 76543210
Note 1: For the 11XXXX1, this bit must be a ‘1’.
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Preliminary
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11AAXXX/11LCXXX
4.4 Write Enable (WREN) and Write Disable (WRDI) Instructions
The following is a list of conditions under which the write enable latch will be reset: • • • • • • Power-up WRDI instruction successfully executed WRSR instruction successfully executed WRITE instruction successfully executed ERAL instruction successfully executed SETAL instruction successfully executed
The 11XX contains a write enable latch. See Table 6-1 for the Write-Protect Functionality Matrix. This latch must be set before any write operation will be completed internally. The WREN instruction will set the latch, and the WRDI instruction will reset the latch. Note: The WREN and WRDI instructions must be terminated with a NoMAK following the command byte. If a NoMAK is not received at this point, the command will be considered invalid, and the device will go into Idle mode without responding with a SAK or executing the command.
FIGURE 4-4:
WRITE ENABLE COMMAND SEQUENCE
MAK NoSAK Standby Pulse Start Header Device Address MAK SAK
DS22067H-page 13
SCIO 01010101 NoMAK SAK 1 0 1 0 0 0 0 0(1)
Command SCIO 10010110
Note 1: For the 11XXXX1, this bit must be a ‘1’.
FIGURE 4-5:
WRITE DISABLE COMMAND SEQUENCE
MAK NoSAK Standby Pulse Start Header Device Address MAK SAK
SCIO 01010101 NoMAK SAK 1 0 1 0 0 0 0 0(1)
Command SCIO 10010001
Note 1: For the 11XXXX1, this bit must be a ‘1’.
2010 Microchip Technology Inc.
Preliminary
11AAXXX/11LCXXX
4.5 Read Status Register (RDSR) Instruction
The Block Protection (BP0 and BP1) bits indicate which blocks are currently write-protected. These bits are set by the user through the WRSR instruction. These bits are nonvolatile. Note: If Read Status Register command is initiated while the 11XX is currently executing an internal write cycle on the STATUS register, the new Block Protection bit values will be read during the entire command. The WIP and WEL bits will update dynamically (asynchronous to issuing the RDSR instruction). Furthermore, after the STATUS register data is received, the master can provide a MAK during the Acknowledge sequence to request that the data be transmitted again. This allows the master to continuously monitor the WIP and WEL bits without the need to issue another full command. Once the master is finished, it provides a NoMAK to end the operation. Note: The current drawn for a Read Status Register command during a write cycle is a combination of the ICC Read and ICC Write operating currents.
The RDSR instruction provides access to the STATUS register. The STATUS register may be read at any time, even during a write cycle. The STATUS register is formatted as follows: 7 6 5 4 3 2 1 0 XXXX BP1 BP0 WEL WIP Note: Bits 4-7 are don’t cares, and will read as ‘0’. The Write-In-Process (WIP) bit indicates whether the 11XX is busy with a write operation. When set to a ‘1’, a write is in progress, when set to a ‘0’, no write is in progress. This bit is read-only. The Write Enable Latch (WEL) bit indicates the status of the write enable latch. When set to a ‘1’, the latch allows writes to the array, when set to a ‘0’, the latch prohibits writes to the array. This bit is set and cleared using the WREN and WRDI instructions, respectively. This bit is read-only for any other instruction.
FIGURE 4-6:
READ STATUS REGISTER COMMAND SEQUENCE
MAK NoSAK
Standby Pulse SCIO
Start Header
Device Address
01010101 NoMAK SAK
1 0 1 0 0 0 0 0(1)
Command SCIO 00000101
MAK SAK
STATUS Register Data 3210 0000
Note 1: For the 11XXXX1, this bit must be a ‘1’. Note 2: The STATUS register data can continuously be read, or polled, by transmitting a MAK in place of the NoMAK.
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Preliminary
2010 Microchip Technology Inc.
MAK SAK
11AAXXX/11LCXXX
4.6 Write Status Register (WRSR) Instruction
After transmitting the STATUS register data, the master must transmit a NoMAK during the Acknowledge sequence in order to initiate the internal write cycle. Note: The WRSR instruction must be terminated with a NoMAK following the data byte. If a NoMAK is not received at this point, the command will be considered invalid, and the device will go into Idle mode without responding with a SAK or executing the command.
The WRSR instruction allows the user to select one of four levels of protection for the array by writing to the appropriate bits in the STATUS register. The array is divided up into four segments. The user has the ability to write-protect none, one, two, or all four of the segments of the array. The partitioning is controlled as illustrated in Table 4-3.
TABLE 4-3:
BP1 0 0 1 1
ARRAY PROTECTION
BP0 0 1 0 1 Address Ranges Write-Protected None Upper 1/4 Upper 1/2 All Address Ranges Unprotected All Lower 3/4 Lower 1/2 None
TABLE 4-4:
1K 2K 4K 8K 16K
PROTECTED ARRAY ADDRESS LOCATIONS
Upper 1/4 60h-7Fh C0h-FFh 180h-1FFh 300h-3FFh 600h-7FFh Upper 1/2 40h-7Fh 80h-FFh 100h-1FFh 200h-3FFh 400h-7FFh All Sectors 00h-7Fh 00h-FFh 000h-1FFh 000h-3FFh 000h-7FFh
Density
FIGURE 4-7:
WRITE STATUS REGISTER COMMAND SEQUENCE
MAK NoSAK Standby Pulse Start Header Device Address MAK SAK
DS22067H-page 15
SCIO 01010101 NoMAK SAK Twc 1 0 1 0 0 0 0 0(1)
Command SCIO 01101110
MAK SAK
Status Register Data 76543210
Note 1: For the 11XXXX1, this bit must be a ‘1’.
2010 Microchip Technology Inc.
Preliminary
11AAXXX/11LCXXX
4.7 Erase All (ERAL) Instruction
The ERAL instruction allows the user to write ‘0x00’ to the entire memory array with one command. Note that the write enable latch (WEL) must first be set by issuing the WREN instruction. Once the write enable latch is set, the user may proceed with issuing a ERAL instruction (including the header and device address bytes). Immediately after the NoMAK bit has been transmitted by the master, the internal write cycle is initiated, during which time all words of the memory array are written to ‘0x00’. The ERAL instruction is ignored if either of the Block Protect bits (BP0, BP1) are not 0, meaning 1/4, 1/2, or all of the array is protected. Note: The ERAL instruction must be terminated with a NoMAK following the command byte. If a NoMAK is not received at this point, the command will be considered invalid, and the device will go into Idle mode without responding with a SAK or executing the command.
FIGURE 4-8:
ERASE ALL COMMAND SEQUENCE
MAK NoSAK Standby Pulse Start Header Device Address MAK SAK MAK SAK
SCIO 01010101 NoMAK SAK 1 0 1 0 0 0 0 0(1)
Command SCIO 01101101
Twc
Note 1: For the 11XXXX1, this bit must be a ‘1’.
4.8
Set All (SETAL) Instruction
The SETAL instruction allows the user to write ‘0xFF’ to the entire memory array with one command. Note that the write enable latch (WEL) must first be set by issuing the WREN instruction. Once the write enable latch is set, the user may proceed with issuing a SETAL instruction (including the header and device address bytes). Immediately after the NoMAK bit has been transmitted by the master, the internal write cycle is initiated, during which time all words of the memory array are written to ‘0xFF’.
The SETAL instruction is ignored if either of the Block Protect bits (BP0, BP1) are not 0, meaning 1/4, 1/2, or all of the array is protected. Note: The SETAL instruction must be terminated with a NoMAK following the command byte. If a NoMAK is not received at this point, the command will be considered invalid, and the device will go into Idle mode without responding with a SAK or executing the command.
FIGURE 4-9:
SET ALL COMMAND SEQUENCE
MAK NoSAK Standby Pulse Start Header Device Address
SCIO 01010101 NoMAK SAK 1 0 1 0 0 0 0 0(1)
Command SCIO 01100111
Twc
Note 1: For the 11XXXX1, this bit must be a ‘1’.
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2010 Microchip Technology Inc.
11AAXXX/11LCXXX
5.0 DATA PROTECTION 6.0 POWER-ON STATE
The following protection has been implemented to prevent inadvertent writes to the array: • The Write Enable Latch (WEL) is reset on powerup • A Write Enable (WREN) instruction must be issued to set the write enable latch • After a write, ERAL, SETAL, or WRSR command, the write enable latch is reset • Commands to access the array or write to the status register are ignored during an internal write cycle and programming is not affected The 11XX powers on in the following state: • The device is in low-power Shutdown mode, requiring a low-to-high transition on SCIO to enter Idle mode • The Write Enable Latch (WEL) is reset • The internal Address Pointer is undefined • A low-to-high transition, standby pulse and subsequent high-to-low transition on SCIO (the first low pulse of the header) are required to enter the active state
.
TABLE 6-1:
WEL 0 1
WRITE PROTECT FUNCTIONALITY MATRIX
Protected Blocks Protected Protected Unprotected Blocks Protected Writable Status Register Protected Writable
2010 Microchip Technology Inc.
Preliminary
DS22067H-page 17
11AAXXX/11LCXXX
7.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 7-1.
TABLE 7-1:
Name SCIO VCC VSS NC
PIN FUNCTION TABLE
3-pin SOT-23 1 2 3 — 3-pin TO-92 2 3 1 — 4-pin CS 3 1 2 4 8-pin PDIP/SOIC/ MSOP/TDFN 5 8 4 1,2,3,6,7 Description Serial Clock, Data Input/Output Supply Voltage Ground No Internal Connection
7.1
Serial Clock, Data Input/Output (SCIO)
SCIO is a bidirectional pin used to transfer commands and addresses into, as well as data into and out of, the device. The serial clock is embedded into the data stream through Manchester encoding. Each bit is represented by a signal transition at the middle of the bit period.
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Preliminary
2010 Microchip Technology Inc.
11AAXXX/11LCXXX
8.0
8.1
PACKAGING INFORMATION
Package Marking Information
8-Lead PDIP
XXXXXXXX T/XXXNNN YYWW
Example:
11AA160 I/P e3 1L7 0828
8-Lead PDIP Package Marking (Pb-Free) Device 11AA010 11AA020 11AA040 11AA080 11AA160 11AA161 Note: Line 1 Marking 11AA010 11AA020 11AA040 11AA080 11AA160 11AA161 Device 11LC010 11LC020 11LC040 11LC080 11LC160 11LC161 Line 1 Marking 11LC010 11LC020 11LC040 11LC080 11LC160 11LC161
T = Temperature Grade (I, E)
Legend: XX...X Y YY WW NNN
e3
* Note:
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
2010 Microchip Technology Inc.
Preliminary
DS22067H-page 19
11AAXXX/11LCXXX
8-Lead SOIC Example:
XXXXXXXT XXXXYYWW NNN
11AA160I SN e3 0828 1L7
8-Lead SOIC Package Marking (Pb-Free) Device 11AA010 11AA020 11AA040 11AA080 11AA160 11AA161 Note: Line 1 Marking 11AA010T 11AA020T 11AA040T 11AA080T 11AA160T 11AA161T Device 11LC010 11LC020 11LC040 11LC080 11LC160 11LC161 Line 1 Marking 11LC010T 11LC020T 11LC040T 11LC080T 11LC160T 11LC161T
T = Temperature Grade (I, E)
Legend: XX...X Y YY WW NNN
e3
* Note:
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
DS22067H-page 20
Preliminary
2010 Microchip Technology Inc.
11AAXXX/11LCXXX
8-Lead MSOP (150 mil)
XXXXXXT YWWNNN
Example:
11A01I e3 8281L7
8-Lead MSOP Package Marking (Pb-Free) Device 11AA010 11AA020 11AA040 11AA080 11AA160 11AA161 Note: T = Temperature Grade (I, E) Line 1 Marking 11A01T 11A02T 11A04T 11A08T 11AAT 11AA1T Device 11LC010 11LC020 11LC040 11LC080 11LC160 11LC161 Line 1 Marking 11L01T 11L02T 11L04T 11L08T 11LAT 11LA1T
Legend: XX...X Y YY WW NNN
e3
* Note:
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
2010 Microchip Technology Inc.
Preliminary
DS22067H-page 21
11AAXXX/11LCXXX
8-Lead 2x3 TDFN Example:
XXX YWW NN
D51 828 17
8-Lead 2x3 TDFN Package Marking (Pb-Free) Device 11AA010 11AA020 11AA040 11AA080 11AA160 11AA161 I-Temp Marking D11 D21 D31 D41 D51 D5D Device 11LC010 11LC020 11LC040 11LC080 11LC160 11LC161 I-Temp Marking D14 D24 D34 D44 D54 D5G E-Temp Marking D15 D25 D35 D45 D55 D5H
Legend: XX...X Y YY WW NN
e3
* Note:
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
DS22067H-page 22
Preliminary
2010 Microchip Technology Inc.
11AAXXX/11LCXXX
3-Lead SOT-23 Example:
XXNN
B517
3-Lead SOT-23 Package Marking (Pb-Free) Device 11AA010 11AA020 11AA040 11AA080 11AA160 11AA161 I-Temp Marking B1NN B2NN B3NN B4NN B5NN B0NN Device 11LC010 11LC020 11LC040 11LC080 11LC160 11LC161 I-Temp Marking M1NN M2NN M3NN M4NN M5NN M0NN E-Temp Marking N1NN N2NN N3NN N4NN N5NN N0NN
Legend: XX...X Y YY WW NNN
e3
* Note:
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
2010 Microchip Technology Inc.
Preliminary
DS22067H-page 23
11AAXXX/11LCXXX
3-Lead TO-92 Example:
XXXXXX T/XXXX YWW NNN
11A160 e3 I/TO e3 928 1L7
3-Lead TO-92 Package Marking (Pb-Free) Device 11AA010 11AA020 11AA040 11AA080 11AA160 11AA161 Note: Line 1 Marking 11A010 11A020 11A040 11A080 11A160 11A161 Device 11LC010 11LC020 11LC040 11LC080 11LC160 11LC161 Line 1 Marking 11L010 11L020 11L040 11L080 11L160 11L161
T = Temperature Grade (I, E)
Legend: XX...X Y YY WW NNN
e3
* Note:
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
DS22067H-page 24
Preliminary
2010 Microchip Technology Inc.
11AAXXX/11LCXXX
4-Lead Chip Scale
Example:
XW NN
E3 17
4-Lead Chip Scale Package Marking (Pb-Free) Device 11AA010 11AA020 11AA040 11AA080 11AA160 11AA161 Line 1 Marking AW BW CW DW EW HW
Legend: XX...X Y YY WW NNN
e3
* Note:
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
2010 Microchip Technology Inc.
Preliminary
DS22067H-page 25
11AAXXX/11LCXXX
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2010 Microchip Technology Inc.
Preliminary
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