16F876

PIC16F87X Data Sheet 28/40-Pin 8-Bit CMOS FLASH Microcontrollers  2001 Microchip Technology Inc. DS30292C “All rights reserved. Copyright © 2001, Microchip Technology Incorporated, USA. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.” Trademarks The Microchip name, logo, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, KEELOQ, SEEVAL, MPLAB and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Total Endurance, ICSP, In-Circuit Serial Programming, FilterLab, MXDEV, microID, FlexROM, fuzzyLAB, MPASM, MPLINK, MPLIB, PICDEM, ICEPIC, Migratable Memory, FanSense, ECONOMONITOR and SelectMode are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Term Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2001, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified. DS30292C - page ii  2001 Microchip Technology Inc. PIC16F87X 28/40-Pin 8-Bit CMOS FLASH Microcontrollers Devices Included in this Data Sheet: • PIC16F873 • PIC16F874 • PIC16F876 • PIC16F877 Pin Diagram PDIP MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1 1 2 3 4 5 6 40 39 38 37 36 35 RB7/PGD RB6/PGC RB5 RB4 RB3/PGM RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 Microcontroller Core Features: • High performance RISC CPU • Only 35 single word instructions to learn • All single cycle instructions except for program branches which are two cycle • Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle • Up to 8K x 14 words of FLASH Program Memory, Up to 368 x 8 bytes of Data Memory (RAM) Up to 256 x 8 bytes of EEPROM Data Memory • Pinout compatible to the PIC16C73B/74B/76/77 • Interrupt capability (up to 14 sources) • Eight level deep hardware stack • Direct, indirect and relative addressing modes • Power-on Reset (POR) • Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) • Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation • Programmable code protection • Power saving SLEEP mode • Selectable oscillator options • Low power, high speed CMOS FLASH/EEPROM technology • Fully static design • In-Circuit Serial Programming (ICSP) via two pins • Single 5V In-Circuit Serial Programming capability • In-Circuit Debugging via two pins • Processor read/write access to program memory • Wide operating voltage range: 2.0V to 5.5V • High Sink/Source Current: 25 mA • Commercial, Industrial and Extended temperature ranges • Low-power consumption: - < 0.6 mA typical @ 3V, 4 MHz - 20 µA typical @ 3V, 32 kHz - < 1 µA typical standby current PIC16F877/874 7 8 9 10 11 12 13 14 15 16 17 18 19 20 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Peripheral Features: • Timer0: 8-bit timer/counter with 8-bit prescaler • Timer1: 16-bit timer/counter with prescaler, can be incremented during SLEEP via external crystal/clock • Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler • Two Capture, Compare, PWM modules - Capture is 16-bit, max. resolution is 12.5 ns - Compare is 16-bit, max. resolution is 200 ns - PWM max. resolution is 10-bit • 10-bit multi-channel Analog-to-Digital converter • Synchronous Serial Port (SSP) with SPI (Master mode) and I2C (Master/Slave) • Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI) with 9-bit address detection • Parallel Slave Port (PSP) 8-bits wide, with external RD, WR and CS controls (40/44-pin only) • Brown-out detection circuitry for Brown-out Reset (BOR)  2001 Microchip Technology Inc. DS30292C-page 1 PIC16F87X Pin Diagrams PDIP, SOIC MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7/PGD RB6/PGC RB5 RB4 RB3/PGM RB2 RB1 RB0/INT VDD VSS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RA3/AN3/VREF+ RA2/AN2/VREFRA1/AN1 RA0/AN0 MCLR/VPP NC RB7/PGD RB6/PGC RB5 RB4 NC 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 PIC16F876/873 PLCC RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1 RC1/T1OSI/CCP2 NC QFP 44 43 42 41 40 39 38 37 36 35 34 NC NC RB4 RB5 RB6/PGC RB7/PGD MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ 12 13 14 15 16 17 18 19 20 21 22 RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 VSS VDD RB0/INT RB1 RB2 RB3/PGM 1 2 3 4 5 6 7 8 9 10 11 PIC16F877 PIC16F874 33 32 31 30 29 28 27 26 25 24 23 NC RC0/T1OSO/T1CKI OSC2/CLKOUT OSC1/CLKIN VSS VDD RE2/AN7/CS RE1/AN6/WR RE0/AN5/RD RA5/AN4/SS RA4/T0CKI DS30292C-page 2 RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RC4/SDI/SDA RC5/SDO RC6/TX/CK NC 18 19 20 21 22 23 24 25 26 27 28 RA4/T0CKI RA5/AN4/SS RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CK1 NC 7 8 9 10 11 12 13 14 15 16 17 PIC16F877 PIC16F874 RB3/PGM RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT  2001 Microchip Technology Inc. PIC16F87X Key Features PICmicro™ Mid-Range Reference Manual (DS33023) Operating Frequency RESETS (and Delays) FLASH Program Memory (14-bit words) Data Memory (bytes) EEPROM Data Memory Interrupts I/O Ports Timers Capture/Compare/PWM Modules Serial Communications Parallel Communications 10-bit Analog-to-Digital Module Instruction Set PIC16F873 DC - 20 MHz POR, BOR (PWRT, OST) 4K 192 128 13 Ports A,B,C 3 2 MSSP, USART — 5 input channels 35 instructions PIC16F874 DC - 20 MHz POR, BOR (PWRT, OST) 4K 192 128 14 Ports A,B,C,D,E 3 2 MSSP, USART PSP 8 input channels 35 instructions PIC16F876 DC - 20 MHz POR, BOR (PWRT, OST) 8K 368 256 13 Ports A,B,C 3 2 MSSP, USART — 5 input channels 35 instructions PIC16F877 DC - 20 MHz POR, BOR (PWRT, OST) 8K 368 256 14 Ports A,B,C,D,E 3 2 MSSP, USART PSP 8 input channels 35 instructions  2001 Microchip Technology Inc. DS30292C-page 3 PIC16F87X Table of Contents 1.0 Device Overview ................................................................................................................................................... 5 2.0 Memory Organization.......................................................................................................................................... 11 3.0 I/O Ports .............................................................................................................................................................. 29 4.0 Data EEPROM and FLASH Program Memory.................................................................................................... 41 5.0 Timer0 Module .................................................................................................................................................... 47 6.0 Timer1 Module .................................................................................................................................................... 51 7.0 Timer2 Module .................................................................................................................................................... 55 8.0 Capture/Compare/PWM Modules ....................................................................................................................... 57 9.0 Master Synchronous Serial Port (MSSP) Module ............................................................................................... 65 10.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART) ........................................ 95 11.0 Analog-to-Digital Converter (A/D) Module......................................................................................................... 111 12.0 Special Features of the CPU............................................................................................................................. 119 13.0 Instruction Set Summary................................................................................................................................... 135 14.0 Development Support ....................................................................................................................................... 143 15.0 Electrical Characteristics................................................................................................................................... 149 16.0 DC and AC Characteristics Graphs and Tables................................................................................................ 177 17.0 Packaging Information ...................................................................................................................................... 189 Appendix A: Revision History .................................................................................................................................... 197 Appendix B: Device Differences ................................................................................................................................ 197 Appendix C: Conversion Considerations ................................................................................................................... 198 Index .......................................................................................................................................................................... 199 On-Line Support ......................................................................................................................................................... 207 Reader Response ...................................................................................................................................................... 208 PIC16F87X Product Identification System ................................................................................................................. 209 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) • The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. DS30292C-page 4  2001 Microchip Technology Inc. PIC16F87X 1.0 DEVICE OVERVIEW This document contains device specific information. Additional information may be found in the PICmicro™ Mid-Range Reference Manual (DS33023), which may be obtained from your local Microchip Sales Representative or downloaded from the Microchip website. The Reference Manual should be considered a complementary document to this data sheet, and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. There are four devices (PIC16F873, PIC16F874, PIC16F876 and PIC16F877) covered by this data sheet. The PIC16F876/873 devices come in 28-pin packages and the PIC16F877/874 devices come in 40-pin packages. The Parallel Slave Port is not implemented on the 28-pin devices. The following device block diagrams are sorted by pin number; 28-pin for Figure 1-1 and 40-pin for Figure 1-2. The 28-pin and 40-pin pinouts are listed in Table 1-1 and Table 1-2, respectively. FIGURE 1-1: Device PIC16F873 PIC16F876 PIC16F873 AND PIC16F876 BLOCK DIAGRAM Program FLASH 4K 8K Data Memory 192 Bytes 368 Bytes 13 Program Counter FLASH Program Memory Data EEPROM 128 Bytes 256 Bytes Data Bus 8 PORTA RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS PORTB RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD PORTC 8 Level Stack (13-bit) RAM File Registers RAM Addr(1) Program Bus 14 Instruction reg Direct Addr 7 9 Addr MUX 8 Indirect Addr FSR reg STATUS reg 8 3 Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset In-Circuit Debugger Low Voltage Programming 8 MUX ALU RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT W reg MCLR VDD, VSS Timer0 Timer1 Timer2 10-bit A/D Data EEPROM CCP1,2 Synchronous Serial Port USART Note 1: Higher order bits are from the STATUS register.  2001 Microchip Technology Inc. DS30292C-page 5 PIC16F87X FIGURE 1-2: Device PIC16F874 PIC16F877 PIC16F874 AND PIC16F877 BLOCK DIAGRAM Program FLASH 4K 8K Data Memory 192 Bytes 368 Bytes 13 FLASH Program Memory 8 Level Stack (13-bit) Program Counter Data EEPROM 128 Bytes 256 Bytes Data Bus 8 PORTA RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS PORTB RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD PORTC RAM File Registers RAM Addr(1) Program Bus 14 Instruction reg Direct Addr 7 9 Addr MUX 8 Indirect Addr FSR reg STATUS reg 8 3 Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset In-Circuit Debugger Low-Voltage Programming 8 MUX ALU RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT PORTD RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 PORTE W reg Parallel Slave Port MCLR VDD, VSS RE0/AN5/RD RE1/AN6/WR RE2/AN7/CS Timer0 Timer1 Timer2 10-bit A/D Data EEPROM CCP1,2 Synchronous Serial Port USART Note 1: Higher order bits are from the STATUS register. DS30292C-page 6  2001 Microchip Technology Inc. PIC16F87X TABLE 1-1: Pin Name OSC1/CLKIN OSC2/CLKOUT PIC16F873 AND PIC16F876 PINOUT DESCRIPTION DIP Pin# 9 10 SOIC Pin# 9 10 I/O/P Type I O Buffer Type Description ST/CMOS(3) Oscillator crystal input/external clock source input. — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. Master Clear (Reset) input or programming voltage input. This pin is an active low RESET to the device. PORTA is a bi-directional I/O port. RA0 can also be analog input0. RA1 can also be analog input1. RA2 can also be analog input2 or negative analog reference voltage. RA3 can also be analog input3 or positive analog reference voltage. RA4 can also be the clock input to the Timer0 module. Output is open drain type. RA5 can also be analog input4 or the slave select for the synchronous serial port. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. MCLR/VPP 1 1 I/P ST RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/SS/AN4 2 3 4 5 6 7 2 3 4 5 6 7 I/O I/O I/O I/O I/O I/O TTL TTL TTL TTL ST TTL RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD 21 22 23 24 25 26 27 28 21 22 23 24 25 26 27 28 I/O I/O I/O I/O I/O I/O I/O I/O TTL/ST(1) TTL TTL TTL TTL TTL TTL/ST(2) TTL/ST(2) RB0 can also be the external interrupt pin. RB3 can also be the low voltage programming input. Interrupt-on-change pin. Interrupt-on-change pin. Interrupt-on-change pin or In-Circuit Debugger pin. Serial programming clock. Interrupt-on-change pin or In-Circuit Debugger pin. Serial programming data. PORTC is a bi-directional I/O port. RC0 can also be the Timer1 oscillator output or Timer1 clock input. RC1 can also be the Timer1 oscillator input or Capture2 input/Compare2 output/PWM2 output. RC2 can also be the Capture1 input/Compare1 output/ PWM1 output. RC3 can also be the synchronous serial clock input/output for both SPI and I2C modes. RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5 can also be the SPI Data Out (SPI mode). RC6 can also be the USART Asynchronous Transmit or Synchronous Clock. RC7 can also be the USART Asynchronous Receive or Synchronous Data. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins. P = power ST = Schmitt Trigger input RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT VSS VDD Legend: I = input 11 12 13 14 15 16 17 18 8, 19 20 11 12 13 14 15 16 17 18 8, 19 20 I/O I/O I/O I/O I/O I/O I/O I/O P P ST ST ST ST ST ST ST ST — — O = output — = Not used I/O = input/output TTL = TTL input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.  2001 Microchip Technology Inc. DS30292C-page 7 PIC16F87X TABLE 1-2: Pin Name OSC1/CLKIN OSC2/CLKOUT PIC16F874 AND PIC16F877 PINOUT DESCRIPTION DIP Pin# 13 14 PLCC Pin# 14 15 QFP Pin# 30 31 I/O/P Type I O Buffer Type ST/CMOS(4) — Description Oscillator crystal input/external clock source input. Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. Master Clear (Reset) input or programming voltage input. This pin is an active low RESET to the device. PORTA is a bi-directional I/O port. RA0 can also be analog input0. RA1 can also be analog input1. RA2 can also be analog input2 or negative analog reference voltage. RA3 can also be analog input3 or positive analog reference voltage. RA4 can also be the clock input to the Timer0 timer/ counter. Output is open drain type. RA5 can also be analog input4 or the slave select for the synchronous serial port. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. MCLR/VPP 1 2 18 I/P ST RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/SS/AN4 2 3 4 5 6 7 3 4 5 6 7 8 19 20 21 22 23 24 I/O I/O I/O I/O I/O I/O TTL TTL TTL TTL ST TTL RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD Legend: I = input 33 34 35 36 37 38 39 40 36 37 38 39 41 42 43 44 8 9 10 11 14 15 16 17 I/O I/O I/O I/O I/O I/O I/O I/O TTL/ST(1) TTL TTL TTL TTL TTL TTL/ST(2) TTL/ST(2) RB0 can also be the external interrupt pin. RB3 can also be the low voltage programming input. Interrupt-on-change pin. Interrupt-on-change pin. Interrupt-on-change pin or In-Circuit Debugger pin. Serial programming clock. Interrupt-on-change pin or In-Circuit Debugger pin. Serial programming data. P = power ST = Schmitt Trigger input O = output — = Not used I/O = input/output TTL = TTL input Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). 4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. DS30292C-page 8  2001 Microchip Technology Inc. PIC16F87X TABLE 1-2: Pin Name PIC16F874 AND PIC16F877 PINOUT DESCRIPTION (CONTINUED) DIP Pin# PLCC Pin# QFP Pin# I/O/P Type Buffer Type Description PORTC is a bi-directional I/O port. RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT 15 16 17 18 23 24 25 26 16 18 19 20 25 26 27 29 32 35 36 37 42 43 44 1 I/O I/O I/O I/O I/O I/O I/O I/O ST ST ST ST ST ST ST ST RC0 can also be the Timer1 oscillator output or a Timer1 clock input. RC1 can also be the Timer1 oscillator input or Capture2 input/Compare2 output/PWM2 output. RC2 can also be the Capture1 input/Compare1 output/PWM1 output. RC3 can also be the synchronous serial clock input/ output for both SPI and I2C modes. RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5 can also be the SPI Data Out (SPI mode). RC6 can also be the USART Asynchronous Transmit or Synchronous Clock. RC7 can also be the USART Asynchronous Receive or Synchronous Data. PORTD is a bi-directional I/O port or parallel slave port when interfacing to a microprocessor bus. RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VSS VDD NC Legend: I = input 19 20 21 22 27 28 29 30 8 9 10 12,31 11,32 — 21 22 23 24 30 31 32 33 9 10 11 13,34 12,35 1,17,28, 40 38 39 40 41 2 3 4 5 25 26 27 6,29 7,28 12,13, 33,34 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O P P ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3) PORTE is a bi-directional I/O port. ST/TTL(3) ST/TTL(3) ST/TTL(3) — — — RE0 can also be read control for the parallel slave port, or analog input5. RE1 can also be write control for the parallel slave port, or analog input6. RE2 can also be select control for the parallel slave port, or analog input7. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins. These pins are not internally connected. These pins should be left unconnected. P = power ST = Schmitt Trigger input O = output — = Not used I/O = input/output TTL = TTL input Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). 4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.  2001 Microchip Technology Inc. DS30292C-page 9 PIC16F87X NOTES: DS30292C-page 10  2001 Microchip Technology Inc. PIC16F87X 2.0 MEMORY ORGANIZATION 2.1 Program Memory Organization There are three memory blocks in each of the PIC16F87X MCUs. The Program Memory and Data Memory have separate buses so that concurrent access can occur and is detailed in this section. The EEPROM data memory block is detailed in Section 4.0. Additional information on device memory may be found in the PICmicro Mid-Range Reference Manual, (DS33023). The PIC16F87X devices have a 13-bit program counter capable of addressing an 8K x 14 program memory space. The PIC16F877/876 devices have 8K x 14 words of FLASH program memory, and the PIC16F873/874 devices have 4K x 14. Accessing a location above the physically implemented address will cause a wraparound. The RESET vector is at 0000h and the interrupt vector is at 0004h. FIGURE 2-1: PIC16F877/876 PROGRAM MEMORY MAP AND STACK PC FIGURE 2-2: PIC16F874/873 PROGRAM MEMORY MAP AND STACK PC CALL, RETURN RETFIE, RETLW 13 CALL, RETURN RETFIE, RETLW 13 Stack Level 1 Stack Level 2 Stack Level 1 Stack Level 2 Stack Level 8 Stack Level 8 RESET Vector 0000h RESET Vector 0000h Interrupt Vector 0004h 0005h Interrupt Vector 0004h 0005h Page 0 07FFh 0800h On-Chip Program Memory Page 0 07FFh 0800h Page 1 On-Chip Program Memory Page 2 17FFh 1800h 0FFFh 1000h Page 1 0FFFh 1000h Page 3 1FFFh 1FFFh  2001 Microchip Technology Inc. DS30292C-page 11 PIC16F87X 2.2 Data Memory Organization The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 (STATUS) and RP0 (STATUS) are the bank select bits. Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as static RAM. All implemented banks contain Special Function Registers. Some frequently used Special Function Registers from one bank may be mirrored in another bank for code reduction and quicker access. Note: EEPROM Data Memory description can be found in Section 4.0 of this data sheet. RP1:RP0 00 01 10 11 Bank 0 1 2 3 2.2.1 GENERAL PURPOSE REGISTER FILE The register file can be accessed either directly, or indirectly through the File Select Register (FSR). DS30292C-page 12  2001 Microchip Technology Inc. PIC16F87X FIGURE 2-3: PIC16F877/876 REGISTER FILE MAP File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD(1) PORTE(1) PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRESH ADCON0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h Indirect addr.(*) OPTION_REG PCL STATUS FSR TRISA TRISB TRISC TRISD(1) TRISE(1) PCLATH INTCON PIE1 PIE2 PCON File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h General Purpose Register 80 Bytes accesses 70h-7Fh 7Fh Bank 0 Bank 1 General Purpose Register 80 Bytes accesses 70h-7Fh Bank 2 Indirect addr.(*) TMR0 PCL STATUS FSR PORTB File Address 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h Indirect addr.(*) OPTION_REG PCL STATUS FSR TRISB File Address 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h PCLATH INTCON EEDATA EEADR EEDATH EEADRH PCLATH INTCON EECON1 EECON2 Reserved(2) Reserved(2) SSPCON2 PR2 SSPADD SSPSTAT TXSTA SPBRG General Purpose Register 16 Bytes General Purpose Register 16 Bytes ADRESL ADCON1 General Purpose Register 96 Bytes EFh F0h FFh 16Fh 170h 17Fh General Purpose Register 80 Bytes accesses 70h - 7Fh Bank 3 1EFh 1F0h 1FFh Unimplemented data memory locations, read as ’0’. * Not a physical register. Note 1: These registers are not implemented on the PIC16F876. 2: These registers are reserved, maintain these registers clear.  2001 Microchip Technology Inc. DS30292C-page 13 PIC16F87X FIGURE 2-4: PIC16F874/873 REGISTER FILE MAP File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD(1) PORTE(1) PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRESH ADCON0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h File Address Indirect addr.(*) OPTION_REG PCL STATUS FSR TRISA TRISB TRISC TRISD(1) TRISE(1) PCLATH INTCON PIE1 PIE2 PCON 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h General Purpose Register 96 Bytes File Address Indirect addr.(*) 100h 101h TMR0 102h PCL 103h STATUS 104h FSR 105h 106h PORTB 107h 108h 109h 10Ah PCLATH 10Bh INTCON 10Ch EEDATA EEADR 10Dh 10Eh EEDATH 10Fh EEADRH 110h File Address Indirect addr.(*) OPTION_REG PCL STATUS FSR TRISB 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h PCLATH INTCON EECON1 EECON2 Reserved(2) Reserved(2) SSPCON2 PR2 SSPADD SSPSTAT TXSTA SPBRG ADRESL ADCON1 120h 1A0h General Purpose Register 96 Bytes accesses 20h-7Fh 16Fh 170h FFh 17Fh Bank 2 accesses A0h - FFh 1EFh 1F0h 1FFh Bank 3 7Fh Bank 0 Bank 1 Unimplemented data memory locations, read as ’0’. * Not a physical register. Note 1: These registers are not implemented on the PIC16F873. 2: These registers are reserved, maintain these registers clear. DS30292C-page 14  2001 Microchip Technology Inc. PIC16F87X 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is given in Table 2-1. The Special Function Registers can be classified into two sets: core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section. Those related to the operation of the peripheral features are described in detail in the peripheral features section. TABLE 2-1: Address Bank 0 00h(3) 01h 02h(3) 03h(3) 04h(3) 05h 06h 07h 08h(4) 09h(4) 0Ah(1,3) 0Bh(3) 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh Legend: Note 1: 2: 3: 4: 5: INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD PORTE PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H Name SPECIAL FUNCTION REGISTER SUMMARY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Details on page: Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module Register Program Counter (PC) Least Significant Byte IRP — RP1 — RP0 TO PD Z DC C Indirect Data Memory Address Pointer PORTA Data Latch when written: PORTA pins when read PORTB Data Latch when written: PORTB pins when read PORTC Data Latch when written: PORTC pins when read PORTD Data Latch when written: PORTD pins when read — — GIE PSPIF(3) — — — PEIE ADIF (5) — — T0IE RCIF — — INTE TXIF EEIF — RBIE SSPIF BCLIF RE2 T0IF CCP1IF — RE1 INTF TMR2IF — RE0 RBIF TMR1IF CCP2IF Write Buffer for the upper 5 bits of the Program Counter 0000 0000 xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx --0x 0000 xxxx xxxx xxxx xxxx xxxx xxxx ---- -xxx ---0 0000 0000 000x 0000 0000 -r-0 0--0 xxxx xxxx xxxx xxxx 27 47 26 18 27 29 31 33 35 36 26 20 22 24 52 52 51 55 55 70, 73 67 57 57 58 96 99 101 57 57 58 116 111 Holding register for the Least Significant Byte of the 16-bit TMR1 Register Holding register for the Most Significant Byte of the 16-bit TMR1 Register — — WCOL — T1CKPS1 T1CKPS0 TOUTPS1 CKP T1OSCEN TOUTPS0 SSPM3 T1SYNC TMR2ON SSPM2 TMR1CS TMR1ON Timer2 Module Register TOUTPS3 TOUTPS2 SSPOV SSPEN Synchronous Serial Port Receive Buffer/Transmit Register SSPM1 SSPM0 Capture/Compare/PWM Register1 (LSB) Capture/Compare/PWM Register1 (MSB) — SPEN — RX9 CCP1X SREN CCP1Y CREN CCP1M3 ADDEN CCP1M2 FERR CCP1M1 OERR CCP1M0 RX9D --00 0000 0000 0000 T2CKPS1 T2CKPS0 -000 0000 xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx --00 0000 0000 000x 0000 0000 0000 0000 xxxx xxxx xxxx xxxx CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRESH ADCON0 USART Transmit Data Register USART Receive Data Register Capture/Compare/PWM Register2 (LSB) Capture/Compare/PWM Register2 (MSB) — ADCS1 — ADCS0 CCP2X CHS2 CCP2Y CHS1 CCP2M3 CHS0 CCP2M2 GO/DONE CCP2M1 — CCP2M0 ADON A/D Result Register High Byte --00 0000 xxxx xxxx 0000 00-0 x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved. Shaded locations are unimplemented, read as ‘0’. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC whose contents are transferred to the upper byte of the program counter. Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear. These registers can be addressed from any bank. PORTD, PORTE, TRISD, and TRISE are not physically implemented on PIC16F873/876 devices; read as ‘0’. PIR2 and PIE2 are reserved on these devices; always maintain these bits clear.  2001 Microchip Technology Inc. DS30292C-page 15 PIC16F87X TABLE 2-1: Address Bank 1 80h(3) 81h 82h(3) 83h(3) 84h(3) 85h 86h 87h 88h(4) 89h(4) 8Ah(1,3) 8Bh(3) 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh Legend: Note 1: 2: 3: 4: 5: INDF OPTION_REG PCL STATUS FSR TRISA TRISB TRISC TRISD TRISE PCLATH INTCON PIE1 PIE2 PCON — — SSPCON2 PR2 SSPADD SSPSTAT — — — TXSTA SPBRG — — — — ADRESL ADCON1 Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU IRP — INTEDG RP1 — T0CS RP0 T0SE TO PSA PD PS2 Z PS1 DC PS0 C Program Counter (PC) Least Significant Byte Indirect Data Memory Address Pointer PORTA Data Direction Register PORTB Data Direction Register PORTC Data Direction Register PORTD Data Direction Register IBF — GIE PSPIE(2) — — OBF — PEIE ADIE (5) — IBOV — T0IE RCIE — — PSPMODE INTE TXIE EEIE — — RBIE SSPIE BCLIE — PORTE Data Direction Bits T0IF CCP1IE — — INTF TMR2IE — POR RBIF TMR1IE CCP2IE BOR Write Buffer for the upper 5 bits of the Program Counter 0000 0000 1111 1111 0000 0000 0001 1xxx xxxx xxxx --11 1111 1111 1111 1111 1111 1111 1111 0000 -111 ---0 0000 0000 000x 0000 0000 -r-0 0--0 ---- --qq SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Details on page: Name 27 19 26 18 27 29 31 33 35 37 26 20 21 23 25 — — 68 55 73, 74 66 — — — 95 97 — — — — 116 112 Unimplemented Unimplemented GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN Timer2 Period Register Synchronous Serial Port (I2C mode) Address Register SMP CKE D/A P S R/W UA BF Unimplemented Unimplemented Unimplemented CSRC TX9 TXEN SYNC — BRGH TRMT TX9D Baud Rate Generator Register Unimplemented Unimplemented Unimplemented Unimplemented A/D Result Register Low Byte ADFM — — — PCFG3 PCFG2 PCFG1 PCFG0 — — 0000 0000 1111 1111 0000 0000 0000 0000 — — — 0000 -010 0000 0000 — — — — xxxx xxxx 0--- 0000 x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved. Shaded locations are unimplemented, read as ‘0’. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC whose contents are transferred to the upper byte of the program counter. Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear. These registers can be addressed from any bank. PORTD, PORTE, TRISD, and TRISE are not physically implemented on PIC16F873/876 devices; read as ‘0’. PIR2 and PIE2 are reserved on these devices; always maintain these bits clear. DS30292C-page 16  2001 Microchip Technology Inc. PIC16F87X TABLE 2-1: Address Bank 2 100h(3) 101h 102h(3) 103h(3) 104h(3) 105h 106h 107h 108h 109h 10Ah(1,3) 10Bh(3) 10Ch 10Dh 10Eh 10Fh Bank 3 180h(3) 181h 182h(3) 183h(3) 184h(3) 185h 186h 187h 188h 189h 18Ah(1,3) 18Bh(3) 18Ch 18Dh 18Eh 18Fh Legend: Note 1: 2: 3: 4: 5: INDF OPTION_REG PCL STATUS FSR — TRISB — — — PCLATH INTCON EECON1 EECON2 — — Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU IRP INTEDG RP1 T0CS RP0 T0SE TO PSA PD PS2 Z PS1 DC PS0 C Program Counter (PC) Least Significant Byte Indirect Data Memory Address Pointer Unimplemented PORTB Data Direction Register Unimplemented Unimplemented Unimplemented — GIE EEPGD — PEIE — — T0IE — Write Buffer for the upper 5 bits of the Program Counter INTE — RBIE WRERR T0IF WREN INTF WR RBIF RD 0000 0000 1111 1111 0000 0000 0001 1xxx xxxx xxxx SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Details on page: Name INDF TMR0 PCL STATUS FSR — PORTB — — — PCLATH INTCON EEDATA EEADR EEDATH EEADRH Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module Register Program Counter’s (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C Indirect Data Memory Address Pointer Unimplemented PORTB Data Latch when written: PORTB pins when read Unimplemented Unimplemented Unimplemented — GIE — PEIE — T0IE Write Buffer for the upper 5 bits of the Program Counter INTE RBIE T0IF INTF RBIF 0000 0000 xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx 27 47 26 18 27 — 31 — — — 26 20 41 41 41 41 27 19 26 18 27 — 31 — — — 26 20 41, 42 41 — — — xxxx xxxx — — — ---0 0000 0000 000x xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx EEPROM Data Register Low Byte EEPROM Address Register Low Byte — — — — EEPROM Data Register High Byte — EEPROM Address Register High Byte — 1111 1111 — — — ---0 0000 0000 000x x--- x000 ---- ---0000 0000 0000 0000 EEPROM Control Register2 (not a physical register) Reserved maintain clear Reserved maintain clear x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved. Shaded locations are unimplemented, read as ‘0’. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC whose contents are transferred to the upper byte of the program counter. Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear. These registers can be addressed from any bank. PORTD, PORTE, TRISD, and TRISE are not physically implemented on PIC16F873/876 devices; read as ‘0’. PIR2 and PIE2 are reserved on these devices; always maintain these bits clear.  2001 Microchip Technology Inc. DS30292C-page 17 PIC16F87X 2.2.2.1 STATUS Register The STATUS register contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable, therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the Z, C or DC bits from the STATUS register. For other instructions not affecting any status bits, see the “Instruction Set Summary." Note: The C and DC bits operate as a borrow and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. REGISTER 2-1: STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h) R/W-0 IRP bit 7 R/W-0 RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit 0 bit 7 IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh) RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow, the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high, or low order bit of the source register. bit 6-5 bit 4 bit 3 bit 2 bit 1 bit 0 Legend: R = Readable bit - n = Value at POR W = Writable bit ’1’ = Bit is set U = Unimplemented bit, read as ‘0’ ’0’ = Bit is cleared x = Bit is unknown DS30292C-page 18  2001 Microchip Technology Inc. PIC16F87X 2.2.2.2 OPTION_REG Register Note: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer. The OPTION_REG Register is a readable and writable register, which contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the External INT Interrupt, TMR0 and the weak pull-ups on PORTB. REGISTER 2-2: OPTION_REG REGISTER (ADDRESS 81h, 181h) R/W-1 RBPU bit 7 R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit 0 bit 7 RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS2:PS0: Prescaler Rate Select bits Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate WDT Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 bit 6 bit 5 bit 4 bit 3 bit 2-0 Legend: R = Readable bit - n = Value at POR Note: W = Writable bit ’1’ = Bit is set U = Unimplemented bit, read as ‘0’ ’0’ = Bit is cleared x = Bit is unknown When using low voltage ICSP programming (LVP) and the pull-ups on PORTB are enabled, bit 3 in the TRISB register must be cleared to disable the pull-up on RB3 and ensure the proper operation of the device  2001 Microchip Technology Inc. DS30292C-page 19 PIC16F87X 2.2.2.3 INTCON Register Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The INTCON Register is a readable and writable register, which contains various enable and flag bits for the TMR0 register overflow, RB Port change and External RB0/INT pin interrupts. REGISTER 2-3: INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh) R/W-0 GIE bit 7 R/W-0 PEIE R/W-0 T0IE R/W-0 INTE R/W-0 RBIE R/W-0 T0IF R/W-0 INTF R/W-x RBIF bit 0 bit 7 GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state; a mismatch condition will continue to set the bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared (must be cleared in software). 0 = None of the RB7:RB4 pins have changed state Legend: R = Readable bit - n = Value at POR W = Writable bit ’1’ = Bit is set U = Unimplemented bit, read as ‘0’ ’0’ = Bit is cleared x = Bit is unknown bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS30292C-page 20  2001 Microchip Technology Inc. PIC16F87X 2.2.2.4 PIE1 Register Note: Bit PEIE (INTCON) must be set to enable any peripheral interrupt. The PIE1 register contains the individual enable bits for the peripheral interrupts. REGISTER 2-4: PIE1 REGISTER (ADDRESS 8Ch) R/W-0 PSPIE(1) bit 7 R/W-0 ADIE R/W-0 RCIE R/W-0 TXIE R/W-0 SSPIE R/W-0 CCP1IE R/W-0 TMR2IE R/W-0 TMR1IE bit 0 bit 7 PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D converter interrupt 0 = Disables the A/D converter interrupt RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: PSPIE is reserved on PIC16F873/876 devices; always maintain this bit clear. Legend: R = Readable bit - n = Value at POR W = Writable bit ’1’ = Bit is set U = Unimplemented bit, read as ‘0’ ’0’ = Bit is cleared x = Bit is unknown bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0  2001 Microchip Technology Inc. DS30292C-page 21 PIC16F87X 2.2.2.5 PIR1 Register Note: The PIR1 register contains the individual flag bits for the peripheral interrupts. Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON). User software should ensure the appropriate interrupt bits are clear prior to enabling an interrupt. REGISTER 2-5: PIR1 REGISTER (ADDRESS 0Ch) R/W-0 PSPIF(1) bit 7 R/W-0 ADIF R-0 RCIF R-0 TXIF R/W-0 SSPIF R/W-0 CCP1IF R/W-0 TMR2IF R/W-0 TMR1IF bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed 0 = The A/D conversion is not complete RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer is full 0 = The USART receive buffer is empty TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer is empty 0 = The USART transmit buffer is full SSPIF: Synchronous Serial Port (SSP) Interrupt Flag 1 = The SSP interrupt condition has occurred, and must be cleared in software before returning from the Interrupt Service Routine. The conditions that will set this bit are: • SPI - A transmission/reception has taken place. • I2C Slave - A transmission/reception has taken place. • I2C Master - A transmission/reception has taken place. - The initiated START condition was completed by the SSP module. - The initiated STOP condition was completed by the SSP module. - The initiated Restart condition was completed by the SSP module. - The initiated Acknowledge condition was completed by the SSP module. - A START condition occurred while the SSP module was idle (Multi-Master system). - A STOP condition occurred while the SSP module was idle (Multi-Master system). 0 = No SSP interrupt condition has occurred. CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Note 1: PSPIF is reserved on PIC16F873/876 devices; always maintain this bit clear. Legend: R = Readable bit - n = Value at POR W = Writable bit ’1’ = Bit is set U = Unimplemented bit, read as ‘0’ ’0’ = Bit is cleared x = Bit is unknown  2001 Microchip Technology Inc. DS30292C-page 22 PIC16F87X 2.2.2.6 PIE2 Register The PIE2 register contains the individual enable bits for the CCP2 peripheral interrupt, the SSP bus collision interrupt, and the EEPROM write operation interrupt. REGISTER 2-6: PIE2 REGISTER (ADDRESS 8Dh) U-0 — bit 7 R/W-0 Reserved U-0 — R/W-0 EEIE R/W-0 BCLIE U-0 — U-0 — R/W-0 CCP2IE bit 0 bit 7 bit 6 bit 5 bit 4 Unimplemented: Read as '0' Reserved: Always maintain this bit clear Unimplemented: Read as '0' EEIE: EEPROM Write Operation Interrupt Enable 1 = Enable EE Write Interrupt 0 = Disable EE Write Interrupt BCLIE: Bus Collision Interrupt Enable 1 = Enable Bus Collision Interrupt 0 = Disable Bus Collision Interrupt Unimplemented: Read as '0' CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt Legend: R = Readable bit - n = Value at POR W = Writable bit ’1’ = Bit is set U = Unimplemented bit, read as ‘0’ ’0’ = Bit is cleared x = Bit is unknown bit 3 bit 2-1 bit 0  2001 Microchip Technology Inc. DS30292C-page 23 PIC16F87X 2.2.2.7 PIR2 Register . The PIR2 register contains the flag bits for the CCP2 interrupt, the SSP bus collision interrupt and the EEPROM write operation interrupt. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 2-7: PIR2 REGISTER (ADDRESS 0Dh) U-0 — bit 7 R/W-0 Reserved U-0 — R/W-0 EEIF R/W-0 BCLIF U-0 — U-0 — R/W-0 CCP2IF bit 0 bit 7 bit 6 bit 5 bit 4 Unimplemented: Read as '0' Reserved: Always maintain this bit clear Unimplemented: Read as '0' EEIF: EEPROM Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software) 0 = The write operation is not complete or has not been started BCLIF: Bus Collision Interrupt Flag bit 1 = A bus collision has occurred in the SSP, when configured for I2C Master mode 0 = No bus collision has occurred Unimplemented: Read as '0' CCP2IF: CCP2 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused Legend: R = Readable bit - n = Value at POR W = Writable bit ’1’ = Bit is set U = Unimplemented bit, read as ‘0’ ’0’ = Bit is cleared x = Bit is unknown bit 3 bit 2-1 bit 0 DS30292C-page 24  2001 Microchip Technology Inc. PIC16F87X 2.2.2.8 PCON Register Note: The Power Control (PCON) Register contains flag bits to allow differentiation between a Power-on Reset (POR), a Brown-out Reset (BOR), a Watchdog Reset (WDT), and an external MCLR Reset. BOR is unknown on POR. It must be set by the user and checked on subsequent RESETS to see if BOR is clear, indicating a brown-out has occurred. The BOR status bit is a “don’t care” and is not predictable if the brown-out circuit is disabled (by clearing the BODEN bit in the configuration word). REGISTER 2-8: PCON REGISTER (ADDRESS 8Eh) U-0 — bit 7 U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 POR R/W-1 BOR bit 0 bit 7-2 bit 1 Unimplemented: Read as '0' POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend: R = Readable bit - n = Value at POR W = Writable bit ’1’ = Bit is set U = Unimplemented bit, read as ‘0’ ’0’ = Bit is cleared x = Bit is unknown bit 0  2001 Microchip Technology Inc. DS30292C-page 25 PIC16F87X 2.3 PCL and PCLATH The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The upper bits (PC) are not readable, but are indirectly writable through the PCLATH register. On any RESET, the upper bits of the PC will be cleared. Figure 2-5 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH → PCH). The lower example in the figure shows how the PC is loaded during a CALL or GOTO instruction (PCLATH → PCH). Note 1: There are no status bits to indicate stack overflow or stack underflow conditions. 2: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions, or the vectoring to an interrupt address. 2.4 Program Memory Paging FIGURE 2-5: LOADING OF PC IN DIFFERENT SITUATIONS PCL 8 7 0 Instruction with PCL as Destination ALU PCH 12 PC 5 PCLATH 8 PCLATH PCH 12 PC 2 PCLATH 11 Opcode PCLATH 11 10 8 7 PCL 0 GOTO,CALL All PIC16F87X devices are capable of addressing a continuous 8K word block of program memory. The CALL and GOTO instructions provide only 11 bits of address to allow branching within any 2K program memory page. When doing a CALL or GOTO instruction, the upper 2 bits of the address are provided by PCLATH. When doing a CALL or GOTO instruction, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is popped off the stack. Therefore, manipulation of the PCLATH bits is not required for the return instructions (which POPs the address from the stack). Note: The contents of the PCLATH register are unchanged after a RETURN or RETFIE instruction is executed. The user must rewrite the contents of the PCLATH register for any subsequent subroutine calls or GOTO instructions. 2.3.1 COMPUTED GOTO Example 2-1 shows the calling of a subroutine in page 1 of the program memory. This example assumes that PCLATH is saved and restored by the Interrupt Service Routine (if interrupts are used). A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256 byte block). Refer to the application note, “Implementing a Table Read" (AN556). EXAMPLE 2-1: CALL OF A SUBROUTINE IN PAGE 1 FROM PAGE 0 ORG 0x500 BCF PCLATH,4 BSF PCLATH,3 CALL SUB1_P1 : : ORG 0x900 SUB1_P1 : : RETURN 2.3.2 STACK ;Select page 1 ;(800h-FFFh) ;Call subroutine in ;page 1 (800h-FFFh) ;page 1 (800h-FFFh) ;called subroutine ;page 1 (800h-FFFh) ;return to ;Call subroutine ;in page 0 ;(000h-7FFh) The PIC16F87X family has an 8-level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed, or an interrupt causes a branch. The stack is POPed in the event of a RETURN,RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). DS30292C-page 26  2001 Microchip Technology Inc. PIC16F87X 2.5 Indirect Addressing, INDF and FSR Registers A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 2-2. The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses the register pointed to by the File Select Register, FSR. Reading the INDF register itself, indirectly (FSR = ’0’) will read 00h. Writing to the INDF register indirectly results in a no operation (although status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS), as shown in Figure 2-6. EXAMPLE 2-2: MOVLW MOVWF CLRF INCF BTFSS GOTO : INDIRECT ADDRESSING 0x20 FSR INDF FSR,F FSR,4 NEXT ;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;no clear next ;yes continue NEXT CONTINUE FIGURE 2-6: DIRECT/INDIRECT ADDRESSING Direct Addressing Indirect Addressing 0 IRP 7 FSR register 0 RP1:RP0 6 From Opcode Bank Select Location Select 00 00h 01 80h 10 100h 11 180h Bank Select Location Select Data Memory(1) 7Fh Bank 0 FFh Bank 1 17Fh Bank 2 1FFh Bank 3 Note 1: For register file map detail, see Figure 2-3.  2001 Microchip Technology Inc. DS30292C-page 27 PIC16F87X NOTES: DS30292C-page 28  2001 Microchip Technology Inc. PIC16F87X 3.0 I/O PORTS FIGURE 3-1: Data Bus Data Latch D Q VDD CK Q P I/O pin(1) Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Additional information on I/O ports may be found in the PICmicro™ Mid-Range Reference Manual, (DS33023). BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS WR Port 3.1 PORTA and the TRISA Register WR TRIS TRIS Latch D Q N PORTA is a 6-bit wide, bi-directional port. The corresponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). Reading the PORTA register reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, the value is modified and then written to the port data latch. Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output. All other PORTA pins have TTL input levels and full CMOS output drivers. Other PORTA pins are multiplexed with analog inputs and analog VREF input. The operation of each pin is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register1). Note: On a Power-on Reset, these pins are configured as analog inputs and read as '0'. CK Q VSS Analog Input Mode RD TRIS TTL Input Buffer Q D EN RD Port To A/D Converter Note 1: I/O pins have protection diodes to VDD and VSS. FIGURE 3-2: Data Bus WR Port BLOCK DIAGRAM OF RA4/T0CKI PIN Data Latch D Q Q N TRIS Latch D Q Q VSS Schmitt Trigger Input Buffer The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. CK I/O pin(1) EXAMPLE 3-1: BCF BCF CLRF INITIALIZING PORTA ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Bank0 Initialize PORTA by clearing output data latches Select Bank 1 Configure all pins as digital inputs Value used to initialize data direction Set RA as inputs RA as outputs TRISAare always read as ’0’. WR TRIS STATUS, RP0 STATUS, RP1 PORTA CK RD TRIS BSF MOVLW MOVWF MOVLW STATUS, RP0 0x06 ADCON1 0xCF Q D EN EN MOVWF TRISA RD Port TMR0 Clock Input Note 1: I/O pin has protection diodes to VSS only.  2001 Microchip Technology Inc. DS30292C-page 29 PIC16F87X TABLE 3-1: Name RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/SS/AN4 PORTA FUNCTIONS Bit# bit0 bit1 bit2 bit3 bit4 bit5 Buffer TTL TTL TTL TTL ST TTL Input/output or analog input. Input/output or analog input. Input/output or analog input. Input/output or analog input or VREF. Input/output or external clock input for Timer0. Output is open drain type. Input/output or slave select input for synchronous serial port or analog input. Function Legend: TTL = TTL input, ST = Schmitt Trigger input TABLE 3-2: Address 05h 85h 9Fh SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 — — Bit 6 — — — Bit 5 RA5 — Bit 4 RA4 — Bit 3 RA3 Bit 2 RA2 Bit 1 RA1 Bit 0 RA0 Value on: Value on all POR, other BOR RESETS --0x 0000 --11 1111 --0- 0000 --0u 0000 --11 1111 --0- 0000 Name PORTA TRISA PORTA Data Direction Register PCFG3 PCFG2 PCFG1 PCFG0 ADCON1 ADFM Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA. Note: When using the SSP module in SPI Slave mode and SS enabled, the A/D converter must be set to one of the following modes, where PCFG3:PCFG0 = 0100,0101, 011x, 1101, 1110, 1111. DS30292C-page 30  2001 Microchip Technology Inc. PIC16F87X 3.2 PORTB and the TRISB Register PORTB is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). Three pins of PORTB are multiplexed with the Low Voltage Programming function: RB3/PGM, RB6/PGC and RB7/PGD. The alternate functions of these pins are described in the Special Features Section. Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION_REG). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. This interrupt can wake the device from SLEEP. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) b) Any read or write of PORTB. This will end the mismatch condition. Clear flag bit RBIF. A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. This interrupt-on-mismatch feature, together with software configureable pull-ups on these four pins, allow easy interface to a keypad and make it possible for wake-up on key depression. Refer to the Embedded Control Handbook, “Implementing Wake-up on Key Strokes” (AN552). RB0/INT is an external interrupt input pin and is configured using the INTEDG bit (OPTION_REG). RB0/INT is discussed in detail in Section 12.10.1. FIGURE 3-3: BLOCK DIAGRAM OF RB3:RB0 PINS VDD Weak P Pull-up Data Latch D CK TRIS Latch D Q TTL Input Buffer Q I/O pin(1) RBPU(2) Data Bus WR Port FIGURE 3-4: BLOCK DIAGRAM OF RB7:RB4 PINS VDD Weak P Pull-up Data Latch D Q CK TRIS Latch D Q I/O pin(1) RBPU(2) WR TRIS CK Data Bus WR Port RD TRIS Q RD Port EN RB0/INT RB3/PGM Schmitt Trigger Buffer RD Port RD Port EN Set RBIF Q1 D WR TRIS CK TTL Input Buffer ST Buffer RD TRIS Q Latch D Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG). Four of the PORTB pins, RB7:RB4, have an interrupton-change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupton-change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The “mismatch” outputs of RB7:RB4 are OR’ed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON). Q From other RB7:RB4 pins RB7:RB6 In Serial Programming Mode D RD Port EN Q3 Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG).  2001 Microchip Technology Inc. DS30292C-page 31 PIC16F87X TABLE 3-3: Name RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD Legend: Note 1: 2: 3: (3) PORTB FUNCTIONS Bit# bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Buffer TTL/ST(1) TTL TTL TTL TTL TTL TTL/ST(2) TTL/ST(2) Function Input/output pin or external interrupt input. Internal software programmable weak pull-up. Input/output pin. Internal software programmable weak pull-up. Input/output pin. Internal software programmable weak pull-up. Input/output pin or programming pin in LVP mode. Internal software programmable weak pull-up. Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Input/output pin (with interrupt-on-change) or In-Circuit Debugger pin. Internal software programmable weak pull-up. Serial programming clock. Input/output pin (with interrupt-on-change) or In-Circuit Debugger pin. Internal software programmable weak pull-up. Serial programming data. TTL = TTL input, ST = Schmitt Trigger input This buffer is a Schmitt Trigger input when configured as the external interrupt. This buffer is a Schmitt Trigger input when used in Serial Programming mode. Low Voltage ICSP Programming (LVP) is enabled by default, which disables the RB3 I/O function. LVP must be disabled to enable RB3 as an I/O pin and allow maximum compatibility to the other 28-pin and 40-pin mid-range devices. TABLE 3-4: Address 06h, 106h 86h, 186h 81h, 181h SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Name Bit 7 RB7 Bit 6 RB6 INTEDG Bit 5 RB5 Bit 4 RB4 Bit 3 Bit 2 Bit 1 Bit 0 RB3 PSA RB2 PS2 RB1 PS1 Value on: POR, BOR Value on all other RESETS PORTB TRISB RB0 xxxx xxxx uuuu uuuu 1111 1111 1111 1111 PORTB Data Direction Register T0CS T0SE PS0 OPTION_REG RBPU 1111 1111 1111 1111 Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB. DS30292C-page 32  2001 Microchip Technology Inc. PIC16F87X 3.3 PORTC and the TRISC Register FIGURE 3-6: PORTC is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). PORTC is multiplexed with several peripheral functions (Table 3-5). PORTC pins have Schmitt Trigger input buffers. When the I2C module is enabled, the PORTC pins can be configured with normal I2C levels, or with SMBus levels by using the CKE bit (SSPSTAT). When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. Since the TRIS bit override is in effect while the peripheral is enabled, read-modifywrite instructions (BSF, BCF, XORWF) with TRISC as destination, should be avoided. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE) RC Port/Peripheral Select(2) Peripheral Data Out Data Bus WR Port D CK Q Q 1 0 VDD P I/O pin(1) Data Latch WR TRIS D CK Q Q N Vss Schmitt Trigger Q D EN 0 Schmitt Trigger with SMBus levels TRIS Latch RD TRIS Peripheral OE(3) RD Port SSPl Input 1 CKE SSPSTAT Note 1: I/O pins have diode protection to VDD and VSS. 2: Port/Peripheral select signal selects between port data and peripheral output. 3: Peripheral OE (output enable) is only activated if peripheral select is active. FIGURE 3-5: PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE) RC, RC Port/Peripheral Select(2) Peripheral Data Out Data Bus WR Port D CK Q Q 0 VDD P I/O pin(1) 1 Data Latch WR TRIS D CK Q Q N VSS Schmitt Trigger Q D EN TRIS Latch RD TRIS Peripheral OE(3) RD Port Peripheral Input Note 1: I/O pins have diode protection to VDD and VSS. 2: Port/Peripheral select signal selects between port data and peripheral output. 3: Peripheral OE (output enable) is only activated if peripheral select is active.  2001 Microchip Technology Inc. DS30292C-page 33 PIC16F87X TABLE 3-5: Name RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT PORTC FUNCTIONS Bit# bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Buffer Type ST ST ST ST ST ST ST ST Function Input/output port pin or Timer1 oscillator output/Timer1 clock input. Input/output port pin or Timer1 oscillator input or Capture2 input/ Compare2 output/PWM2 output. Input/output port pin or Capture1 input/Compare1 output/ PWM1 output. RC3 can also be the synchronous serial clock for both SPI and I2C modes. RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). Input/output port pin or Synchronous Serial Port data output. Input/output port pin or USART Asynchronous Transmit or Synchronous Clock. Input/output port pin or USART Asynchronous Receive or Synchronous Data. Legend: ST = Schmitt Trigger input TABLE 3-6: Address 07h 87h SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 7 RC7 Bit 6 RC6 Bit 5 RC5 Bit 4 RC4 Bit 3 RC3 Bit 2 RC2 Bit 1 RC1 Bit 0 RC0 Value on: POR, BOR xxxx xxxx 1111 1111 Name PORTC TRISC Value on all other RESETS uuuu uuuu 1111 1111 PORTC Data Direction Register Legend: x = unknown, u = unchanged DS30292C-page 34  2001 Microchip Technology Inc. PIC16F87X 3.4 PORTD and TRISD Registers FIGURE 3-7: Data Bus WR Port PORTD and TRISD are not implemented on the PIC16F873 or PIC16F876. PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configureable as an input or output. PORTD can be configured as an 8-bit wide microprocessor port (parallel slave port) by setting control bit PSPMODE (TRISE). In this mode, the input buffers are TTL. PORTD BLOCK DIAGRAM (IN I/O PORT MODE) I/O pin(1) Data Latch D Q CK TRIS Latch D Q WR TRIS CK Schmitt Trigger Input Buffer RD TRIS Q D EN EN RD Port Note 1: I/O pins have protection diodes to VDD and VSS. TABLE 3-7: Name RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 PORTD FUNCTIONS Bit# bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Buffer Type ST/TTL(1) ST/TTL(1) ST/TTL(1) ST/TTL ST/TTL (1) Function Input/output port pin or parallel slave port bit0. Input/output port pin or parallel slave port bit1. Input/output port pin or parallel slave port bit2. Input/output port pin or parallel slave port bit3. Input/output port pin or parallel slave port bit4. Input/output port pin or parallel slave port bit5. Input/output port pin or parallel slave port bit6. Input/output port pin or parallel slave port bit7. ST/TTL(1) (1) ST/TTL(1) ST/TTL(1) Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode. TABLE 3-8: Address 08h 88h 89h SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Bit 7 RD7 IBF Bit 6 RD6 Bit 5 RD5 Bit 4 RD4 Bit 3 RD3 — Bit 2 RD2 Bit 1 RD1 Bit 0 RD0 Value on: POR, BOR xxxx xxxx 1111 1111 Name PORTD TRISD TRISE Value on all other RESETS uuuu uuuu 1111 1111 0000 -111 PORTD Data Direction Register OBF IBOV PSPMODE PORTE Data Direction Bits 0000 -111 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTD.  2001 Microchip Technology Inc. DS30292C-page 35 PIC16F87X 3.5 PORTE and TRISE Register FIGURE 3-8: PORTE and TRISE are not implemented on the PIC16F873 or PIC16F876. PORTE has three pins (RE0/RD/AN5, RE1/WR/AN6, and RE2/CS/AN7) which are individually configureable as inputs or outputs. These pins have Schmitt Trigger input buffers. The PORTE pins become the I/O control inputs for the microprocessor port when bit PSPMODE (TRISE) is set. In this mode, the user must make certain that the TRISE bits are set, and that the pins are configured as digital inputs. Also ensure that ADCON1 is configured for digital I/O. In this mode, the input buffers are TTL. Register 3-1 shows the TRISE register, which also controls the parallel slave port operation. PORTE pins are multiplexed with analog inputs. When selected for analog input, these pins will read as ’0’s. TRISE controls the direction of the RE pins, even when they are being used as analog inputs. The user must make sure to keep the pins configured as inputs when using them as analog inputs. Note: On a Power-on Reset, these pins are configured as analog inputs, and read as ‘0’. PORTE BLOCK DIAGRAM (IN I/O PORT MODE) I/O pin(1) Data Bus WR Port Data Latch D Q CK TRIS Latch D Q Schmitt Trigger Input Buffer WR TRIS CK RD TRIS Q D EN EN RD Port Note 1: I/O pins have protection diodes to VDD and VSS. TABLE 3-9: Name PORTE FUNCTIONS Bit# Buffer Type Function I/O port pin or read control input in Parallel Slave Port mode or analog input: RD 1 = Idle 0 = Read operation. Contents of PORTD register are output to PORTD I/O pins (if chip selected) I/O port pin or write control input in Parallel Slave Port mode or analog input: WR 1 = Idle 0 = Write operation. Value of PORTD I/O pins is latched into PORTD register (if chip selected) I/O port pin or chip select control input in Parallel Slave Port mode or analog input: CS 1 = Device is not selected 0 = Device is selected RE0/RD/AN5 bit0 ST/TTL(1) RE1/WR/AN6 bit1 ST/TTL(1) RE2/CS/AN7 bit2 ST/TTL(1) Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode. TABLE 3-10: Address 09h 89h 9Fh SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Bit 7 — IBF ADFM Bit 6 — OBF — Bit 5 — IBOV — Bit 4 — PSPMODE — Bit 3 — — PCFG3 Bit 2 RE2 PCFG2 Bit 1 RE1 PCFG1 Bit 0 RE0 PCFG0 Value on: POR, BOR ---- -xxx 0000 -111 --0- 0000 Name PORTE TRISE ADCON1 Value on all other RESETS ---- -uuu 0000 -111 --0- 0000 PORTE Data Direction Bits Legend: x = unknown, u = unchanged, - = unimplemented, read as ’0’. Shaded cells are not used by PORTE. DS30292C-page 36  2001 Microchip Technology Inc. PIC16F87X REGISTER 3-1: TRISE REGISTER (ADDRESS 89h) R-0 IBF bit 7 Parallel Slave Port Status/Control Bits: bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode) 1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred PSPMODE: Parallel Slave Port Mode Select bit 1 = PORTD functions in Parallel Slave Port mode 0 = PORTD functions in general purpose I/O mode Unimplemented: Read as '0' PORTE Data Direction Bits: bit 2 Bit2: Direction Control bit for pin RE2/CS/AN7 1 = Input 0 = Output Bit1: Direction Control bit for pin RE1/WR/AN6 1 = Input 0 = Output Bit0: Direction Control bit for pin RE0/RD/AN5 1 = Input 0 = Output Legend: R = Readable bit - n = Value at POR W = Writable bit ’1’ = Bit is set U = Unimplemented bit, read as ‘0’ ’0’ = Bit is cleared x = Bit is unknown R-0 OBF R/W-0 IBOV R/W-0 PSPMODE U-0 — R/W-1 Bit2 R/W-1 Bit1 R/W-1 Bit0 bit 0 bit 6 bit 5 bit 4 bit 3 bit 1 bit 0  2001 Microchip Technology Inc. DS30292C-page 37 PIC16F87X 3.6 Parallel Slave Port The Parallel Slave Port (PSP) is not implemented on the PIC16F873 or PIC16F876. PORTD operates as an 8-bit wide Parallel Slave Port or microprocessor port, when control bit PSPMODE (TRISE) is set. In Slave mode, it is asynchronously readable and writable by the external world through RD control input pin RE0/RD and WR control input pin RE1/WR. The PSP can directly interface to an 8-bit microprocessor data bus. The external microprocessor can read or write the PORTD latch as an 8-bit latch. Setting bit PSPMODE enables port pin RE0/RD to be the RD input, RE1/WR to be the WR input and RE2/CS to be the CS (chip select) input. For this functionality, the corresponding data direction bits of the TRISE register (TRISE) must be configured as inputs (set). The A/D port configuration bits PCFG3:PCFG0 (ADCON1) must be set to configure pins RE2:RE0 as digital I/O. There are actually two 8-bit latches: one for data output, and one for data input. The user writes 8-bit data to the PORTD data latch and reads data from the port pin latch (note that they have the same address). In this mode, the TRISD register is ignored, since the external device is controlling the direction of data flow. A write to the PSP occurs when both the CS and WR lines are first detected low. When either the CS or WR lines become high (level triggered), the Input Buffer Full (IBF) status flag bit (TRISE) is set on the Q4 clock cycle, following the next Q2 cycle, to signal the write is complete (Figure 3-10). The interrupt flag bit PSPIF (PIR1) is also set on the same Q4 clock cycle. IBF can only be cleared by reading the PORTD input latch. The Input Buffer Overflow (IBOV) status flag bit (TRISE) is set if a second write to the PSP is attempted when the previous byte has not been read out of the buffer. A read from the PSP occurs when both the CS and RD lines are first detected low. The Output Buffer Full (OBF) status flag bit (TRISE) is cleared immediately (Figure 3-11), indicating that the PORTD latch is waiting to be read by the external bus. When either the CS or RD pin becomes high (level triggered), the interrupt flag bit PSPIF is set on the Q4 clock cycle, following the next Q2 cycle, indicating that the read is complete. OBF remains low until data is written to PORTD by the user firmware. When not in PSP mode, the IBF and OBF bits are held clear. However, if flag bit IBOV was previously set, it must be cleared in firmware. An interrupt is generated and latched into flag bit PSPIF when a read or write operation is completed. PSPIF must be cleared by the user in firmware and the interrupt can be disabled by clearing the interrupt enable bit PSPIE (PIE1). FIGURE 3-9: PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) Data Bus D WR Port Q RDx pin TTL Q RD Port One bit of PORTD Set Interrupt Flag PSPIF(PIR1) D EN EN CK Read TTL RD Chip Select TTL Write TTL Note 1: I/O pins have protection diodes to VDD and VSS. CS WR DS30292C-page 38  2001 Microchip Technology Inc. PIC16F87X FIGURE 3-10: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD IBF OBF PSPIF FIGURE 3-11: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD IBF OBF PSPIF TABLE 3-11: Address 08h 09h 89h 0Ch 8Ch 9Fh REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other RESETS Name PORTD PORTE TRISE PIR1 PIE1 ADCON1 Port Data Latch when written: Port pins when read — IBF PSPIF(1) PSPIE(1) ADFM — OBF ADIF ADIE — — IBOV RCIF RCIE — — PSPMODE TXIF TXIE — — — SSPIF SSPIE PCFG3 RE2 CCP1IF CCP1IE PCFG2 RE1 TMR2IF PCFG1 RE0 PORTE Data Direction Bits xxxx xxxx uuuu uuuu ---- -xxx ---- -uuu 0000 -111 0000 -111 TMR1IF 0000 0000 0000 0000 PCFG0 --0- 0000 --0- 0000 TMR2IE TMR1IE 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Parallel Slave Port. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F873/876; always maintain these bits clear.  2001 Microchip Technology Inc. DS30292C-page 39 PIC16F87X NOTES: DS30292C-page 40  2001 Microchip Technology Inc. PIC16F87X 4.0 DATA EEPROM AND FLASH PROGRAM MEMORY The EEPROM data memory allows byte read and write operations without interfering with the normal operation of the microcontroller. When interfacing to EEPROM data memory, the EEADR register holds the address to be accessed. Depending on the operation, the EEDATA register holds the data to be written, or the data read, at the address in EEADR. The PIC16F873/874 devices have 128 bytes of EEPROM data memory and therefore, require that the MSb of EEADR remain clear. The EEPROM data memory on these devices do not wrap around to 0, i.e., 0x80 in the EEADR does not map to 0x00. The PIC16F876/877 devices have 256 bytes of EEPROM data memory and therefore, uses all 8-bits of the EEADR. The FLASH program memory allows non-intrusive read access, but write operations cause the device to stop executing instructions, until the write completes. When interfacing to the program memory, the EEADRH:EEADR registers form a two-byte word, which holds the 13-bit address of the memory location being accessed. The register combination of EEDATH:EEDATA holds the 14-bit data for writes, or reflects the value of program memory after a read operation. Just as in EEPROM data memory accesses, the value of the EEADRH:EEADR registers must be within the valid range of program memory, depending on the device: 0000h to 1FFFh for the PIC16F873/874, or 0000h to 3FFFh for the PIC16F876/877. Addresses outside of this range do not wrap around to 0000h (i.e., 4000h does not map to 0000h on the PIC16F877). The Data EEPROM and FLASH Program Memory are readable and writable during normal operation over the entire VDD range. These operations take place on a single byte for Data EEPROM memory and a single word for Program memory. A write operation causes an erase-then-write operation to take place on the specified byte or word. A bulk erase operation may not be issued from user code (which includes removing code protection). Access to program memory allows for checksum calculation. The values written to program memory do not need to be valid instructions. Therefore, up to 14-bit numbers can be stored in memory for use as calibration parameters, serial numbers, packed 7-bit ASCII, etc. Executing a program memory location containing data that form an invalid instruction, results in the execution of a NOP instruction. The EEPROM Data memory is rated for high erase/ write cycles (specification D120). The FLASH program memory is rated much lower (specification D130), because EEPROM data memory can be used to store frequently updated values. An on-chip timer controls the write time and it will vary with voltage and temperature, as well as from chip to chip. Please refer to the specifications for exact limits (specifications D122 and D133). A byte or word write automatically erases the location and writes the new value (erase before write). Writing to EEPROM data memory does not impact the operation of the device. Writing to program memory will cease the execution of instructions until the write is complete. The program memory cannot be accessed during the write. During the write operation, the oscillator continues to run, the peripherals continue to function and interrupt events will be detected and essentially “queued” until the write is complete. When the write completes, the next instruction in the pipeline is executed and the branch to the interrupt vector will take place, if the interrupt is enabled and occurred during the write. Read and write access to both memories take place indirectly through a set of Special Function Registers (SFR). The six SFRs used are: • • • • • • EEDATA EEDATH EEADR EEADRH EECON1 EECON2 4.1 EECON1 and EECON2 Registers The EECON1 register is the control register for configuring and initiating the access. The EECON2 register is not a physically implemented register, but is used exclusively in the memory write sequence to prevent inadvertent writes. There are many bits used to control the read and write operations to EEPROM data and FLASH program memory. The EEPGD bit determines if the access will be a program or data memory access. When clear, any subsequent operations will work on the EEPROM data memory. When set, all subsequent operations will operate in the program memory. Read operations only use one additional bit, RD, which initiates the read operation from the desired memory location. Once this bit is set, the value of the desired memory location will be available in the data registers. This bit cannot be cleared by firmware. It is automatically cleared at the end of the read operation. For EEPROM data memory reads, the data will be available in the EEDATA register in the very next instruction cycle after the RD bit is set. For program memory reads, the data will be loaded into the EEDATH:EEDATA registers, following the second instruction after the RD bit is set.  2001 Microchip Technology Inc. DS30292C-page 41 PIC16F87X Write operations have two control bits, WR and WREN, and two status bits, WRERR and EEIF. The WREN bit is used to enable or disable the write operation. When WREN is clear, the write operation will be disabled. Therefore, the WREN bit must be set before executing a write operation. The WR bit is used to initiate the write operation. It also is automatically cleared at the end of the write operation. The interrupt flag EEIF is used to determine when the memory write completes. This flag must be cleared in software before setting the WR bit. For EEPROM data memory, once the WREN bit and the WR bit have been set, the desired memory address in EEADR will be erased, followed by a write of the data in EEDATA. This operation takes place in parallel with the microcontroller continuing to execute normally. When the write is complete, the EEIF flag bit will be set. For program memory, once the WREN bit and the WR bit have been set, the microcontroller will cease to execute instructions. The desired memory location pointed to by EEADRH:EEADR will be erased. Then, the data value in EEDATH:EEDATA will be programmed. When complete, the EEIF flag bit will be set and the microcontroller will continue to execute code. The WRERR bit is used to indicate when the PIC16F87X device has been reset during a write operation. WRERR should be cleared after Power-on Reset. Thereafter, it should be checked on any other RESET. The WRERR bit is set when a write operation is interrupted by a MCLR Reset, or a WDT Time-out Reset, during normal operation. In these situations, following a RESET, the user should check the WRERR bit and rewrite the memory location, if set. The contents of the data registers, address registers and EEPGD bit are not affected by either MCLR Reset, or WDT Timeout Reset, during normal operation. REGISTER 4-1: EECON1 REGISTER (ADDRESS 18Ch) R/W-x EEPGD bit 7 U-0 — U-0 — U-0 — R/W-x WRERR R/W-0 WREN R/S-0 WR R/S-0 RD bit 0 bit 7 EEPGD: Program/Data EEPROM Select bit 1 = Accesses program memory 0 = Accesses data memory (This bit cannot be changed while a read or write operation is in progress) Unimplemented: Read as '0' WRERR: EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any MCLR Reset or any WDT Reset during normal operation) 0 = The write operation completed WREN: EEPROM Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the EEPROM WR: Write Control bit 1 = Initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the EEPROM is complete RD: Read Control bit 1 = Initiates an EEPROM read. (RD is cleared in hardware. The RD bit can only be set (not cleared) in software.) 0 = Does not initiate an EEPROM read Legend: R = Readable bit - n = Value at POR W = Writable bit ’1’ = Bit is set U = Unimplemented bit, read as ‘0’ ’0’ = Bit is cleared x = Bit is unknown bit 6-4 bit 3 bit 2 bit 1 bit 0 DS30292C-page 42  2001 Microchip Technology Inc. PIC16F87X 4.2 Reading the EEPROM Data Memory The steps to write to EEPROM data memory are: 1. If step 10 is not implemented, check the WR bit to see if a write is in progress. 2. Write the address to EEADR. Make sure that the address is not larger than the memory size of the PIC16F87X device. 3. Write the 8-bit data value to be programmed in the EEDATA register. 4. Clear the EEPGD bit to point to EEPROM data memory. 5. Set the WREN bit to enable program operations. 6. Disable interrupts (if enabled). 7. Execute the special five instruction sequence: • Write 55h to EECON2 in two steps (first to W, then to EECON2) • Write AAh to EECON2 in two steps (first to W, then to EECON2) • Set the WR bit 8. Enable interrupts (if using interrupts). 9. Clear the WREN bit to disable program operations. 10. At the completion of the write cycle, the WR bit is cleared and the EEIF interrupt flag bit is set. (EEIF must be cleared by firmware.) If step 1 is not implemented, then firmware should check for EEIF to be set, or WR to clear, to indicate the end of the program cycle. Reading EEPROM data memory only requires that the desired address to access be written to the EEADR register and clear the EEPGD bit. After the RD bit is set, data will be available in the EEDATA register on the very next instruction cycle. EEDATA will hold this value until another read operation is initiated or until it is written by firmware. The steps to reading the EEPROM data memory are: 1. Write the address to EEDATA. Make sure that the address is not larger than the memory size of the PIC16F87X device. Clear the EEPGD bit to point to EEPROM data memory. Set the RD bit to start the read operation. Read the data from the EEDATA register. 2. 3. 4. EXAMPLE 4-1: BSF BCF MOVF MOVWF BSF BCF BSF BCF MOVF STATUS, STATUS, ADDR, W EEADR STATUS, EECON1, EECON1, STATUS, RP1 RP0 EEPROM DATA READ ; ;Bank 2 ;Write address ;to read from ;Bank 3 ;Point to Data memory ;Start read operation ;Bank 2 ;W = EEDATA RP0 EEPGD RD RP0 EEDATA, W EXAMPLE 4-2: EEPROM DATA WRITE ; ;Bank 3 ;Wait for ;write to finish ;Bank 2 ;Address to ;write to ;Data to ;write ;Bank 3 ;Point to Data memory ;Enable writes ;Only disable interrupts ;if already enabled, ;otherwise discard ;Write 55h to ;EECON2 ;Write AAh to ;EECON2 ;Start write operation ;Only enable interrupts ;if using interrupts, ;otherwise discard ;Disable writes 4.3 Writing to the EEPROM Data Memory There are many steps in writing to the EEPROM data memory. Both address and data values must be written to the SFRs. The EEPGD bit must be cleared, and the WREN bit must be set, to enable writes. The WREN bit should be kept clear at all times, except when writing to the EEPROM data. The WR bit can only be set if the WREN bit was set in a previous operation, i.e., they both cannot be set in the same operation. The WREN bit should then be cleared by firmware after the write. Clearing the WREN bit before the write actually completes will not terminate the write in progress. Writes to EEPROM data memory must also be prefaced with a special sequence of instructions, that prevent inadvertent write operations. This is a sequence of five instructions that must be executed without interruptions. The firmware should verify that a write is not in progress, before starting another cycle. BSF BSF BTFSC GOTO BCF MOVF MOVWF MOVF MOVWF BSF BCF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF BCF STATUS, RP1 STATUS, RP0 EECON1, WR $-1 STATUS, RP0 ADDR, W EEADR VALUE, W EEDATA STATUS, RP0 EECON1, EEPGD EECON1, WREN INTCON, GIE 0x55 EECON2 0xAA EECON2 EECON1, WR INTCON, GIE EECON1, WREN  2001 Microchip Technology Inc. DS30292C-page 43 PIC16F87X 4.4 Reading the FLASH Program Memory 4.5 Writing to the FLASH Program Memory Reading FLASH program memory is much like that of EEPROM data memory, only two NOP instructions must be inserted after the RD bit is set. These two instruction cycles that the NOP instructions execute, will be used by the microcontroller to read the data out of program memory and insert the value into the EEDATH:EEDATA registers. Data will be available following the second NOP instruction. EEDATH and EEDATA will hold their value until another read operation is initiated, or until they are written by firmware. The steps to reading the FLASH program memory are: 1. Write the address to EEADRH:EEADR. Make sure that the address is not larger than the memory size of the PIC16F87X device. Set the EEPGD bit to point to FLASH program memory. Set the RD bit to start the read operation. Execute two NOP instructions to allow the microcontroller to read out of program memory. Read the data from the EEDATH:EEDATA registers. Writing to FLASH program memory is unique, in that the microcontroller does not execute instructions while programming is taking place. The oscillator continues to run and all peripherals continue to operate and queue interrupts, if enabled. Once the write operation completes (specification D133), the processor begins executing code from where it left off. The other important difference when writing to FLASH program memory, is that the WRT configuration bit, when clear, prevents any writes to program memory (see Table 4-1). Just like EEPROM data memory, there are many steps in writing to the FLASH program memory. Both address and data values must be written to the SFRs. The EEPGD bit must be set, and the WREN bit must be set to enable writes. The WREN bit should be kept clear at all times, except when writing to the FLASH Program memory. The WR bit can only be set if the WREN bit was set in a previous operation, i.e., they both cannot be set in the same operation. The WREN bit should then be cleared by firmware after the write. Clearing the WREN bit before the write actually completes will not terminate the write in progress. Writes to program memory must also be prefaced with a special sequence of instructions that prevent inadvertent write operations. This is a sequence of five instructions that must be executed without interruption for each byte written. These instructions must then be followed by two NOP instructions to allow the microcontroller to setup for the write operation. Once the write is complete, the execution of instructions starts with the instruction after the second NOP. The steps to write to program memory are: 1. Write the address to EEADRH:EEADR. Make sure that the address is not larger than the memory size of the PIC16F87X device. Write the 14-bit data value to be programmed in the EEDATH:EEDATA registers. Set the EEPGD bit to point to FLASH program memory. Set the WREN bit to enable program operations. Disable interrupts (if enabled). Execute the special five instruction sequence: • Write 55h to EECON2 in two steps (first to W, then to EECON2) • Write AAh to EECON2 in two steps (first to W, then to EECON2) • Set the WR bit Execute two NOP instructions to allow the microcontroller to setup for write operation. Enable interrupts (if using interrupts). Clear the WREN bit to disable program operations. 2. 3. 4. 5. EXAMPLE 4-3: BSF BCF MOVF MOVWF MOVF MOVWF BSF BSF BSF NOP NOP BCF MOVF MOVWF MOVF MOVWF FLASH PROGRAM READ ; ;Bank 2 ;Write the ;address bytes ;for the desired ;address to read ;Bank 3 ;Point to Program memory ;Start read operation ;Required two NOPs ; ;Bank 2 ;DATAL = EEDATA ; ;DATAH = EEDATH ; STATUS, RP1 STATUS, RP0 ADDRL, W EEADR ADDRH,W EEADRH STATUS, RP0 EECON1, EEPGD EECON1, RD STATUS, RP0 EEDATA, W DATAL EEDATH,W DATAH 2. 3. 4. 5. 6. 7. 8. 9. DS30292C-page 44  2001 Microchip Technology Inc. PIC16F87X At the completion of the write cycle, the WR bit is cleared and the EEIF interrupt flag bit is set. (EEIF must be cleared by firmware.) Since the microcontroller does not execute instructions during the write cycle, the firmware does not necessarily have to check either EEIF, or WR, to determine if the write had finished. 4.7 Protection Against Spurious Writes EXAMPLE 4-4: BSF BCF MOVF MOVWF MOVF MOVWF MOVF MOVWF MOVF MOVWF BSF BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF NOP NOP BSF BCF FLASH PROGRAM WRITE ; ;Bank 2 ;Write address ;of desired ;program memory ;location ;Write value to ;program at ;desired memory ;location ;Bank 3 ;Point to Program memory ;Enable writes ;Only disable interrupts ;if already enabled, ;otherwise discard ;Write 55h to ;EECON2 ;Write AAh to ;EECON2 ;Start write operation ;Two NOPs to allow micro ;to setup for write ;Only enable interrupts ;if using interrupts, ;otherwise discard ;Disable writes STATUS, RP1 STATUS, RP0 ADDRL, W EEADR ADDRH, W EEADRH VALUEL, W EEDATA VALUEH, W EEDATH STATUS, RP0 EECON1, EEPGD EECON1, WREN INTCON, GIE 0x55 EECON2 0xAA EECON2 EECON1, WR There are conditions when the device may not want to write to the EEPROM data memory or FLASH program memory. To protect against these spurious write conditions, various mechanisms have been built into the PIC16F87X devices. On power-up, the WREN bit is cleared and the Power-up Timer (if enabled) prevents writes. The write initiate sequence, and the WREN bit together, help prevent any accidental writes during brown-out, power glitches, or firmware malfunction. 4.8 Operation While Code Protected The PIC16F87X devices have two code protect mechanisms, one bit for EEPROM data memory and two bits for FLASH program memory. Data can be read and written to the EEPROM data memory, regardless of the state of the code protection bit, CPD. When code protection is enabled and CPD cleared, external access via ICSP is disabled, regardless of the state of the program memory code protect bits. This prevents the contents of EEPROM data memory from being read out of the device. The state of the program memory code protect bits, CP0 and CP1, do not affect the execution of instructions out of program memory. The PIC16F87X devices can always read the values in program memory, regardless of the state of the code protect bits. However, the state of the code protect bits and the WRT bit will have different effects on writing to program memory. Table 4-1 shows the effect of the code protect bits and the WRT bit on program memory. Once code protection has been enabled for either EEPROM data memory or FLASH program memory, only a full erase of the entire device will disable code protection. INTCON, GIE EECON1, WREN 4.6 Write Verify The PIC16F87X devices do not automatically verify the value written during a write operation. Depending on the application, good programming practice may dictate that the value written to memory be verified against the original value. This should be used in applications where excessive writes can stress bits near the specified endurance limits.  2001 Microchip Technology Inc. DS30292C-page 45 PIC16F87X 4.9 FLASH Program Memory Write Protection The configuration word contains a bit that write protects the FLASH program memory, called WRT. This bit can only be accessed when programming the PIC16F87X device via ICSP. Once write protection is enabled, only an erase of the entire device will disable it. When enabled, write protection prevents any writes to FLASH program memory. Write protection does not affect program memory reads. TABLE 4-1: READ/WRITE STATE OF INTERNAL FLASH PROGRAM MEMORY Memory Location Internal Read Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Internal Write No No No Yes No No No Yes No No Yes ICSP Read No Yes No Yes No Yes No Yes No Yes Yes ICSP Write No No No No No No No No No Yes Yes Configuration Bits CP1 0 0 0 0 0 1 1 1 1 1 1 CP0 0 1 1 1 1 0 0 0 0 1 1 WRT x 0 0 1 1 0 0 1 1 0 1 All program memory Unprotected areas Protected areas Unprotected areas Protected areas Unprotected areas Protected areas Unprotected areas Protected areas All program memory All program memory TABLE 4-2: Address REGISTERS ASSOCIATED WITH DATA EEPROM/PROGRAM FLASH Name Bit 7 GIE Bit 6 PEIE Bit 5 T0IE Bit 4 INTE Bit 3 RBIE Bit 2 T0IF Bit 1 INTF Bit 0 RBIF Value on: POR, BOR 0000 000x xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx Value on all other RESETS 0000 000u uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu x--- u000 0Bh, 8Bh, INTCON 10Bh, 18Bh 10Dh 10Fh 10Ch 10Eh 18Ch 18Dh 8Dh 0Dh Legend: EEADR EEADRH EEDATA EEDATH EECON1 EEPROM Address Register, Low Byte — — — EEPROM Address, High Byte EEPROM Data Register, Low Byte — EEPGD — — EEPROM Data Register, High Byte — — WRERR WREN WR RD x--- x000 EECON2 EEPROM Control Register2 (not a physical register) PIE2 PIR2 — — (1) (1) — — EEIE EEIF BCLIE BCLIF — — — — — CCP2IE -r-0 0--0 CCP2IF -r-0 0--0 — -r-0 0--0 -r-0 0--0 x = unknown, u = unchanged, r = reserved, - = unimplemented, read as '0'. Shaded cells are not used during FLASH/EEPROM access. Note 1: These bits are reserved; always maintain these bits clear. DS30292C-page 46  2001 Microchip Technology Inc. PIC16F87X 5.0 TIMER0 MODULE The Timer0 module timer/counter has the following features: • • • • • • 8-bit timer/counter Readable and writable 8-bit software programmable prescaler Internal or external clock select Interrupt on overflow from FFh to 00h Edge select for external clock Counter mode is selected by setting bit T0CS (OPTION_REG). In Counter mode, Timer0 will increment either on every rising, or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit, T0SE (OPTION_REG). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 5.2. The prescaler is mutually exclusively shared between the Timer0 module and the Watchdog Timer. The prescaler is not readable or writable. Section 5.3 details the operation of the prescaler. Figure 5-1 is a block diagram of the Timer0 module and the prescaler shared with the WDT. Additional information on the Timer0 module is available in the PICmicro™ Mid-Range MCU Family Reference Manual (DS33023). Timer mode is selected by clearing bit T0CS (OPTION_REG). In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. 5.1 Timer0 Interrupt The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit T0IF (INTCON). The interrupt can be masked by clearing bit T0IE (INTCON). Bit T0IF must be cleared in software by the Timer0 module Interrupt Service Routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from SLEEP, since the timer is shut-off during SLEEP. FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER Data Bus 8 1 0 M U X SYNC 2 Cycles TMR0 Reg CLKOUT (= FOSC/4) 0 RA4/T0CKI pin 1 T0SE M U X T0CS PSA PRESCALER Set Flag Bit T0IF on Overflow 0 M U X 8-bit Prescaler 8 8 - to - 1MUX PS2:PS0 Watchdog Timer 1 PSA 0 MUX 1 PSA WDT Enable bit WDT Time-out Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG).  2001 Microchip Technology Inc. DS30292C-page 47 PIC16F87X 5.2 Using Timer0 with an External Clock Timer0 module means that there is no prescaler for the Watchdog Timer, and vice-versa. This prescaler is not readable or writable (see Figure 5-1). The PSA and PS2:PS0 bits (OPTION_REG) determine the prescaler assignment and prescale ratio. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g. CLRF 1, MOVWF 1, BSF 1,x....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog Timer. The prescaler is not readable or writable. Note: Writing to TMR0, when the prescaler is assigned to Timer0, will clear the prescaler count, but will not change the prescaler assignment. When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, it is necessary for T0CKI to be high for at least 2Tosc (and a small RC delay of 20 ns) and low for at least 2Tosc (and a small RC delay of 20 ns). Refer to the electrical specification of the desired device. 5.3 Prescaler There is only one prescaler available, which is mutually exclusively shared between the Timer0 module and the Watchdog Timer. A prescaler assignment for the REGISTER 5-1: OPTION_REG REGISTER R/W-1 RBPU bit 7 R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit 0 bit 7 bit 6 bit 5 RBPU INTEDG T0CS: TMR0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS2:PS0: Prescaler Rate Select bits Bit Value TMR0 Rate WDT Rate 000 001 010 011 100 101 110 111 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 bit 4 bit 3 bit 2-0 Legend: R = Readable bit - n = Value at POR W = Writable bit ’1’ = Bit is set U = Unimplemented bit, read as ‘0’ ’0’ = Bit is cleared x = Bit is unknown Note: To avoid an unintended device RESET, the instruction sequence shown in the PICmicro™ Mid-Range MCU Family Reference Manual (DS33023) must be executed when changing the prescaler assignment from Timer0 to the WDT. This sequence must be followed even if the WDT is disabled. DS30292C-page 48  2001 Microchip Technology Inc. PIC16F87X TABLE 5-1: Address 01h,101h REGISTERS ASSOCIATED WITH TIMER0 Name TMR0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other RESETS Timer0 Module’s Register GIE PEIE T0IE INTE RBIE PSA T0IF PS2 INTF PS1 xxxx xxxx uuuu uuuu 0Bh,8Bh, INTCON 10Bh,18Bh 81h,181h RBIF 0000 000x 0000 000u PS0 1111 1111 1111 1111 OPTION_REG RBPU INTEDG T0CS T0SE Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.  2001 Microchip Technology Inc. DS30292C-page 49 PIC16F87X NOTES: DS30292C-page 50  2001 Microchip Technology Inc. PIC16F87X 6.0 TIMER1 MODULE The Timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L), which are readable and writable. The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 Interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit TMR1IF (PIR1). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE (PIE1). Timer1 can operate in one of two modes: • As a timer • As a counter The operating mode is determined by the clock select bit, TMR1CS (T1CON). In Timer mode, Timer1 increments every instruction cycle. In Counter mode, it increments on every rising edge of the external clock input. Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON (T1CON). Timer1 also has an internal “RESET input”. This RESET can be generated by either of the two CCP modules (Section 8.0). Register 6-1 shows the Timer1 control register. When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC value is ignored, and these pins read as ‘0’. Additional information on timer modules is available in the PICmicro™ Mid-Range MCU Family Reference Manual (DS33023). REGISTER 6-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h) U-0 — bit 7 U-0 — R/W-0 R/W-0 R/W-0 T1OSCEN R/W-0 R/W-0 R/W-0 bit 0 T1CKPS1 T1CKPS0 T1SYNC TMR1CS TMR1ON bit 7-6 bit 5-4 Unimplemented: Read as '0' T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value T1OSCEN: Timer1 Oscillator Enable Control bit 1 = Oscillator is enabled 0 = Oscillator is shut-off (the oscillator inverter is turned off to eliminate power drain) T1SYNC: Timer1 External Clock Input Synchronization Control bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge) 0 = Internal clock (FOSC/4) TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend: R = Readable bit - n = Value at POR W = Writable bit ’1’ = Bit is set U = Unimplemented bit, read as ‘0’ ’0’ = Bit is cleared x = Bit is unknown bit 3 bit 2 bit 1 bit 0  2001 Microchip Technology Inc. DS30292C-page 51 PIC16F87X 6.1 Timer1 Operation in Timer Mode 6.2 Timer1 Counter Operation Timer mode is selected by clearing the TMR1CS (T1CON) bit. In this mode, the input clock to the timer is FOSC/4. The synchronize control bit T1SYNC (T1CON) has no effect, since the internal clock is always in sync. Timer1 may operate in either a Synchronous, or an Asynchronous mode, depending on the setting of the TMR1CS bit. When Timer1 is being incremented via an external source, increments occur on a rising edge. After Timer1 is enabled in Counter mode, the module must first have a falling edge before the counter begins to increment. FIGURE 6-1: T1CKI (Default High) TIMER1 INCREMENTING EDGE T1CKI (Default Low) Note: Arrows indicate counter increments. 6.3 Timer1 Operation in Synchronized Counter Mode Counter mode is selected by setting bit TMR1CS. In this mode, the timer increments on every rising edge of clock input on pin RC1/T1OSI/CCP2, when bit T1OSCEN is set, or on pin RC0/T1OSO/T1CKI, when bit T1OSCEN is cleared. If T1SYNC is cleared, then the external clock input is synchronized with internal phase clocks. The synchronization is done after the prescaler stage. The prescaler stage is an asynchronous ripple-counter. In this configuration, during SLEEP mode, Timer1 will not increment even if the external clock is present, since the synchronization circuit is shut-off. The prescaler, however, will continue to increment. FIGURE 6-2: TIMER1 BLOCK DIAGRAM Set Flag bit TMR1IF on Overflow TMR1H TMR1 TMR1L 0 1 TMR1ON On/Off T1SYNC Synchronized Clock Input T1OSC RC0/T1OSO/T1CKI T1OSCEN FOSC/4 Enable Internal Oscillator(1) Clock 1 Prescaler 1, 2, 4, 8 0 2 T1CKPS1:T1CKPS0 TMR1CS Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain. Q Clock Synchronize det RC1/T1OSI/CCP2(2) DS30292C-page 52  2001 Microchip Technology Inc. PIC16F87X 6.4 Timer1 Operation in Asynchronous Counter Mode TABLE 6-1: Osc Type LP CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR Freq. C1 C2 If control bit T1SYNC (T1CON) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during SLEEP and can generate an interrupt-on-overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (Section 6.4.1). In Asynchronous Counter mode, Timer1 cannot be used as a time-base for capture or compare operations. 32 kHz 33 pF 33 pF 100 kHz 15 pF 15 pF 200 kHz 15 pF 15 pF These values are for design guidance only. Crystals Tested: 32.768 kHz Epson C-001R32.768K-A ± 20 PPM 100 kHz Epson C-2 100.00 KC-P ± 20 PPM 200 kHz STD XTL 200.000 kHz ± 20 PPM Note 1: Higher capacitance increases the stability of oscillator, but also increases the start-up time. 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 6.4.1 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock, will guarantee a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the timer register. Reading the 16-bit value requires some care. Examples 12-2 and 12-3 in the PICmicro™ Mid-Range MCU Family Reference Manual (DS33023) show how to read and write Timer1 when it is running in Asynchronous mode. 6.6 Resetting Timer1 using a CCP Trigger Output If the CCP1 or CCP2 module is configured in Compare mode to generate a “special event trigger” (CCP1M3:CCP1M0 = 1011), this signal will reset Timer1. Note: The special event triggers from the CCP1 and CCP2 modules will not set interrupt flag bit TMR1IF (PIR1). 6.5 Timer1 Oscillator Timer1 must be configured for either Timer or Synchronized Counter mode to take advantage of this feature. If Timer1 is running in Asynchronous Counter mode, this RESET operation may not work. In the event that a write to Timer1 coincides with a special event trigger from CCP1 or CCP2, the write will take precedence. In this mode of operation, the CCPRxH:CCPRxL register pair effectively becomes the period register for Timer1. A crystal oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit T1OSCEN (T1CON). The oscillator is a low power oscillator, rated up to 200 kHz. It will continue to run during SLEEP. It is primarily intended for use with a 32 kHz crystal. Table 6-1 shows the capacitor selection for the Timer1 oscillator. The Timer1 oscillator is identical to the LP oscillator. The user must provide a software time delay to ensure proper oscillator start-up.  2001 Microchip Technology Inc. DS30292C-page 53 PIC16F87X 6.7 Resetting of Timer1 Register Pair (TMR1H, TMR1L) 6.8 Timer1 Prescaler The prescaler counter is cleared on writes to the TMR1H or TMR1L registers. TMR1H and TMR1L registers are not reset to 00h on a POR, or any other RESET, except by the CCP1 and CCP2 special event triggers. T1CON register is reset to 00h on a Power-on Reset, or a Brown-out Reset, which shuts off the timer and leaves a 1:1 prescale. In all other RESETS, the register is unaffected. TABLE 6-2: Address 0Bh,8Bh, 10Bh, 18Bh 0Ch 8Ch 0Eh 0Fh 10h Name REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR 0000 000x 0000 0000 0000 0000 xxxx xxxx xxxx xxxx Value on all other RESETS 0000 000u 0000 0000 0000 0000 uuuu uuuu uuuu uuuu --uu uuuu INTCON PIR1 PIE1 TMR1L TMR1H T1CON GIE PSPIF(1) PSPIE (1) PEIE ADIF ADIE T0IE RCIF RCIE INTE TXIF TXIE RBIE SSPIF SSPIE T0IF CCP1IF CCP1IE INTF TMR2IF TMR2IE RBIF TMR1IF TMR1IE Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F873/876; always maintain these bits clear. DS30292C-page 54  2001 Microchip Technology Inc. PIC16F87X 7.0 TIMER2 MODULE Register 7-1 shows the Timer2 control register. Additional information on timer modules is available in the PICmicro™ Mid-Range MCU Family Reference Manual (DS33023). Timer2 is an 8-bit timer with a prescaler and a postscaler. It can be used as the PWM time-base for the PWM mode of the CCP module(s). The TMR2 register is readable and writable, and is cleared on any device RESET. The input clock (FOSC/4) has a prescale option of 1:1, 1:4, or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON). The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon RESET. The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit TMR2IF, (PIR1)). Timer2 can be shut-off by clearing control bit TMR2ON (T2CON), to minimize power consumption. FIGURE 7-1: Sets Flag bit TMR2IF TMR2 Output(1) RESET Postscaler 1:1 to 1:16 4 T2OUTPS3: T2OUTPS0 TIMER2 BLOCK DIAGRAM TMR2 Reg Comparator Prescaler 1:1, 1:4, 1:16 2 T2CKPS1: T2CKPS0 FOSC/4 EQ PR2 Reg Note 1: TMR2 register output can be software selected by the SSP module as a baud clock. REGISTER 7-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h) U-0 — bit 7 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 0 TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 6-3 Unimplemented: Read as '0' TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale 0010 = 1:3 Postscale • • • 1111 = 1:16 Postscale TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 Legend: R = Readable bit - n = Value at POR W = Writable bit ’1’ = Bit is set U = Unimplemented bit, read as ‘0’ ’0’ = Bit is cleared x = Bit is unknown bit 2 bit 1-0  2001 Microchip Technology Inc. DS30292C-page 55 PIC16F87X 7.1 Timer2 Prescaler and Postscaler 7.2 Output of TMR2 The prescaler and postscaler counters are cleared when any of the following occurs: • a write to the TMR2 register • a write to the T2CON register • any device RESET (POR, MCLR Reset, WDT Reset, or BOR) TMR2 is not cleared when T2CON is written. The output of TMR2 (before the postscaler) is fed to the SSP module, which optionally uses it to generate shift clock. TABLE 7-1: Address Name REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Bit 7 GIE PSPIF(1) PSPIE(1) — Bit 6 PEIE ADIF ADIE TOUTPS3 Bit 5 T0IE RCIF RCIE Bit 4 INTE TXIF TXIE Bit 3 RBIE SSPIF SSPIE Bit 2 T0IF CCP1IF CCP1IE Bit 1 INTF TMR2IF TMR2IE Bit 0 RBIF TMR1IF TMR1IE Value on: POR, BOR Value on all other RESETS 0Bh,8Bh, INTCON 10Bh,18Bh 0Ch 8Ch 11h 12h 92h PIR1 PIE1 TMR2 T2CON PR2 0000 000x 0000 000u 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Timer2 Module’s Register Timer2 Period Register TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer2 module. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F873/876; always maintain these bits clear. DS30292C-page 56  2001 Microchip Technology Inc. PIC16F87X 8.0 CAPTURE/COMPARE/PWM MODULES CCP2 Module: Capture/Compare/PWM Register2 (CCPR2) is comprised of two 8-bit registers: CCPR2L (low byte) and CCPR2H (high byte). The CCP2CON register controls the operation of CCP2. The special event trigger is generated by a compare match and will reset Timer1 and start an A/D conversion (if the A/D module is enabled). Additional information on CCP modules is available in the PICmicro™ Mid-Range MCU Family Reference Manual (DS33023) and in application note AN594, “Using the CCP Modules” (DS00594). Each Capture/Compare/PWM (CCP) module contains a 16-bit register which can operate as a: • 16-bit Capture register • 16-bit Compare register • PWM Master/Slave Duty Cycle register Both the CCP1 and CCP2 modules are identical in operation, with the exception being the operation of the special event trigger. Table 8-1 and Table 8-2 show the resources and interactions of the CCP module(s). In the following sections, the operation of a CCP module is described with respect to CCP1. CCP2 operates the same as CCP1, except where noted. CCP1 Module: Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. The special event trigger is generated by a compare match and will reset Timer1. TABLE 8-1: CCP MODE - TIMER RESOURCES REQUIRED Timer Resource Timer1 Timer1 Timer2 CCP Mode Capture Compare PWM TABLE 8-2: INTERACTION OF TWO CCP MODULES Interaction Same TMR1 time-base The compare should be configured for the special event trigger, which clears TMR1 The compare(s) should be configured for the special event trigger, which clears TMR1 The PWMs will have the same frequency and update rate (TMR2 interrupt) None None CCPx Mode CCPy Mode Capture Capture Compare PWM PWM PWM Capture Compare Compare PWM Capture Compare  2001 Microchip Technology Inc. DS30292C-page 57 PIC16F87X REGISTER 8-1: CCP1CON REGISTER/CCP2CON REGISTER (ADDRESS: 17h/1Dh) U-0 — bit 7 bit 7-6 bit 5-4 Unimplemented: Read as '0' CCPxX:CCPxY: PWM Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. CCPxM3:CCPxM0: CCPx Mode Select bits 0000 = Capture/Compare/PWM disabled (resets CCPx module) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCPxIF bit is set) 1001 = Compare mode, clear output on match (CCPxIF bit is set) 1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is unaffected) 1011 = Compare mode, trigger special event (CCPxIF bit is set, CCPx pin is unaffected); CCP1 resets TMR1; CCP2 resets TMR1 and starts an A/D conversion (if A/D module is enabled) 11xx = PWM mode Legend: R = Readable bit - n = Value at POR W = Writable bit ’1’ = Bit is set U = Unimplemented bit, read as ‘0’ ’0’ = Bit is cleared x = Bit is unknown U-0 — R/W-0 CCPxX R/W-0 CCPxY R/W-0 CCPxM3 R/W-0 CCPxM2 R/W-0 CCPxM1 R/W-0 CCPxM0 bit 0 bit 3-0 DS30292C-page 58  2001 Microchip Technology Inc. PIC16F87X 8.1 Capture Mode 8.1.2 TIMER1 MODE SELECTION In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC2/CCP1. An event is defined as one of the following: • • • • Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge Timer1 must be running in Timer mode, or Synchronized Counter mode, for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work. 8.1.3 SOFTWARE INTERRUPT The type of event is configured by control bits CCP1M3:CCP1M0 (CCPxCON). When a capture is made, the interrupt request flag bit CCP1IF (PIR1) is set. The interrupt flag must be cleared in software. If another capture occurs before the value in register CCPR1 is read, the old captured value is overwritten by the new value. When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCP1IE (PIE1) clear to avoid false interrupts and should clear the flag bit CCP1IF, following any such change in operating mode. 8.1.4 CCP PRESCALER 8.1.1 CCP PIN CONFIGURATION There are four prescaler settings, specified by bits CCP1M3:CCP1M0. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any RESET will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared, therefore, the first capture may be from a non-zero prescaler. Example 8-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the “false” interrupt. In Capture mode, the RC2/CCP1 pin should be configured as an input by setting the TRISC bit. Note: If the RC2/CCP1 pin is configured as an output, a write to the port can cause a capture condition. FIGURE 8-1: CAPTURE MODE OPERATION BLOCK DIAGRAM Set Flag bit CCP1IF (PIR1) EXAMPLE 8-1: CLRF MOVLW RC2/CCP1 pin CHANGING BETWEEN CAPTURE PRESCALERS Prescaler ÷ 1, 4, 16 CCPR1H and edge detect Capture Enable TMR1H CCP1CON Qs CCPR1L MOVWF CCP1CON ; Turn CCP module off NEW_CAPT_PS ; Load the W reg with ; the new prescaler ; move value and CCP ON CCP1CON ; Load CCP1CON with this ; value TMR1L  2001 Microchip Technology Inc. DS30292C-page 59 PIC16F87X 8.2 Compare Mode 8.2.2 TIMER1 MODE SELECTION In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the RC2/CCP1 pin is: • Driven high • Driven low • Remains unchanged The action on the pin is based on the value of control bits CCP1M3:CCP1M0 (CCP1CON). At the same time, interrupt flag bit CCP1IF is set. Timer1 must be running in Timer mode, or Synchronized Counter mode, if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. 8.2.3 SOFTWARE INTERRUPT MODE When Generate Software Interrupt mode is chosen, the CCP1 pin is not affected. The CCPIF bit is set, causing a CCP interrupt (if enabled). 8.2.4 FIGURE 8-2: COMPARE MODE OPERATION BLOCK DIAGRAM SPECIAL EVENT TRIGGER In this mode, an internal hardware trigger is generated, which may be used to initiate an action. The special event trigger output of CCP1 resets the TMR1 register pair. This allows the CCPR1 register to effectively be a 16-bit programmable period register for Timer1. The special event trigger output of CCP2 resets the TMR1 register pair and starts an A/D conversion (if the A/D module is enabled). Note: The special event trigger from the CCP1and CCP2 modules will not set interrupt flag bit TMR1IF (PIR1). Special event trigger will: reset Timer1, but not set interrupt flag bit TMR1IF (PIR1), and set bit GO/DONE (ADCON0). Special Event Trigger Set Flag bit CCP1IF (PIR1) RC2/CCP1 pin Q S R TRISC Output Enable Output Logic Match CCPR1H CCPR1L Comparator TMR1H TMR1L CCP1CON Mode Select 8.2.1 CCP PIN CONFIGURATION The user must configure the RC2/CCP1 pin as an output by clearing the TRISC bit. Note: Clearing the CCP1CON register will force the RC2/CCP1 compare output latch to the default low level. This is not the PORTC I/O data latch. DS30292C-page 60  2001 Microchip Technology Inc. PIC16F87X 8.3 PWM Mode (PWM) 8.3.1 PWM PERIOD In Pulse Width Modulation mode, the CCPx pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch. The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula: PWM period = [(PR2) + 1] • 4 • TOSC • (TMR2 prescale value) PWM frequency is defined as 1 / [PWM period]. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: • TMR2 is cleared • The CCP1 pin is set (exception: if PWM duty cycle = 0%, the CCP1 pin will not be set) • The PWM duty cycle is latched from CCPR1L into CCPR1H Note: The Timer2 postscaler (see Section 7.1) is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. Figure 8-3 shows a simplified block diagram of the CCP module in PWM mode. For a step-by-step procedure on how to set up the CCP module for PWM operation, see Section 8.3.3. FIGURE 8-3: SIMPLIFIED PWM BLOCK DIAGRAM CCP1CON Duty Cycle Registers CCPR1L 8.3.2 CCPR1H (Slave) RC2/CCP1 Comparator R Q PWM DUTY CYCLE TMR2 (Note 1) S The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON bits. Up to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON. The following equation is used to calculate the PWM duty cycle in time: PWM duty cycle =(CCPR1L:CCP1CON) • TOSC • (TMR2 prescale value) CCPR1L and CCP1CON can be written to at any time, but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register. The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitch-free PWM operation. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock, or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by the formula: FOSC log FPWM Comparator Clear Timer, CCP1 pin and latch D.C. TRISC PR2 Note 1: The 8-bit timer is concatenated with 2-bit internal Q clock, or 2 bits of the prescaler, to create 10-bit timebase. A PWM output (Figure 8-4) has a time-base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period). FIGURE 8-4: Period PWM OUTPUT Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2 Resolution = ( ) bits log(2) Note: If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared.  2001 Microchip Technology Inc. DS30292C-page 61 PIC16F87X 8.3.3 SETUP FOR PWM OPERATION 3. 4. 5. The following steps should be taken when configuring the CCP module for PWM operation: 1. 2. Set the PWM period by writing to the PR2 register. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON bits. Make the CCP1 pin an output by clearing the TRISC bit. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. Configure the CCP1 module for PWM operation. TABLE 8-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz 1.22 kHz 16 0xFFh 10 4.88 kHz 4 0xFFh 10 19.53 kHz 1 0xFFh 10 78.12kHz 1 0x3Fh 8 156.3 kHz 1 0x1Fh 7 208.3 kHz 1 0x17h 5.5 PWM Frequency Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits) TABLE 8-4: Address REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1 Name Bit 7 GIE PSPIF(1) — PSPIE(1) — Bit 6 PEIE ADIF — ADIE — Bit 5 T0IE RCIF — RCIE — Bit 4 INTE TXIF — TXIE — Bit 3 RBIE SSPIF — SSPIE — Bit 2 T0IF CCP1IF — CCP1IE — Bit 1 INTF TMR2IF — TMR2IE — Bit 0 RBIF Value on: POR, BOR Value on all other RESETS 0Bh,8Bh, INTCON 10Bh, 18Bh 0Ch 0Dh 8Ch 8Dh 87h 0Eh 0Fh 10h 15h 16h 17h 1Bh 1Ch 1Dh PIR1 PIR2 PIE1 PIE2 TRISC TMR1L TMR1H T1CON CCPR1L CCPR1H CCP1CON CCPR2L CCPR2H CCP2CON 0000 000x 0000 000u TMR1IF 0000 0000 0000 0000 CCP2IF ---- ---0 ---- ---0 TMR1IE 0000 0000 0000 0000 CCP2IE ---- ---0 ---- ---0 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu PORTC Data Direction Register Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu Capture/Compare/PWM Register1 (LSB) Capture/Compare/PWM Register1 (MSB) — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu Capture/Compare/PWM Register2 (LSB) Capture/Compare/PWM Register2 (MSB) — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1. Note 1: The PSP is not implemented on the PIC16F873/876; always maintain these bits clear. DS30292C-page 62  2001 Microchip Technology Inc. PIC16F87X TABLE 8-5: Address REGISTERS ASSOCIATED WITH PWM AND TIMER2 Name Bit 7 GIE PSPIF(1) — PSPIE(1) — Bit 6 PEIE ADIF — ADIE — Bit 5 T0IE RCIF — RCIE — Bit 4 INTE TXIF — TXIE — Bit 3 RBIE SSPIF — SSPIE — Bit 2 T0IF CCP1IF — CCP1IE — Bit 1 INTF TMR2IF — TMR2IE — Bit 0 RBIF Value on: POR, BOR Value on all other RESETS 0Bh,8Bh, INTCON 10Bh, 18Bh 0Ch 0Dh 8Ch 8Dh 87h 11h 92h 12h 15h 16h 17h 1Bh 1Ch 1Dh PIR1 PIR2 PIE1 PIE2 TRISC TMR2 PR2 T2CON CCPR1L CCPR1H CCP1CON CCPR2L CCPR2H CCP2CON 0000 000x 0000 000u TMR1IF 0000 0000 0000 0000 CCP2IF ---- ---0 ---- ---0 TMR1IE 0000 0000 0000 0000 CCP2IE ---- ---0 ---- ---0 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 PORTC Data Direction Register Timer2 Module’s Register Timer2 Module’s Period Register — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu Capture/Compare/PWM Register1 (LSB) Capture/Compare/PWM Register1 (MSB) — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu Capture/Compare/PWM Register2 (LSB) Capture/Compare/PWM Register2 (MSB) — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PWM and Timer2. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F873/876; always maintain these bits clear.  2001 Microchip Technology Inc. DS30292C-page 63 PIC16F87X NOTES: DS30292C-page 64  2001 Microchip Technology Inc. PIC16F87X 9.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module can operate in one of two modes: • Serial Peripheral Interface (SPI) • Inter-Integrated Circuit (I 2C) Figure 9-1 shows a block diagram for the SPI mode, while Figure 9-5 and Figure 9-9 show the block diagrams for the two different I2C modes of operation. The Application Note AN734, “Using the PICmicro® SSP for Slave I2CTM Communication” describes the slave operation of the MSSP module on the PIC16F87X devices. AN735, “Using the PICmicro® MSSP Module for I2CTM Communications” describes the master operation of the MSSP module on the PIC16F87X devices.  2001 Microchip Technology Inc. DS30292C-page 65 PIC16F87X REGISTER 9-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS: 94h) R/W-0 SMP bit 7 bit 7 SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in slave mode In I2 C Master or Slave mode: 1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for high speed mode (400 kHz) CKE: SPI Clock Edge Select (Figure 9-2, Figure 9-3 and Figure 9-4) SPI mode: For CKP = 0 1 = Data transmitted on rising edge of SCK 0 = Data transmitted on falling edge of SCK For CKP = 1 1 = Data transmitted on falling edge of SCK 0 = Data transmitted on rising edge of SCK In I2 C Master or Slave mode: 1 = Input levels conform to SMBus spec 0 = Input levels conform to I2C specs D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address P: STOP bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a STOP bit has been detected last (this bit is ’0’ on RESET) 0 = STOP bit was not detected last S: START bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a START bit has been detected last (this bit is ’0’ on RESET) 0 = START bit was not detected last R/W: Read/Write bit Information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next START bit, STOP bit or not ACK bit. In I2 C Slave mode: 1 = Read 0 = Write In I2 C Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress Logical OR of this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is in IDLE mode. UA: Update Address (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated BF: Buffer Full Status bit Receive (SPI and I2 C modes): 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I2 C mode only): 1 = Data transmit in progress (does not include the ACK and STOP bits), SSPBUF is full 0 = Data transmit complete (does not include the ACK and STOP bits), SSPBUF is empty Legend: R = Readable bit - n = Value at POR W = Writable bit ’1’ = Bit is set U = Unimplemented bit, read as ‘0’ ’0’ = Bit is cleared x = Bit is unknown R/W-0 CKE R-0 D/A R-0 P R-0 S R-0 R/W R-0 UA R-0 BF bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit DS30292C-page 66  2001 Microchip Technology Inc. PIC16F87X REGISTER 9-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h) R/W-0 WCOL bit 7 bit 7 WCOL: Write Collision Detect bit Master mode: 1 = A write to SSPBUF was attempted while the I2C conditions were not valid 0 = No collision Slave mode: 1 = SSPBUF register is written while still transmitting the previous word (must be cleared in software) 0 = No collision SSPOV: Receive Overflow Indicator bit In SPI mode: 1 = A new byte is received while SSPBUF holds previous data. Data in SSPSR is lost on overflow. In Slave mode, the user must read the SSPBUF, even if only transmitting data, to avoid overflows. In Master mode, the overflow bit is not set, since each operation is initiated by writing to the SSPBUF register. (Must be cleared in software.) 0 = No overflow In I2 C mode: 1 = A byte is received while the SSPBUF is holding the previous byte. SSPOV is a "don’t care" in Transmit mode. (Must be cleared in software.) 0 = No overflow SSPEN: Synchronous Serial Port Enable bit In SPI mode, When enabled, these pins must be properly configured as input or output 1 = Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial port pins 0 = Disables serial port and configures these pins as I/O port pins In I2 C mode, When enabled, these pins must be properly configured as input or output 1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins 0 = Disables serial port and configures these pins as I/O port pins CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I2 C Slave mode: SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) In I2 C Master mode: Unused in this mode SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 0000 = SPI Master mode, clock = FOSC/4 0001 = SPI Master mode, clock = FOSC/16 0010 = SPI Master mode, clock = FOSC/64 0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled. 0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin. 0110 = I2C Slave mode, 7-bit address 0111 = I2C Slave mode, 10-bit address 1000 = I2C Master mode, clock = FOSC / (4 * (SSPADD+1)) 1011 = I2C Firmware Controlled Master mode (slave idle) 1110 = I2C Firmware Controlled Master mode, 7-bit address with START and STOP bit interrupts enabled 1111 = I2C Firmware Controlled Master mode, 10-bit address with START and STOP bit interrupts enabled 1001, 1010, 1100, 1101 = Reserved Legend: R = Readable bit - n = Value at POR W = Writable bit ’1’ = Bit is set U = Unimplemented bit, read as ‘0’ ’0’ = Bit is cleared x = Bit is unknown R/W-0 SSPOV R/W-0 SSPEN R/W-0 CKP R/W-0 SSPM3 R/W-0 SSPM2 R/W-0 SSPM1 R/W-0 SSPM0 bit 0 bit 6 bit 5 bit 4 bit 3-0  2001 Microchip Technology Inc. DS30292C-page 67 PIC16F87X REGISTER 9-3: SSPCON2: SYNC SERIAL PORT CONTROL REGISTER2 (ADDRESS 91h) R/W-0 GCEN bit 7 bit 7 GCEN: General Call Enable bit (In I2C Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled ACKSTAT: Acknowledge Status bit (In I2C Master mode only) In Master Transmit mode: 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave ACKDT: Acknowledge Data bit (In I2C Master mode only) In Master Receive mode: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. 1 = Not Acknowledge 0 = Acknowledge ACKEN: Acknowledge Sequence Enable bit (In I2C Master mode only) In Master Receive mode: 1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence idle RCEN: Receive Enable bit (In I2C Master mode only) 1 = Enables Receive mode for I2C 0 = Receive idle PEN: STOP Condition Enable bit (In I2C Master mode only) SCK Release Control: 1 = Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware. 0 = STOP condition idle RSEN: Repeated START Condition Enable bit (In I2C Master mode only) 1 = Initiate Repeated START condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated START condition idle SEN: START Condition Enable bit (In I2C Master mode only) 1 = Initiate START condition on SDA and SCL pins. Automatically cleared by hardware. 0 = START condition idle Note: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the IDLE mode, this bit may not be set (no spooling), and the SSPBUF may not be written (or writes to the SSPBUF are disabled). R/W-0 ACKSTAT R/W-0 ACKDT R/W-0 ACKEN R/W-0 RCEN R/W-0 PEN R/W-0 RSEN R/W-0 SEN bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Legend: R = Readable bit - n = Value at POR W = Writable bit ’1’ = Bit is set U = Unimplemented bit, read as ‘0’ ’0’ = Bit is cleared x = Bit is unknown DS30292C-page 68  2001 Microchip Technology Inc. PIC16F87X 9.1 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four modes of SPI are supported. To accomplish communication, typically three pins are used: • Serial Data Out (SDO) • Serial Data In (SDI) • Serial Clock (SCK) Additionally, a fourth pin may be used when in a Slave mode of operation: • Slave Select (SS) When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON and SSPSTAT). These control bits allow the following to be specified: • • • • Master mode (SCK is the clock output) Slave mode (SCK is the clock input) Clock Polarity (Idle state of SCK) Data input sample phase (middle or end of data output time) • Clock edge (output data on rising/falling edge of SCK) • Clock Rate (Master mode only) • Slave Select mode (Slave mode only) Figure 9-4 shows the block diagram of the MSSP module when in SPI mode. To enable the serial port, MSSP Enable bit, SSPEN (SSPCON) must be set. To reset or reconfigure SPI mode, clear bit SSPEN, re-initialize the SSPCON registers, and then set bit SSPEN. This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed. That is: • SDI is automatically controlled by the SPI module • SDO must have TRISC cleared • SCK (Master mode) must have TRISC cleared • SCK (Slave mode) must have TRISC set • SS must have TRISA set and register ADCON1 (see Section 11.0: A/D Module) must be set in a way that pin RA5 is configured as a digital I/O Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. FIGURE 9-1: MSSP BLOCK DIAGRAM (SPI MODE) Internal Data Bus Read SSPBUF Reg Write SSPSR Reg SDI bit0 Shift Clock SDO SS Control Enable SS Edge Select 2 Clock Select SSPM3:SSPM0 SMP:CKE 4 2 Edge Select SCK TMR2 Output 2 Prescaler 4, 16, 64 TOSC Data to TX/RX in SSPSR Data Direction bit  2001 Microchip Technology Inc. DS30292C-page 69 PIC16F87X 9.1.1 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 9-5) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI module is only going to receive, the SDO output could be disabled (programmed as an input). The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPBUF register as if a normal received byte (interrupts and status bits appropriately set). This could be useful in receiver applications as a “line activity monitor”. The clock polarity is selected by appropriately programming bit CKP (SSPCON). This then, would give waveforms for SPI communication as shown in Figure 9-6, Figure 9-8 and Figure 9-9, where the MSb is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: • • • • FOSC/4 (or TCY) FOSC/16 (or 4 • TCY) FOSC/64 (or 16 • TCY) Timer2 output/2 This allows a maximum bit clock frequency (at 20 MHz) of 5.0 MHz. Figure 9-6 shows the waveforms for Master mode. When CKE = 1, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPBUF is loaded with the received data is shown. FIGURE 9-2: SCK (CKP = 0, CKE = 0) SCK (CKP = 0, CKE = 1) SCK (CKP = 1, CKE = 0) SCK (CKP = 1, CKE = 1) SDO SDI (SMP = 0) SPI MODE TIMING, MASTER MODE bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 SDI (SMP = 1) bit7 SSPIF bit0 bit0 DS30292C-page 70  2001 Microchip Technology Inc. PIC16F87X 9.1.2 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the interrupt flag bit SSPIF (PIR1) is set. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in SLEEP mode, the slave can transmit/receive data. When a byte is received, the device will wake-up from SLEEP. Note 1: When the SPI module is in Slave mode with SS pin control enabled (SSPCON = 0100), the SPI module will reset if the SS pin is set to VDD. 2: If the SPI is used in Slave mode with CKE = ’1’, then SS pin control must be enabled. FIGURE 9-3: SS (optional) SPI MODE TIMING (SLAVE MODE WITH CKE = 0) SCK (CKP = 0) SCK (CKP = 1) SDO SDI (SMP = 0) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 SSPIF bit0 FIGURE 9-4: SS SPI MODE TIMING (SLAVE MODE WITH CKE = 1) SCK (CKP = 0) SCK (CKP = 1) SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI (SMP = 0) bit7 SSPIF bit0  2001 Microchip Technology Inc. DS30292C-page 71 PIC16F87X TABLE 9-1: Address REGISTERS ASSOCIATED WITH SPI OPERATION Name Bit 7 GIE PSPIF(1) PSPIE(1) WCOL SMP Bit 6 PEIE ADIF ADIE Bit 5 T0IE RCIF RCIE Bit 4 INTE TXIF TXIE CKP P Bit 3 RBIE SSPIF SSPIE SSPM3 S Bit 2 T0IF CCP1IF CCP1IE SSPM2 R/W Bit 1 INTF TMR2IF TMR2IE SSPM1 UA Bit 0 RBIF Value on: POR, BOR 0000 000x Value on: MCLR, WDT 0000 000u 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 8Ch 13h 14h 94h PIR1 PIE1 SSPBUF SSPCON SSPSTAT TMR1IF 0000 0000 TMR1IE 0000 0000 xxxx xxxx Synchronous Serial Port Receive Buffer/Transmit Register SSPOV SSPEN CKE D/A SSPM0 BF 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as ’0’. Shaded cells are not used by the SSP in SPI mode. Note 1: These bits are reserved on PCI16F873/876 devices; always maintain these bits clear. DS30292C-page 72  2001 Microchip Technology Inc. PIC16F87X 9.2 MSSP I 2C Operation The MSSP module in I2C mode, fully implements all master and slave functions (including general call support) and provides interrupts on START and STOP bits in hardware, to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. Refer to Application Note AN578, "Use of the SSP Module in the I 2C Multi-Master Environment." A "glitch" filter is on the SCL and SDA pins when the pin is an input. This filter operates in both the 100 kHz and 400 kHz modes. In the 100 kHz mode, when these pins are an output, there is a slew rate control of the pin that is independent of device frequency. The SSPCON register allows control of the I 2C operation. Four mode selection bits (SSPCON) allow one of the following I 2C modes to be selected: • • • • I 2C Slave mode (7-bit address) I 2C Slave mode (10-bit address) I 2C Master mode, clock = OSC/4 (SSPADD +1) I2C firmware modes (provided for compatibility to other mid-range products) Before selecting any I 2C mode, the SCL and SDA pins must be programmed to inputs by setting the appropriate TRIS bits. Selecting an I 2C mode by setting the SSPEN bit, enables the SCL and SDA pins to be used as the clock and data lines in I 2C mode. Pull-up resistors must be provided externally to the SCL and SDA pins for the proper operation of the I2C module. The CKE bit (SSPSTAT) sets the levels of the SDA and SCL pins in either Master or Slave mode. When CKE = 1, the levels will conform to the SMBus specification. When CKE = 0, the levels will conform to the I2C specification. The SSPSTAT register gives the status of the data transfer. This information includes detection of a START (S) or STOP (P) bit, specifies if the received byte was data or address, if the next byte is the completion of 10-bit address, and if this will be a read or write data transfer. SSPBUF is the register to which the transfer data is written to, or read from. The SSPSR register shifts the data in or out of the device. In receive operations, the SSPBUF and SSPSR create a doubled buffered receiver. This allows reception of the next byte to begin before reading the last byte of received data. When the complete byte is received, it is transferred to the SSPBUF register and flag bit SSPIF is set. If another complete byte is received before the SSPBUF register is read, a receiver overflow has occurred and bit SSPOV (SSPCON) is set and the byte in the SSPSR is lost. The SSPADD register holds the slave address. In 10-bit mode, the user needs to write the high byte of the address (1111 0 A9 A8 0). Following the high byte address match, the low byte of the address needs to be loaded (A7:A0). FIGURE 9-5: I2C SLAVE MODE BLOCK DIAGRAM Internal Data Bus Read SSPBUF Reg Shift Clock SSPSR Reg Write SCL SDA MSb LSb Match Detect Addr Match SSPADD Reg START and STOP bit Detect Set, Reset S, P bits (SSPSTAT Reg) Two pins are used for data transfer. These are the SCL pin, which is the clock, and the SDA pin, which is the data. The SDA and SCL pins are automatically configured when the I2C mode is enabled. The SSP module functions are enabled by setting SSP Enable bit SSPEN (SSPCON). The MSSP module has six registers for I2C operation. They are the: • • • • • SSP Control Register (SSPCON) SSP Control Register2 (SSPCON2) SSP Status Register (SSPSTAT) Serial Receive/Transmit Buffer (SSPBUF) SSP Shift Register (SSPSR) - Not directly accessible • SSP Address Register (SSPADD)  2001 Microchip Technology Inc. DS30292C-page 73 PIC16F87X 9.2.1 SLAVE MODE In Slave mode, the SCL and SDA pins must be configured as inputs. The MSSP module will override the input state with the output data, when required (slavetransmitter). When an address is matched, or the data transfer after an address match is received, the hardware automatically will generate the Acknowledge (ACK) pulse, and then load the SSPBUF register with the received value currently in the SSPSR register. There are certain conditions that will cause the MSSP module not to give this ACK pulse. These are if either (or both): a) b) The buffer full bit BF (SSPSTAT) was set before the transfer was received. The overflow bit SSPOV (SSPCON) was set before the transfer was received. For a 10-bit address, the first byte would equal ‘1111 0 A9 A8 0’, where A9 and A8 are the two MSbs of the address. The sequence of events for a 10-bit address is as follows, with steps 7-9 for slave-transmitter: 1. 2. Receive first (high) byte of Address (bits SSPIF, BF and UA (SSPSTAT) are set). Update the SSPADD register with the second (low) byte of Address (clears bit UA and releases the SCL line). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive second (low) byte of Address (bits SSPIF, BF and UA are set). Update the SSPADD register with the first (high) byte of Address. This will clear bit UA and release the SCL line. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive Repeated Start condition. Receive first (high) byte of Address (bits SSPIF and BF are set). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Note: Following the Repeated START condition (step 7) in 10-bit mode, the user only needs to match the first 7-bit address. The user does not update the SSPADD for the second half of the address. 3. 4. 5. 6. 7. 8. 9. If the BF bit is set, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF and SSPOV are set. Table 9-2 shows what happens when a data transfer byte is received, given the status of bits BF and SSPOV. The shaded cells show the condition where user software did not properly clear the overflow condition. Flag bit BF is cleared by reading the SSPBUF register, while bit SSPOV is cleared through software. The SCL clock input must have a minimum high and low time for proper operation. The high and low times of the I2C specification, as well as the requirement of the MSSP module, is shown in timing parameter #100 and parameter #101 of the electrical specifications. 9.2.1.2 Slave Reception 9.2.1.1 Addressing Once the MSSP module has been enabled, it waits for a START condition to occur. Following the START condition, the 8-bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR is compared to the value of the SSPADD register. The address is compared on the falling edge of the eighth clock (SCL) pulse. If the addresses match, and the BF and SSPOV bits are clear, the following events occur: a) The SSPSR register value is loaded into the SSPBUF register on the falling edge of the 8th SCL pulse. The buffer full bit, BF, is set on the falling edge of the 8th SCL pulse. An ACK pulse is generated. SSP interrupt flag bit, SSPIF (PIR1), is set (interrupt is generated if enabled) on the falling edge of the 9th SCL pulse. When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register. When the address byte overflow condition exists, then no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT) is set, or bit SSPOV (SSPCON) is set. This is an error condition due to user firmware. An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF (PIR1) must be cleared in software. The SSPSTAT register is used to determine the status of the received byte. Note: The SSPBUF will be loaded if the SSPOV bit is set and the BF flag is cleared. If a read of the SSPBUF was performed, but the user did not clear the state of the SSPOV bit before the next receive occurred, the ACK is not sent and the SSPBUF is updated. b) c) d) In 10-bit address mode, two address bytes need to be received by the slave. The five Most Significant bits (MSbs) of the first address byte specify if this is a 10-bit address. Bit R/W (SSPSTAT) must specify a write so the slave device will receive the second address byte. DS30292C-page 74  2001 Microchip Technology Inc. PIC16F87X TABLE 9-2: DATA TRANSFER RECEIVED BYTE ACTIONS SSPSR → SSPBUF Yes No No Yes Generate ACK Pulse Yes No No No Set bit SSPIF (SSP Interrupt occurs if enabled) Yes Yes Yes Yes Status Bits as Data Transfer is Received BF 0 1 1 0 Note: SSPOV 0 0 1 1 Shaded cells show the conditions where the user software did not properly clear the overflow condition. 9.2.1.3 Slave Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The ACK pulse will be sent on the ninth bit, and the SCL pin is held low. The transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then, the SCL pin should be enabled by setting bit CKP (SSPCON). The master must monitor the SCL pin prior to asserting another clock pulse. The slave devices may be holding off the master by stretching the clock. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time (Figure 9-7). An SSP interrupt is generated for each data transfer byte. The SSPIF flag bit must be cleared in software and the SSPSTAT register is used to determine the status of the byte transfer. The SSPIF flag bit is set on the falling edge of the ninth clock pulse. As a slave-transmitter, the ACK pulse from the master receiver is latched on the rising edge of the ninth SCL input pulse. If the SDA line is high (not ACK), then the data transfer is complete. When the not ACK is latched by the slave, the slave logic is reset and the slave then monitors for another occurrence of the START bit. If the SDA line was low (ACK), the transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then the SCL pin should be enabled by setting the CKP bit. FIGURE 9-6: I 2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS) Receiving Address R/W=0 ACK Not Receiving Data Receiving Data ACK ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P SDA A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 SCL SSPIF S Bus Master Terminates Transfer Cleared in software SSPBUF register is read BF (SSPSTAT) SSPOV (SSPCON) Bit SSPOV is set because the SSPBUF register is still full. ACK is not sent.  2001 Microchip Technology Inc. DS30292C-page 75 PIC16F87X FIGURE 9-7: I 2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS) R/W = 1 Receiving Address SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 Transmitting Data D3 D2 D1 D0 R/W = 0 Not ACK SCL S 1 2 Data in sampled 3 4 5 6 7 8 9 1 SCL held low while CPU responds to SSPIF 2 3 4 5 6 7 8 9 P SSPIF BF (SSPSTAT) Cleared in software SSPBUF is written in software CKP (SSPCON) Set bit after writing to SSPBUF (the SSPBUF must be written to, before the CKP bit can be set) From SSP Interrupt Service Routine 9.2.2 GENERAL CALL ADDRESS SUPPORT The addressing procedure for the I2C bus is such that the first byte after the START condition usually determines which device will be the slave addressed by the master. The exception is the general call address, which can address all devices. When this address is used, all devices should, in theory, respond with an acknowledge. The general call address is one of eight addresses reserved for specific purposes by the I2C protocol. It consists of all 0’s with R/W = 0. The general call address is recognized when the General Call Enable bit (GCEN) is enabled (SSPCON2 is set). Following a START bit detect, 8 bits are shifted into SSPSR and the address is compared against SSPADD. It is also compared to the general call address and fixed in hardware. If the general call address matches, the SSPSR is transferred to the SSPBUF, the BF flag is set (eighth bit), and on the falling edge of the ninth bit (ACK bit), the SSPIF flag is set. When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the SSPBUF to determine if the address was device specific, or a general call address. In 10-bit mode, the SSPADD is required to be updated for the second half of the address to match, and the UA bit is set (SSPSTAT). If the general call address is sampled when GCEN is set, while the slave is configured in 10-bit address mode, then the second half of the address is not necessary, the UA bit will not be set, and the slave will begin receiving data after the Acknowledge (Figure 9-8). FIGURE 9-8: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT MODE) Address is compared to General Call Address after ACK, set interrupt flag General Call Address R/W = 0 ACK D7 Receiving data D6 D5 D4 D3 D2 D1 D0 ACK SDA SCL S SSPIF 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 BF (SSPSTAT) Cleared in software SSPBUF is read ’0’ SSPOV (SSPCON) GCEN (SSPCON2) ’1’ DS30292C-page 76  2001 Microchip Technology Inc. PIC16F87X 9.2.3 SLEEP OPERATION 9.2.4 EFFECTS OF A RESET While in SLEEP mode, the I2C module can receive addresses or data. When an address match or complete byte transfer occurs, wake the processor from SLEEP (if the SSP interrupt is enabled). A RESET disables the SSP module and terminates the current transfer. TABLE 9-3: Address REGISTERS ASSOCIATED WITH I2C OPERATION Name Bit 7 GIE PSPIF(1) PSPIE(1) — — WCOL GCEN Bit 6 PEIE ADIF ADIE (2) (2) SSPOV ACKSTAT Bit 5 T0IE RCIF RCIE — — SSPEN ACKDT Bit 4 INTE TXIF TXIE EEIF EEIE CKP ACKEN Bit 3 RBIE SSPIF SSPIE BCLIF BCLIE Bit 2 T0IF Bit 1 INTF Bit 0 RBIF Value on: POR, BOR Value on: MCLR, WDT 0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 8Ch 0Dh 8Dh 13h 14h 91h 93h 94h PIR1 PIE1 PIR2 PIE2 SSPBUF SSPCON SSPCON2 SSPADD SSPSTAT 0000 000x 0000 000u CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 — — — — SSPM1 RSEN CCP2IF -r-0 0--0 -r-0 0--0 CCP2IE -r-0 0--0 -r-0 0--0 xxxx xxxx uuuu uuuu Synchronous Serial Port Receive Buffer/Transmit Register SSPM3 SSPM2 RCEN PEN SEN SSPM0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 I2C Slave Address/Master Baud Rate Register SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the SSP in I2C mode. Note 1: These bits are reserved on PIC16F873/876 devices; always maintain these bits clear. 2: These bits are reserved on these devices; always maintain these bits clear.  2001 Microchip Technology Inc. DS30292C-page 77 PIC16F87X 9.2.5 MASTER MODE Master mode of operation is supported by interrupt generation on the detection of the START and STOP conditions. The STOP (P) and START (S) bits are cleared from a RESET, or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit is set, or the bus is idle, with both the S and P bits clear. In Master mode, the SCL and SDA lines are manipulated by the MSSP hardware. The following events will cause the SSP Interrupt Flag bit, SSPIF, to be set (an SSP interrupt will occur if enabled): • • • • • START condition STOP condition Data transfer byte transmitted/received Acknowledge transmit Repeated START FIGURE 9-9: SSP BLOCK DIAGRAM (I2C MASTER MODE) Internal Data Bus Read SSPBUF Write Baud Rate Generator Clock Arbitrate/WCOL Detect (hold off clock source)  2001 Microchip Technology Inc. Shift Clock SSPSR Receive Enable MSb LSb SSPM3:SSPM0, SSPADD SDA SDA in SCL SCL in Bus Collision START bit Detect, STOP bit Detect Write Collision Detect Clock Arbitration State Counter for end of XMIT/RCV Set/Reset, S, P, WCOL (SSPSTAT) Set SSPIF, BCLIF Reset ACKSTAT, PEN (SSPCON2) 9.2.6 MULTI-MASTER MODE In Multi-Master mode, the interrupt generation on the detection of the START and STOP conditions allows the determination of when the bus is free. The STOP (P) and START (S) bits are cleared from a RESET or when the MSSP module is disabled. Control of the I 2C bus may be taken when bit P (SSPSTAT) is set, or the bus is idle with both the S and P bits clear. When the bus is busy, enabling the SSP Interrupt will generate the interrupt when the STOP condition occurs. In Multi-Master operation, the SDA line must be monitored for arbitration to see if the signal level is the expected output level. This check is performed in hardware, with the result placed in the BCLIF bit. The states where arbitration can be lost are: • • • • • Address Transfer Data Transfer A START Condition A Repeated START Condition An Acknowledge Condition DS30292C-page 78 Clock Cntl START bit, STOP bit, Acknowledge Generate PIC16F87X 9.2.7 I2C MASTER MODE SUPPORT Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON and by setting the SSPEN bit. Once Master mode is enabled, the user has six options: • Assert a START condition on SDA and SCL. • Assert a Repeated START condition on SDA and SCL. • Write to the SSPBUF register initiating transmission of data/address. • Generate a STOP condition on SDA and SCL. • Configure the I2C port to receive data. • Generate an Acknowledge condition at the end of a received byte of data. Note: The MSSP Module, when configured in I2C Master mode, does not allow queueing of events. For instance, the user is not allowed to initiate a START condition and immediately write the SSPBUF register to initiate transmission before the START condition is complete. In this case, the SSPBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPBUF did not occur. SSPBUF. Once the given operation is complete (i.e., transmission of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state. A typical transmit sequence would go as follows: a) b) c) d) e) User generates a START condition by setting the START enable bit (SEN) in SSPCON2. SSPIF is set. The module will wait the required start time before any other operation takes place. User loads SSPBUF with address to transmit. Address is shifted out the SDA pin until all 8 bits are transmitted. MSSP module shifts in the ACK bit from the slave device and writes its value into the SSPCON2 register (SSPCON2). MSSP module generates an interrupt at the end of the ninth clock cycle by setting SSPIF. User loads SSPBUF with eight bits of data. DATA is shifted out the SDA pin until all 8 bits are transmitted. MSSP module shifts in the ACK bit from the slave device, and writes its value into the SSPCON2 register (SSPCON2). MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. User generates a STOP condition by setting the STOP enable bit, PEN, in SSPCON2. Interrupt is generated once the STOP condition is complete. f) g) h) i) j) k) l) 9.2.7.1 I2C Master Mode Operation The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a Repeated START condition. Since the Repeated START condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the Read/Write (R/W) bit. In this case, the R/W bit will be logic '0'. Serial data is transmitted 8 bits at a time. After each byte is transmitted, an Acknowledge bit is received. START and STOP conditions are output to indicate the beginning and the end of a serial transfer. In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the R/W bit. In this case, the R/W bit will be logic '1'. Thus, the first byte transmitted is a 7-bit slave address followed by a '1' to indicate receive bit. Serial data is received via SDA, while SCL outputs the serial clock. Serial data is received 8 bits at a time. After each byte is received, an Acknowledge bit is transmitted. START and STOP conditions indicate the beginning and end of transmission. The baud rate generator used for SPI mode operation is now used to set the SCL clock frequency for either 100 kHz, 400 kHz, or 1 MHz I2C operation. The baud rate generator reload value is contained in the lower 7 bits of the SSPADD register. The baud rate generator will automatically begin counting on a write to the 9.2.8 I2C BAUD RATE GENERATOR In Master mode, the reload value for the BRG is located in the lower 7 bits of the SSPADD register (Figure 9-10). When the BRG is loaded with this value, the BRG counts down to 0 and stops until another reload has taken place. The BRG count is decremented twice per instruction cycle (TCY), on the Q2 and Q4 clock. In I2C Master mode, the BRG is reloaded automatically. If clock arbitration is taking place, the BRG will be reloaded when the SCL pin is sampled high (Figure 9-11). Note: Baud Rate = FOSC / (4 * (SSPADD + 1) ) FIGURE 9-10: SSPM3:SSPM0 BAUD RATE GENERATOR BLOCK DIAGRAM SSPADD SSPM3:SSPM0 SCL CLKOUT Reload Control Reload BRG Down Counter FOSC/4  2001 Microchip Technology Inc. DS30292C-page 79 PIC16F87X FIGURE 9-11: SDA BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION DX DX-1 SCL allowed to transition high SCL de-asserted but slave holds SCL low (clock arbitration) SCL BRG decrements (on Q2 and Q4 cycles) BRG Value 03h 02h 01h 00h (hold off) 03h 02h SCL is sampled high, reload takes place, and BRG starts its count BRG Reload 9.2.9 I2C MASTER MODE START CONDITION TIMING Note: To initiate a START condition, the user sets the START condition enable bit, SEN (SSPCON2). If the SDA and SCL pins are sampled high, the baud rate generator is reloaded with the contents of SSPADD and starts its count. If SCL and SDA are both sampled high when the baud rate generator times out (TBRG), the SDA pin is driven low. The action of the SDA being driven low while SCL is high is the START condition, and causes the S bit (SSPSTAT) to be set. Following this, the baud rate generator is reloaded with the contents of SSPADD and resumes its count. When the baud rate generator times out (TBRG), the SEN bit (SSPCON2) will be automatically cleared by hardware. The baud rate generator is suspended, leaving the SDA line held low, and the START condition is complete. If, at the beginning of START condition, the SDA and SCL pins are already sampled low, or if during the START condition the SCL line is sampled low before the SDA line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag (BCLIF) is set, the START condition is aborted, and the I2C module is reset into its IDLE state. 9.2.9.1 WCOL Status Flag If the user writes the SSPBUF when a START sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). Note: Because queueing of events is not allowed, writing to the lower 5 bits of SSPCON2 is disabled until the START condition is complete. FIGURE 9-12: FIRST START BIT TIMING Write to SEN bit occurs here SDA = 1, SCL = 1 Set S bit (SSPSTAT) At completion of START bit, Hardware clears SEN bit and sets SSPIF bit TBRG Write to SSPBUF occurs here 1st Bit SDA TBRG 2nd Bit TBRG SCL S TBRG DS30292C-page 80  2001 Microchip Technology Inc. PIC16F87X 9.2.10 I2C MASTER MODE REPEATED START CONDITION TIMING Immediately following the SSPIF bit getting set, the user may write the SSPBUF with the 7-bit address in 7-bit mode, or the default first address in 10-bit mode. After the first eight bits are transmitted and an ACK is received, the user may then transmit an additional eight bits of address (10-bit mode), or eight bits of data (7-bit mode). A Repeated START condition occurs when the RSEN bit (SSPCON2) is programmed high and the I2C module is in the IDLE state. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the baud rate generator is loaded with the contents of SSPADD and begins counting. The SDA pin is released (brought high) for one baud rate generator count (TBRG). When the baud rate generator times out, if SDA is sampled high, the SCL pin will be de-asserted (brought high). When SCL is sampled high the baud rate generator is reloaded with the contents of SSPADD and begins counting. SDA and SCL must be sampled high for one TBRG. This action is then followed by assertion of the SDA pin (SDA is low) for one TBRG, while SCL is high. Following this, the RSEN bit in the SSPCON2 register will be automatically cleared and the baud rate generator will not be reloaded, leaving the SDA pin held low. As soon as a START condition is detected on the SDA and SCL pins, the S bit (SSPSTAT) will be set. The SSPIF bit will not be set until the baud rate generator has timed out. Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. 2: A bus collision during the Repeated START condition occurs if: • SDA is sampled low when SCL goes from low to high. • SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data "1". 9.2.10.1 WCOL Status Flag If the user writes the SSPBUF when a Repeated START sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). Note: Because queueing of events is not allowed, writing of the lower 5 bits of SSPCON2 is disabled until the Repeated START condition is complete. FIGURE 9-13: REPEAT START CONDITION WAVEFORM Write to SSPCON2 occurs here SDA = 1, SCL (no change) Set S (SSPSTAT) SDA = 1, SCL = 1 At completion of START bit, hardware clears RSEN bit and sets SSPIF TBRG 1st bit Write to SSPBUF occurs here TBRG TBRG Sr = Repeated START TBRG SDA Falling edge of ninth clock End of Xmit SCL TBRG  2001 Microchip Technology Inc. DS30292C-page 81 PIC16F87X 9.2.11 I2C MASTER MODE TRANSMISSION 9.2.11.1 BF Status Flag In Transmit mode, the BF bit (SSPSTAT) is set when the CPU writes to SSPBUF and is cleared when all 8 bits are shifted out. Transmission of a data byte, a 7-bit address, or either half of a 10-bit address, is accomplished by simply writing a value to SSPBUF register. This action will set the Buffer Full flag (BF) and allow the baud rate generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted (see data hold time spec). SCL is held low for one baud rate generator rollover count (TBRG). Data should be valid before SCL is released high (see data setup time spec). When the SCL pin is released high, it is held that way for TBRG. The data on the SDA pin must remain stable for that duration and some hold time after the next falling edge of SCL. After the eighth bit is shifted out (the falling edge of the eighth clock), the BF flag is cleared and the master releases SDA allowing the slave device being addressed to respond with an ACK bit during the ninth bit time, if an address match occurs or if data was received properly. The status of ACK is read into the ACKDT on the falling edge of the ninth clock. If the master receives an Acknowledge, the Acknowledge Status bit (ACKSTAT) is cleared. If not, the bit is set. After the ninth clock, the SSPIF is set and the master clock (baud rate generator) is suspended until the next data byte is loaded into the SSPBUF, leaving SCL low and SDA unchanged (Figure 9-14). After the write to the SSPBUF, each bit of address will be shifted out on the falling edge of SCL, until all seven address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will de-assert the SDA pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDA pin to see if the address was recognized by a slave. The status of the ACK bit is loaded into the ACKSTAT status bit (SSPCON2). Following the falling edge of the ninth clock transmission of the address, the SSPIF is set, the BF flag is cleared, and the baud rate generator is turned off until another write to the SSPBUF takes place, holding SCL low and allowing SDA to float. 9.2.11.2 WCOL Status Flag If the user writes the SSPBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte), then WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). WCOL must be cleared in software. 9.2.11.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit (SSPCON2) is cleared when the slave has sent an Acknowledge (ACK = 0), and is set when the slave does not Acknowledge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. DS30292C-page 82  2001 Microchip Technology Inc. FIGURE 9-14: Write SSPCON2 SEN = 1 START condition begins From slave clear ACKSTAT bit SSPCON2 R/W = 0 A1 D7 D6 D5 D4 D3 D2 ACK = 0 Transmitting Data or Second Half of 10-bit address D1 D0 SEN = 0 Transmit Address to Slave SDA SSPBUF written with 7-bit address and R/W start transmit SCL S 1 2 3 4 5 6 7 8 9 1 SCL held low while CPU responds to SSPIF 2 3 4 5 6 7 8 9 A7 A6 A5 A4 A3 A2  2001 Microchip Technology Inc. ACKSTAT in SSPCON2 = 1 ACK P SSPIF Cleared in software Cleared in software service routine From SSP interrupt Cleared in software BF (SSPSTAT) SSPBUF written SEN After START condition SEN, cleared by hardware. SSPBUF is written in software PEN R/W I 2C MASTER MODE TIMING (TRANSMISSION, 7 OR 10-BIT ADDRESS) PIC16F87X DS30292C-page 83 PIC16F87X 9.2.12 I2C MASTER MODE RECEPTION 9.2.12.1 BF Status Flag Master mode reception is enabled by programming the Receive Enable bit, RCEN (SSPCON2). Note: The SSP module must be in an IDLE state before the RCEN bit is set, or the RCEN bit will be disregarded. In receive operation, BF is set when an address or data byte is loaded into SSPBUF from SSPSR. It is cleared when SSPBUF is read. 9.2.12.2 SSPOV Status Flag The baud rate generator begins counting, and on each rollover, the state of the SCL pin changes (high to low/ low to high), and data is shifted into the SSPSR. After the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the SSPSR are loaded into the SSPBUF, the BF flag is set, the SSPIF is set, and the baud rate generator is suspended from counting, holding SCL low. The SSP is now in IDLE state, awaiting the next command. When the buffer is read by the CPU, the BF flag is automatically cleared. The user can then send an Acknowledge bit at the end of reception, by setting the Acknowledge Sequence Enable bit, ACKEN (SSPCON2). In receive operation, SSPOV is set when 8 bits are received into the SSPSR, and the BF flag is already set from a previous reception. 9.2.12.3 WCOL Status Flag If the user writes the SSPBUF when a receive is already in progress (i.e., SSPSR is still shifting in a data byte), then WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). DS30292C-page 84  2001 Microchip Technology Inc. FIGURE 9-15: Write to SSPCON2 to start Acknowledge sequence SDA = ACKDT (SSPCON2) = 0 Master configured as a receiver by programming SSPCON2, (RCEN = 1) ACK from Slave R/W = 1 A1 D7 D1 D0 D7 D1 D6 D4 D3 D6 D4 D3 ACK D5 D5 D2 D2 ACK Receiving Data from Slave Receiving Data from Slave D0 ACK RCEN cleared automatically RCEN = 1 start next receive RCEN cleared automatically ACK from Master SDA = ACKDT = 0 Set ACKEN to start Acknowledge sequence SDA = ACKDT = 1 PEN bit = 1 written here  2001 Microchip Technology Inc. A4 A3 A2 ACK is not sent 4 5 1 2 3 4 5 1 2 3 4 6 8 6 7 8 9 7 9 5 6 7 8 9 Set SSPIF at end of receive Bus Master terminates transfer P Set SSPIF interrupt at end of Acknowledge sequence Data shifted in on falling edge of CLK Set SSPIF interrupt at end of receive Set SSPIF interrupt at end of acknowledge sequence Cleared in software Cleared in software Cleared in software Cleared in software Set P bit (SSPSTAT) and SSPIF Last bit is shifted into SSPSR and contents are unloaded into SSPBUF SSPOV is set because SSPBUF is still full Write to SSPCON2 (SEN = 1) Begin START Condition SEN = 0 Write to SSPBUF occurs here Start XMIT Transmit Address to Slave SDA A7 A6 A5 SCL S 1 2 3 SSPIF SDA = 0, SCL = 1 while CPU responds to SSPIF Cleared in software BF (SSPSTAT) I 2C MASTER MODE TIMING (RECEPTION, 7-BIT ADDRESS) SSPOV ACKEN PIC16F87X DS30292C-page 85 PIC16F87X 9.2.13 ACKNOWLEDGE SEQUENCE TIMING rate generator counts for TBRG. The SCL pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the baud rate generator is turned off, and the SSP module then goes into IDLE mode (Figure 9-16). An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable bit, ACKEN (SSPCON2). When this bit is set, the SCL pin is pulled low and the contents of the Acknowledge data bit is presented on the SDA pin. If the user wishes to generate an Acknowledge, the ACKDT bit should be cleared. If not, the user should set the ACKDT bit before starting an Acknowledge sequence. The baud rate generator then counts for one rollover period (TBRG), and the SCL pin is de-asserted high. When the SCL pin is sampled high (clock arbitration), the baud 9.2.13.1 WCOL Status Flag If the user writes the SSPBUF when an Acknowledge sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). FIGURE 9-16: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, Write to SSPCON2 ACKEN = 1, ACKDT = 0 TBRG SDA D0 ACK TBRG ACKEN automatically cleared SCL 8 9 SSPIF Set SSPIF at the end of receive Cleared in software Cleared in software Set SSPIF at the end of Acknowledge sequence Note: TBRG = one baud rate generator period. DS30292C-page 86  2001 Microchip Technology Inc. PIC16F87X 9.2.14 STOP CONDITION TIMING A STOP bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN (SSPCON2). At the end of a receive/ transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the baud rate generator is reloaded and counts down to 0. When the baud rate generator times out, the SCL pin will be brought high, and one TBRG (baud rate generator rollover count) later, the SDA pin will be de-asserted. When the SDA pin is sampled high while SCL is high, the P bit (SSPSTAT) is set. A TBRG later, the PEN bit is cleared and the SSPIF bit is set (Figure 9-17). Whenever the firmware decides to take control of the bus, it will first determine if the bus is busy by checking the S and P bits in the SSPSTAT register. If the bus is busy, then the CPU can be interrupted (notified) when a STOP bit is detected (i.e., bus is free). 9.2.14.1 WCOL Status Flag If the user writes the SSPBUF when a STOP sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). FIGURE 9-17: STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSPCON2 Set PEN Falling edge of 9th clock TBRG SCL SCL = 1 for TBRG, followed by SDA = 1 for TBRG after SDA sampled high. P bit (SSPSTAT) is set. PEN bit (SSPCON2) is cleared by hardware and the SSPIF bit is set SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup STOP condition Note: TBRG = one baud rate generator period.  2001 Microchip Technology Inc. DS30292C-page 87 PIC16F87X 9.2.15 CLOCK ARBITRATION 9.2.16 SLEEP OPERATION Clock arbitration occurs when the master, during any receive, transmit, or Repeated START/STOP condition, de-asserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the baud rate generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the baud rate generator is reloaded with the contents of SSPADD and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 9-18). While in SLEEP mode, the I2C module can receive addresses or data, and when an address match or complete byte transfer occurs, wake the processor from SLEEP (if the SSP interrupt is enabled). 9.2.17 EFFECTS OF A RESET A RESET disables the SSP module and terminates the current transfer. FIGURE 9-18: CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE BRG overflow, Release SCL, If SCL = 1, Load BRG with SSPADD, and start count to measure high time interval BRG overflow occurs, Release SCL, Slave device holds SCL low SCL = 1, BRG starts counting clock high interval SCL SCL line sampled once every machine cycle (TOSC • 4). Hold off BRG until SCL is sampled high. SDA TBRG TBRG TBRG DS30292C-page 88  2001 Microchip Technology Inc. PIC16F87X 9.2.18 MULTI -MASTER COMMUNICATION, BUS COLLISION, AND BUS ARBITRATION If a START, Repeated START, STOP, or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDA and SCL lines are de-asserted, and the respective control bits in the SSPCON2 register are cleared. When the user services the bus collision Interrupt Service Routine, and if the I2C bus is free, the user can resume communication by asserting a START condition. The master will continue to monitor the SDA and SCL pins and if a STOP condition occurs, the SSPIF bit will be set. A write to the SSPBUF will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of START and STOP conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPSTAT register, or the bus is idle and the S and P bits are cleared. Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a ’1’ on SDA, by letting SDA float high and another master asserts a ’0’. When the SCL pin floats high, data should be stable. If the expected data on SDA is a ’1’ and the data sampled on the SDA pin = ’0’, a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLIF and reset the I2C port to its IDLE state (Figure 9-19). If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF flag is cleared, the SDA and SCL lines are de-asserted, and the SSPBUF can be written to. When the user services the bus collision Interrupt Service Routine, and if the I2C bus is free, the user can resume communication by asserting a START condition. FIGURE 9-19: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA line pulled low by another source SDA released by master Sample SDA. While SCL is high, data doesn’t match what is driven by the master. Bus collision has occurred. SDA SCL Set bus collision interrupt BCLIF  2001 Microchip Technology Inc. DS30292C-page 89 PIC16F87X 9.2.18.1 Bus Collision During a START Condition During a START condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the START condition (Figure 9-20). SCL is sampled low before SDA is asserted low (Figure 9-21). If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 9-22). If, however, a '1' is sampled on the SDA pin, the SDA pin is asserted low at the end of the BRG count. The baud rate generator is then reloaded and counts down to 0. During this time, if the SCL pins are sampled as '0', a bus collision does not occur. At the end of the BRG count, the SCL pin is asserted low. During a START condition, both the SDA and the SCL pins are monitored. If either the SDA pin or the SCL pin is already low, then these events all occur: • the START condition is aborted, • and the BCLIF flag is set, • and the SSP module is reset to its IDLE state (Figure 9-20). The START condition begins with the SDA and SCL pins de-asserted. When the SDA pin is sampled high, the baud rate generator is loaded from SSPADD and counts down to 0. If the SCL pin is sampled low while SDA is high, a bus collision occurs, because it is assumed that another master is attempting to drive a data '1' during the START condition. Note: The reason that bus collision is not a factor during a START condition is that no two bus masters can assert a START condition at the exact same time. Therefore, one master will always assert SDA before the other. This condition does not cause a bus collision, because the two masters must be allowed to arbitrate the first address following the START condition. If the address is the same, arbitration must be allowed to continue into the data portion, Repeated START, or STOP conditions. FIGURE 9-20: BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCLIF, S bit and SSPIF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable START condition if SDA = 1, SCL = 1 SEN SDA sampled low before START condition. Set BCLIF. S bit and SSPIF set because SDA = 0, SCL = 1. SSPIF and BCLIF are cleared in software S SEN cleared automatically because of bus collision. SSP module reset into IDLE state. BCLIF SSPIF SSPIF and BCLIF are cleared in software DS30292C-page 90  2001 Microchip Technology Inc. PIC16F87X FIGURE 9-21: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG SDA TBRG SCL Set SEN, enable START sequence if SDA = 1, SCL = 1 SCL = 0 before SDA = 0, Bus collision occurs, Set BCLIF SCL = 0 before BRG time-out, Bus collision occurs, Set BCLIF SEN BCLIF Interrupts cleared in software S SSPIF ’0’ ’0’ ’0’ ’0’ FIGURE 9-22: BRG RESET DUE TO SDA COLLISION DURING START CONDITION SDA = 0, SCL = 1 Set S Less than TBRG TBRG SDA pulled low by other master. Reset BRG and assert SDA. Set SSPIF SDA SCL s SCL pulled low after BRG Time-out Set SEN, enable START sequence if SDA = 1, SCL = 1 SEN BCLIF ’0’ S SSPIF SDA = 0, SCL = 1 Set SSPIF Interrupts cleared in software  2001 Microchip Technology Inc. DS30292C-page 91 PIC16F87X 9.2.18.2 Bus Collision During a Repeated START Condition During a Repeated START condition, a bus collision occurs if: a) b) A low level is sampled on SDA when SCL goes from low level to high level. SCL goes low before SDA is asserted low, indicating that another master is attempting to transmit a data ’1’. SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high to low before the BRG times out, no bus collision occurs, because no two masters can assert SDA at exactly the same time. If, however, SCL goes from high to low before the BRG times out and SDA has not already been asserted, a bus collision occurs. In this case, another master is attempting to transmit a data’1’ during the Repeated START condition. If at the end of the BRG time-out, both SCL and SDA are still high, the SDA pin is driven low, the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated START condition is complete (Figure 9-23). When the user de-asserts SDA and the pin is allowed to float high, the BRG is loaded with SSPADD and counts down to 0. The SCL pin is then de-asserted, and when sampled high, the SDA pin is sampled. If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data’0’). If, however, FIGURE 9-23: SDA BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SCL Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. RSEN BCLIF Cleared in software ’0’ ’0’ S SSPIF ’0’ ’0’ FIGURE 9-24: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL SCL goes low before SDA, Set BCLIF. Release SDA and SCL. Interrupt cleared in software RSEN S SSPIF ’0’ ’0’ ’0’ ’0’ BCLIF DS30292C-page 92  2001 Microchip Technology Inc. PIC16F87X 9.2.18.3 Bus Collision During a STOP Condition Bus collision occurs during a STOP condition if: a) After the SDA pin has been de-asserted and allowed to float high, SDA is sampled low after the BRG has timed out. After the SCL pin is de-asserted, SCL is sampled low before SDA goes high. The STOP condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the baud rate generator is loaded with SSPADD and counts down to 0. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ’0’. If the SCL pin is sampled low before SDA is allowed to float high, a bus collision occurs. This is a case of another master attempting to drive a data ’0’ (Figure 9-25). b) FIGURE 9-25: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA sampled low after TBRG, Set BCLIF SDA SDA asserted low SCL PEN BCLIF P SSPIF ’0’ ’0’ ’0’ ’0’ FIGURE 9-26: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA Assert SDA SCL PEN BCLIF P SSPIF ’0’ ’0’ SCL goes low before SDA goes high, Set BCLIF  2001 Microchip Technology Inc. DS30292C-page 93 PIC16F87X 9.3 Connection Considerations for I2C Bus example, with a supply voltage of VDD = 5V±10% and VOL max = 0.4V at 3 mA, Rp min = (5.5-0.4)/0.003 = 1.7 kΩ. VDD as a function of Rp is shown in Figure 9-27. The desired noise margin of 0.1VDD for the low level limits the maximum value of Rs. Series resistors are optional and used to improve ESD susceptibility. The bus capacitance is the total capacitance of wire, connections, and pins. This capacitance limits the maximum value of Rp due to the specified rise time (Figure 9-27). The SMP bit is the slew rate control enabled bit. This bit is in the SSPSTAT register, and controls the slew rate of the I/O pins when in I2C mode (master or slave). For standard-mode I2C bus devices, the values of resistors Rp and Rs in Figure 9-27 depend on the following parameters: • Supply voltage • Bus capacitance • Number of connected devices (input current + leakage current) The supply voltage limits the minimum value of resistor Rp, due to the specified minimum sink current of 3 mA at VOL max = 0.4V, for the specified output stages. For FIGURE 9-27: SAMPLE DEVICE CONFIGURATION FOR I2C BUS VDD + 10% Rp Rp DEVICE Rs Rs SDA SCL Cb=10 - 400 pF Note: I2C devices with input levels related to VDD must have one common supply line to which the pull-up resistor is also connected. DS30292C-page 94  2001 Microchip Technology Inc. PIC16F87X 10.0 ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART) The USART can be configured in the following modes: • Asynchronous (full duplex) • Synchronous - Master (half duplex) • Synchronous - Slave (half duplex) Bit SPEN (RCSTA) and bits TRISC have to be set in order to configure pins RC6/TX/CK and RC7/RX/DT as the Universal Synchronous Asynchronous Receiver Transmitter. The USART module also has a multi-processor communication capability using 9-bit address detection. The Universal Synchronous Asynchronous Receiver Transmitter (USART) module is one of the two serial I/O modules. (USART is also known as a Serial Communications Interface or SCI.) The USART can be configured as a full duplex asynchronous system that can communicate with peripheral devices such as CRT terminals and personal computers, or it can be configured as a half duplex synchronous system that can communicate with peripheral devices such as A/D or D/A integrated circuits, serial EEPROMs etc. REGISTER 10-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h) R/W-0 CSRC bit 7 R/W-0 TX9 R/W-0 TXEN R/W-0 SYNC U-0 — R/W-0 BRGH R-1 TRMT R/W-0 TX9D bit 0 bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled Note: SREN/CREN overrides TXEN in SYNC mode. bit 6 bit 5 bit 4 SYNC: USART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode Unimplemented: Read as '0' BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full TX9D: 9th bit of Transmit Data, can be parity bit Legend: R = Readable bit - n = Value at POR W = Writable bit ’1’ = Bit is set U = Unimplemented bit, read as ‘0’ ’0’ = Bit is cleared x = Bit is unknown bit 3 bit 2 bit 1 bit 0  2001 Microchip Technology Inc. DS30292C-page 95 PIC16F87X REGISTER 10-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h) R/W-0 SPEN bit 7 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RC7/RX/DT and RC6/TX/CK pins as serial port pins) 0 = Serial port disabled RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception SREN: Single Receive Enable bit Asynchronous mode: Don’t care Synchronous mode - master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - slave: Don’t care CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables continuous receive 0 = Disables continuous receive Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enables interrupt and load of the receive buffer when RSR is set 0 = Disables address detection, all bytes are received, and ninth bit can be used as parity bit FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error RX9D: 9th bit of Received Data (can be parity bit, but must be calculated by user firmware) Legend: R = Readable bit - n = Value at POR W = Writable bit ’1’ = Bit is set U = Unimplemented bit, read as ‘0’ ’0’ = Bit is cleared x = Bit is unknown R/W-0 RX9 R/W-0 SREN R/W-0 CREN R/W-0 ADDEN R-0 FERR R-0 OERR R-x RX9D bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS30292C-page 96  2001 Microchip Technology Inc. PIC16F87X 10.1 USART Baud Rate Generator (BRG) It may be advantageous to use the high baud rate (BRGH = 1), even for slower baud clocks. This is because the FOSC/(16(X + 1)) equation can reduce the baud rate error in some cases. Writing a new value to the SPBRG register causes the BRG timer to be reset (or cleared). This ensures the BRG does not wait for a timer overflow before outputting the new baud rate. The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit baud rate generator. The SPBRG register controls the period of a free running 8-bit timer. In Asynchronous mode, bit BRGH (TXSTA) also controls the baud rate. In Synchronous mode, bit BRGH is ignored. Table 10-1 shows the formula for computation of the baud rate for different USART modes which only apply in Master mode (internal clock). Given the desired baud rate and FOSC, the nearest integer value for the SPBRG register can be calculated using the formula in Table 10-1. From this, the error in baud rate can be determined. 10.1.1 SAMPLING The data on the RC7/RX/DT pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RX pin. TABLE 10-1: SYNC 0 1 BAUD RATE FORMULA BRGH = 0 (Low Speed) (Asynchronous) Baud Rate = FOSC/(64(X+1)) (Synchronous) Baud Rate = FOSC/(4(X+1)) BRGH = 1 (High Speed) Baud Rate = FOSC/(16(X+1)) N/A X = value in SPBRG (0 to 255) TABLE 10-2: Address 98h 18h 99h REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Bit 7 CSRC SPEN Bit 6 TX9 RX9 Bit 5 TXEN SREN Bit 4 SYNC CREN Bit 3 — ADDEN Bit 2 BRGH FERR Bit 1 TRMT OERR Bit 0 TX9D RX9D Value on: POR, BOR 0000 -010 0000 000x 0000 0000 Name TXSTA RCSTA SPBRG Value on all other RESETS 0000 -010 0000 000x 0000 0000 Baud Rate Generator Register Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used by the BRG.  2001 Microchip Technology Inc. DS30292C-page 97 PIC16F87X TABLE 10-3: BAUD RATE (K) 0.3 1.2 2.4 9.6 19.2 28.8 33.6 57.6 HIGH LOW BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0) FOSC = 20 MHz % ERROR 1.75 0.17 1.73 1.72 8.51 3.34 8.51 FOSC = 4 MHz SPBRG value (decimal) 255 129 31 15 9 8 4 255 0 FOSC = 16 MHz % ERROR 0.17 0.17 0.16 0.16 3.55 6.29 8.51 SPBRG value (decimal) 207 103 25 12 8 6 3 255 0 FOSC = 10 MHz % ERROR 0.17 0.17 1.73 1.72 8.51 6.99 9.58 SPBRG value (decimal) 129 64 15 7 4 4 2 255 0 KBAUD 1.221 2.404 9.766 19.531 31.250 34.722 62.500 1.221 312.500 KBAUD 1.202 2.404 9.615 19.231 27.778 35.714 62.500 0.977 250.000 KBAUD 1.202 2.404 9.766 19.531 31.250 31.250 52.083 0.610 156.250 FOSC = 3.6864 MHz % ERROR 0 0 0 0 0 0 0 SPBRG value (decimal) 191 47 23 5 2 1 0 255 0 BAUD RATE (K) KBAUD 0.3 1.2 2.4 9.6 19.2 28.8 33.6 57.6 HIGH LOW 0.300 1.202 2.404 8.929 20.833 31.250 62.500 0.244 62.500 % ERROR 0 0.17 0.17 6.99 8.51 8.51 8.51 - SPBRG value (decimal) 207 51 25 6 2 1 0 255 0 KBAUD 0.3 1.2 2.4 9.6 19.2 28.8 57.6 0.225 57.6 TABLE 10-4: BAUD RATE (K) 0.3 1.2 2.4 9.6 19.2 28.8 33.6 57.6 HIGH LOW BAUD RATE (K) KBAUD 0.3 1.2 2.4 9.6 19.2 28.8 33.6 57.6 HIGH LOW 1.202 2.404 9.615 19.231 27.798 35.714 62.500 0.977 250.000 BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1) FOSC = 20 MHz % ERROR 0.16 0.16 0.94 0.55 3.34 FOSC = 4 MHz % ERROR 0.17 0.17 0.16 0.16 3.55 6.29 8.51 SPBRG value (decimal) 207 103 25 12 8 6 3 255 0 SPBRG value (decimal) 129 64 42 36 20 255 0 FOSC = 16 MHz % ERROR 0.16 0.16 2.13 0.79 2.13 SPBRG value (decimal) 103 51 33 29 16 255 0 FOSC = 10 MHz % ERROR 1.71 0.16 1.72 1.36 2.10 1.36 SPBRG value (decimal) 255 64 31 21 18 10 255 0 KBAUD 9.615 19.231 29.070 33.784 59.524 4.883 1250.000 KBAUD 9.615 19.231 29.412 33.333 58.824 3.906 1000.000 KBAUD 2.441 9.615 19.531 28.409 32.895 56.818 2.441 625.000 FOSC = 3.6864 MHz % ERROR 0 0 0 0 0 2.04 0 SPBRG value (decimal) 191 95 23 11 7 6 3 255 0 KBAUD 1.2 2.4 9.6 19.2 28.8 32.9 57.6 0.9 230.4 DS30292C-page 98  2001 Microchip Technology Inc. PIC16F87X 10.2 USART Asynchronous Mode In this mode, the USART uses standard non-return-tozero (NRZ) format (one START bit, eight or nine data bits, and one STOP bit). The most common data format is 8-bits. An on-chip, dedicated, 8-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. The USART transmits and receives the LSb first. The transmitter and receiver are functionally independent, but use the same data format and baud rate. The baud rate generator produces a clock, either x16 or x64 of the bit shift rate, depending on bit BRGH (TXSTA). Parity is not supported by the hardware, but can be implemented in software (and stored as the ninth data bit). Asynchronous mode is stopped during SLEEP. Asynchronous mode is selected by clearing bit SYNC (TXSTA). The USART Asynchronous module consists of the following important elements: • • • • Baud Rate Generator Sampling Circuit Asynchronous Transmitter Asynchronous Receiver enabled/disabled by setting/clearing enable bit TXIE ( PIE1). Flag bit TXIF will be set, regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicates the status of the TXREG register, another bit TRMT (TXSTA) shows the status of the TSR register. Status bit TRMT is a read only bit, which is set when the TSR register is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR register is empty. Note 1: The TSR register is not mapped in data memory, so it is not available to the user. 2: Flag bit TXIF is set when enable bit TXEN is set. TXIF is cleared by loading TXREG. Transmission is enabled by setting enable bit TXEN (TXSTA). The actual transmission will not occur until the TXREG register has been loaded with data and the baud rate generator (BRG) has produced a shift clock (Figure 10-2). The transmission can also be started by first loading the TXREG register and then setting enable bit TXEN. Normally, when transmission is first started, the TSR register is empty. At that point, transfer to the TXREG register will result in an immediate transfer to TSR, resulting in an empty TXREG. A back-to-back transfer is thus possible (Figure 10-3). Clearing enable bit TXEN during a transmission will cause the transmission to be aborted and will reset the transmitter. As a result, the RC6/TX/CK pin will revert to hi-impedance. In order to select 9-bit transmission, transmit bit TX9 (TXSTA) should be set and the ninth bit should be written to TX9D (TXSTA). The ninth bit must be written before writing the 8-bit data to the TXREG register. This is because a data write to the TXREG register can result in an immediate transfer of the data to the TSR register (if the TSR is empty). In such a case, an incorrect ninth data bit may be loaded in the TSR register. 10.2.1 USART ASYNCHRONOUS TRANSMITTER The USART transmitter block diagram is shown in Figure 10-1. The heart of the transmitter is the transmit (serial) shift register (TSR). The shift register obtains its data from the read/write transmit buffer, TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the STOP bit has been transmitted from the previous load. As soon as the STOP bit is transmitted, the TSR is loaded with new data from the TXREG register (if available). Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG register is empty and flag bit TXIF (PIR1) is set. This interrupt can be FIGURE 10-1: USART TRANSMIT BLOCK DIAGRAM Data Bus TXIF TXREG Register 8 MSb (8) Interrupt TXEN Baud Rate CLK TRMT SPBRG Baud Rate Generator TX9 TX9D SPEN ••• TSR Register LSb 0 Pin Buffer and Control RC6/TX/CK pin TXIE  2001 Microchip Technology Inc. DS30292C-page 99 PIC16F87X When setting up an Asynchronous Transmission, follow these steps: 1. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH (Section 10.1). Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, then set enable bit TXIE. If 9-bit transmission is desired, then set transmit bit TX9. 5. 6. 7. 8. Enable the transmission by setting bit TXEN, which will also set bit TXIF. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Load data to the TXREG register (starts transmission). If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set. 2. 3. 4. FIGURE 10-2: Write to TXREG BRG Output (Shift Clock) RC6/TX/CK (pin) TXIF bit (Transmit Buffer Reg. Empty Flag) ASYNCHRONOUS MASTER TRANSMISSION Word 1 START Bit Bit 0 Bit 1 Word 1 Bit 7/8 STOP Bit TRMT bit (Transmit Shift Reg. Empty Flag) Word 1 Transmit Shift Reg FIGURE 10-3: Write to TXREG BRG Output (Shift Clock) RC6/TX/CK (pin) TXIF bit (Interrupt Reg. Flag) TRMT bit (Transmit Shift Reg. Empty Flag) ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK) Word 1 Word 2 START Bit Bit 0 Bit 1 Word 1 Bit 7/8 STOP Bit START Bit Word 2 Bit 0 Word 1 Transmit Shift Reg. Word 2 Transmit Shift Reg. Note: This timing diagram shows two consecutive transmissions. TABLE 10-5: Address REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 7 GIE PSPIF(1) SPEN PSPIE(1) CSRC Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 T0IE RCIF SREN RCIE TXEN Bit 4 INTE TXIF CREN TXIE SYNC Bit 3 RBIE SSPIF — Bit 2 T0IF CCP1IF FERR Bit 1 INTF TMR2IF OERR TMR2IE TRMT Bit 0 R0IF TMR1IF RX9D TMR1IE TX9D Value on: POR, BOR 0000 000x 0000 0000 0000 -00x 0000 0000 0000 0000 0000 -010 0000 0000 Name Value on all other RESETS 0000 000u 0000 0000 0000 -00x 0000 0000 0000 0000 0000 -010 0000 0000 0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 19h 8Ch 98h 99h PIR1 RCSTA TXREG PIE1 TXSTA USART Transmit Register SSPIE CCP1IE — BRGH SPBRG Baud Rate Generator Register Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous transmission. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F873/876; always maintain these bits clear. DS30292C-page 100  2001 Microchip Technology Inc. PIC16F87X 10.2.2 USART ASYNCHRONOUS RECEIVER is possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte to begin shifting to the RSR register. On the detection of the STOP bit of the third byte, if the RCREG register is still full, the overrun error bit OERR (RCSTA) will be set. The word in the RSR will be lost. The RCREG register can be read twice to retrieve the two bytes in the FIFO. Overrun bit OERR has to be cleared in software. This is done by resetting the receive logic (CREN is cleared and then set). If bit OERR is set, transfers from the RSR register to the RCREG register are inhibited, and no further data will be received. It is therefore, essential to clear error bit OERR if it is set. Framing error bit FERR (RCSTA) is set if a STOP bit is detected as clear. Bit FERR and the 9th receive bit are buffered the same way as the receive data. Reading the RCREG will load bits RX9D and FERR with new values, therefore, it is essential for the user to read the RCSTA register before reading the RCREG register in order not to lose the old FERR and RX9D information. The receiver block diagram is shown in Figure 10-4. The data is received on the RC7/RX/DT pin and drives the data recovery block. The data recovery block is actually a high speed shifter, operating at x16 times the baud rate; whereas, the main receive serial shifter operates at the bit rate or at FOSC. Once Asynchronous mode is selected, reception is enabled by setting bit CREN (RCSTA). The heart of the receiver is the receive (serial) shift register (RSR). After sampling the STOP bit, the received data in the RSR is transferred to the RCREG register (if it is empty). If the transfer is complete, flag bit RCIF (PIR1) is set. The actual interrupt can be enabled/ disabled by setting/clearing enable bit RCIE (PIE1). Flag bit RCIF is a read only bit, which is cleared by the hardware. It is cleared when the RCREG register has been read and is empty. The RCREG is a double buffered register (i.e., it is a two deep FIFO). It FIGURE 10-4: USART RECEIVE BLOCK DIAGRAM x64 Baud Rate CLK CREN OERR FERR FOSC SPBRG Baud Rate Generator ÷64 or ÷16 MSb STOP (8) 7 RSR Register ••• 1 LSb 0 START RC7/RX/DT Pin Buffer and Control Data Recovery RX9 SPEN RX9D RCREG Register FIFO 8 Interrupt RCIF RCIE Data Bus  2001 Microchip Technology Inc. DS30292C-page 101 PIC16F87X FIGURE 10-5: RX (pin) Rcv Shift Reg Rcv Buffer Reg Read Rcv Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. ASYNCHRONOUS RECEPTION START bit bit0 bit1 bit7/8 STOP bit START bit bit0 bit7/8 STOP bit START bit bit7/8 STOP bit Word 1 RCREG Word 2 RCREG When setting up an Asynchronous Reception, follow these steps: 1. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH (Section 10.1). Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, then set enable bit RCIE. If 9-bit reception is desired, then set bit RX9. Enable the reception by setting bit CREN. 6. 2. 3. 4. 5. Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE is set. 7. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 8. Read the 8-bit received data by reading the RCREG register. 9. If any error occurred, clear the error by clearing enable bit CREN. 10. If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set. TABLE 10-6: Address REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 GIE PSPIF(1) SPEN PSPIE(1) CSRC Bit 6 PEIE ADIF RX9 Bit 5 T0IE RCIF SREN Bit 4 INTE TXIF CREN Bit 3 RBIE SSPIF — Bit 2 T0IF Bit 1 INTF Bit 0 R0IF Value on: POR, BOR 0000 000x 0000 0000 0000 -00x 0000 0000 Name Value on all other RESETS 0000 000u 0000 0000 0000 -00x 0000 0000 0000 0000 0000 -010 0000 0000 0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 1Ah 8Ch 98h 99h PIR1 RCSTA CCP1IF TMR2IF TMR1IF FERR OERR RX9D RCREG USART Receive Register PIE1 TXSTA SPBRG ADIE TX9 RCIE TXEN TXIE SYNC SSPIE CCP1IE TMR2IE TMR1IE — BRGH TRMT TX9D 0000 0000 0000 -010 0000 0000 Baud Rate Generator Register Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception. Note 1: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear. DS30292C-page 102  2001 Microchip Technology Inc. PIC16F87X 10.2.3 SETTING UP 9-BIT MODE WITH ADDRESS DETECT • Flag bit RCIF will be set when reception is complete, and an interrupt will be generated if enable bit RCIE was set. • Read the RCSTA register to get the ninth bit and determine if any error occurred during reception. • Read the 8-bit received data by reading the RCREG register, to determine if the device is being addressed. • If any error occurred, clear the error by clearing enable bit CREN. • If the device has been addressed, clear the ADDEN bit to allow data bytes and address bytes to be read into the receive buffer, and interrupt the CPU. When setting up an Asynchronous Reception with Address Detect Enabled: • Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH. • Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. • If interrupts are desired, then set enable bit RCIE. • Set bit RX9 to enable 9-bit reception. • Set ADDEN to enable address detect. • Enable the reception by setting enable bit CREN. FIGURE 10-6: USART RECEIVE BLOCK DIAGRAM x64 Baud Rate CLK CREN OERR FERR FOSC SPBRG ÷ 64 Baud Rate Generator RC7/RX/DT Pin Buffer and Control Data Recovery RX9 ÷ 16 or MSb STOP (8) 7 RSR Register ••• 1 LSb 0 START 8 SPEN RX9 ADDEN RX9 ADDEN RSR Enable Load of Receive Buffer 8 RX9D RCREG Register FIFO 8 Interrupt RCIF RCIE Data Bus  2001 Microchip Technology Inc. DS30292C-page 103 PIC16F87X FIGURE 10-7: RC7/RX/DT (pin) ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT START bit bit0 bit1 bit8 STOP bit START bit0 bit bit8 STOP bit Load RSR Bit8 = 0, Data Byte Read Bit8 = 1, Address Byte Word 1 RCREG RCIF Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (receive buffer) because ADDEN = 1. FIGURE 10-8: RC7/RX/DT (pin) ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST START bit bit0 bit1 bit8 STOP bit START bit bit0 bit8 STOP bit Load RSR Bit8 = 1, Address Byte Read Bit8 = 0, Data Byte Word 1 RCREG RCIF Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (receive buffer) because ADDEN was not updated and still = 0. TABLE 10-7: Address REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 GIE PSPIF(1) SPEN PSPIE(1) CSRC Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 T0IE RCIF SREN RCIE TXEN Bit 4 INTE TXIF Bit 3 RBIE SSPIF Bit 2 T0IF Bit 1 INTF Bit 0 R0IF Value on: POR, BOR 0000 000x Name Value on all other RESETS 0000 000u 0000 0000 0000 000x 0000 0000 0000 0000 0000 -010 0000 0000 0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 1Ah 8Ch 98h 99h PIR1 RCSTA RCREG PIE1 TXSTA SPBRG CCP1IF TMR2IF TMR1IF 0000 0000 FERR OERR RX9D 0000 000x 0000 0000 CREN ADDEN TXIE SYNC SSPIE — USART Receive Register BRGH TRMT TX9D CCP1IE TMR2IE TMR1IE 0000 0000 0000 -010 0000 0000 Baud Rate Generator Register Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception. Note 1: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear. DS30292C-page 104  2001 Microchip Technology Inc. PIC16F87X 10.3 USART Synchronous Master Mode Clearing enable bit TXEN during a transmission will cause the transmission to be aborted and will reset the transmitter. The DT and CK pins will revert to hiimpedance. If either bit CREN or bit SREN is set during a transmission, the transmission is aborted and the DT pin reverts to a hi-impedance state (for a reception). The CK pin will remain an output if bit CSRC is set (internal clock). The transmitter logic, however, is not reset, although it is disconnected from the pins. In order to reset the transmitter, the user has to clear bit TXEN. If bit SREN is set (to interrupt an on-going transmission and receive a single word), then after the single word is received, bit SREN will be cleared and the serial port will revert back to transmitting, since bit TXEN is still set. The DT line will immediately switch from hiimpedance Receive mode to transmit and start driving. To avoid this, bit TXEN should be cleared. In order to select 9-bit transmission, the TX9 (TXSTA) bit should be set and the ninth bit should be written to bit TX9D (TXSTA). The ninth bit must be written before writing the 8-bit data to the TXREG register. This is because a data write to the TXREG can result in an immediate transfer of the data to the TSR register (if the TSR is empty). If the TSR was empty and the TXREG was written before writing the “new” TX9D, the “present” value of bit TX9D is loaded. Steps to follow when setting up a Synchronous Master Transmission: 1. 2. 3. 4. 5. 6. 7. 8. Initialize the SPBRG register for the appropriate baud rate (Section 10.1). Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set bit TX9. Enable the transmission by setting bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREG register. If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set. In Synchronous Master mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA). In addition, enable bit SPEN (RCSTA) is set in order to configure the RC6/TX/CK and RC7/RX/DT I/O pins to CK (clock) and DT (data) lines, respectively. The Master mode indicates that the processor transmits the master clock on the CK line. The Master mode is entered by setting bit CSRC (TXSTA). 10.3.1 USART SYNCHRONOUS MASTER TRANSMISSION The USART transmitter block diagram is shown in Figure 10-6. The heart of the transmitter is the transmit (serial) shift register (TSR). The shift register obtains its data from the read/write transmit buffer register TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the last bit has been transmitted from the previous load. As soon as the last bit is transmitted, the TSR is loaded with new data from the TXREG (if available). Once the TXREG register transfers the data to the TSR register (occurs in one Tcycle), the TXREG is empty and interrupt bit TXIF (PIR1) is set. The interrupt can be enabled/disabled by setting/clearing enable bit TXIE (PIE1). Flag bit TXIF will be set, regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicates the status of the TXREG register, another bit TRMT (TXSTA) shows the status of the TSR register. TRMT is a read only bit which is set when the TSR is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR register is empty. The TSR is not mapped in data memory, so it is not available to the user. Transmission is enabled by setting enable bit TXEN (TXSTA). The actual transmission will not occur until the TXREG register has been loaded with data. The first data bit will be shifted out on the next available rising edge of the clock on the CK line. Data out is stable around the falling edge of the synchronous clock (Figure 10-9). The transmission can also be started by first loading the TXREG register and then setting bit TXEN (Figure 10-10). This is advantageous when slow baud rates are selected, since the BRG is kept in RESET when bits TXEN, CREN and SREN are clear. Setting enable bit TXEN will start the BRG, creating a shift clock immediately. Normally, when transmission is first started, the TSR register is empty, so a transfer to the TXREG register will result in an immediate transfer to TSR, resulting in an empty TXREG. Back-to-back transfers are possible.  2001 Microchip Technology Inc. DS30292C-page 105 PIC16F87X TABLE 10-8: Address REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 GIE PSPIF(1) SPEN PSPIE(1) CSRC Bit 6 PEIE ADIF RX9 Bit 5 T0IE RCIF Bit 4 INTE TXIF Bit 3 RBIE SSPIF — Bit 2 T0IF CCP1IF FERR Bit 1 INTF TMR2IF OERR Bit 0 R0IF TMR1IF RX9D Value on: POR, BOR 0000 000x 0000 0000 0000 -00x 0000 0000 Name Value on all other RESETS 0000 000u 0000 0000 0000 -00x 0000 0000 0000 0000 0000 -010 0000 0000 0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 19h 8Ch 98h 99h PIR1 RCSTA TXREG PIE1 TXSTA SPBRG SREN CREN USART Transmit Register ADIE TX9 RCIE TXEN TXIE SYNC SSPIE — CCP1IE TMR2IE TMR1IE BRGH TRMT TX9D 0000 0000 0000 -010 0000 0000 Baud Rate Generator Register Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous master transmission. Note 1: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear. FIGURE 10-9: SYNCHRONOUS TRANSMISSION Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4 Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2 Q3Q4 RC7/RX/DT pin RC6/TX/CK pin Write to TXREG reg Write Word1 TXIF bit (Interrupt Flag) TRMT bit ’1’ bit 0 bit 1 Word 1 bit 2 bit 7 bit 0 bit 1 Word 2 bit 7 Write Word2 TXEN bit ’1’ Note: Sync Master mode; SPBRG = ’0’. Continuous transmission of two 8-bit words. FIGURE 10-10: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) bit0 bit1 bit2 bit6 bit7 RC7/RX/DT pin RC6/TX/CK pin Write to TXREG Reg TXIF bit TRMT bit TXEN bit DS30292C-page 106  2001 Microchip Technology Inc. PIC16F87X 10.3.2 USART SYNCHRONOUS MASTER RECEPTION receive bit is buffered the same way as the receive data. Reading the RCREG register will load bit RX9D with a new value, therefore, it is essential for the user to read the RCSTA register before reading RCREG in order not to lose the old RX9D information. When setting up a Synchronous Master Reception: 1. Initialize the SPBRG register for the appropriate baud rate (Section 10.1). 2. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. 3. Ensure bits CREN and SREN are clear. 4. If interrupts are desired, then set enable bit RCIE. 5. If 9-bit reception is desired, then set bit RX9. 6. If a single reception is required, set bit SREN. For continuous reception, set bit CREN. 7. Interrupt flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE was set. 8. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREG register. 10. If any error occurred, clear the error by clearing bit CREN. 11. If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set. Once synchronous mode is selected, reception is enabled by setting either enable bit SREN (RCSTA), or enable bit CREN (RCSTA). Data is sampled on the RC7/RX/DT pin on the falling edge of the clock. If enable bit SREN is set, then only a single word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are set, CREN takes precedence. After clocking the last bit, the received data in the Receive Shift Register (RSR) is transferred to the RCREG register (if it is empty). When the transfer is complete, interrupt flag bit RCIF (PIR1) is set. The actual interrupt can be enabled/ disabled by setting/clearing enable bit RCIE (PIE1). Flag bit RCIF is a read only bit, which is reset by the hardware. In this case, it is reset when the RCREG register has been read and is empty. The RCREG is a double buffered register (i.e., it is a two deep FIFO). It is possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte to begin shifting into the RSR register. On the clocking of the last bit of the third byte, if the RCREG register is still full, then overrun error bit OERR (RCSTA) is set. The word in the RSR will be lost. The RCREG register can be read twice to retrieve the two bytes in the FIFO. Bit OERR has to be cleared in software (by clearing bit CREN). If bit OERR is set, transfers from the RSR to the RCREG are inhibited, so it is essential to clear bit OERR if it is set. The ninth TABLE 10-9: Address REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Bit 7 GIE PSPIF(1) SPEN PSPIE(1) CSRC Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 T0IE RCIF Bit 4 INTE TXIF Bit 3 RBIE SSPIF — SSPIE — Bit 2 T0IF CCP1IF FERR Bit 1 INTF TMR2IF OERR Bit 0 R0IF TMR1IF RX9D Value on: POR, BOR 0000 000x 0000 0000 0000 -00x 0000 0000 0000 0000 0000 -010 0000 0000 Name Value on all other RESETS 0000 000u 0000 0000 0000 -00x 0000 0000 0000 0000 0000 -010 0000 0000 0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 1Ah 8Ch 98h 99h PIR1 RCSTA RCREG PIE1 TXSTA SPBRG SREN CREN RCIE TXEN TXIE SYNC USART Receive Register CCP1IE TMR2IE TMR1IE BRGH TRMT TX9D Baud Rate Generator Register Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous master reception. Note 1: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear.  2001 Microchip Technology Inc. DS30292C-page 107 PIC16F87X FIGURE 10-11: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 RC7/RX/DT pin RC6/TX/CK pin Write to bit SREN SREN bit CREN bit RCIF bit (Interrupt) Read RXREG ’0’ bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 ’0’ Note: Timing diagram demonstrates SYNC Master mode with bit SREN = ’1’ and bit BRG = ’0’. 10.4 USART Synchronous Slave Mode e) Synchronous Slave mode differs from the Master mode in the fact that the shift clock is supplied externally at the RC6/TX/CK pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in SLEEP mode. Slave mode is entered by clearing bit CSRC (TXSTA). If enable bit TXIE is set, the interrupt will wake the chip from SLEEP and if the global interrupt is enabled, the program will branch to the interrupt vector (0004h). When setting up a Synchronous Slave Transmission, follow these steps: 1. Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit CSRC. Clear bits CREN and SREN. If interrupts are desired, then set enable bit TXIE. If 9-bit transmission is desired, then set bit TX9. Enable the transmission by setting enable bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREG register. If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set. 10.4.1 USART SYNCHRONOUS SLAVE TRANSMIT The operation of the Synchronous Master and Slave modes is identical, except in the case of the SLEEP mode. If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: a) b) c) d) The first word will immediately transfer to the TSR register and transmit. The second word will remain in TXREG register. Flag bit TXIF will not be set. When the first word has been shifted out of TSR, the TXREG register will transfer the second word to the TSR and flag bit TXIF will now be set. 2. 3. 4. 5. 6. 7. 8. TABLE 10-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Address Name Bit 7 GIE PSPIF(1) SPEN PSPIE(1) CSRC Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 T0IE RCIF SREN RCIE TXEN Bit 4 INTE TXIF CREN TXIE SYNC Bit 3 RBIE SSPIF ADDEN SSPIE — Bit 2 T0IF Bit 1 INTF Bit 0 R0IF Value on: POR, BOR 0000 000x Value on all other RESETS 0000 000u 0000 0000 0000 000x 0000 0000 0000 0000 0000 -010 0000 0000 0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 19h 8Ch 98h 99h PIR1 RCSTA TXREG PIE1 TXSTA SPBRG CCP1IF TMR2IF TMR1IF 0000 0000 FERR OERR RX9D 0000 000x 0000 0000 USART Transmit Register BRGH TRMT TX9D CCP1IE TMR2IE TMR1IE 0000 0000 0000 -010 0000 0000 Baud Rate Generator Register Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous slave transmission. Note 1: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear. DS30292C-page 108  2001 Microchip Technology Inc. PIC16F87X 10.4.2 USART SYNCHRONOUS SLAVE RECEPTION 2. 3. 4. 5. If interrupts are desired, set enable bit RCIE. If 9-bit reception is desired, set bit RX9. To enable reception, set enable bit CREN. Flag bit RCIF will be set when reception is complete and an interrupt will be generated, if enable bit RCIE was set. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. Read the 8-bit received data by reading the RCREG register. If any error occurred, clear the error by clearing bit CREN. If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set. The operation of the Synchronous Master and Slave modes is identical, except in the case of the SLEEP mode. Bit SREN is a “don't care” in Slave mode. If receive is enabled by setting bit CREN prior to the SLEEP instruction, then a word may be received during SLEEP. On completely receiving the word, the RSR register will transfer the data to the RCREG register and if enable bit RCIE bit is set, the interrupt generated will wake the chip from SLEEP. If the global interrupt is enabled, the program will branch to the interrupt vector (0004h). When setting up a Synchronous Slave Reception, follow these steps: 1. Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit CSRC. 6. 7. 8. 9. TABLE 10-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Address Name Bit 7 GIE PSPIF(1) SPEN PSPIE(1) CSRC Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 T0IE RCIF SREN RCIE TXEN Bit 4 INTE TXIF CREN TXIE SYNC Bit 3 RBIE SSPIF ADDEN SSPIE — Bit 2 T0IF CCP1IF FERR Bit 1 INTF TMR2IF OERR Bit 0 R0IF Value on: POR, BOR 0000 000x Value on all other RESETS 0000 000u 0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 1Ah 8Ch 98h 99h PIR1 RCSTA RCREG PIE1 TXSTA SPBRG TMR1IF 0000 0000 0000 0000 RX9D 0000 000x 0000 000x 0000 0000 0000 0000 USART Receive Register BRGH TRMT TX9D CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 0000 -010 0000 -010 0000 0000 0000 0000 Baud Rate Generator Register Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous slave reception. Note 1: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices, always maintain these bits clear.  2001 Microchip Technology Inc. DS30292C-page 109 PIC16F87X NOTES: DS30292C-page 110  2001 Microchip Technology Inc. PIC16F87X 11.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The A/D module has four registers. These registers are: • • • • A/D Result High Register (ADRESH) A/D Result Low Register (ADRESL) A/D Control Register0 (ADCON0) A/D Control Register1 (ADCON1) The Analog-to-Digital (A/D) Converter module has five inputs for the 28-pin devices and eight for the other devices. The analog input charges a sample and hold capacitor. The output of the sample and hold capacitor is the input into the converter. The converter then generates a digital result of this analog level via successive approximation. The A/D conversion of the analog input signal results in a corresponding 10-bit digital number. The A/D module has high and low voltage reference input that is software selectable to some combination of VDD, VSS, RA2, or RA3. The A/D converter has a unique feature of being able to operate while the device is in SLEEP mode. To operate in SLEEP, the A/D clock must be derived from the A/D’s internal RC oscillator. The ADCON0 register, shown in Register 11-1, controls the operation of the A/D module. The ADCON1 register, shown in Register 11-2, configures the functions of the port pins. The port pins can be configured as analog inputs (RA3 can also be the voltage reference), or as digital I/O. Additional information on using the A/D module can be found in the PICmicro™ Mid-Range MCU Family Reference Manual (DS33023). REGISTER 11-1: ADCON0 REGISTER (ADDRESS: 1Fh) R/W-0 ADCS1 bit 7 R/W-0 ADCS0 R/W-0 CHS2 R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE U-0 — R/W-0 ADON bit 0 bit 7-6 ADCS1:ADCS0: A/D Conversion Clock Select bits 00 = FOSC/2 01 = FOSC/8 10 = FOSC/32 11 = FRC (clock derived from the internal A/D module RC oscillator) CHS2:CHS0: Analog Channel Select bits 000 = channel 0, (RA0/AN0) 001 = channel 1, (RA1/AN1) 010 = channel 2, (RA2/AN2) 011 = channel 3, (RA3/AN3) 100 = channel 4, (RA5/AN4) 101 = channel 5, (RE0/AN5)(1) 110 = channel 6, (RE1/AN6)(1) 111 = channel 7, (RE2/AN7)(1) GO/DONE: A/D Conversion Status bit If ADON = 1: 1 = A/D conversion in progress (setting this bit starts the A/D conversion) 0 = A/D conversion not in progress (this bit is automatically cleared by hardware when the A/D conversion is complete) Unimplemented: Read as '0' ADON: A/D On bit 1 = A/D converter module is operating 0 = A/D converter module is shut-off and consumes no operating current Note 1: These channels are not available on PIC16F873/876 devices. Legend: R = Readable bit - n = Value at POR W = Writable bit ’1’ = Bit is set U = Unimplemented bit, read as ‘0’ ’0’ = Bit is cleared x = Bit is unknown bit 5-3 bit 2 bit 1 bit 0  2001 Microchip Technology Inc. DS30292C-page 111 PIC16F87X REGISTER 11-2: ADCON1 REGISTER (ADDRESS 9Fh) U-0 ADFM bit 7 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified. 6 Most Significant bits of ADRESH are read as ‘0’. 0 = Left justified. 6 Least Significant bits of ADRESL are read as ‘0’. Unimplemented: Read as '0' PCFG3:PCFG0: A/D Port Configuration Control bits: PCFG3: AN7(1) AN6(1) AN5(1) RE2 RE1 RE0 PCFG0 0000 0001 0010 0011 0100 0101 011x 1000 1001 1010 1011 1100 1101 1110 1111 U-0 — R/W-0 — U-0 — R/W-0 PCFG3 R/W-0 PCFG2 R/W-0 PCFG1 R/W-0 PCFG0 bit 0 bit 6-4 bit 3-0 AN4 RA5 A A A A D D D A A A A A D D D AN3 RA3 A VREF+ A VREF+ A VREF+ D VREF+ A VREF+ VREF+ VREF+ VREF+ D VREF+ AN2 RA2 A A A A D D D VREFA A VREFVREFVREFD VREF- AN1 RA1 A A A A A A D A A A A A A D D AN0 RA0 A A A A A A D A A A A A A A A VREF+ VDD RA3 VDD RA3 VDD RA3 VDD RA3 VDD RA3 RA3 RA3 RA3 VDD RA3 VREFVSS VSS VSS VSS VSS VSS VSS RA2 VSS VSS RA2 RA2 RA2 VSS RA2 CHAN/ Refs(2) 8/0 7/1 5/0 4/1 3/0 2/1 0/0 6/2 6/0 5/1 4/2 3/2 2/2 1/0 1/2 A A D D D D D A D D D D D D D A A D D D D D A D D D D D D D A A D D D D D A A A A D D D D A = Analog input D = Digital I/O Note 1: These channels are not available on PIC16F873/876 devices. 2: This column indicates the number of analog channels available as A/D inputs and the number of analog channels used as voltage reference inputs. Legend: R = Readable bit - n = Value at POR W = Writable bit ’1’ = Bit is set U = Unimplemented bit, read as ‘0’ ’0’ = Bit is cleared x = Bit is unknown The ADRESH:ADRESL registers contain the 10-bit result of the A/D conversion. When the A/D conversion is complete, the result is loaded into this A/D result register pair, the GO/DONE bit (ADCON0) is cleared and the A/D interrupt flag bit ADIF is set. The block diagram of the A/D module is shown in Figure 11-1. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as inputs. To determine sample time, see Section 11.1. After this acquisition time has elapsed, the A/D conversion can be started. DS30292C-page 112  2001 Microchip Technology Inc. PIC16F87X These steps should be followed for doing an A/D Conversion: 1. Configure the A/D module: • Configure analog pins/voltage reference and digital I/O (ADCON1) • Select A/D input channel (ADCON0) • Select A/D conversion clock (ADCON0) • Turn on A/D module (ADCON0) Configure A/D interrupt (if desired): • Clear ADIF bit • Set ADIE bit • Set PEIE bit • Set GIE bit 3. 4. 5. Wait the required acquisition time. Start conversion: • Set GO/DONE bit (ADCON0) Wait for A/D conversion to complete, by either: • Polling for the GO/DONE bit to be cleared (with interrupts enabled); OR • Waiting for the A/D interrupt Read A/D result register pair (ADRESH:ADRESL), clear bit ADIF if required. For the next conversion, go to step 1 or step 2, as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2TAD is required before the next acquisition starts. 6. 7. 2. FIGURE 11-1: A/D BLOCK DIAGRAM CHS2:CHS0 111 110 101 100 RE2/AN7(1) RE1/AN6(1) RE0/AN5(1) RA5/AN4 VAIN (Input Voltage) 011 010 RA3/AN3/VREF+ RA2/AN2/VREF- A/D Converter 001 RA1/AN1 VDD VREF+ (Reference Voltage) PCFG3:PCFG0 000 RA0/AN0 VREF(Reference Voltage) VSS PCFG3:PCFG0 Note 1: Not available on PIC16F873/876 devices.  2001 Microchip Technology Inc. DS30292C-page 113 PIC16F87X 11.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 11-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 11-2. The maximum recommended impedance for analog sources is 10 kΩ. As the impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (changed), this acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 11-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution. To calculate the minimum acquisition time, TACQ, see the PICmicro™ Mid-Range Reference Manual (DS33023). EQUATION 11-1: TACQ ACQUISITION TIME = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = = = = = = = TAMP + TC + TCOFF 2µs + TC + [(Temperature -25°C)(0.05µs/°C)] CHOLD (RIC + RSS + RS) In(1/2047) - 120pF (1kΩ + 7kΩ + 10kΩ) In(0.0004885) 16.47µs 2µs + 16.47µs + [(50°C -25°C)(0.05µs/°C) 19.72µs TC TACQ Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin leakage specification. 4: After a conversion has completed, a 2.0TAD delay must complete before acquisition can begin again. During this time, the holding capacitor is not connected to the selected A/D input channel. FIGURE 11-2: ANALOG INPUT MODEL VDD RS VA ANx CPIN 5 pF VT = 0.6V RIC ≤ 1k I LEAKAGE ± 500 nA Sampling Switch SS RSS CHOLD = DAC capacitance = 120 pF VSS VT = 0.6V Legend CPIN = input capacitance VT = threshold voltage I LEAKAGE = leakage current at the pin due to various junctions RIC = interconnect resistance SS = sampling switch CHOLD = sample/hold capacitance (from DAC) 6V 5V VDD 4V 3V 2V 5 6 7 8 9 10 11 Sampling Switch (kΩ) DS30292C-page 114  2001 Microchip Technology Inc. PIC16F87X 11.2 Selecting the A/D Conversion Clock For correct A/D conversions, the A/D conversion clock (TAD) must be selected to ensure a minimum TAD time of 1.6 µs. Table 11-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected. The A/D conversion time per bit is defined as TAD. The A/D conversion requires a minimum 12TAD per 10-bit conversion. The source of the A/D conversion clock is software selected. The four possible options for TAD are: • • • • 2TOSC 8TOSC 32TOSC Internal A/D module RC oscillator (2-6 µs) TABLE 11-1: TAD vs. MAXIMUM DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (C)) AD Clock Source (TAD) Maximum Device Frequency Max. 1.25 MHz 5 MHz 20 MHz (Note 1) Operation 2TOSC 8TOSC 32TOSC RC(1, 2, 3) ADCS1:ADCS0 00 01 10 11 Note 1: The RC source has a typical TAD time of 4 µs, but can vary between 2-6 µs. 2: When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only recommended for SLEEP operation. 3: For extended voltage devices (LC), please refer to the Electrical Characteristics (Sections 15.1 and 15.2). 11.3 Configuring Analog Port Pins The ADCON1 and TRIS registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the CHS2:CHS0 bits and the TRIS bits. Note 1: When reading the port register, any pin configured as an analog input channel will read as cleared (a low level). Pins configured as digital inputs will convert an analog input. Analog levels on a digitally configured input will not affect the conversion accuracy. 2: Analog levels on any pin that is defined as a digital input (including the AN7:AN0 pins), may cause the input buffer to consume current that is out of the device specifications.  2001 Microchip Technology Inc. DS30292C-page 115 PIC16F87X 11.4 A/D Conversions Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D result register pair will NOT be updated with the partially completed A/D conversion sample. That is, the ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers). After the A/D conversion is aborted, a 2TAD wait is required before the next acquisition is started. After this 2TAD wait, acquisition on the selected channel is automatically started. The GO/DONE bit can then be set to start the conversion. In Figure 11-3, after the GO bit is set, the first time segment has a minimum of TCY and a maximum of TAD. Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. FIGURE 11-3: A/D CONVERSION TAD CYCLES TAD2 b9 Conversion starts TAD3 b8 TCY to TAD TAD1 TAD4 b7 TAD5 b6 TAD6 b5 TAD7 b4 TAD8 b3 TAD9 TAD10 TAD11 b2 b1 b0 Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit ADRES is loaded GO bit is cleared ADIF bit is set Holding capacitor is connected to analog input 11.4.1 A/D RESULT REGISTERS The ADRESH:ADRESL register pair is the location where the 10-bit A/D result is loaded at the completion of the A/D conversion. This register pair is 16-bits wide. The A/D module gives the flexibility to left or right justify the 10-bit result in the 16-bit result register. The A/D Format Select bit (ADFM) controls this justification. Figure 11-4 shows the operation of the A/D result justification. The extra bits are loaded with ’0’s’. When an A/D result will not overwrite these locations (A/D disable), these registers may be used as two general purpose 8-bit registers. FIGURE 11-4: A/D RESULT JUSTIFICATION 10-bit Result ADFM = 1 ADFM = 0 7 0000 00 2107 0 7 0765 0000 00 0 ADRESH ADRESL ADRESH ADRESL 10-bit Result Right Justified 10-bit Result Left Justified DS30292C-page 116  2001 Microchip Technology Inc. PIC16F87X 11.5 A/D Operation During SLEEP The A/D module can operate during SLEEP mode. This requires that the A/D clock source be set to RC (ADCS1:ADCS0 = 11). When the RC clock source is selected, the A/D module waits one instruction cycle before starting the conversion. This allows the SLEEP instruction to be executed, which eliminates all digital switching noise from the conversion. When the conversion is completed, the GO/DONE bit will be cleared and the result loaded into the ADRES register. If the A/D interrupt is enabled, the device will wake-up from SLEEP. If the A/D interrupt is not enabled, the A/D module will then be turned off, although the ADON bit will remain set. When the A/D clock source is another clock option (not RC), a SLEEP instruction will cause the present conversion to be aborted and the A/D module to be turned off, though the ADON bit will remain set. Turning off the A/D places the A/D module in its lowest current consumption state. Note: For the A/D module to operate in SLEEP, the A/D clock source must be set to RC (ADCS1:ADCS0 = 11). To allow the conversion to occur during SLEEP, ensure the SLEEP instruction immediately follows the instruction that sets the GO/DONE bit. 11.6 Effects of a RESET A device RESET forces all registers to their RESET state. This forces the A/D module to be turned off, and any conversion is aborted. All A/D input pins are configured as analog inputs. The value that is in the ADRESH:ADRESL registers is not modified for a Power-on Reset. The ADRESH:ADRESL registers will contain unknown data after a Power-on Reset. TABLE 11-2: Address REGISTERS/BITS ASSOCIATED WITH A/D Bit 7 GIE PSPIF(1) PSPIE(1) Bit 6 PEIE ADIF ADIE Bit 5 T0IE RCIF RCIE Bit 4 INTE TXIF TXIE Bit 3 RBIE SSPIF SSPIE Bit 2 T0IF CCP1IF CCP1IE Bit 1 INTF Bit 0 RBIF Value on POR, BOR Value on MCLR, WDT Name 0Bh,8Bh, INTCON 10Bh,18Bh 0Ch 8Ch 1Eh 9Eh 1Fh 9Fh 85h 05h 89h(1) 09h(1) PIR1 PIE1 ADRESH ADRESL ADCON0 ADCON1 TRISA PORTA TRISE PORTE 0000 000x 0000 000u TMR2IF TMR1IF 0000 0000 0000 0000 TMR2IE TMR1IE 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu A/D Result Register High Byte A/D Result Register Low Byte ADCS1 ADFM — — IBF — ADCS0 CHS2 — — — OBF — — CHS1 — CHS0 PCFG3 GO/DONE PCFG2 — PCFG1 ADON PCFG0 0000 00-0 0000 00-0 --0- 0000 --0- 0000 --11 1111 --11 1111 --0x 0000 --0u 0000 0000 -111 0000 -111 ---- -xxx ---- -uuu PORTA Data Direction Register PORTA Data Latch when written: PORTA pins when read IBOV — PSPMODE — — — PORTE Data Direction bits RE2 RE1 RE0 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used for A/D conversion. Note 1: These registers/bits are not available on the 28-pin devices.  2001 Microchip Technology Inc. DS30292C-page 117 PIC16F87X NOTES: DS30292C-page 118  2001 Microchip Technology Inc. PIC16F87X 12.0 SPECIAL FEATURES OF THE CPU SLEEP mode is designed to offer a very low current Power-down mode. The user can wake-up from SLEEP through external RESET, Watchdog Timer Wake-up, or through an interrupt. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits is used to select various options. Additional information on special features is available in the PICmicro™ Mid-Range Reference Manual, (DS33023). All PIC16F87X devices have a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These are: • Oscillator Selection • RESET - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) • Interrupts • Watchdog Timer (WDT) • SLEEP • Code Protection • ID Locations • In-Circuit Serial Programming • Low Voltage In-Circuit Serial Programming • In-Circuit Debugger PIC16F87X devices have a Watchdog Timer, which can be shut-off only through configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in RESET until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 72 ms (nominal) on power-up only. It is designed to keep the part in RESET while the power supply stabilizes. With these two timers on-chip, most applications need no external RESET circuitry. 12.1 Configuration Bits The configuration bits can be programmed (read as '0'), or left unprogrammed (read as '1'), to select various device configurations. The erased, or unprogrammed value of the configuration word is 3FFFh. These bits are mapped in program memory location 2007h. It is important to note that address 2007h is beyond the user program memory space, which can be accessed only during programming.  2001 Microchip Technology Inc. DS30292C-page 119 PIC16F87X REGISTER 12-1: CP1 bit13 bit 13-12, bit 5-4 CP1:CP0: FLASH Program Memory Code Protection bits(2) 11 = Code protection off 10 = 1F00h to 1FFFh code protected (PIC16F877, 876) 10 = 0F00h to 0FFFh code protected (PIC16F874, 873) 01 = 1000h to 1FFFh code protected (PIC16F877, 876) 01 = 0800h to 0FFFh code protected (PIC16F874, 873) 00 = 0000h to 1FFFh code protected (PIC16F877, 876) 00 = 0000h to 0FFFh code protected (PIC16F874, 873) DEBUG: In-Circuit Debugger Mode 1 = In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins 0 = In-Circuit Debugger enabled, RB6 and RB7 are dedicated to the debugger. Unimplemented: Read as ‘1’ WRT: FLASH Program Memory Write Enable 1 = Unprotected program memory may be written to by EECON control 0 = Unprotected program memory may not be written to by EECON control CPD: Data EE Memory Code Protection 1 = Code protection off 0 = Data EEPROM memory code protected LVP: Low Voltage In-Circuit Serial Programming Enable bit 1 = RB3/PGM pin has PGM function, low voltage programming enabled 0 = RB3 is digital I/O, HV on MCLR must be used for programming BODEN: Brown-out Reset Enable bit(3) 1 = BOR enabled 0 = BOR disabled PWRTE: Power-up Timer Enable bit(3) 1 = PWRT disabled 0 = PWRT enabled WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator CP0 CONFIGURATION WORD (ADDRESS 2007h)(1) — WRT CPD LVP BODEN CP1 CP0 PWRTE WDTE F0SC1 F0SC0 bit0 DEBUG bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 3 bit 2 bit 1-0 Note 1: The erased (unprogrammed) value of the configuration word is 3FFFh. 2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed. 3: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT), regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled any time Brown-out Reset is enabled. DS30292C-page 120  2001 Microchip Technology Inc. PIC16F87X 12.2 12.2.1 Oscillator Configurations OSCILLATOR TYPES FIGURE 12-2: The PIC16F87X can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: • • • • LP XT HS RC Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Resistor/Capacitor EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION) Clock from Ext. System Open OSC1 PIC16F87X OSC2 12.2.2 CRYSTAL OSCILLATOR/CERAMIC RESONATORS TABLE 12-1: CERAMIC RESONATORS Ranges Tested: Mode XT Freq. 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz OSC1 68 - 100 pF 15 - 68 pF 15 - 68 pF 10 - 68 pF 10 - 22 pF OSC2 68 - 100 pF 15 - 68 pF 15 - 68 pF 10 - 68 pF 10 - 22 pF In XT, LP or HS modes, a crystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure 12-1). The PIC16F87X oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in XT, LP or HS modes, the device can have an external clock source to drive the OSC1/ CLKIN pin (Figure 12-2). HS FIGURE 12-1: CRYSTAL/CERAMIC RESONATOR OPERATION (HS, XT OR LP OSC CONFIGURATION) OSC1 To Internal Logic SLEEP PIC16F87X These values are for design guidance only. See notes following Table 12-2. Resonators Used: 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz Panasonic EFO-A455K04B Murata Erie CSA2.00MG Murata Erie CSA4.00MG Murata Erie CSA8.00MT Murata Erie CSA16.00MX ± 0.3% ± 0.5% ± 0.5% ± 0.5% ± 0.5% C1(1) XTAL OSC2 C2(1) Rs (2) RF(3) All resonators used did not have built-in capacitors. Note 1: See Table 12-1 and Table 12-2 for recommended values of C1 and C2. 2: A series resistor (Rs) may be required for AT strip cut crystals. 3: RF varies with the crystal chosen.  2001 Microchip Technology Inc. DS30292C-page 121 PIC16F87X TABLE 12-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Cap. Range C1 33 pF 15 pF 47-68 pF 15 pF 15 pF 15 pF 15-33 pF 15-33 pF Cap. Range C2 33 pF 15 pF 47-68 pF 15 pF 15 pF 15 pF 15-33 pF 15-33 pF 12.2.3 RC OSCILLATOR Osc Type LP XT Crystal Freq. 32 kHz 200 kHz 200 kHz 1 MHz 4 MHz HS 4 MHz 8 MHz 20 MHz For timing insensitive applications, the “RC” device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 12-3 shows how the R/C combination is connected to the PIC16F87X. These values are for design guidance only. See notes following this table. Crystals Used 32 kHz 200 kHz 1 MHz 4 MHz 8 MHz 20 MHz Epson C-001R32.768K-A STD XTL 200.000KHz ECS ECS-10-13-1 ECS ECS-40-20-1 EPSON CA-301 8.000M-C EPSON CA-301 20.000MC ± 20 PPM ± 20 PPM ± 50 PPM ± 50 PPM ± 30 PPM ± 30 PPM FIGURE 12-3: VDD REXT RC OSCILLATOR MODE OSC1 CEXT VSS FOSC/4 Recommended values: OSC2/CLKOUT Internal Clock PIC16F87X 3 kΩ ≤ REXT ≤ 100 kΩ CEXT > 20pF Note 1: Higher capacitance increases the stability of oscillator, but also increases the startup time. 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 3: Rs may be required in HS mode, as well as XT mode, to avoid overdriving crystals with low drive level specification. 4: When migrating from other PICmicro devices, oscillator performance should be verified. DS30292C-page 122  2001 Microchip Technology Inc. PIC16F87X 12.3 RESET The PIC16F87X differentiates between various kinds of RESET: • • • • • • Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset (during normal operation) WDT Wake-up (during SLEEP) Brown-out Reset (BOR) SLEEP, and Brown-out Reset (BOR). They are not affected by a WDT Wake-up, which is viewed as the resumption of normal operation. The TO and PD bits are set or cleared differently in different RESET situations as indicated in Table 12-4. These bits are used in software to determine the nature of the RESET. See Table 12-6 for a full description of RESET states of all registers. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 12-4. These devices have a MCLR noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. Some registers are not affected in any RESET condition. Their status is unknown on POR and unchanged in any other RESET. Most other registers are reset to a “RESET state” on Power-on Reset (POR), on the MCLR and WDT Reset, on MCLR Reset during FIGURE 12-4: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset MCLR WDT Module VDD Rise Detect VDD Brown-out Reset OST/PWRT OST Chip_Reset 10-bit Ripple Counter OSC1 (1) On-chip RC OSC PWRT 10-bit Ripple Counter R Q Power-on Reset S WDT SLEEP Time-out Reset BODEN Enable PWRT Enable OST Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.  2001 Microchip Technology Inc. DS30292C-page 123 PIC16F87X 12.4 Power-On Reset (POR) 12.7 Brown-out Reset (BOR) A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.2V - 1.7V). To take advantage of the POR, tie the MCLR pin directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset. A maximum rise time for VDD is specified. See Electrical Specifications for details. When the device starts normal operation (exits the RESET condition), device operating parameters (voltage, frequency, temperature,...) must be met to ensure operation. If these conditions are not met, the device must be held in RESET until the operating conditions are met. Brown-out Reset may be used to meet the start-up conditions. For additional information, refer to Application Note, AN007, “Power-up Trouble Shooting”, (DS00007). The configuration bit, BODEN, can enable or disable the Brown-out Reset circuit. If VDD falls below VBOR (parameter D005, about 4V) for longer than TBOR (parameter #35, about 100µS), the brown-out situation will reset the device. If VDD falls below VBOR for less than TBOR, a RESET may not occur. Once the brown-out occurs, the device will remain in Brown-out Reset until VDD rises above VBOR. The Power-up Timer then keeps the device in RESET for TPWRT (parameter #33, about 72mS). If VDD should fall below VBOR during TPWRT, the Brown-out Reset process will restart when VDD rises above VBOR with the Power-up Timer Reset. The Power-up Timer is always enabled when the Brown-out Reset circuit is enabled, regardless of the state of the PWRT configuration bit. 12.8 12.5 Power-up Timer (PWRT) The Power-up Timer provides a fixed 72 ms nominal time-out on power-up only from the POR. The Powerup Timer operates on an internal RC oscillator. The chip is kept in RESET as long as the PWRT is active. The PWRT’s time delay allows VDD to rise to an acceptable level. A configuration bit is provided to enable/disable the PWRT. The power-up time delay will vary from chip to chip due to VDD, temperature and process variation. See DC parameters for details (TPWRT, parameter #33). Time-out Sequence On power-up, the time-out sequence is as follows: The PWRT delay starts (if enabled) when a POR Reset occurs. Then OST starts counting 1024 oscillator cycles when PWRT ends (LP, XT, HS). When the OST ends, the device comes out of RESET. If MCLR is kept low long enough, the time-outs will expire. Bringing MCLR high will begin execution immediately. This is useful for testing purposes or to synchronize more than one PIC16F87X device operating in parallel. Table 12-5 shows the RESET conditions for the STATUS, PCON and PC registers, while Table 12-6 shows the RESET conditions for all the registers. 12.6 Oscillator Start-up Timer (OST) The Oscillator Start-up Timer (OST) provides a delay of 1024 oscillator cycles (from OSC1 input) after the PWRT delay is over (if PWRT is enabled). This helps to ensure that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset or Wake-up from SLEEP. 12.9 Power Control/Status Register (PCON) The Power Control/Status Register, PCON, has up to two bits depending upon the device. Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is unknown on a Power-on Reset. It must then be set by the user and checked on subsequent RESETS to see if bit BOR cleared, indicating a BOR occurred. When the Brown-out Reset is disabled, the state of the BOR bit is unpredictable and is, therefore, not valid at any time. Bit1 is POR (Power-on Reset Status bit). It is cleared on a Power-on Reset and unaffected otherwise. The user must set this bit following a Power-on Reset. TABLE 12-3: TIME-OUT IN VARIOUS SITUATIONS Power-up Brown-out PWRTE = 0 PWRTE = 1 1024TOSC — 72 ms + 1024TOSC 72 ms 72 ms + 1024TOSC 72 ms Wake-up from SLEEP 1024TOSC — Oscillator Configuration XT, HS, LP RC DS30292C-page 124  2001 Microchip Technology Inc. PIC16F87X TABLE 12-4: POR 0 0 0 1 1 1 1 1 BOR x x x 0 1 1 1 1 STATUS BITS AND THEIR SIGNIFICANCE TO 1 0 x 1 0 0 u 1 PD 1 x 0 1 1 0 u 0 Power-on Reset Illegal, TO is set on POR Illegal, PD is set on POR Brown-out Reset WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during SLEEP or interrupt wake-up from SLEEP Legend: x = don’t care, u = unchanged TABLE 12-5: RESET CONDITION FOR SPECIAL REGISTERS Condition Program Counter 000h 000h 000h 000h PC + 1 000h PC + 1 (1) STATUS Register 0001 1xxx 000u uuuu 0001 0uuu 0000 1uuu uuu0 0uuu 0001 1uuu uuu1 0uuu PCON Register ---- --0x ---- --uu ---- --uu ---- --uu ---- --uu ---- --u0 ---- --uu Power-on Reset MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset WDT Wake-up Brown-out Reset Interrupt wake-up from SLEEP Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0' Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).  2001 Microchip Technology Inc. DS30292C-page 125 PIC16F87X TABLE 12-6: Register W INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD PORTE PCLATH INTCON PIR1 INITIALIZATION CONDITIONS FOR ALL REGISTERS Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset Wake-up via WDT or Interrupt 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu 873 874 876 877 N/A N/A N/A 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu 873 874 876 877 0000h 0000h PC + 1(2) (3) 873 874 876 877 0001 1xxx 000q quuu uuuq quuu(3) 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu 873 874 876 877 --0x 0000 --0u 0000 --uu uuuu 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu 873 874 876 877 ---- -xxx ---- -uuu ---- -uuu 873 874 876 877 ---0 0000 ---0 0000 ---u uuuu 873 874 876 877 0000 000x 0000 000u uuuu uuuu(1) 873 874 876 877 r000 0000 r000 0000 ruuu uuuu(1) 873 874 876 877 0000 0000 0000 0000 uuuu uuuu(1) PIR2 873 874 876 877 -r-0 0--0 -r-0 0--0 -r-u u--u(1) TMR1L 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu TMR1H 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu T1CON 873 874 876 877 --00 0000 --uu uuuu --uu uuuu TMR2 873 874 876 877 0000 0000 0000 0000 uuuu uuuu T2CON 873 874 876 877 -000 0000 -000 0000 -uuu uuuu SSPBUF 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu SSPCON 873 874 876 877 0000 0000 0000 0000 uuuu uuuu CCPR1L 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1H 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 873 874 876 877 --00 0000 --00 0000 --uu uuuu RCSTA 873 874 876 877 0000 000x 0000 000x uuuu uuuu TXREG 873 874 876 877 0000 0000 0000 0000 uuuu uuuu RCREG 873 874 876 877 0000 0000 0000 0000 uuuu uuuu CCPR2L 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu CCPR2H 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON 873 874 876 877 0000 0000 0000 0000 uuuu uuuu ADRESH 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 873 874 876 877 0000 00-0 0000 00-0 uuuu uu-u OPTION_REG 873 874 876 877 1111 1111 1111 1111 uuuu uuuu TRISA 873 874 876 877 --11 1111 --11 1111 --uu uuuu TRISB 873 874 876 877 1111 1111 1111 1111 uuuu uuuu TRISC 873 874 876 877 1111 1111 1111 1111 uuuu uuuu TRISD 873 874 876 877 1111 1111 1111 1111 uuuu uuuu TRISE 873 874 876 877 0000 -111 0000 -111 uuuu -uuu PIE1 873 874 876 877 r000 0000 r000 0000 ruuu uuuu 873 874 876 877 0000 0000 0000 0000 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on condition, r = reserved, maintain clear Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 12-5 for RESET value for specific condition.  2001 Microchip Technology Inc. DS30292C-page 126 PIC16F87X TABLE 12-6: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset Wake-up via WDT or Interrupt PIE2 873 874 876 877 -r-0 0--0 -r-0 0--0 -r-u u--u PCON 873 874 876 877 ---- --qq ---- --uu ---- --uu PR2 873 874 876 877 1111 1111 1111 1111 1111 1111 SSPADD 873 874 876 877 0000 0000 0000 0000 uuuu uuuu SSPSTAT 873 874 876 877 --00 0000 --00 0000 --uu uuuu TXSTA 873 874 876 877 0000 -010 0000 -010 uuuu -uuu SPBRG 873 874 876 877 0000 0000 0000 0000 uuuu uuuu ADRESL 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu ADCON1 873 874 876 877 0--- 0000 0--- 0000 u--- uuuu EEDATA 873 874 876 877 0--- 0000 0--- 0000 u--- uuuu EEADR 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu EEDATH 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu EEADRH 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu EECON1 873 874 876 877 x--- x000 u--- u000 u--- uuuu EECON2 873 874 876 877 ---- ------- ------- ---Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on condition, r = reserved, maintain clear Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 12-5 for RESET value for specific condition. FIGURE 12-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET  2001 Microchip Technology Inc. DS30292C-page 127 PIC16F87X FIGURE 12-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 12-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 12-8: SLOW RISE TIME (MCLR TIED TO VDD) 5V VDD MCLR 0V 1V INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS30292C-page 128  2001 Microchip Technology Inc. PIC16F87X 12.10 Interrupts The PIC16F87X family has up to 14 sources of interrupt. The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. Note: Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit, or the GIE bit. The RB0/INT pin interrupt, the RB port change interrupt, and the TMR0 overflow interrupt flags are contained in the INTCON register. The peripheral interrupt flags are contained in the special function registers, PIR1 and PIR2. The corresponding interrupt enable bits are contained in special function registers, PIE1 and PIE2, and the peripheral interrupt enable bit is contained in special function register INTCON. When an interrupt is responded to, the GIE bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the PC is loaded with 0004h. Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts. For external interrupt events, such as the INT pin or PORTB change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends when the interrupt event occurs. The latency is the same for one or two-cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit, PEIE bit, or GIE bit. A global interrupt enable bit, GIE (INTCON) enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts. When bit GIE is enabled, and an interrupt’s flag bit and mask bit are set, the interrupt will vector immediately. Individual interrupts can be disabled through their corresponding enable bits in various registers. Individual interrupt bits are set, regardless of the status of the GIE bit. The GIE bit is cleared on RESET. The “return from interrupt” instruction, RETFIE, exits the interrupt routine, as well as sets the GIE bit, which re-enables interrupts. FIGURE 12-9: EEIF EEIE PSPIF PSPIE ADIF ADIE INTERRUPT LOGIC T0IF T0IE RCIF RCIE TXIF TXIE SSPIF SSPIE CCP1IF CCP1IE TMR2IF TMR2IE INTF INTE RBIF RBIE PEIE GIE Wake-up (If in SLEEP mode) Interrupt to CPU TMR1IF TMR1IE CCP2IF CCP2IE BCLIF BCLIE The following table shows which devices have which interrupts. Device PIC16F876/873 PIC16F877/874 T0IF INTF RBIF PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF EEIF BCLIF CCP2IF Yes Yes Yes Yes Yes Yes — Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes  2001 Microchip Technology Inc. DS30292C-page 129 PIC16F87X 12.10.1 INT INTERRUPT 12.11 Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt, (i.e., W register and STATUS register). This will have to be implemented in software. For the PIC16F873/874 devices, the register W_TEMP must be defined in both banks 0 and 1 and must be defined at the same offset from the bank base address (i.e., If W_TEMP is defined at 0x20 in bank 0, it must also be defined at 0xA0 in bank 1). The registers, PCLATH_TEMP and STATUS_TEMP, are only defined in bank 0. Since the upper 16 bytes of each bank are common in the PIC16F876/877 devices, temporary holding registers W_TEMP, STATUS_TEMP, and PCLATH_TEMP should be placed in here. These 16 locations don’t require banking and therefore, make it easier for context save and restore. The same code shown in Example 12-1 can be used. External interrupt on the RB0/INT pin is edge triggered, either rising, if bit INTEDG (OPTION_REG) is set, or falling, if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, flag bit INTF (INTCON) is set. This interrupt can be disabled by clearing enable bit INTE (INTCON). Flag bit INTF must be cleared in software in the Interrupt Service Routine before re-enabling this interrupt. The INT interrupt can wake-up the processor from SLEEP, if bit INTE was set prior to going into SLEEP. The status of global interrupt enable bit, GIE, decides whether or not the processor branches to the interrupt vector following wake-up. See Section 12.13 for details on SLEEP mode. 12.10.2 TMR0 INTERRUPT An overflow (FFh → 00h) in the TMR0 register will set flag bit T0IF (INTCON). The interrupt can be enabled/disabled by setting/clearing enable bit T0IE (INTCON) (Section 5.0). 12.10.3 PORTB INTCON CHANGE An input change on PORTB sets flag bit RBIF (INTCON). The interrupt can be enabled/disabled by setting/clearing enable bit RBIE (INTCON) (Section 3.2). EXAMPLE 12-1: MOVWF SWAPF CLRF MOVWF MOVF MOVWF CLRF : :(ISR) : MOVF MOVWF SWAPF MOVWF SWAPF SWAPF SAVING STATUS, W, AND PCLATH REGISTERS IN RAM ;Copy ;Swap ;bank ;Save ;Only ;Save ;Page W to TEMP register status to be saved into W 0, regardless of current bank, Clears IRP,RP1,RP0 status to bank zero STATUS_TEMP register required if using pages 1, 2 and/or 3 PCLATH into W zero, regardless of current page W_TEMP STATUS,W STATUS STATUS_TEMP PCLATH, W PCLATH_TEMP PCLATH ;(Insert user code here) PCLATH_TEMP, W PCLATH STATUS_TEMP,W STATUS W_TEMP,F W_TEMP,W ;Restore PCLATH ;Move W into PCLATH ;Swap STATUS_TEMP register into W ;(sets bank to original state) ;Move W into STATUS register ;Swap W_TEMP ;Swap W_TEMP into W DS30292C-page 130  2001 Microchip Technology Inc. PIC16F87X 12.12 Watchdog Timer (WDT) The Watchdog Timer is a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT will run, even if the clock on the OSC1/CLKIN and OSC2/ CLKOUT pins of the device has been stopped, for example, by execution of a SLEEP instruction. During normal operation, a WDT time-out generates a device RESET (Watchdog Timer Reset). If the device is in SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal operation (Watchdog Timer Wake-up). The TO bit in the STATUS register will be cleared upon a Watchdog Timer time-out. The WDT can be permanently disabled by clearing configuration bit WDTE (Section 12.1). WDT time-out period values may be found in the Electrical Specifications section under parameter #31. Values for the WDT prescaler (actually a postscaler, but shared with the Timer0 prescaler) may be assigned using the OPTION_REG register. Note 1: The CLRWDT and SLEEP instructions clear the WDT and the postscaler, if assigned to the WDT, and prevent it from timing out and generating a device RESET condition. 2: When a CLRWDT instruction is executed and the prescaler is assigned to the WDT, the prescaler count will be cleared, but the prescaler assignment is not changed. FIGURE 12-10: WATCHDOG TIMER BLOCK DIAGRAM From TMR0 Clock Source (Figure 5-1) 0 WDT Timer 1 M U X Postscaler 8 8 - to - 1 MUX PS2:PS0 WDT Enable Bit PSA To TMR0 (Figure 5-1) 0 MUX 1 PSA WDT Time-out Note: PSA and PS2:PS0 are bits in the OPTION_REG register. TABLE 12-7: Address 2007h 81h,181h SUMMARY OF WATCHDOG TIMER REGISTERS Name Bit 7 (1) RBPU Bit 6 BODEN(1) INTEDG Bit 5 CP1 T0CS Bit 4 CP0 T0SE Bit 3 PWRTE(1) PSA Bit 2 WDTE PS2 Bit 1 FOSC1 PS1 Bit 0 FOSC0 PS0 Config. bits OPTION_REG Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register 12-1 for operation of these bits.  2001 Microchip Technology Inc. DS30292C-page 131 PIC16F87X 12.13 Power-down Mode (SLEEP) Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (STATUS) is cleared, the TO (STATUS) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, low, or hi-impedance). For lowest current consumption in this mode, place all I/O pins at either VDD or VSS, ensure no external circuitry is drawing current from the I/O pin, power-down the A/D and disable external clocks. Pull all I/O pins that are hi-impedance inputs, high or low externally, to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip pull-ups on PORTB should also be considered. The MCLR pin must be at a logic high level (VIHMC). When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. 12.13.2 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: • If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT postscaler will not be cleared, the TO bit will not be set and PD bits will not be cleared. • If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake-up from SLEEP. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT postscaler will be cleared, the TO bit will be set and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction. 12.13.1 WAKE-UP FROM SLEEP The device can wake-up from SLEEP through one of the following events: 1. 2. 3. External RESET input on MCLR pin. Watchdog Timer Wake-up (if WDT was enabled). Interrupt from INT pin, RB port change or peripheral interrupt. External MCLR Reset will cause a device RESET. All other events are considered a continuation of program execution and cause a “wake-up”. The TO and PD bits in the STATUS register can be used to determine the cause of device RESET. The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The TO bit is cleared if a WDT time-out occurred and caused wake-up. The following peripheral interrupts can wake the device from SLEEP: 1. 2. 3. 4. 5. 6. 7. 8. 9. PSP read or write (PIC16F874/877 only). TMR1 interrupt. Timer1 must be operating as an asynchronous counter. CCP Capture mode interrupt. Special event trigger (Timer1 in Asynchronous mode using an external clock). SSP (START/STOP) bit detect interrupt. SSP transmit or receive in Slave mode (SPI/I2C). USART RX or TX (Synchronous Slave mode). A/D conversion (when A/D clock source is RC). EEPROM write operation completion Other peripherals cannot generate interrupts since during SLEEP, no on-chip clocks are present. DS30292C-page 132  2001 Microchip Technology Inc. PIC16F87X FIGURE 12-11: OSC1 CLKOUT(4) INT pin INTF Flag (INTCON) GIE bit (INTCON) INSTRUCTION FLOW PC Instruction Fetched Instruction Executed PC Inst(PC) = SLEEP Inst(PC - 1) PC+1 Inst(PC + 1) SLEEP PC+2 PC+2 Inst(PC + 2) Inst(PC + 1) Dummy cycle PC + 2 0004h Inst(0004h) Dummy cycle 0005h Inst(0005h) Inst(0004h) Processor in SLEEP Interrupt Latency(2) TOST(2) WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Note 1: XT, HS or LP oscillator mode assumed. 2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode. 3: GIE = ’1’ assumed. In this case, after wake- up, the processor jumps to the interrupt routine. If GIE = ’0’, execution will continue in-line. 4: CLKOUT is not available in these osc modes, but shown here for timing reference. 12.14 In-Circuit Debugger When the DEBUG bit in the configuration word is programmed to a ’0’, the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB® ICD. When the microcontroller has this feature enabled, some of the resources are not available for general use. Table 12-8 shows which features are consumed by the background debugger. 12.15 Program Verification/Code Protection If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verification purposes. 12.16 ID Locations Four memory locations (2000h - 2003h) are designated as ID locations, where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution, but are readable and writable during program/verify. It is recommended that only the 4 Least Significant bits of the ID location are used. TABLE 12-8: I/O pins Stack DEBUGGER RESOURCES RB6, RB7 1 level Address 0000h must be NOP Last 100h words 0x070 (0x0F0, 0x170, 0x1F0) 0x1EB - 0x1EF Program Memory Data Memory To use the In-Circuit Debugger function of the microcontroller, the design must implement In-Circuit Serial Programming connections to MCLR/VPP, VDD, GND, RB7 and RB6. This will interface to the In-Circuit Debugger module available from Microchip, or one of the third party development tool companies.  2001 Microchip Technology Inc. DS30292C-page 133 PIC16F87X 12.17 In-Circuit Serial Programming Note 1: The High Voltage Programming mode is always available, regardless of the state of the LVP bit, by applying VIHH to the MCLR pin. 2: While in Low Voltage ICSP mode, the RB3 pin can no longer be used as a general purpose I/O pin. 3: When using low voltage ICSP programming (LVP) and the pull-ups on PORTB are enabled, bit 3 in the TRISB register must be cleared to disable the pull-up on RB3 and ensure the proper operation of the device. 4: RB3 should not be allowed to float if LVP is enabled. An external pull-down device should be used to default the device to normal operating mode. If RB3 floats high, the PIC16F87X device will enter Programming mode. 5: LVP mode is enabled by default on all devices shipped from Microchip. It can be disabled by clearing the LVP bit in the CONFIG register. 6: Disabling LVP will provide maximum compatibility to other PIC16CXXX devices. If Low Voltage Programming mode is not used, the LVP bit can be programmed to a '0' and RB3/PGM becomes a digital I/O pin. However, the LVP bit may only be programmed when programming is entered with VIHH on MCLR. The LVP bit can only be charged when using high voltage on MCLR. It should be noted, that once the LVP bit is programmed to 0, only the High Voltage Programming mode is available and only High Voltage Programming mode can be used to program the device. When using low voltage ICSP, the part must be supplied at 4.5V to 5.5V, if a bulk erase will be executed. This includes reprogramming of the code protect bits from an on-state to off-state. For all other cases of low voltage ICSP, the part may be programmed at the normal operating voltage. This means calibration values, unique user IDs, or user code can be reprogrammed or added. PIC16F87X microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for power, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware, or a custom firmware to be programmed. When using ICSP, the part must be supplied at 4.5V to 5.5V, if a bulk erase will be executed. This includes reprogramming of the code protect, both from an onstate to off-state. For all other cases of ICSP, the part may be programmed at the normal operating voltages. This means calibration values, unique user IDs, or user code can be reprogrammed or added. For complete details of serial programming, please refer to the EEPROM Memory Programming Specification for the PIC16F87X (DS39025). 12.18 Low Voltage ICSP Programming The LVP bit of the configuration word enables low voltage ICSP programming. This mode allows the microcontroller to be programmed via ICSP using a VDD source in the operating voltage range. This only means that VPP does not have to be brought to VIHH, but can instead be left at the normal operating voltage. In this mode, the RB3/PGM pin is dedicated to the programming function and ceases to be a general purpose I/O pin. During programming, VDD is applied to the MCLR pin. To enter Programming mode, VDD must be applied to the RB3/PGM, provided the LVP bit is set. The LVP bit defaults to on (‘1’) from the factory. DS30292C-page 134  2001 Microchip Technology Inc. PIC16F87X 13.0 INSTRUCTION SET SUMMARY Each PIC16F87X instruction is a 14-bit word, divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16F87X instruction set summary in Table 13-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 13-1 shows the opcode field descriptions. For byte-oriented instructions, ’f’ represents a file register designator and ’d’ represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If ’d’ is zero, the result is placed in the W register. If ’d’ is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, ’b’ represents a bit field designator which selects the number of the bit affected by the operation, while ’f’ represents the address of the file in which the bit is located. For literal and control operations, ’k’ represents an eight or eleven bit constant or literal value. All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 µs. If a conditional test is true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 µs. Table 13-2 lists the instructions recognized by the MPASMTM assembler. Figure 13-1 shows the general formats that the instructions can have. Note: To maintain upward compatibility with future PIC16F87X products, do not use the OPTION and TRIS instructions. All examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit. FIGURE 13-1: TABLE 13-1: Field f W b k x OPCODE FIELD DESCRIPTIONS Description GENERAL FORMAT FOR INSTRUCTIONS 0 Byte-oriented file register operations 13 876 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 76 OPCODE b (BIT #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE k = 8-bit immediate value CALL and GOTO instructions only 13 11 OPCODE 10 k (literal) 8 7 k (literal) Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1. Program Counter Time-out bit Power-down bit 0 f (FILE #) d PC TO PD 0 The instruction set is highly orthogonal and is grouped into three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations 0 k = 11-bit immediate value A description of each instruction is available in the PICmicro™ Mid-Range Reference Manual, (DS33023).  2001 Microchip Technology Inc. DS30292C-page 135 PIC16F87X TABLE 13-2: Mnemonic, Operands PIC16F87X INSTRUCTION SET 14-Bit Opcode Description Cycles MSb BYTE-ORIENTED FILE REGISTER OPERATIONS LSb Status Affected Notes ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff C,DC,Z Z Z Z Z Z Z Z Z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 C C C,DC,Z Z 1,2 1,2 1,2 1,2 1,2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW f, b f, b f, b f, b k k k k k k k k k Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into standby mode Subtract W from literal Exclusive OR literal with W 1 1 1 (2) 1 (2) 1 1 2 1 2 1 1 2 2 2 1 1 1 01 01 01 01 11 11 10 00 10 11 11 00 11 00 00 11 11 00bb 01bb 10bb 11bb 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 bfff bfff bfff bfff kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk ffff ffff ffff ffff kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk 1,2 1,2 3 3 C,DC,Z Z TO,PD Z LITERAL AND CONTROL OPERATIONS TO,PD C,DC,Z Z Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ’0’. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 module. 3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Note: Additional information on the mid-range instruction set is available in the PICmicro™ Mid-Range MCU Family Reference Manual (DS33023). DS30292C-page 136  2001 Microchip Technology Inc. PIC16F87X 13.1 ADDLW Syntax: Operands: Operation: Status Affected: Description: Instruction Descriptions Add Literal and W [label] ADDLW 0 ≤ k ≤ 255 (W) + k → (W) C, DC, Z The contents of the W register are added to the eight bit literal ’k’ and the result is placed in the W register. Operation: Status Affected: Description: k BCF Syntax: Operands: Bit Clear f [label] BCF 0 ≤ f ≤ 127 0≤b≤7 0 → (f) None Bit 'b' in register 'f' is cleared. f,b ADDWF Syntax: Operands: Operation: Status Affected: Description: Add W and f [label] ADDWF 0 ≤ f ≤ 127 d ∈ [0,1] (W) + (f) → (destination) C, DC, Z Add the contents of the W register with register ’f’. If ’d’ is 0, the result is stored in the W register. If ’d’ is 1, the result is stored back in register ’f’. f,d BSF Syntax: Operands: Operation: Status Affected: Description: Bit Set f [label] BSF 0 ≤ f ≤ 127 0≤b≤7 1 → (f) None Bit 'b' in register 'f' is set. f,b ANDLW Syntax: Operands: Operation: Status Affected: Description: AND Literal with W [label] ANDLW 0 ≤ k ≤ 255 (W) .AND. (k) → (W) Z The contents of W register are AND’ed with the eight bit literal 'k'. The result is placed in the W register. k BTFSS Syntax: Operands: Operation: Status Affected: Description: Bit Test f, Skip if Set [label] BTFSS f,b 0 ≤ f ≤ 127 0≤b VDD) ..................................................................................................................... ± 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) ............................................................................................................. ± 20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by PORTA, PORTB, and PORTE (combined) (Note 3) ...................................................200 mA Maximum current sourced by PORTA, PORTB, and PORTE (combined) (Note 3)..............................................200 mA Maximum current sunk by PORTC and PORTD (combined) (Note 3) .................................................................200 mA Maximum current sourced by PORTC and PORTD (combined) (Note 3) ............................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL) 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR pin, rather than pulling this pin directly to VSS. 3: PORTD and PORTE are not implemented on PIC16F873/876 devices. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  2001 Microchip Technology Inc. DS30292C-page 149 PIC16F87X FIGURE 15-1: PIC16F87X-20 VOLTAGE-FREQUENCY GRAPH (COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ONLY) 6.0 V 5.5 V 5.0 V Voltage 4.5 V 4.0 V 3.5 V 3.0 V 2.5 V 2.0 V 16 MHz 20 MHz Frequency FIGURE 15-2: PIC16LF87X-04 VOLTAGE-FREQUENCY GRAPH (COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ONLY) 6.0 V 5.5 V 5.0 V Voltage 4.5 V 4.0 V 3.5 V 3.0 V 2.5 V 2.0 V 4 MHz 10 MHz Frequency FMAX = (6.0 MHz/V) (VDDAPPMIN - 2.0 V) + 4 MHz Note 1: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application. Note 2: FMAX has a maximum frequency of 10MHz. DS30292C-page 150  2001 Microchip Technology Inc. PIC16F87X FIGURE 15-3: PIC16F87X-04 VOLTAGE-FREQUENCY GRAPH (ALL TEMPERATURE RANGES) 6.0 V 5.5 V 5.0 V PIC16F87X-04 Voltage 4.5 V 4.0 V 3.5 V 3.0 V 2.5 V 2.0 V 4 MHz Frequency FIGURE 15-4: PIC16F87X-10 VOLTAGE-FREQUENCY GRAPH (EXTENDED TEMPERATURE RANGE ONLY) 6.0 V 5.5 V 5.0 V PIC16F87X-10 Voltage 4.5 V 4.0 V 3.5 V 3.0 V 2.5 V 2.0 V 10 MHz Frequency  2001 Microchip Technology Inc. DS30292C-page 151 PIC16F87X 15.1 DC Characteristics: PIC16F873/874/876/877-04 (Commercial, Industrial) PIC16F873/874/876/877-20 (Commercial, Industrial) PIC16LF873/874/876/877-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial 0°C ≤ TA ≤ +70°C for commercial Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial 0°C ≤ TA ≤ +70°C for commercial Min Typ† Max Units Conditions PIC16LF873/874/876/877-04 (Commercial, Industrial) PIC16F873/874/876/877-04 PIC16F873/874/876/877-20 (Commercial, Industrial) Param No. D001 D001 D001A D002 D003 VDR VPOR RAM Data Retention Voltage(1) VDD Start Voltage to ensure internal Power-on Reset signal VDD Rise Rate to ensure internal Power-on Reset signal Brown-out Reset Voltage Symbol VDD Characteristic/ Device Supply Voltage 16LF87X 16F87X 2.0 4.0 4.5 VBOR — — — — 5.5 5.5 5.5 5.5 V V V V V V LP, XT, RC osc configuration (DC to 4 MHz) LP, XT, RC osc configuration HS osc configuration BOR enabled, FMAX = 14 MHz(7) 1.5 VSS — — See section on Power-on Reset for details D004 SVDD 0.05 — — V/ms See section on Power-on Reset for details V BODEN bit in configuration word enabled D005 VBOR 3.7 4.0 4.35 Legend: Rows with standard voltage device data only are shaded for improved readability. † Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only, and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading, switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from characterization and is for design guidance only. This is not tested. 6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached. DS30292C-page 152  2001 Microchip Technology Inc. PIC16F87X 15.1 DC Characteristics: PIC16F873/874/876/877-04 (Commercial, Industrial) PIC16F873/874/876/877-20 (Commercial, Industrial) PIC16LF873/874/876/877-04 (Commercial, Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial 0°C ≤ TA ≤ +70°C for commercial Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial 0°C ≤ TA ≤ +70°C for commercial Min Typ† Max Units Conditions PIC16LF873/874/876/877-04 (Commercial, Industrial) PIC16F873/874/876/877-04 PIC16F873/874/876/877-20 (Commercial, Industrial) Param No. D010 D010 D010A Symbol IDD Characteristic/ Device Supply Current(2,5) 16LF87X 16F87X 16LF87X — — — 0.6 1.6 20 2.0 4 35 mA mA µA XT, RC osc configuration FOSC = 4 MHz, VDD = 3.0V RC osc configurations FOSC = 4 MHz, VDD = 5.5V LP osc configuration FOSC = 32 kHz, VDD = 3.0V, WDT disabled HS osc configuration, FOSC = 20 MHz, VDD = 5.5V BOR enabled, VDD = 5.0V D013 D015 ∆IBOR 16F87X Brown-out Reset Current(6) — — 7 85 15 200 mA µA Legend: Rows with standard voltage device data only are shaded for improved readability. † Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only, and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading, switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from characterization and is for design guidance only. This is not tested. 6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.  2001 Microchip Technology Inc. DS30292C-page 153 PIC16F87X 15.1 DC Characteristics: PIC16F873/874/876/877-04 (Commercial, Industrial) PIC16F873/874/876/877-20 (Commercial, Industrial) PIC16LF873/874/876/877-04 (Commercial, Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial 0°C ≤ TA ≤ +70°C for commercial Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial 0°C ≤ TA ≤ +70°C for commercial Min Typ† Max Units Conditions PIC16LF873/874/876/877-04 (Commercial, Industrial) PIC16F873/874/876/877-04 PIC16F873/874/876/877-20 (Commercial, Industrial) Param No. D020 D020 D021 D021 D021A D021A D023 ∆IBOR Brown-out Reset Current(6) Symbol IPD Characteristic/ Device Power-down Current(3,5) 16LF87X 16F87X 16LF87X 16F87X 16LF87X 16F87X — — — — 7.5 10.5 0.9 1.5 0.9 1.5 30 42 5 16 5 19 200 µA µA µA µA µA µA µA VDD = 3.0V, WDT enabled, -40°C to +85°C VDD = 4.0V, WDT enabled, -40°C to +85°C VDD = 3.0V, WDT enabled, 0°C to +70°C VDD = 4.0V, WDT enabled, -40°C to +85°C VDD = 3.0V, WDT enabled, -40°C to +85°C VDD = 4.0V, WDT enabled, -40°C to +85°C BOR enabled, VDD = 5.0V — 85 Legend: Rows with standard voltage device data only are shaded for improved readability. † Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only, and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading, switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from characterization and is for design guidance only. This is not tested. 6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached. DS30292C-page 154  2001 Microchip Technology Inc. PIC16F87X 15.2 DC Characteristics: PIC16F873/874/876/877-04 (Commercial, Industrial) PIC16F873/874/876/877-20 (Commercial, Industrial) PIC16LF873/874/876/877-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial 0°C ≤ TA ≤ +70°C for commercial Operating voltage VDD range as described in DC specification (Section 15.1) Characteristic Input Low Voltage I/O ports with TTL buffer with Schmitt Trigger buffer MCLR, OSC1 (in RC mode) OSC1 (in XT, HS and LP) Ports RC3 and RC4 with Schmitt Trigger buffer with SMBus Input High Voltage I/O ports with TTL buffer Min Typ† Max Units Conditions DC CHARACTERISTICS Param No. Sym VIL D030 D030A D031 D032 D033 D034 D034A VIH D040 D040A D041 D042 D042A D043 D044 D044A D070 Vss Vss Vss VSS VSS Vss -0.5 — 0.15VDD — 0.8V — 0.2VDD — 0.2VDD — 0.3VDD — — 0.3VDD — 0.6 — — — — — — — — — 250 V V V V V V V For entire VDD range 4.5V ≤ VDD ≤ 5.5V (Note 1) For entire VDD range for VDD = 4.5 to 5.5V with Schmitt Trigger buffer MCLR OSC1 (XT, HS and LP) OSC1 (in RC mode) Ports RC3 and RC4 with Schmitt Trigger buffer with SMBus IPURB PORTB Weak Pull-up Current IIL Input Leakage Current(2, 3) I/O ports MCLR, RA4/T0CKI OSC1 2.0 0.25VDD + 0.8V 0.8VDD 0.8VDD 0.7VDD 0.9VDD 0.7VDD 1.4 50 VDD VDD VDD VDD VDD VDD VDD 5.5 400 V V V V V V 4.5V ≤ VDD ≤ 5.5V For entire VDD range For entire VDD range (Note 1) V For entire VDD range V for VDD = 4.5 to 5.5V µA VDD = 5V, VPIN = VSS, -40°C TO +85°C µA Vss ≤ VPIN ≤ VDD, Pin at hi-impedance µA Vss ≤ VPIN ≤ VDD µA Vss ≤ VPIN ≤ VDD, XT, HS and LP osc configuration D060 D061 D063 * † — — — — — — ±1 ±5 ±5 These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16F87X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.  2001 Microchip Technology Inc. DS30292C-page 155 PIC16F87X 15.2 DC Characteristics: PIC16F873/874/876/877-04 (Commercial, Industrial) PIC16F873/874/876/877-20 (Commercial, Industrial) PIC16LF873/874/876/877-04 (Commercial, Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial 0°C ≤ TA ≤ +70°C for commercial Operating voltage VDD range as described in DC specification (Section 15.1) Characteristic Output Low Voltage I/O ports OSC2/CLKOUT (RC osc config) VOH D090 D092 D150* VOD Output High Voltage I/O ports(3) OSC2/CLKOUT (RC osc config) Open-Drain High Voltage Capacitive Loading Specs on Output Pins COSC2 OSC2 pin VDD - 0.7 VDD - 0.7 — — — — — — 8.5 V V V IOH = -3.0 mA, VDD = 4.5V, -40°C to +85°C IOH = -1.3 mA, VDD = 4.5V, -40°C to +85°C RA4 pin Min Typ† Max Units Conditions DC CHARACTERISTICS Param No. D080 D083 Sym VOL — — — — 0.6 0.6 V V IOL = 8.5 mA, VDD = 4.5V, -40°C to +85°C IOL = 1.6 mA, VDD = 4.5V, -40°C to +85°C D100 — — 15 D101 D102 D120 D121 D122 D130 D131 D132A D133 * † All I/O pins and OSC2 (RC mode) SCL, SDA (I2C mode) Data EEPROM Memory ED Endurance VDRW VDD for read/write TDEW Erase/write cycle time Program FLASH Memory EP Endurance VPR VDD for read VDD for erase/write CIO CB — — 100K VMIN — 1000 VMIN VMIN — — — — 4 — — — 50 400 — 5.5 8 — 5.5 5.5 pF In XT, HS and LP modes when external clock is used to drive OSC1 pF pF E/W 25°C at 5V V Using EECON to read/write VMIN = min. operating voltage ms E/W 25°C at 5V V VMIN = min operating voltage V Using EECON to read/write, VMIN = min. operating voltage ms TPEW Erase/Write cycle time — 4 8 These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16F87X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. DS30292C-page 156  2001 Microchip Technology Inc. PIC16F87X 15.3 DC Characteristics: PIC16F873/874/876/877-04 (Extended) PIC16F873/874/876/877-10 (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Min Typ† Max Units Conditions PIC16F873/874/876/877-04 PIC16F873/874/876/877-20 (Extended) Param No. D001 D001A D001A D002 D003 VDR VPOR RAM Data Retention Voltage(1) VDD Start Voltage to ensure internal Power-on Reset signal VDD Rise Rate to ensure internal Power-on Reset signal Brown-out Reset Voltage Symbol VDD Characteristic/ Device Supply Voltage 4.0 4.5 VBOR — — — 5.5 5.5 5.5 V V V V V LP, XT, RC osc configuration HS osc configuration BOR enabled, FMAX = 10 MHz(7) 1.5 VSS — — See section on Power-on Reset for details D004 SVDD 0.05 — — V/ms See section on Power-on Reset for details V BODEN bit in configuration word enabled D005 † Note 1: 2: VBOR 3.7 4.0 4.35 3: 4: 5: 6: 7: Data is “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only, and are not tested. This is the limit to which VDD can be lowered without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading, switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from characterization and is for design guidance only. This is not tested. The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.  2001 Microchip Technology Inc. DS30292C-page 157 PIC16F87X 15.3 DC Characteristics: PIC16F873/874/876/877-04 (Extended) PIC16F873/874/876/877-10 (Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Min Typ† Max Units Conditions PIC16F873/874/876/877-04 PIC16F873/874/876/877-20 (Extended) Param No. D010 D013 D015 ∆IBOR IPD D020A D021B D023 † Note 1: 2: ∆IBOR Brown-out Reset Current(6) Brown-out Reset Current(6) Power-down Current(3,5) Symbol IDD Characteristic/ Device Supply Current(2,5) — — — 1.6 7 85 4 15 200 mA mA µA RC osc configurations FOSC = 4 MHz, VDD = 5.5V HS osc configuration, FOSC = 10 MHz, VDD = 5.5V BOR enabled, VDD = 5.0V 10.5 1.5 — 85 60 30 200 µA µA µA VDD = 4.0V, WDT enabled VDD = 4.0V, WDT disabled BOR enabled, VDD = 5.0V 3: 4: 5: 6: 7: Data is “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only, and are not tested. This is the limit to which VDD can be lowered without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading, switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from characterization and is for design guidance only. This is not tested. The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached. DS30292C-page 158  2001 Microchip Technology Inc. PIC16F87X 15.4 DC Characteristics: PIC16F873/874/876/877-04 (Extended) PIC16F873/874/876/877-10 (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Operating voltage VDD range as described in DC specification (Section 15.1) Characteristic Input Low Voltage I/O ports with TTL buffer with Schmitt Trigger buffer MCLR, OSC1 (in RC mode) OSC1 (in XT, HS and LP) Ports RC3 and RC4 with Schmitt Trigger buffer with SMBus VIH D040 D040A D041 D042 D042A D043 D044 D044A D070A D060 D061 D063 * † Input High Voltage I/O ports with TTL buffer Min Typ† Max Units Conditions DC CHARACTERISTICS Param No. Sym VIL D030 D030A D031 D032 D033 D034 D034A Vss Vss Vss VSS VSS Vss -0.5 — 0.15VDD — 0.8V — 0.2VDD — 0.2VDD — 0.3VDD — — — — — — — — — — — 250 0.3VDD 0.6 V V V V V V V For entire VDD range 4.5V ≤ VDD ≤ 5.5V (Note 1) For entire VDD range for VDD = 4.5 to 5.5V with Schmitt Trigger buffer MCLR OSC1 (XT, HS and LP) OSC1 (in RC mode) Ports RC3 and RC4 with Schmitt Trigger buffer with SMBus IPURB PORTB Weak Pull-up Current IIL Input Leakage Current(2, 3) I/O ports MCLR, RA4/T0CKI OSC1 2.0 0.25VDD + 0.8V 0.8VDD 0.8VDD 0.7VDD 0.9VDD 0.7VDD 1.4 50 - VDD VDD VDD VDD VDD VDD VDD 5.5 400 ±1 ±5 ±5 V V V V V V V V µA µA µA µA 4.5V ≤ VDD ≤ 5.5V For entire VDD range For entire VDD range (Note 1) For entire VDD range for VDD = 4.5 to 5.5V VDD = 5V, VPIN = VSS, Vss ≤ VPIN ≤ VDD, Pin at hi-impedance Vss ≤ VPIN ≤ VDD Vss ≤ VPIN ≤ VDD, XT, HS and LP osc configuration These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16F87X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.  2001 Microchip Technology Inc. DS30292C-page 159 PIC16F87X 15.4 DC Characteristics: PIC16F873/874/876/877-04 (Extended) PIC16F873/874/876/877-10 (Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Operating voltage VDD range as described in DC specification (Section 15.1) Characteristic Output Low Voltage I/O ports OSC2/CLKOUT (RC osc config) Output High Voltage Min Typ† Max Units Conditions DC CHARACTERISTICS Param No. D080A D083A VOH D090A D092A D150* D100 Sym VOL — — — — — — — — 0.6 0.6 — — 8.5 15 V V V V V pF IOL = 7.0 mA, VDD = 4.5V IOL = 1.2 mA, VDD = 4.5V IOH = -2.5 mA, VDD = 4.5V IOH = -1.0 mA, VDD = 4.5V RA4 pin In XT, HS and LP modes when external clock is used to drive OSC1 VOD COSC2 VDD - 0.7 I/O ports(3) OSC2/CLKOUT (RC osc config) VDD - 0.7 Open Drain High Voltage — Capacitive Loading Specs on Output Pins OSC2 pin — D101 D102 D120 D121 D122 D130 D131 D132A D133 * † All I/O pins and OSC2 (RC mode) SCL, SDA (I2C mode) Data EEPROM Memory ED Endurance VDRW VDD for read/write TDEW Erase/write cycle time Program FLASH Memory EP Endurance VPR VDD for read VDD for erase/write CIO CB — — 100K VMIN — 1000 VMIN VMIN — — — — 4 — — — 50 400 — 5.5 8 — 5.5 5.5 pF pF E/W 25°C at 5V V Using EECON to read/write VMIN = min. operating voltage ms E/W 25°C at 5V V VMIN = min operating voltage V Using EECON to read/write, VMIN = min. operating voltage ms TPEW Erase/Write cycle time — 4 8 These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16F87X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. DS30292C-page 160  2001 Microchip Technology Inc. PIC16F87X 15.5 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low I2C only AA BUF output access Bus free T Time 3. TCC:ST 4. Ts (I2C specifications only) (I2C specifications only) osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCK SS T0CKI T1CKI WR P R V Z High Low Period Rise Valid Hi-impedance High Low TCC:ST (I2C specifications only) CC HD Hold ST DAT DATA input hold STA START condition SU STO Setup STOP condition FIGURE 15-5: LOAD CONDITIONS Load Condition 1 VDD/2 Load Condition 2 RL Pin VSS RL CL = 464 Ω CL Pin VSS CL = 50 pF for all pins except OSC2, but including PORTD and PORTE outputs as ports, 15 pF for OSC2 output Note: PORTD and PORTE are not implemented on PIC16F873/876 devices.  2001 Microchip Technology Inc. DS30292C-page 161 PIC16F87X FIGURE 15-6: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 2 CLKOUT 3 3 4 4 TABLE 15-1: Parameter No. EXTERNAL CLOCK TIMING REQUIREMENTS Sym Characteristic Min DC DC DC DC DC DC 0.1 4 4 5 250 250 100 50 5 250 250 250 100 50 5 200 Typ† — — — — — — — — — — — — — — — — — — — — — TCY Max 4 4 10 20 200 4 4 10 20 200 — — — — — — 10,000 — 250 250 — DC Units MHz MHz MHz MHz kHz MHz MHz MHz MHz kHz ns ns ns ns µs ns ns ns ns ns µs ns Conditions XT and RC osc mode HS osc mode (-04) HS osc mode (-10) HS osc mode (-20) LP osc mode RC osc mode XT osc mode HS osc mode (-10) HS osc mode (-20) LP osc mode XT and RC osc mode HS osc mode (-04) HS osc mode (-10) HS osc mode (-20) LP osc mode RC osc mode XT osc mode HS osc mode (-04) HS osc mode (-10) HS osc mode (-20) LP osc mode TCY = 4/FOSC FOSC External CLKIN Frequency (Note 1) Oscillator Frequency (Note 1) 1 TOSC External CLKIN Period (Note 1) Oscillator Period (Note 1) 2 3 100 — — ns XT oscillator 2.5 — — µs LP oscillator 15 — — ns HS oscillator 4 TosR, External Clock in (OSC1) Rise or — — 25 ns XT oscillator TosF Fall Time — — 50 ns LP oscillator — — 15 ns HS oscillator † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions, with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "max." cycle time limit is "DC" (no clock) for all devices. Instruction Cycle Time (Note 1) TosL, External Clock in (OSC1) High or TosH Low Time TCY DS30292C-page 162  2001 Microchip Technology Inc. PIC16F87X FIGURE 15-7: CLKOUT AND I/O TIMING Q4 OSC1 10 CLKOUT 13 14 I/O Pin (Input) 17 I/O Pin (Output) Old Value 15 New Value 19 18 12 16 11 Q1 Q2 Q3 20, 21 Note: Refer to Figure 15-5 for load conditions. TABLE 15-2: Param No. 10* 11* 12* 13* 14* 15* 16* 17* 18* Symbol CLKOUT AND I/O TIMING REQUIREMENTS Characteristic Min — — — — — TOSC + 200 0 — Standard (F) Extended (LF) 100 200 0 — — — — TCY TCY Typ† 75 75 35 35 — — — 100 — — — 10 — 10 — — — Max 200 200 100 100 0.5TCY + 20 — — 255 — — — 40 145 40 145 — — Units Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) TosH2ckL OSC1↑ to CLKOUT↓ TosH2ck OSC1↑ to CLKOUT↑ H TckR TckF CLKOUT rise time CLKOUT fall time TckL2ioV CLKOUT ↓ to Port out valid TioV2ckH Port in valid before CLKOUT ↑ TckH2ioI Port in hold after CLKOUT ↑ TosH2ioV OSC1↑ (Q1 cycle) to Port out valid TosH2ioI OSC1↑ (Q2 cycle) to Port input invalid (I/O in hold time) TioR TioF Tinp Trbp Port output rise time Port output fall time INT pin high or low time RB7:RB4 change INT high or low time 19* 20* 21* 22††* 23††* * † TioV2osH Port input valid to OSC1↑ (I/O in setup time) Standard (F) Extended (LF) Standard (F) Extended (LF) These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.  2001 Microchip Technology Inc. DS30292C-page 163 PIC16F87X FIGURE 15-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR Internal POR 33 PWRT Time-out OSC Time-out Internal Reset Watchdog Timer Reset 34 I/O Pins Note: Refer to Figure 15-5 for load conditions. 32 30 31 34 FIGURE 15-9: BROWN-OUT RESET TIMING VDD VBOR 35 TABLE 15-3: Parameter No. 30 31* 32 33* 34 35 * † RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Oscillation Start-up Timer Period Power-up Timer Period I/O Hi-impedance from MCLR Low or Watchdog Timer Reset Brown-out Reset pulse width Min 2 7 — 28 — 100 Typ† — 18 1024 TOSC 72 — — Max — 33 — 132 2.1 — Units µs ms — ms µs µs VDD ≤ VBOR (D005) Conditions VDD = 5V, -40°C to +85°C VDD = 5V, -40°C to +85°C TOSC = OSC1 period VDD = 5V, -40°C to +85°C Symbol TmcL Twdt Tost Tpwrt TIOZ TBOR These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30292C-page 164  2001 Microchip Technology Inc. PIC16F87X FIGURE 15-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 40 41 42 RC0/T1OSO/T1CKI 45 46 47 TMR0 or TMR1 Note: Refer to Figure 15-5 for load conditions. 48 TABLE 15-4: Param No. 40* 41* 42* Symbol Tt0H Tt0L Tt0P TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Characteristic T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period No Prescaler With Prescaler No Prescaler With Prescaler No Prescaler With Prescaler Min 0.5TCY + 20 10 0.5TCY + 20 10 TCY + 40 Greater of: 20 or TCY + 40 N 0.5TCY + 20 15 25 30 50 0.5TCY + 20 15 25 30 50 Greater of: 30 OR TCY + 40 N Greater of: 50 OR TCY + 40 N 60 100 DC Typ† Max Units — — — — — — — — — — — — ns ns ns ns ns ns Conditions Must also meet parameter 42 Must also meet parameter 42 N = prescale value (2, 4,..., 256) Must also meet parameter 47 45* Tt1H 46* Tt1L 47* Tt1P T1CKI High Time Synchronous, Prescaler = 1 Synchronous, Standard(F) Prescaler = 2,4,8 Extended(LF) Asynchronous Standard(F) Extended(LF) T1CKI Low Time Synchronous, Prescaler = 1 Synchronous, Standard(F) Prescaler = 2,4,8 Extended(LF) Asynchronous Standard(F) Extended(LF) T1CKI input Synchronous Standard(F) period Extended(LF) — — — — — — — — — — — — — — — — — — — — — — ns ns ns ns ns ns ns ns ns ns ns Must also meet parameter 47 N = prescale value (1, 2, 4, 8) N = prescale value (1, 2, 4, 8) 48 * † Standard(F) — — ns Extended(LF) — — ns Ft1 Timer1 oscillator input frequency range — 200 kHz (oscillator enabled by setting bit T1OSCEN) TCKEZtmr1 Delay from external clock edge to timer increment 2TOSC — 7TOSC — These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Asynchronous  2001 Microchip Technology Inc. DS30292C-page 165 PIC16F87X FIGURE 15-11: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) RC1/T1OSI/CCP2 and RC2/CCP1 (Capture Mode) 50 52 51 RC1/T1OSI/CCP2 and RC2/CCP1 (Compare or PWM Mode) 53 Note: Refer to Figure 15-5 for load conditions. 54 TABLE 15-5: Param No. 50* Sym CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2) Characteristic No Prescaler Standard(F) With Prescaler Extended(LF) Min 0.5TCY + 20 10 20 0.5TCY + 20 Standard(F) With Prescaler Extended(LF) 10 20 3TCY + 40 N Standard(F) Extended(LF) — — — — Typ† Max Units — — — — — — — 10 25 10 25 — — — — — — — 25 50 25 45 ns ns ns ns ns ns ns ns ns ns ns N = prescale value (1, 4 or 16) Conditions TccL CCP1 and CCP2 input low time 51* TccH CCP1 and CCP2 input high time No Prescaler 52* 53* TccP CCP1 and CCP2 input period TccR CCP1 and CCP2 output rise time 54* TccF CCP1 and CCP2 output fall time Standard(F) Extended(LF) * † These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30292C-page 166  2001 Microchip Technology Inc. PIC16F87X FIGURE 15-12: RE2/CS PARALLEL SLAVE PORT TIMING (PIC16F874/877 ONLY) RE0/RD RE1/WR 65 RD7:RD0 62 63 Note: Refer to Figure 15-5 for load conditions. 64 TABLE 15-6: Parameter No. 62 PARALLEL SLAVE PORT REQUIREMENTS (PIC16F874/877 ONLY) Symbol Characteristic Min Typ† Max Units 20 25 20 35 — — 10 — — — — — — — — — — — 80 90 30 ns ns ns ns ns ns ns Extended Range Only Conditions TdtV2wrH Data in valid before WR↑ or CS↑ (setup time) Extended Range Only 63* TwrH2dtI WR↑ or CS↑ to data–in invalid (hold time) Standard(F) Extended(LF) RD↓ and CS↓ to data–out valid 64 TrdL2dtV 65 * † TrdH2dtI RD↑ or CS↓ to data–out invalid These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2001 Microchip Technology Inc. DS30292C-page 167 PIC16F87X FIGURE 15-13: SS 70 SCK (CKP = 0) 71 72 SPI MASTER MODE TIMING (CKE = 0, SMP = 0) 78 79 SCK (CKP = 1) 79 78 80 SDO MSb 75, 76 SDI MSb IN 74 73 Note: Refer to Figure 15-5 for load conditions. BIT6 - - - -1 BIT6 - - - - - -1 LSb LSb IN FIGURE 15-14: SPI MASTER MODE TIMING (CKE = 1, SMP = 1) SS 81 SCK (CKP = 0) 71 73 SCK (CKP = 1) 80 78 72 79 SDO MSb 75, 76 BIT6 - - - - - -1 LSb SDI MSb IN 74 BIT6 - - - -1 LSb IN Note: Refer to Figure 15-5 for load conditions. DS30292C-page 168  2001 Microchip Technology Inc. PIC16F87X FIGURE 15-15: SS 70 SCK (CKP = 0) 71 72 83 SPI SLAVE MODE TIMING (CKE = 0) 78 79 SCK (CKP = 1) 79 78 80 SDO MSb 75, 76 SDI MSb IN 74 73 Note: Refer to Figure 15-5 for load conditions. BIT6 - - - -1 BIT6 - - - - - -1 LSb 77 LSb IN FIGURE 15-16: SS SPI SLAVE MODE TIMING (CKE = 1) 82 SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 SDO MSb 75, 76 BIT6 - - - - - -1 LSb 77 SDI MSb IN 74 BIT6 - - - -1 LSb IN Note: Refer to Figure 15-5 for load conditions.  2001 Microchip Technology Inc. DS30292C-page 169 PIC16F87X TABLE 15-7: Param No. 70* 71* 72* 73* 74* 75* 76* 77* 78* 79* 80* 81* 82* 83* * † SPI MODE REQUIREMENTS Characteristic SS↓ to SCK↓ or SCK↑ input SCK input high time (Slave mode) SCK input low time (Slave mode) Setup time of SDI data input to SCK edge Hold time of SDI data input to SCK edge SDO data output rise time SDO data output fall time SS↑ to SDO output hi-impedance SCK output rise time (Master mode) Standard(F) Extended(LF) SCK output fall time (Master mode) SDO data output valid after SCK edge SDO data output setup to SCK edge SDO data output valid after SS↓ edge SS ↑ after SCK edge Standard(F) Extended(LF) Standard(F) Extended(LF) Min Tcy TCY + 20 TCY + 20 100 100 — — — 10 — — — — — Tcy — 1.5TCY + 40 Typ† — — — — — 10 25 10 — 10 25 10 — — — — — Max — — — — — 25 50 25 50 25 50 25 50 145 — 50 — Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Conditions Symbol TssL2scH, TssL2scL TscH TscL TdiV2scH, TdiV2scL TscH2diL, TscL2diL TdoR TdoF TssH2doZ TscR TscF TscH2doV, TscL2doV TdoV2scH, TdoV2scL TssL2doV TscH2ssH, TscL2ssH These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 15-17: I2C BUS START/STOP BITS TIMING SCL 90 SDA 91 92 93 START Condition Note: Refer to Figure 15-5 for load conditions. STOP Condition DS30292C-page 170  2001 Microchip Technology Inc. PIC16F87X TABLE 15-8: Parameter No. 90 91 92 93 I2C BUS START/STOP BITS REQUIREMENTS Symbol Tsu:sta Thd:sta Tsu:sto Thd:sto Characteristic START condition Setup time START condition Hold time STOP condition Setup time STOP condition Hold time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode Min 4700 600 4000 600 4700 600 4000 600 Typ Max — — — — — — — — — — — — — — — — ns ns ns Units ns Conditions Only relevant for Repeated START condition After this period, the first clock pulse is generated FIGURE 15-18: I2C BUS DATA TIMING 103 100 101 102 SCL 90 91 106 107 92 SDA In 110 109 SDA Out Note: Refer to Figure 15-5 for load conditions. 109  2001 Microchip Technology Inc. DS30292C-page 171 PIC16F87X TABLE 15-9: Param No. 100 I2C BUS DATA REQUIREMENTS Characteristic Clock high time 100 kHz mode 400 kHz mode SSP Module Min 4.0 0.6 0.5TCY 4.7 1.3 0.5TCY — 20 + 0.1Cb — 20 + 0.1Cb 4.7 0.6 4.0 0.6 0 0 250 100 4.7 0.6 — — 4.7 1.3 — Max — — — — — — 1000 300 300 300 — — — — — 0.9 — — — — 3500 — — — 400 ns ns ns ns µs µs µs µs ns µs ns ns µs µs ns ns µs µs pF Time the bus must be free before a new transmission can start (Note 1) (Note 2) Cb is specified to be from 10 to 400 pF Only relevant for Repeated START condition After this period, the first clock pulse is generated Cb is specified to be from 10 to 400 pF µs µs Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz Units µs µs Conditions Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz Sym Thigh 101 Tlow Clock low time 100 kHz mode 400 kHz mode SSP Module 102 Tr SDA and SCL rise time 100 kHz mode 400 kHz mode 103 Tf SDA and SCL fall time 100 kHz mode 400 kHz mode 90 91 106 107 92 109 110 Tsu:sta Thd:sta Thd:dat Tsu:dat Tsu:sto Taa Tbuf START condition setup time 100 kHz mode 400 kHz mode START condition hold 100 kHz mode time 400 kHz mode Data input hold time Data input setup time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode STOP condition setup 100 kHz mode time 400 kHz mode Output valid from clock Bus free time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode Cb Bus capacitive loading Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast mode (400 kHz) I2C bus device can be used in a standard mode (100 kHz) I2C bus system, but the requirement that Tsu:dat ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+ Tsu:dat = 1000 + 250 = 1250 ns (according to the standard mode I2C bus specification) before the SCL line is released. DS30292C-page 172  2001 Microchip Technology Inc. PIC16F87X FIGURE 15-19: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK Pin RC7/RX/DT Pin 121 121 120 122 Note: Refer to Figure 15-5 for load conditions. TABLE 15-10: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No. 120 Sym TckH2dtV Characteristic SYNC XMIT (MASTER & SLAVE) Clock high to data out valid Standard(F) — Extended(LF) — — — — — — — — — — — 80 100 45 50 45 50 ns ns ns ns ns ns Min Typ† Max Units Conditions 121 122 † Tckrf Tdtrf Clock out rise time and fall time Standard(F) (Master mode) Extended(LF) Data out rise time and fall time Standard(F) Extended(LF) Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 15-20: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX/CK pin RC7/RX/DT pin 125 126 Note: Refer to Figure 15-5 for load conditions. TABLE 15-11: USART SYNCHRONOUS RECEIVE REQUIREMENTS Parameter No. 125 Sym Characteristic Min Typ† Max Units Conditions TdtV2ckL SYNC RCV (MASTER & SLAVE) Data setup before CK ↓ (DT setup time) TckL2dtl Data hold after CK ↓ (DT hold time) 15 15 — — — — ns ns 126 † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2001 Microchip Technology Inc. DS30292C-page 173 PIC16F87X TABLE 15-12: PIC16F87X-04 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16F87X-10 (EXTENDED) PIC16F87X-20 (COMMERCIAL, INDUSTRIAL) PIC16LF87X-04 (COMMERCIAL, INDUSTRIAL) Param No. A01 A03 A04 A06 A07 A10 A20 Sym NR EIL EDL Characteristic Resolution Integral linearity error Differential linearity error Min — — — — — — 2.0 Typ† — — — — — guaranteed — Max 10-bits